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PRELIMINARY DATA SHEET

MICRONAS

VDP 31xxB Video Processor Family

Edition Sept. 25, 1998 6251-437-2PD

MICRONAS

VDP 31xxB
Contents Page 5 6 7 7 7 7 7 7 7 7 7 9 10 10 11 11 11 11 11 11 12 12 13 13 13 14 15 15 15 16 17 17 17 17 18 18 18 18 19 19 19 19 Section 1. 1.1. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.1.7. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.4. 2.5. 2.6. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.8.5. 2.8.6. 2.8.7. 2.8.8. 2.8.9. 2.8.10. 2.8.11. 2.8.12. 2.8.13. 2.8.14. 2.8.15. Title Introduction VDP Applications Functional Description Analog Front-End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters ADC Range Digitally Controlled Clock Oscillator Analog Video Output Adaptive Comb Filter Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection Color Killer Operation PAL Compensation /1-H Comb Filter Luminance Notch Filter Skew Filtering Horizontal Scaler Black-Line Detector Test Pattern Generator Video Sync Processing Display Part Luma Contrast Adjustment Black Level Expander Dynamic Peaking Digital Brightness Adjustment Soft Limiter Chroma Input Chroma Interpolation Chroma Transient Improvement Inverse Matrix RGB Processing OSD Color Lookup Table Picture Frame Generator Priority Codec Scan Velocity Modulation Display Phase Shifter

PRELIMINARY DATA SHEET

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PRELIMINARY DATA SHEET

VDP 31xxB

Contents, continued Page 21 21 22 23 23 24 24 24 26 26 26 28 28 29 29 30 30 30 43 46 47 47 47 49 51 52 54 54 54 54 55 56 56 56 57 57 57 58 59 60 60 60 Section 2.9. 2.9.1. 2.9.2. 2.9.3. 2.9.4. 2.9.5. 2.9.6. 2.10. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.12. 2.13. 3. 3.1. 3.2. 3.2.1. 3.2.2. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. Title Analog Back End CRT Measurement and Control SCART Output Signal Average Beam Current Limiter Analog RGB Insertion Fast Blank Monitor Half Contrast Control IO Port Expander Synchronization and Deflection Deflection Processing Horizontal Phase Adjustment Vertical and East/West Deflection Protection Circuitry Reset Function Standby and Power-On Serial Interface I2C-Bus Interface Control and Status Registers Scaler Adjustment Calculation of Vertical and East-West Deflection Coefficients Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics 5 MHz Clock Output 20 MHz Clock Input/Output, External Clock Input (XTAL1) Reset Input, Test Input I2C-Bus Interface IO Port Expander Analog Video Inputs Analog Front-End and ADCs Picture Bus Input INTLC, Front Sync Output Main Sync Output Combined Sync Output

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Contents, continued Page 61 61 61 61 62 62 62 63 64 66 66 67 72 Section 4.6.4.12. 4.6.4.13. 4.6.4.14. 4.6.4.15. 4.6.4.16. 4.6.4.17. 4.6.4.18. 4.6.4.19. 4.6.4.20. 4.6.4.21. 4.6.4.22. 5. 6. Title Horizontal Flyback Input Horizontal Drive Output Vertical Protection Input Vertical Safety Input Vertical and East/West Drive Output Sense A/D Converter Input Analog RGB and FB Inputs Half Contrast Switch Input Analog RGB Outputs, D/A Converters DAC Reference, Beam Current Safety Scan Velocity Modulation Output Application Circuit Data Sheet History

PRELIMINARY DATA SHEET

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PRELIMINARY DATA SHEET

VDP 31xxB
VPC 3200A Video Processor and DDP 3300A Display and Deflection Processor. Each member of the family contains the entire video, display, and deflection processing for 4:3 and 16:9 50/60 TV sets. Its performance and flexibility allow the user to standardize his product development. Hardware and software applications can profit from the modularity, as well as manufacturing, systems support, or maintenance. An overview of the VDP 31xxB video processor family is shown in Fig. 1­1.

Video, Display, and Deflection Processor Release Notes: This data sheet describes functions and characteristics of the VDP 31xxB­C2. Revision bars indicate significant changes to the previous edition. 1. Introduction The VDP 31xxB is a Video IC family of high-quality single-chip video processors. Modular design and a submicron technology allow the economic integration of features in all classes of TV sets. The VDP 31xxB family is based on functional blocks contained in the two chips:

Color Trans. Impr.

2H adapt. Comb

Scan Vel. Mod.

Prog. RGB Matrix

Horizontal Scaler

1H Combfilter

RGB Insertion n n n n n

VDP 31xxB Family VDP 3104B VDP 3108B VDP 3112B VDP 3116B VDP 3120B

n n n n n n n n n n n n n n n n n

n n n n n

Fig. 1­1: VDP 31xxB family overview

VRT

Tube Control n n n n n

Color Bus

XREF

CIN VIN1 VIN2 VIN3 VIN4 VOUT Analog Frontend AGC, 2*8bit ADC 2H Adaptive Combfilter Color Decoder NTSC, PAL, SECAM Horizontal Scaler Panorama Mode Display Processor RGB Matrix, CLUT, Scan Veloc. Analog Backend 3*10bit DAC, Tube Control, RGB Switch

RGB/FB IN1 RGB/FB IN2 Half Contrast RGB OUT

SVM

20.25 MHz

Clock Gen. DCO

I2C

Sync & Deflection

Measurement ADC

I2C

H/V/EW

Sense

Fig. 1­2: Block diagram of the VDP 3120B Micronas 5

VDP 31xxB
1.1. VDP Applications As a member of the VDP 31xxB family, the VDP 3120B offers all video features necessary to design a state-ofthe-art TV set: Video Decoding ­ 4 composite inputs, 1 S-VHS input ­ composite video & sync output ­ integrated high-quality A/D converters ­ adaptive 2H comb filter Y/C separator ­ 1H NTSC comb filter ­ multistandard color decoder (1 crystal) ­ multistandard sync decoder ­ black line detector Miscellaneous Video Processing ­ horizontal scaling (0.25 to 4) ­ panorama vision ­ black level expander ­ dynamic peaking ­ soft limiter (gamma correction) ­ color transient improvement Deflection RGB Processing

PRELIMINARY DATA SHEET

­ programmable RGB matrix ­ digital color bus interface ­ additional analog RGB / fast blank input ­ half-contrast switch ­ picture frame generator

­ scan velocity modulation output ­ high-performance H/V deflection ­ separate ADC for tube measurements ­ EHT compensation

­ one 20.25 MHz crystal, few external components ­ embedded RISC controller (80 MIPS) ­ I2C-Bus Interface ­ single 5 V power supply ­ submicron CMOS technology ­ 64-pin PSDIP package

Video 1 Video 2

TPU 3040

DRAM

CCU 300x

VDP 3120B

RGB H/VDefl.

RGB 1 RGB 2 Audio
MSP 3410

3 x Stereo

DPL 3420

Dolby Surround

Fig. 1­3: Full-feature TV set with VDP 3120B

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PRELIMINARY DATA SHEET

VDP 31xxB
2.1.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/­4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. 2.1.4. Analog-to-Digital Converters

2. Functional Description 2.1. Analog Front-End This block provides the analog interfaces to all video inputs and mainly carries out analog-to digital conversion for the following digital video processing. A block diagram is given in Fig. 2­1. Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (`FP') embedded in the decoder.

Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. 2.1.5. ADC Range The ADC input range for the various input signals and the digital representation is given in Table 2­1 and Fig. 2­2. The corresponding output signal levels of the VDP 31xxB are also shown. 2.1.6. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within ±150 ppm. 2.1.7. Analog Video Output The input signal of the Luma ADC is available at the analog video output pin. The signal at this pin must be buffered by a source follower. The output voltage is 2 V, thus the signal can be used to drive a 75 W line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC.

2.1.1. Input Selector Up to five analog inputs can be connected. Four inputs are for input of composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for connection of S-VHS carrier-chrominance signal. This input is internally biased and has a fixed gain amplifier.

2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to the center of the ADC input range.

Analog Video Output CVBS/Y VIN4 CVBS/Y CVBS/Y VIN3 input mux VIN2 clamp 3

AGC +6/­4.5 dB ADC gain digital CVBS or Luma

CVBS/Y/C VIN1 Chroma CIN

bias

ADC

digital Chroma system clocks

reference generation

frequency

DVCO ±150 ppm 20.25 MHz

Fig. 2­1: Analog front-end Micronas 7

VDP 31xxB
Table 2­1: ADC input range for PAL input signal and corresponding signal ranges Signal Input Level [mVpp]

PRELIMINARY DATA SHEET

ADC Range [steps] 252 213 149 64 68

YCrCb Internal Range [steps] ­ ­ 224 ­ 16 ­ 128±112 128±84 128

­6 dB CVBS 100% CVBS 75% CVBS video (luma) sync height clamp level Chroma burst 100% Chroma 75% Chroma bias level 667 500 350 150

0 dB 1333 1000 700 300

+4.5 dB

2238 1679 1175 504

300 890 670

64 190 143 128

CVBS/Y

Chroma
headroom = 56 steps = 2.1 dB 228 192

217 192

white

video = 100 IRE 128

128 black = clamp level

68 32 0

80 sync = 41 IRE

lower headroom = 4 steps = 0.2 dB

Fig. 2­2: ADC ranges for CVBS/Luma and Chroma, PAL input signal 8

ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ

32

ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ
100% Chroma 75% Chroma burst

ÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍ

255

upper headroom = 38 steps = 1.4 dB = 25 IRE

Micronas

PRELIMINARY DATA SHEET

VDP 31xxB
Two parameters (KY, KC) set the global gain of luma and chroma comb separately; these values directly weigh the adaption algorithm output. In this way, it is possible to obtain a luma/chroma separation ranging from standard notch/bandpass to full comb decoding. The parameter KB allows to choose between the two proposed comb booster modes. This so-called feature widely improves vertical high to low frequency transitions areas, the typical example being a multiburst to dc change. For KB=0, this improvement is kept moderate, whereas, in case of KB=1, it is maximum, but the risk to increase the "hanging dots" amount for some given color transitions is higher. Using the default setting, the comb filter has separate luma and chroma decision algorithms; it is however possible to switch the chroma comb factor to the current luma adaption output by setting CC to 1. Another interesting feature is the programmable limitation of the luma comb amount; proper limitation, associated to adequate luma peaking, gives rise to an enhanced 2-D resolution homogeneity. This limitation is set by the parameter CLIM, ranging from 0 (no limitation) to 31 (max. limitation). The DAA parameter (1:off , 0:on) is used to disable/enable a very efficient built-in "rain effect" suppressor; many comb filters show this side effect which gives some vertical correlation to a 2-D uniform random area, due to the vertical filtering. This unnatural-looking phenomenon is mostly visible on tuner images, since they are always corrupted by some noise; and this looks like rain.

2.2. Adaptive Comb Filter The adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color artifacts. The adaptive algorithm can eliminate most of the mentioned errors without introducing new artifacts or noise. A block diagram of the comb filter is shown in Fig. 2­3. The filter uses two line delays to process the information of three adjacent video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 MHz) is fractionally locked to the color subcarrier. This allows the processing of all color standards and substandards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass / notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/ notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. The comb filter uses the middle line as reference, therefore, the comb filter delay is one line. If the comb filter is switched off, the delay lines are used to pass the luma/ chroma signals from the A/D converters to the luma/ chroma outputs. Thus, the comb filter delay is always one line. Various parameters of the comb filter are adjustable, hence giving to the user the ability to adjust his own desired picture quality.

CVBS Input 1 H Line Delay Bandpass/ Notch Filter

Luma / Chroma Mixers Adaption Logic

Bandpass Filter

Luma Output

Chroma Output

1 H Line Delay Chroma Input

Bandpass Filter

Fig. 2­3: Block diagram of the adaptive comb filter

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2.3. Color Decoder In this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. A block diagram of the color decoder is shown in Fig. 2­5. The luma as well as the chroma processing, is shown here. The color decoder provides also some special modes, e.g. wide band chroma format which is intended for S-VHS wide bandwidth chroma. If the adaptive comb filter is used for luma chroma separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCrCb in a 4:2:2 format.

PRELIMINARY DATA SHEET

2.3.1. IF-Compensation With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Four different settings of the IFcompensation are possible: ­ flat (no compensation) ­ 6 dB /octave ­ 12 dB /octave ­ 10 dB/MHz The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL standard.

Fig. 2­4: Frequency response of chroma IF-compensation

Luma / CVBS

Notch Filter

Luma

MUX

1 H Delay

Cross-Switch

Chroma / CrCb

ACC MUX IF Compensation DC-Reject MIXER Lowpass Filter Phase/Freq Demodulator

Chroma

Color-PLL / Color-ACC

Fig. 2­5: Color decoder 10 Micronas

PRELIMINARY DATA SHEET

VDP 31xxB
2.3.4. Frequency Demodulator The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled to standard CrCb amplitudes and fed to the crossoverswitch. 2.3.5. Burst Detection In the PAL/NTSC-system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-lock-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/NTSC. The ACC has a control range of +30 ... ­6 dB. For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they can be used for automatic standard detection as well. 2.3.6. Color Killer Operation The color killer uses the burst-phase / burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis. 2.3.7. PAL Compensation / 1-H Comb Filter

2.3.2. Demodulator The entire signal (which might still contain luma) is now quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chroma. After the mixer, a lowpass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be demodulated.

2.3.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luma information is eliminated. The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard. For PAL/ NTSC, a wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide bandwidth S-VHS signal.

PAL/NTSC

The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: ­ NTSC: ­ PAL: 1-H comb filter or color compensation color compensation

­ SECAM: crossover-switch In the NTSC compensated mode, Fig. 2­7 c), the color signal is averaged for two adjacent lines. Thus, crosscolor distortion and chroma noise is reduced. In the NTSC combfilter mode, Fig. 2­7 d), the delay line is in the composite signal path, thus allowing reduction of 11

SECAM

Fig. 2­6: Frequency response of chroma filters

Micronas

VDP 31xxB
cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information.

PRELIMINARY DATA SHEET

2.3.8. Luminance Notch Filter If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems are shown in Fig. 2­10.
10 dB

CVBS
8

Notch filter Chroma Process.

Y CrC b

Luma
8

Y
Chroma Process.

Chroma
8

CrC b

a) conventional
CVBS
8 Notch filter

b) S-VHS
Y

0

­10 Chroma Process. 1H Delay

CrC b

­20

c) compensated
Notch filter 1H Delay

­30

CVBS
8

Y

­40 0 2 4 6 8 10

MHz

PAL/NTSC notch filter
dB

Chroma Process.

CrC b

10

0

d) comb filter
­10

Fig. 2­7: NTSC color decoding options

­20

­30

CVBS
8

Notch filter

Y

­40 0 2 4 6 8 10

MHz

SECAM notch filter
Chroma Process. 1H Delay

CrC b

a) conventional
Luma
8

Fig. 2­10: Frequency responses of the luma notch filter for PAL, NTSC, and SECAM

Y

2.3.9. Skew Filtering The system clock is free-running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. The skew filters allow the application of a group delay to the input signals without introducing waveform or frequency response distortion.

Chroma
8

Chroma Process.

1H Delay

CrC b

b) S-VHS Fig. 2­8: PAL color decoding options

CVBS
8

Notch filter

Y

Chroma Process.

1H Delay

MUX

CrC b

Fig. 2­9: SECAM color decoding

The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. Thus the 4:2:2 YCrCb data is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR. Micronas

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PRELIMINARY DATA SHEET

VDP 31xxB
2.5. Black-Line Detector In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower part of the picture are visible. It is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. The VDP 31xxB supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared to the previous measurement and the minima are stored in the I2C-register BLKLIN. To adjust the picture amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the VDP. Letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are processed as non-black lines. Therefore the subtitles are visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. Dark video scenes with a low contrast level compared to the letterbox area are indicated by the BLKPIC bit.

2.4. Horizontal Scaler The 4:2:2 YCrCb signal from the color decoder is processed by the horizontal scaler. The scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. Nonlinear scaling, also called "panorama vision", provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect can be produced by the scaler. A summary of scaler modes is given in Table 2­2. The scaler contains a programmable decimation filter, a 1-line FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel skew correction, see 2.3.9. The decimator/interpolator structure allows optimal use of the FIFO memory. The controlling of the scaler is done by the internal Fast Processor. Table 2­2: Scaler modes Mode Compression 4:3 16:9 Panorama 4:3 16:9 Zoom 4:3 4:3 Scale Factor 0.75 linear nonlinear compr 1.33 linear Description 4:3 source displayed on a 16:9 tube, with side panels 4:3 source displayed on a 16:9 tube, Borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan with cropping of side panels Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping

2.6. Test Pattern Generator The YCrCb outputs of the front-end can be switched to a test mode where YCrCb data are generated digitally in the VDP 31xxB. Test patterns include luma/chroma ramps, flat fields and a pseudo color bar pattern.

Panorama 4:3 4:3

nonlinear zoom

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VDP 31xxB
2.7. Video Sync Processing Fig. 2­11 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 MHz. The sync is separated by a slicer; the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated sync pulse. The sync phase error is filtered by a phase-locked loop that is computed by the FP. All timing in the front-end is derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. A separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. This information is processed by the FP and used for gain control and clamping.

PRELIMINARY DATA SHEET

For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The format of the front sync signal is given in Fig. 2­12. The data for the vertical deflection, the sawtooth, and the East-West correction signal is calculated by the VDP 31xxB. The data is buffered in a FIFO and transferred to the back-end by a single wire interface. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked clock generation. Horizontal and vertical syncs are latched with the line-locked clock.

PLL1
lowpass 1 MHz & syncslicer video input front-end timing clamp & signal meas. clamping, colorkey, FIFO_write clock synthesizer syncs clock H/V syncs horizontal sync separation phase comparator & lowpass counter front sync generator front sync skew vblank field

vertical sync separation

Sawtooth Parabola Calculation

FIFO

vertical serial data

vertical E/W sawtooth

Fig. 2­11: Sync separation block diagram

F1 input analog video

skew LSB

skew not MSB used

F

V

F0 reserved (not in scale)
F0 F1

V: vertical sync 0 = off Parity 1 = on F: field # 0 = field 1 1 = field 2

FSY

Fig. 2­12: Front sync format

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PRELIMINARY DATA SHEET

VDP 31xxB
2.8.2. Black Level Expander The black level expander enhances the contrast of the picture. Therefore the luminance signal is modified with an adjustable, non-linear function. Dark areas of the picture are changed to black, while bright areas remain unchanged. The advantage of this black level expander is that the black expansion is performed only if it will be most noticeable to the viewer. The black level expander works adaptively. Depending on the measured amplitudes `Lmin' and `Lmax' of the lowpass-filtered luminance and an adjustable coefficient BTLT, a tilt point `Lt' is established by Lt = Lmin + BTLT (Lmax ­ Lmin). Above this value there is no expansion, while all luminance values below this point are expanded according to: Lout = Lin + BAM (Lin ­ Lt) A second threshold, Ltr, can be programmed, above which there is no expansion. The characteristics of the black level expander are shown in Fig. 2­13 and Fig. 2­14. The tilt point Lt is a function of the dynamic range of the video signal. Thus, the black level expansion is only performed when the video signal has a large dynamic range. Otherwise, the expansion to black is zero. This allows the correction of the characteristics of the picture tube.

2.8. Display Part In the display part the conversion from digital YCrCb to analog RGB is carried out. A block diagram is shown in Figure 2­20. In the luminance processing path, contrast and brightness adjustments and a variety of features, such as black level expansion, dynamic peaking and soft limiting, are provided. In the chrominance path, the CrCb signals are converted to 20.25 MHz sampling rate and filtered by a color transient improvement circuit. The YCrCb signals are converted by a programmable matrix to RGB color space. The display processor provides separate control settings for two pictures, i.e. different coefficients for a `main' and a `side' picture. The digital OSD insertion circuit allows the insertion of a 5-bit OSD signal. The color space for this signal is controlled by a partially programmable color look-up table (CLUT) and contrast adjustment. The OSD signals and the display clock are synchronized to the horizontal flyback. For the display clock, a gate delay phase shifter is used. In the analog backend, three 10-bit digital-to-analog converters provide the analog output signals.

2.8.1. Luma Contrast Adjustment The contrast of the luminance signal can be adjusted by multiplication with a 6-bit contrast value. The contrast value corresponds to a gain factor from 0 to 2, where the value 32 is equivalent to a gain of 1. The contrast can be adjusted separately for main picture and side picture.

a)

Lmax

Lt Lmin

Lout Ltr Lt BAM BTLT Lmin

Lmax

b)

Lt

Ltr

BTHR

Lin

Fig. 2­13: Characteristics of the black level expander

Fig. 2­14: Black-level-expansion a) luminance input b) luminance input and output 15

Micronas

VDP 31xxB
2.8.3. Dynamic Peaking Especially with decoded composite signals and notch filter luminance separation, as input signals, it is necessary to improve the luminance frequency characteristics. With transparent, high-bandwidth signals, it is sometimes desirable to soften the image. In the VDP 31xxB, the luma response is improved by `dynamic' peaking. The algorithm has been optimized regarding step and frequency response. It adapts to the amplitude of the high frequency part. Small AC amplitudes are processed, while large AC amplitudes stay nearly unmodified. The dynamic range can be adjusted from *14 to )14 dB for small high frequency signals. There is separate adjustment for signal overshoot and for signal undershoot. For large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. The peaking can be switched over to "softening" by inverting the peaking term by software.

PRELIMINARY DATA SHEET

The center frequency of the peaking filter is switchable from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter color decoding, the total system frequency responses for both PAL and NTSC are shown in figure 2­16. Transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus.
dB 20 15 10 5 0 ­5 ­10 ­15 ­20 0 2 4 6 8 10 MHz

Fig. 2­15: Dynamic peaking frequency response

dB 20 15 10 5 0 ­5 ­10 ­15 ­20 0 dB 20 15 10 5 0 ­5 ­10 ­15 ­20 0 2 4 6 8 10 MHz 20 2 4 6 8 10 MHz 20 15

dB

CF= 2.5 MHz

CF= 3.2 MHz

10 5

S-VHS

0 ­5 ­10 ­15 ­20 0 dB 2 4 6 8 10 MHz

CF= 3.2 MHz

15 10 5

CF= 2.5 MHz

PAL/SECAM

0 ­5 ­10 ­15 ­20 0 dB 20 2 4 6 8 10 MHz

dB 20 15 10 5 0 ­5 ­10 ­15 ­20 0 2 4 6 8 10 MHz

CF= 3.2 MHz

15 10 5

CF= 2.5 MHz

NTSC

0 ­5 ­10 ­15 ­20 0 2 4 6 8 10 MHz

Fig. 2­16: Total frequency response for peaking filter and S-VHS, PAL, NTSC

16

Micronas

PRELIMINARY DATA SHEET

VDP 31xxB
signal itself. Therefore, the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. The tilt value can be adjusted from 0 to 511. Part 2 has the same characteristics as part 1. The subtracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input signal is above the both tilt values (see characteristics). Finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511. 2.8.6. Chroma Input

2.8.4. Digital Brightness Adjustment The DC-level of the luminance signal can be adjusted by adding an 8-bit number in the luminance signal path in front of the softlimiter. With a contrast adjustment of 32 (gain+1) the signal can be shifted by "100%. After the brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. The digital brightness adjustment is separate for main and side picture. 2.8.5. Soft Limiter The dynamic range of the processed luma signal must be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking and brightness can be adjusted by the TV manufacturer according to the CRT characteristics. All signals above this limit will be `soft'-clipped. A characteristic diagram of the soft limiter is shown in Fig. 2­17. The total limiter consists of three parts: Part 1 includes adjustable tilt point and gain. The gain before the tilt value is 1. Above the tilt value, a part (0...15/16) of the input signal is subtracted from the input

The chroma input signal is a multiplexed CR and CB signal in 8-bit binary offset code. It can be switched between normal and inverted signal and between two's complement and binary offset code. The delay in respect to the luminance input can be adjusted in 5 steps within a range of "2 clock periods. 2.8.7. Chroma Interpolation A linear phase interpolator is used to convert the chroma sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz (4:4:4). All further processing is carried out at the full sampling rate.

Output 511

Part 1

Part 2 0 2 4 6 8 10 12 14 slope 2 [0...15]

Hard limiter

400

300

200

slope 1 [0...15] 0 2 4 6 8 10 12 14

Calculation Example for the Softlimiter Input Amplitude. (The real signal processing in the limiter is 2 bit more than described here) Y Input Black Level Contrast Dig. Brightness BLE Peaking 16...235 (ITUR) 16 (constant) 63 20 off off

range= 256...511

100 tilt 1 [ 0...511] 0 0 100 200 300 400 500 600 700 800 900 tilt 2 [0...511]

Limiter input signal: (Yin-Black Level)·Contr./32 + Brightn. (235­16) · 63/32 + 20 = 451 Limiter Input 1023

Fig. 2­17: Characteristic of soft limiter a and b and hard limiter Micronas 17

VDP 31xxB
2.8.8. Chroma Transient Improvement The intention of this block is to enhance the chroma resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate `wrong colors', which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically.
a)

PRELIMINARY DATA SHEET

2.8.9. Inverse Matrix A 6-multiplier matrix transcodes the Cr and Cb signals to R­Y, B­Y, and G­Y. The multipliers are also used to adjust color saturation in the range of 0 to 2. The coefficients are signed and have a resolution of 9 bits. There are separate matrix coefficients for main and side pictures. The matrix computes: R­Y+MR1*Cb)MR2*Cr G­Y+MG1*Cb)MG2*Cr B­Y+MB1*Cb)MB2*Cr The initialization values for the matrix are computed from the standard ITUR (CCIR) matrix: R G + B 1 0 1.402 1 * 0.345 * 0.713 1 1.773 0 Y Cb Cr

Cr in Cb in

For a contrast setting of CTM+32, the matrix values are scaled by a factor of 64, see also table 3­1.
t b)

2.8.10. RGB Processing After adding the post-processed luma, the digital RGB signals are limited to 10 bits. Three multipliers are used to digitally adjust the white drive. Using the same multipliers an average beam current limiter is implemented. See also section 2.9.1. `CRT Measurement and Control'. 2.8.11. OSD Color Lookup Table The VDP 31xxB has five input lines for an OSD signal. This signal forms a 5-bit address for a color look-up table (CLUT). The CLUT is a memory with 32 words where each word holds a RGB value. Bits 0 to 3 (bit 4+0) form the addresses for the ROM part of the OSD, which generates full RGB signals (bit 0 to 2) and half-contrast RGB signals (bit 3). Bit 4 addresses the RAM part of the OSD with 16 freely programmable colors, addressable with bit 0 to 3. The programming is done via the I2C-bus. The amplitude of the CLUT output signals can be adjusted separately for R, G and B via the I2C-bus. The switchover between video RGB and OSD RGB is done via the Priority bus.

Ampl.

t c)

Cr out Cb out

t

a) Cr Cb input of DTI b) Cr Cb input)Correction signal c) sharpened and limited Cr Cb Fig. 2­18: Digital Color Transient Improvement

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PRELIMINARY DATA SHEET

VDP 31xxB
2.8.14. Scan Velocity Modulation The RGB input signal of the SVM is converted to Y in a simple matrix. Then the Y signal is differentiated by a filter of the transfer function 1­Z­N, where N is programmable from 1 to 6. With a coring, some noise can be suppressed. This is followed by a gain adjustment and an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter. The signal delay can be adjusted by ±3.5 clocks in halfclock steps. For the gain and filter adjustment there are two parameter sets. The switching between these two sets is done with the same RGB switch signal that is used for switching between video-RGB and OSD-RGB for the RGB outputs. (See Fig. 2­19). 2.8.15. Display Phase Shifter

2.8.12. Picture Frame Generator When the picture does not fill the total screen (height or width too small) it is surrounded with black areas. These areas (and more) can be colored with the picture frame generator. This is done by switching over the RGB signal from the matrix to the signal from the OSD color look-up table. The width of each area (left, right, upper, lower) can be adjusted separately. The generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. This means, it runs during horizontal, respectively vertical flyback. The color of the complete border can be stored in the programmable OSD color look-up table in a separate address. The format is 3 4 bit RGB. The contrast can be adjusted separately. The picture frame generator includes a priority master circuit. Its priority is programmable and the border is generated only if the priority is higher than the priority at the PRIO bus. Therefore the border can be underlay or overlay depending on the picture source. 2.8.13. Priority Codec The priority decoder has three input lines for up to eight priorities. The highest priority is all three lines at low level. A 5-bit information is attached to each priority (see table 3­1 `Priority Bus'). These bits are programmable via the I2C-bus and have the following meanings: ­ one of two contrast, brightness and matrix values for main and side picture ­ RGB from video signal or color look-up table ­ disable/enable black level expander ­ disable/enable peaking transient suppression when signal is switched ­ disable/enable analog fast blank input 1 ­ disable/enable analog fast blank input 2

A phase shifter is used to partially compensate the phase differences between the video source and the flyback signal. By using the described clock system, this phase shifter works with an accuracy of approximately 1 ns. It has a range of 1 clock period which is equivalent to ±24.7 ns at 20.25 MHz. The large amount of phase shift (full clock periods) is realized in the front-end circuit.

R

G

B N1 N2

Coring

Gain1

Gain2

RGB Switch Limit Delay

Matrix and Shaping Modulation Notch

Differentiator 1­Z­Nx

Coring adjustment

Gain adjustment

Limiter

Delay adjustment

D/A Converter

Output

Fig. 2­19: SVM block diagram Micronas 19

20 Micronas

VDP 31xxB

Fig. 2­20: Digital back-end
dig. Y in
8 5

contrast

brightness + offset

whitedrive measurement

dynamic peaking

clock

prio

softlimiter

luma insert for CRTmeasurement

Picture Frame Generator
whitedrive R x beamcurr. lim.

display & clock control

horizontal flyback

CLUT, Contrast

dig. OSD in black level expander
8 blanking for CRTmeasurement

Y Matrix R'

Phase Shift 0...1 clock R
whitedrive G x beamcurr. lim.

dig. Rout
10

prio

Cr

dig. CrCb in

DTI (Cr)

Interpol 4:4:4 DTI (Cb)

Matrix G'

Phase Shift 0...1 clock G
whitedrive B x beamcurr. lim.

dig. Gout
10

Cb

PRIO in
3

side picture

PRIO decoder

select coefficients
main picture

Matrix B'

Phase Shift 0...1 clock B

dig. Bout

PRELIMINARY DATA SHEET

10

Scan Velocity Modulation
Matrix saturation

SVMout

PRELIMINARY DATA SHEET

VDP 31xxB
Cutoff and white drive current measurement are carried out during the vertical blanking interval. They always use the small bandwidth setting. The current range for the cutoff measurement is set by connecting a sense resistor to the MADC input. For the whitedrive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (RSW2). During the active picture, the minimum and maximum beam current is measured. The measurement range can be set by using the range select switch 1 pin (RSW1) as shown in Fig. 2­21 and Fig. 2­22. The timing window of this measurement is programmable. The intention is to automatically detect letterbox transmission or to measure the actual beam current. All control loops are closed via the external control microprocessor.
beam current A D MADC
SENSE

2.9. Analog Back End The digital RGB signals are converted to analog RGBs using three video digital to analog converters (DAC) with 10-bit resolution. An analog brightness value is provided by three additional DACs. The adjustment range is 40% of the full RGB range. Controlling the whitedrive/analog brightness and also the external contrast and brightness adjustments is done via the Fast Processor, located in the front-end. Control of the cutoff DACs is via I2C-bus registers. Finally cutoff and blanking values are added to the RGB signals. Cutoff (dark current) is provided by three 9-bit DACs. The adjustment range is 60% of full scale RGB range. The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. An external half contrast signal can be used to reduce the output current of the RGB outputs to 50%. 2.9.1. CRT Measurement and Control The display processor is equipped with an 8-bit PDMADC for all measuring purposes. The ADC is connected to the sense input pin, the input range is 0 to 1.5V. The bandwidth of the PDM filter can be selected; it is 40/80 kHz for small/large bandwidth setting. The input impedance is more than 1 M.

RSW1 RSW2

R2 R3

R1

Fig. 2­21: MADC Range Switches

CR + IBRM + WDRV·WDR CR + IBRM white drive cutoff R R

black ultra black

R
cutoff G

CG + IBRM

G
cutoff B

CB + IBRM

B

active measurement resistor

R1øR2øR3 RSW1=on, RSW2=on PICTURE MEAS. PMSO

R1

R1øR3 RSW2 =on

R1øR2øR3 RSW1=on, RSW2=on PICTURE MEAS.

TUBE MEASUREMENT TML PMST

Lines

Fig. 2­22: MADC Measurement Timing

Micronas

21

VDP 31xxB
In each field two sets of measurements can be taken: a) The picture tube measurement returns results for ­ cutoff R ­ cutoff G ­ cutoff B ­ white drive R or G or B (sequentially) b) The picture measurement returns data on ­ active picture maximum current ­ active picture minimum current
active video field 1/ 2

PRELIMINARY DATA SHEET

The vertical timing for the picture measurement is programmable, and may even be a single line. Also the signal bandwidth is switchable for the picture measurement. Two horizontal windows are available for the picture measurement. The large window is active for the entire active line. Tube measurement is always carried out with the small window. Measurement windows for picture and tube measurement are shown in Figure 2­23.
tube measurement picture meas. start

picture meas. end

Fig. 2­23: Windows for tube and picture measurements

2.9.2. SCART Output Signal The RGB output of the VDP 31xxB can also be used to drive a SCART output. In the case of the SCART signal, the parameter CLMPR (clamping reference) has to be set to 1. Then, during blanking, the RGB outputs are automatically set to 50% of the maximum brightness. The DC offset values can be adjusted with the cutoff parameters CR, CG, and CB. The amplitudes can be adjusted with the drive parameters WDR, WDG, and WDB.

The picture measurement must be enabled by the control microprocessor after reading the min./max. result registers. If a `1' is written into bit 2 in subaddress 25, the measurement runs for one field. For the next measurement a `1' has to be written again. The measurement is always started at the beginning of active video.

22

ÍÍÍÍÍÍÍÍÍ ÍÍÍ ÍÍÍ
small window for tube measurement (cutoff, white drive) large window for active picture

The tube measurement is automatically started when the cutoff blue result register is read. Cutoff control for RGB requires one field only while a complete white-drive control requires three fields. If the measurement mode is set to `offset check', a measurement cycle is run with the cutoff/whitedrive signals set to zero. This allows to compensate the MADC offset as well as input the leakage currents. During cutoff and whitedrive measurements, the average beam current limiter function (ref. 2.9.3.) is switched off and a programmable value is used for the brightness setting. The start line of the tube measurement can be programmed via I2C-bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line.

Micronas

PRELIMINARY DATA SHEET

VDP 31xxB
2.9.4. Analog RGB Insertion The VDP 31xxB allows insertion of 2 external analog RGB signals. Each RGB signal is key-clamped and inserted into the main RGB by the fast blank switch. The selected external RGB input is virtually handled as a priority bus signal. Thus, it can be overlaid or underlaid to the digital picture. The external RGB signals can be adjusted independently as regards DC-level (brightness) and magnitude (contrast). Which analog RGB input is selected depends on the fast blank input signals and the programming of a number of I2C-bus register settings (see Table 2­3 and Fig. 2­25). Both fast blank inputs must be either active-low or active-high. All signals for analog RGB insertion (RIN1/2, GIN1/2, BIN1/2, FBLIN1/2, HCS) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be visible. The VDP 31xxB has no means for timing correction of the analog RGB input signals. Table 2­3: RGB Input Selection
FBFOH1 = 0, FBFOH2 = 0, FBFOL1 = 0, FBFOL2 = 0
FBLIN1 0 0 1 1 FBLIN2 0 1 0 1 1 0 0 1 0 1 FBPOL 0 0 0 0 0 1 1 1 1 1 FBPRIO x x x 0 1 0 1 x x x RGB output Video RGB input 2 RGB input 1 RGB input 1 RGB input 2 RGB input 1 RGB input 2 RGB input 1 RGB input 2 Video

2.9.3. Average Beam Current Limiter The average beam current limiter (BCL) uses the sense input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture. The filter bandwidth is approx. 2 kHz. The beam current limiter has an automatic offset adjustment that is active two lines before the first cutoff measurement line. The beam current limiter function is located in the frontend. The data exchange between the front-end and the back-end is done via a single-wire serial interface. The beam current limiter allows the setting of a threshold current. If the beam current is above the threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by adjusting the white-drive multipliers for the internal (digital) RGB signals, and the analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During the tube measurement, the ABL attenuation is switched off. After the white drive measurement line it takes 3 lines to switch back to BCL limited drives and brightness. Typical characteristics of the ABL for different loop gains are shown in Fig. 2­24; for this example the tube has been assumed to have square law characteristics.

beam current

1 0 0 0 1 1 drive

Fig. 2­24: Beam current limiter characteristics: beam current output vs. drive BCL threshold: 1

Micronas

23

VDP 31xxB
2.9.5. Fast Blank Monitor The presence of external analog RGB sources can be detected by means of a fast blank monitor. The status of the selected fast blank input can be monitored via an I2C bus register. There is a 2 bit information, giving static and dynamic indication of a fast blank signal. The static bit is directly reading the fast blank input line, whereas the dynamic bit is reading the status of a flip-flop triggered by the negative edge of the fast blank signal. With this monitor logic it is possible to detect if there is an external RGB source active and if it is a full screen insertion or only a box. The monitor logic is connected directly to the FBLIN1 or FBLIN2 pin. Selection is done via I2C bus register.

PRELIMINARY DATA SHEET

2.9.6. Half Contrast Control Insertion of transparent text pages or OSD onto the video picture is often difficult to read, especially if the video contrast is high. The VDP 31xxB allows contrast reduction of the video background by means of a half contrast input (HCS pin). This input can be supplied with a fast switching signal (similar to the fast blank input), typically defining a rectangular box in which the video picture is displayed with reduced contrast. The analog RGB inputs are still displayed with full contrast. The HCS input is multiplexed with the PORT0 input/output on the same pin, selection is done via I2C-bus register. If the HCS input is selected, then the port function of this pin is disabled and writing data into PORT0 will have no effect. If the HCS input is not selected, the I2C-bus register bits HCSFOH and HCSPOL must be used to disable the half contrast function.
HCSPOL

FBFOH1

FBFOL1

FBPOL

FBPRIO

FBLIN1

#
HCS FB int

Fast Blank Monitor FBLIN2

Fast Blank Selection

#

HCS intern

#

HCSEN

HCSFOH

Fig. 2­26: Half Contrast Switch Logic

FBFOH2

FBFOL2

FBMON

2.10. IO Port Expander The VDP 31xxB provides a general purpose IO port to control and monitor up to seven external signals. The port direction is programmable for each bit individually. Via I2C bus register it is possible to write or read each port pin. Because of the relatively low I2C bus speed, only slow or static signals can be handled. The port signals are multiplexed with other signals to minimize pin count. PORT0 is multiplexed with the HCS input signal, PORT1 is multiplexed with the FSY output signal, PORT[6:2] are multiplexed with the color bus input COLOR[4:0]. The pin configuration is programmable via I2C bus register. All register bits can be read back, the default configuration after reset is input on PORT[1:0] and COLOR[4:0] enabled.

Fig. 2­25: Fast Blank Selection Logic

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Micronas

PRELIMINARY DATA SHEET

VDP 31xxB

digital SVM in 8

8 bit DAC SVM 1.88mA 0.94mA
int. brightness * white drive R

analog SVM out

HCS

cutoff R

9 bit DAC 1.5 mA

digital R in 10

10 bit DAC Video 3.75mA
int. brightness * white drive G

9 bit DAC 2.2 mA

blanking 750 µA

analog R out

cutoff G

9 bit DAC 1.5 mA

digital G in 10

10 bit DAC Video 3.75mA
int. brightness * white drive B

9 bit DAC 2.2 mA

blanking 750 µA

analog G out

cutoff B

9 bit DAC 1.5 mA

digital B in 10

10 bit DAC Video 3.75mA

9 bit DAC 2.2 mA

blanking 750 µA

analog B out

H
ext. brightness * white drive R ext. brightness * white drive G ext. brightness * white drive B

V

serial interface

white drive R white drive G

9 bit DAC 1.5 mA

9 bit DAC 1.5 mA

9 bit DAC 1.5 mA

blank & measurem. timing

ext. contrast * white drive R * beam current lim.

ext. contrast * white drive G * beam current lim.

white drive B int . brightness ext. contrast ext. brightness

9 bit U/I­DAC 3.75mA clamp & mux

9 bit U/I­DAC 3.75mA clamp & mux

ext. contrast * white drive B * beam current lim.

9 bit U/I­DAC 3.75mA clamp & mux FBL prio

8 bit ADC measurm.

key

1 2 analog R in

1 2 analog G in

1 2 analog B in

1 2 fast blank in

Sense Input

Fig. 2­27: Analog back-end

Micronas

measurement buffer

I/O

25

VDP 31xxB
2.11. Synchronization and Deflection The synchronization and deflection processing is distributed over front-end and back-end. The video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front-end. Most of the processing that runs at the horizontal frequency is programmed on the internal Fast Processor (FP). Also the values for vertical and East/ West deflection are calculated by the FP software. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and distributed internally to the rest of the video processing system. The data for the vertical deflection, the sawtooth and the East/West correction signal is calculated in the front end. The data is transferred to the back-end by a single wire interface. The display related synchronization, i.e. generation of horizontal and vertical drive and synchronization of horizontal and vertical drive to the video timing extracted in the front-end, are implemented in hardware in the backend. 2.11.1. Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (see Fig. 2­28). This block contains two phase-locked loops: ­ PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. Phase and frequency are synchronized by the front sync signal. ­ PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. Phase and frequency are synchronized by the oscillator signal of PLL2. The horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse. The generator runs at 1 MHz; in the output

PRELIMINARY DATA SHEET

stage the frequency is divided down to give drive-pulse period and width. In standby mode, the output stage is driven from an internal 1 MHz clock that is derived from the 5 MHz clock signal and a fixed drive pulse width is used. When the circuit is switched out of standby operation, the drive pulse width is programmable. The horizontal drive uses an open drain output transistor. The Main Sync (MSY) signal that is generated from PLL3 is a multiplex of all display-related data (Fig. 2­29). This signal is intended for use by other processors, e.g. a PIP processor can use this signal to adjust to a certain display position. 2.11.2. Horizontal Phase Adjustment This section describes a simple way to align PLL phases and the horizontal frame position. 1. The parameter NEWLIN in the front-end has to be adjusted. The minimum possible value is 34 (recommended for a standard 4:3 signal). 2. With HDRV, the duration of the horizontal drive pulse has to be adjusted. 3. With POFS2, the clamping pulse for the analog RGB input has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 4. With POFS3, the horizontal position of the analog RGB signal (from SCART) has to be adjusted. 5. With HPOS, the digital RGB output signal (from VPC) has to be adjusted to the correct horizontal position. 6. With HBST and HBSO, the start and stop values for the horizontal blanking have to be adjusted. Note: The processing delay of the internal digital video path differs depending on the comb filter option of the VDP 31xxB. The versions with comb filter have an additional delay of 35 clock cycles. Therefore, the timing of the external analog RGB signals has to be adjusted (with POFS2 and POFS3) according to the actual hardware version of the VDP 31xxB. The hardware version can be read out via FP subaddress 0xF1.

26

Micronas

PRELIMINARY DATA SHEET

VDP 31xxB
H flyback

PLL3
MSY main sync generator skew measure­ ment phase comparator & lowpass DCO sinewave DAC & generator LPF 1:64 & output stage H drive

blanking, clamping, etc.

Standby clock

display timing front sync interface phase comparator & lowpass

PLL2
line counter composite sync generator CSY

FSY

DCO

vertical reset

clock & control

V flyback

E/W correction VDATA vertical serial data sawtooth

PWM 15 bit

E/W ouput

PWM 15 bit

V output

Fig. 2­28: Deflection processing block diagram

M1 input analog video M1 M2 M2 (not in scale) timing reference for PICTURE bus ­ chroma multiplex sync ­ active picture data after xxx clocks

line [0] line not not not not not [8] used used used used used V: F

line [7] Parity V Parity

MSY

Vert. blanking 0 = off 1 = on F: Field # 0 = Field 1 1 = Field 2 line: Field line # 1...N

Fig. 2­29: Main sync format

Micronas

27

VDP 31xxB
2.11.3. Vertical and East/West Deflection The calculations of the vertical and East/West deflection waveforms is done by the internal Fast Processor (FP). The algorithm uses a chain of accumulators to generate the required polynomial waveforms. To produce the deflection waveforms, the accumulators are initialized at the beginning of each field. The initialization values must be computed by the TV control processor and are written to the front-end once. The waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. P: a + b(x­0.5) + c(x­0.5)2 + d(x­0.5)3 + e(x­0.5)4 The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East/West deflection are 12-bit values. The vertical waveform can be scaled according the average beam current. This is used to compensate the effects of electric high tension changes due to beam current variations. In order to get a faster vertical retrace timing, the output impedance of the vertical D/A-converter can be reduced by 50% during the retrace. Fig. 2­30 shows several vertical and East/West deflection waveforms. The polynomial coefficients are also stated.

PRELIMINARY DATA SHEET

2.11.4. Protection Circuitry ­ Picture tube and drive stage protection is provided through the following measures: ­ Vertical flyback protection input: this pin searches for a negative edge in every field, otherwise the RGB drive signals are blanked. ­ Drive shutoff during flyback: this feature can be selected by software. ­ Safety input pin: this input has two thresholds. Between zero and the lower threshold, normal functioning takes place. Between the lower and the higher threshold, the RGB signals are blanked. Above the higher threshold, the RGB signals are blanked and the horizontal drive is shut off. Both thresholds have a small hysteresis. ­ The main oscillator and the horizontal drive circuitry are run from a separate (standby) power supply and are already active while the TV set is powering up.

Vertical:

a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1

East/West:

a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1

Fig. 2­30: Vertical and East/West deflection waveforms

28

Micronas

PRELIMINARY DATA SHEET

VDP 31xxB
In the standby mode the following functions are still available (see also 2.11.1.): ­ 20.25 MHz crystal oscillator ­ 5 MHz clock output (CLK5) ­ horizontal drive output (HOUT) The clock source for the horizontal output generator is switched to the standby clock which is derived from the 5 MHz clock. The duty cycle of HOUT is set to 50%. Protection modes with safety and horizontal flyback pins are not available. The VDP 31xxB has clock and voltage supervision circuits to generate a stable HOUT signal during power-on and standby. The HOUT signal is disabled until a proper CLK5 signal (5 MHz clock) is detected. When released, the HOUT generator runs with the standby clock. Coupling the HOUT generator to the deflection PLL has to be done by CCU using the EHPLL bit. Fig. 2­32 shows the signals during power-on and standby.

2.12. Reset Function Reset of most VDP 31xxB functions is performed by the RESET pin. When this pin becomes active, all internal registers and counters are lost. When the RESET pin is released, the internal reset is still active for 4 µs. After that time, the initialization of all required registers is performed by the internal Fast Processor. During this initialization procedure (see Fig. 2­31) it is not possible to access the VDP 31xxB via the serial interface (I2C). Access to other ICs via the serial bus is possible during that time. The 5 MHz clock divider and the 1 MHz standby clock divider are not affected by reset. The clock source for the horizontal output generator is switched to the standby clock during reset.

Reset Internal Reset Initialization

4µs

approx. 60µs

VSTBY XTAL 1 µs CLK5

Fig. 2­31: External Reset

2.13. Standby and Power-On In standby mode the whole signal processing of the VDP 31xxB is disabled and only some basic functions are working. The standby mode is realized by switching off the supplies for analog front-end (VSUPF), analog backend (VSUPO) and digital circuitry (VSUPD). The standby supply (VSTBY) still has its nominal voltage. To disable all the analog and digital functions, it is necessary to bring the analog and digital supplies below 0.5 V. Only this guarantees that all the normal functions are disabled and the standby current for analog and digital supply is at its minimum. When switched off, the negative slope of the supply voltage VSUPD should not be larger than approximately 0.2 V/µs (see Recommended Operating Conditions). In the standby mode, all registers and counter values in the VDP 31xxB are lost, they will be re-initialized via the internal Fast Processor after analog and digital supplies are switched on again and the RESET pin is released.

Clock Release HOUT standby mode

VSUPD RESET

Fig. 2­32: Power-On, Standby On/Off

Switching the HOUT signal into standby mode can be done by the CCU via the EHPLL bit or by the internal voltage supervision. The voltage supervision activates a power-down signal when the supply for the digital circuits (VSUPD) goes below X4.5 V for more than 50ns. This power down signal is extended by 50µs after VSUPD is back again. The power-down signal switches the clock source for the HOUT generation to the standby clock and sets the duty cycle to 50%. This is exactly what the EHPLL bit does. As the clocks from the deflection PLL and the standby clock are not in phase, the actual phase (High/Low) of the HOUT signal may be up to one PLL or standby clock (X1 µs) longer than a regular one when the clock source is changed. 29

Micronas

VDP 31xxB
3. Serial Interface 3.1. I2C-Bus Interface Communication between the VDP and the external controller is done via I2C-bus. The VDP has two I2C-bus slave interfaces (for compatibility with VPC/DDP applications) ­ one in the front-end and one in the backend. Both I2C-bus interfaces use I2C clock synchronization to slow down the interface if required. Both I2C-bus interfaces use one level of subaddress: the I2C-bus chip address is used to address the IC and a subaddress selects one of the internal registers. The I2C-bus chip addresses are given below:

PRELIMINARY DATA SHEET

3.2. Control and Status Registers Table 3­1 gives definitions of the VDP control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be `don't care' on write operations and `0' on read operations. Write registers that can be read back are indicated in Table 3­1. Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 3­3. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3­1. The register modes given in Table 3­1 are ­ w: ­ w/r: ­ r: ­ v: ­ h: write only register write/read data register read data from VDP register is latched with vertical sync register is latched with horizontal sync

Chip Address front-end back-end

A6

A5

A4

A3

A2

A1

A0

R/W

1 1

0 0

0 0

0 0

1 1

1 0

1 1

1/0 1/0

The registers of the VDP have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Figure 3­1 shows I2C-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set.

The mnemonics used in the Micronas VDP demo software are given in the last column.

S

1000 111

W

Ack

0111 1100

Ack

1 or 2 byte Data

Ack

P

I2C write access subaddress 7c
high byte Data low byte Data Ack Nak P

S

1000 111

W

Ack

0111 1100

Ack

S

1000 111

R

Ack

I2C read access subaddress 7c

SDA

S
SCL

1 0

P

W R Ack Nak S P

= = = = = =

0 1 0 1 Start Stop

Fig. 3­1: I2C-bus protocols 30 Micronas

PRELIMINARY DATA SHEET

VDP 31xxB

Table 3­1: I2C control and status registers of front-end
I2C Sub address Number of bits Mode Function Default Name

FP INTERFACE h'35 8 r FP status bit [0] bit [1] bit [2] bit[8:0] bit[11:9] bit[8:0] bit[11:9] bit[11:0] FPSTA write request read request busy 9-bit FP read address reserved, set to zero 9-bit FP write address reserved, set to zero FP data register, reading/writing to this register will autoincrement the FP read/ write address. Only 16 bit of data are transferred per I2C telegram. FPRD FPWR FPDAT

h'36 h'37 h'38

16 16 16

w w w/r

BLACK LINE DETECTOR h'12 16 w/r read only register, do not write to this register! after reading, LOWLIN and UPLIN are reset to 127 to start a new measurement bit[6:0] number of lower bl