Text preview for : CDC621H-IC.pdf part of Sharp CD-C621H Service Manual Audio Stereo - Tot. 17 File - Part. 1/2
Back to : audio_hi-fi_©_.part1.rar | Home
CD-C621H
FUNCTION TABLE OF IC
IC1 VHiLA9241M/-1: Servo Amp. (LA9241M) (1/2)
Pin No. 1 2 3 4 5 6 7 8 9 10 11* 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48* 49 50 Port Name FIN2 FIN1 E F TB TETE TESI SCI TH TA TDTD JP TO FD FDFA FAFE FEAGND NC SPI SPG SPSPD SLEQ SLD SLSL+ JPJP+ TGL TOFF TES HFL SLOF CVCV+ RFSM RFSSLC SLI DGND FSC TBC NC DEF CLK Function Connection pin for photodiode of pickup. RF signal is generated through addition with FIN pin, and FE signal is generated through subtraction. Connection pin for photodiode of pickup. Connection pin for photodiode of pickup. TE signal is generated through subtraction with F pin. Connection pin for photodiode of pickup. Pin for input of DC component of TE signal. Pin to connect gain setting resistor of TE signal to TE signal. TE signal output pin. TES (Track error sense) comparator input pin. TE signal is band-passed and input. Input pin for shock detection. Pin to set time constant of tracking gain. TA amplifier output pin. Pin to compose tracking phase compensation constant between TD and VR pins. Pin to set tracking phase compensation. Pin to set amplitude of tracking jump signal (kick pulse). Tracking control signal output pin. Focusing control signal output pin. Pin to compose focusing phase compensation constant between FD and FA pins. Pin to compose focusing phase compensation constant between FD-/FA-pins. Pin to compose focusing phase compensation constant between FA and FE pins. Output pin of FE signal. Pin to connect gain setting resistor of FE signal across TE pin. GND for analog signal. No connect. Spindle amplifier input. Pin to connect gain setting resistor in the 12cm mode of spindle. Pin to connect spindle phase compensation constant together with SPD pin. Spindle control signal output pin. Pin to connect thread phase compensation constant. Thread control signal output pin. Input pin of thread feed signal from micro computer. Input pin of thread feed signal from micro computer. Input pin of tracking jump signal from DSP. Input pin of tracking jump signal from DSP. Input pin of tracking gain control signal from DSP. TGL = Gain low at "H" Input pin of tracking off control signal from DSP. TOFF = Off at "H" Output pin of TES signal to DSP. (HIGH FREQUENCY LEVEL) is used to judge whether main beam is positioned on the bit or on the mirror. Thread servo off control input pin. Pin to input CLV error signal from DSP. Pin to input CLV error signal from DSP. RF output pin. Pin to set gain of RF and set 3T compensation constant together with RFSM pin. (SLICE LEVEL CONTROL) is the output pin to control of the level of the data slice with RF waveform DSP. Input pin to control the level of data slice with DSP. GND pin in the digital system. Output pin for focus search smoothening capacitor. (Tracking Balance Control) Pin to set EF balance variable range. No connect. Defect detection output pin of disk. Reference clock input pin. 4.23MHz of DSP is input.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside. 43
CD-C621H
IC1 VHiLA9241M/-1:Servo Amp.(LA9241M) (2/2)
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Port Name CL DAT CE DRF FSS VCC2 REFI VR LF2 PH1 BH1 LDD LDS VCC1
VCC1 64
Function Micro computer command clock input pin. Micro computer command data input pin. Micro computer command chip enable input pin. (DETECT RF) RF level detection output. (Focus Serch Select) Pin to switch focus search mode. (± search/+ search for reference voltage) VCC pin for servo system and digital system. Pin to connect pass control for reference voltage. Reference voltage output pin. Pin to set defect detection time constant of disk. Pin to connect capacitor for peak hold of RF signal. Pin to connect capacitor for bottom hold of RF signal. APC circuit output pin. APC circuit output pin. RF system VCC pin.
LDS 63 LDD 62 BH1 61 PH1 60 LP2 59 VR 58 REFI 57 VCC2 56 FSS DRF CE DAT CL CLK 55 54 53 52 51 50 DEF 49
APC
FIN2 1
RF DET
REF
48 NC
FIN1
2
47 TBC
I/V
E 3
VCA
46 FSC
F
4
BAL
VCA
µ-COM INTER FACE
SLC
45 DGND
44 SLI
TB
5
43 SLC
42 RFSTETE 6 7
TE
41 RFSM
TESI SCI
8 9
RF AMP
40 CV+
T.SERVO & T.LOGIC
TH 10
39 CV38 SLOF 37 HFL 36 TES
TA 11
35 TOFF 34 TGL
TD- 12
F.SERVO & F.LOGIC
TD 13 JP 14
SPINDLE SERVO
SLED SERVO
33 JP+
TO 15
FD 16 17 FD18 FA 19 FA20 FE 21 22 23 NC FE- AGND SP 24 SPI 25 SPG 26 SP27 SPD 28 SLEQ 29 SLD 30 31 SL- SL+ 32 JP-
Figure 44 BLOCK DIAGRAM OF IC 44
CD-C621H
IC2 VHiLC78622N-1: Servo/Signal Control (LC78622NE) (1/2)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21* 22* Terminal Name Input/Output DEFI TAI PDO VVSS ISET VVDD FR VSS EFMO EFMIN TEST2 CLV+ CLVV/P HLF TES TOFF TGL JP+ JPPCK FSEQ Input Input Output -- Input -- Input -- Output Input Input Outout Output Output Intput Input Output Output Output Output Output Output Function Defect detection signal (DFF) input terminal. (When this terminal is not used, connect it to 0V.) For PLL Input terminal for test. Pull-down resistor built in. Be sure to connect this terminal to 0V. Phase comparison output terminal for external VCO control. Grounding terminal for built-in VCO. Be sure to connect this terminal to 0V. Resistor connection terminal for adjustment of PDO output current. Power terminal for built-in VCO. For VCO frequency range adjustment. Digital system grounding terminal. Be sure to connect this terminal to 0V. For slice level control EFM signal output terminal. EFM signal input terminal. Input terminal for test. Pull-down resistor built-in. Be sure to connect this terminal to 0V. Output for disc motor control. 3-value output is enabled according to command. Output for disc motor control. 3-value output is enabled according to command. Rough servo/phase control automatic selection monitor output terminal. "H": Rough servo, "L": Phase servo Track detection signal input terminal. Schmidt input. Tracking error signal input terminal. Schmidt input. Tracking OFF output terminal. Output terminal for tracking gain selection. "L": Gain raising. Output for track jump control. 3-value output is enabled according to command. Output for track jump control. 3-value output is enabled according to command. Clock monitor terminal for EFM data play-back. Phase lock: 4.3218 MHz. Sync signal detection output terminal. When the sync signal detected from the EFM signal coincides with the internally generated sync signal: "H" Digital system power terminal. Control with serial data command from microcomputer. When this terminal is not used, set it as an input terminal and connect to 0V or set it as an output terminal and open.
23 24 25 26 27 28* 29* 30* 31* 32* 33 34
VDD CONT1 CONT2 CONT3 CONT4 CONT5 EMPH/CONT6 C2F DOUT TEST3 TEST4 PCCL
--
Input/Output General-use input/output terminal 1. Input/Output General-use input/output terminal 2. Input/Output General-use input/output terminal 3. Input/Output General-use input/output terminal 4. Input/Output General-use input/output terminal 5. Output Output Output Input Input Input
Deemphasis monitor terminal. "H": Deemphasis disc play-back. General-use output terminal 6. C2 flag output terminal. Digital OUT output terminal. (EIAJ format) Input terminal for test. Pull-down resistor built-in. Be sure to connect this terminal to 0V. Input terminal for test. Pull-down resistor built-in. Be sure to connect this terminal to 0V. General-use input/output command recognition terminal. Pull-down resistor built in. When this terminal is used for the same function as that of LC78622E, open or connect this terminal to 0V. H: Only the general-use input/output port command is controllable. L: All command controls are enabled. L channel 1-bit DAC Mute output terminal for L channel. General-use output terminal 7. Power terminal for L channel. L channel output terminal. Grounding terminal for L channel. Be sure to connect this terminal to 0V. R channel 1-bit DAC Grounding terminal for R channel. Be sure to connect this terminal to 0V. R channel output terminal. Power terminal for R channel. Mute output terminal for R channel. General-use output terminal 8. Power terminal for crystal oscillation. 16.9344 MHz crystal oscillator connection terminal. 16.9344 MHz crystal oscillator connection terminal. Grounding terminal for crystal oscillation. Be sure to connect this terminal to 0V.
35* 36 37 38 39 40 41 42* 43 44 45 46
MUTEL/CONT7 LVDD LCHO LVSS RVSS RCHO RVDD MUTER/CONT8 XVDD XOUT XIN XVSS
Output -- Output -- -- Output -- Output -- Output Input --
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside. 45
CD-C621H
IC2 VHiLC78622N-1: Servo/Signal Control (LC78622NE) (2/2)
Pin No. 47* 48* 49* 50* 51 52* 53 54 55 56 57 58 59* 60* 61 62 63 64 Terminal Name Input/Output SBSY EFLG PW SFSY SBCK FSX WRQ RWC SQOUT COIN CQCK RES TEST11 16M 4.2M TEST5 CS TEST1 Output Output Output Output Input Output Output Input Output Input Input Input Output Output Output Input Input Input Sub-code clock sync signal output terminal. C1, C2, single, double correction monitor terminal. Sub-code P, Q, R, S, T, U, and W output terminal. Sub-code frame sync signal output terminal. Falling occurs when the sub-code is in standby state. Sub-code read clock input terminal. Schmidt input (When this terminal is not used, connect it to 0V.) 7.35 kHz sync signal (frequency-divided from crystal oscillation) output terminal. Sub-code Q output standby output terminal. Read/Write control input terminal. Schmidt input. Sub-code Q output terminal. Command input terminal from microcomputer. Command input taking-in clock or sub-code taking-out (from SQOUT) clock input terminal. Schmidt input LSI resetting input terminal. When power is turned on, once "L" is set. Output terminal for test. Use this terminal in open state (usually "L" output). 16.9344 MHz output terminal. 4.2336 MHz output terminal. Input terminal for test. Pull-down resistor built-in. Be sure to connect this terminal to 0V. Chip selection input terminal. Pull-down resistor built-in. In noncontrol state connect this terminal to 0V. Input terminal for test. Pull-down resistor is not provided. Be sure to connect this terminal to 0V. Function
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD). In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
TAI TST11 TEST1 TEST2 TEST3 TEST4 TEST5
EFMO
I SET
VVDD VVss
PDO
PCK
VDD
DEFI EFMIN
Vss
RAM address generator Interpolation mute Bilingual Digital OUT
FR
Slice level control
VCO colck oscillation clock control
2K x 8bit RAM
FSEQ
Sync detection EFM demodulation
C2F DOUT
CLV+ CLVV/P PW SBCK SBSY SFSY CS WRQ SQOUT CQCK COIN RWC
CLV Digital servo
Flag processing of C1/C2 error detection and correction
Digital attenuator
Subcode division QCRC
X4 oversampling digital filter
µCOM Interface
1bitDAC
Servo commander
General-use port
XTAL system timing generator
L.P.F
RVss RVDD MUTER/CONT7
Figure 46 BLOCK DIAGRAM OF IC 46
MUTEL/CONT8 LVss LVDD
EMPH/CONT6
HFL TES TOFF
TGL PCCL CONT1 CONT2 CONT3 CONT4 CONT5
16M 4.2M XVss FSX XIN XOUT XVDD
EFLG
RCHO
LCHO
JPJP+ RES
CD-C621H
IC3 VHiM63001FP-1: Focus/Tracking/Spin/Slide Driver (M63001FP)
Pin No. 1 2 3 4 5 6 7 8-14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29-35 36 37 38 39 40 41 42 Terminal Name IN2IN1AIN1BOUT1OUT1+ OUT2OUT2+ GND OUT3+ OUT3IN3VCC1 STANDBY VRFE MUTE IN5IN5+ VCC2 IN4OUT4OUT4+ VCC3 GND OUT5+ OUT5OUT6+ OUT6VCC4 IN6IN6+ Function CH2 inverted input. CH1 inverted input. CH1 output offset control. CH1 inverted output. CH1 non-inverted output. CH2 inverted output. CH2 non-inverted output. GND CH3 non-inverted output. CH3 inverted output. CH3 inverted input. Power supply 1 (CH1, CH2, CH3) STANDBY signal input. CH1-CH4 Reference voltage input. Mute signal input (CH6). CH5 inverted input. CH5 non-inverted input. Power supply 2 (CH4). CH4 inverted input. CH4 inverted output. CH4 non-inverted output. Power supply 3 (CH5). GND CH5 non-inverted output. CH5 inverted output. CH6 non-inverted output. CH6 inverted output. Power supply 4 (CH6). CH6 inverted input. CH6 non-inverted input.
IN2 IN1A IN1B OUT1 OUT1+ OUT2 OUT2+ 1 2 3 4 5 6 7 8 42 41 40 39 38 37 36 35 IN6+ IN6 VCC4 OUT6 OUT6+ OUT5 OUT5+
M63001FP
9 10 GND 11 12 13 14 OUT3+ OUT3 IN3 VCC1 STANDBY VTEF MUTE 15 16 17 18 19 20 21
34 33 32 31 30 29 28 27 26 25 24 23 22 VCC3 OUT4+ OUT4 IN4 VCC2 IN5+ IN5 GND
IC562,563 VHiKiA4558P-1: Ope Amp. (KIA4558P)
OUT A IN A +IN A VEE
1 2 3 4 A + + B
8 7 6 5
VCC OUT E IN B +IN B
IC601 VHiM62439SP-1: Audio Processor (M62439SP)
REC OUT1 1 INA1 2 INB1 3 INC1 4 IND1 5 TONE1 6 TONEL1 7 OUT1 8 GND 9 Vcc 10 20 REC OUT2 19 INA2 18 INB2 17 INC2 16 IND2 15 TONE2 14 TONEL2 13 OUT2 12 Vss 11 CONT
Figure 47 BLOCK DIAGRAM OF IC 47
CD-C621H
IC701 RH-iX0281AWZZ:System Microcomputer (IX0281AW) (1/2)
Pin No. 1 2* 3 4 5 6 7,8* 9 10 11 12 13 14* 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31-33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Port Name VDD P37 P36 P35 P34 P33 P32, P31 P30 RESET X2 X1 Vpp XT2 P04 VDD P27 P26 P25 P24 P23 P22 P21 P20 AVss ANI7 ANI6 ANI5 ANI4 ANI3 ANI2-ANI0 AVDD AVREF P03 P02 INTP1 INTP0 Vss P74 P73 P72 P71 P70 VDD P127 P126 P125 P124 P123 P122 P121 P120 P117 Terminal Name VDD ENA DO DI CE CLK LCK1, LCK2 RWC RESET X2 X1 VPP XT2 WRQ VDD PCCL COIN SQOUT CQCK DSP RES FRF (DRF) SLD+ SLDAVSS SPEANA3 SPEANA2 SPEANA1 TUN SM T2 RUN KEYIN3-KEYIN1 AVDD AVREF PUIN SW O/C SW SYS STOP REMOCON VSS DNO SW U/D SW TIMER LED T_SOL T_MOT VDD CAM SW TIFAS FPA H/P AC RLY_CONT REC/PLAY T_BIAS T_T1T2 DISTO Input/Output -- Output Input Output Output Output Output Output Input Output Input -- -- Input -- Output Outout Input Output Output Input Output Output -- Input Input Input Input Input Input -- -- Input Input Input Input -- Input Input Output Output Output -- Input Input Input Input Output Output Output Output Input CD DSP READ WRITE CONTROL RESET MAIN CLOCK MAIN CLOCK POWER SUPPLY TERMINAL OPEN CD DSP WRITE REQUEST (+) POWER SUPPLY CD DSP PCCL CD DSP COMAND CD DSP CODE Q OUT CD DSP CLOCK CD DSP RESET CD RF LEVEL DETECTION CD SLIDE MOTOR + CD SLIDE MOTOR ANALOG GROUND SPEANA DATA INPUT 16 KHz SPEANA DATA INPUT 1 KHz SPEANA DATA INPUT 63 Hz TUNER SIGNAL METER INPUT TAPE2 RUN PULSE INPUT KEY INPUT ANALOG VDD ANALOG REF VOLTAGE CD PUIN SWITCH CD OPEN/CLOSE SWITCH SYSTEM STOP INPUT REMOCON INPUT GROUND VOLTAGE CD DISC NO. SWITCH CD UP/DOWN SWITCH TIMER LED CONTROL TAPE SOLENOID CONTROL TAPE MOTOR CONTROL (+) POWER SUPPLY TAPE CAM SWITCH TAPE1 FULL AUTOSTOP PULSE INPUT TAPE2 A-SIDE FULL PROOF HEADPHONE INPUT AC RELAY CONTROL TAPE REC/PLAY CHANGE TAPE Record bias control TAPE T1/T2 CHANGE DISTINATION INPUT (+) POWER SUPPLY DOLBY PROLOGIC ENABLE TERMINAL DATA INPUT DATA OUTPUT CE OUTPUT CLOCK OUTPUT Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside. 48
CD-C621H
IC701 RH-iX0281AWZZ:System Microcomputer (IX0281AW) (2/2)
Pin No. 56 57 58 59* 60* 61 62* 63 64 65 66* 67 68 69 70 71-78 79 80-100 Port Name P116 P115 P114 P113 P112 P111 P110 P107 P106 P105 P104 P103/FIP32 P102/FIP31 P101/FIP30 P100/FIP29 Terminal Name KEY JOG A KEY JOG B S MUTE C MUTE SR MUTE HI-CUT POWER SPRLY SP_DET SPN_P DISTOUT DIAS4/P22 DIAS3/P21 DIAS2/P20/P15 DIAS1/P19/P16 Input/Output Input Input Output Output Output Output Output Output Input Input Output Input/Output Input/Output Input/Output Input/Output Output -- Output KEY JOG INPUT A KEY JOG INPUT B SYSTEM MUTE CENTER MUTE SURROUND MUTE HI-CUT OUTPUT POWER OUTPUT SPEAKER OUTPUT RELAY CONTROL SPEAKER OUTPUT DETECTION TUNER SPAN CHANGE DISTINATION OUTPUT FL DISPLAY SEGMENT DRIVER DISTINATION INPUT FL DISPLAY SEGMENT DRIVER DISTINATION INPUT FL DISPLAY SEGMENT DRIVER DISTINATION INPUT FL DISPLAY SEGMENT DRIVER DISTINATION INPUT FL DISPLAY SEGMENT DRIVER FL DRIVER () POWER SUPP, 30V FL DISPLAY SEGMENT DRIVER Function
FIP28-FIP21 P18/P13-P11/P7 VLOAD FIP20-FIP0 VLOAD P10/P6-G1/9G
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
49