11.3 Accessory ......................................... 271
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1. INTRODUCTION
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company's employees, agents, subcontractors, or person working on your
company's behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it. The manufacturer will not
be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the phones or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing the
user to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on the phones must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
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1. INTRODUCTION
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation
A phone may interfere with sensitive laboratory equipment, medical equipment, etc.
Interference from unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:
· Service personnel should ground themselves by using a wrist strap when exchange system boards.
· When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.
· Use a suitable, grounded soldering iron.
· Keep sensitive parts in these protective packages until these are used.
· When returning system boards or parts like EEPROM to the factory, use the protective package as
described.
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1. INTRODUCTION
1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current Constant Voltage
CLA Cigar Lighter Adapter
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milliwatt
DSP Digital Signal Processing
DTC DeskTop Charger
EEPROM Electrical Erasable Programmable Read-Only Memory
EL Electroluminescence
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GPRS General Packet Radio Service
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
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1. INTRODUCTION
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
UMTS Universal Mobile Telephony System
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2. PERFORMANCE
2. PERFORMANCE
2.1 System Overview
Item Specification
Shape GSM900/1 800 & WCDMA Folder- Dual Mode Handset
Size 49.5 x 95.7 x 22.5 mm
Weight 120g (with Battery)
Power 4.0V > 1200mAh Li-Ion
Over 140 Min (WCDMA, Tx=12 dBm, Voice)
Talk Time
Over 180 Min (GSM, Tx=Max, Voice)
Over 120 hrs (WCDMA, DRX=1.28)
Standby Time
Over 1 50 hrs (GSM, Paging period=9)
Antenna Fixed Type (Fixed Screw)
LCD 176 x 220 Pixel
Main LCD BL White LED Back Light
Sub LCD BL 7-color LED
Vibrator Yes (Coin Type)
LED Indicator 7-color(Sub LCD BL)
C-MIC Yes
Receiver Yes
Earphone Jack Yes
SIM Socket Yes (3.0V/1.8V)
Volume Key Push Type(+,-)
Voice Key Push Type (Memo)
I/O Connect 24 Pin
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2. PERFORMANCE
2.2 Usable environment
1) Environment
Item Spec. Unit
Voltage 4.0 (Typ), 3.4 (Min), (Shut Down: 3.2) V
Size -20 ~ + 60 °C
Storage -30 ~ + 85 °C
Humidity max. 85 %
2) Environment(Accessory)
Item Spec. Min Typ. Max Unit
Power Available power 100 220 240 Vac
* CLA: 12~24V(DC)
2.3 Radio Performance
1) Transmitter -GSM Mode
No Item GSM DCS
9k ~ 1GHz -39dBm
100k ~ 1GHz -39dBm
MS allocated 1G ~ 1710MHz -33dBm
Channel 1710M ~ 1785MHz -39dBm
1G ~ 12.75GHz -33dBm
Conducted 1785M ~ 12.75GHz -33dBm
1 Spurious 100k ~ 880MHz -60dBm 100k ~ 880MHz -60dBm
Emission 880M ~ 915MHz -62dBm 880M ~ 915MHz -62dBm
915M ~ 1000Mz -60dBm 915M ~ 1000MHz -60dBm
Idle Mode
1G ~ 1.71GHz -50dBm 1G ~ 1.71GHz -50dBm
1.71G ~ 1.785GHz -56dBm 1.71G ~ 1.785GHz -56dBm
1.785G ~ 12.75GHz -50dBm 1.785G ~ 12.75GHz -50dBm
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2. PERFORMANCE
No Item GSM DCS
30M ~ 1GHz -36dBm
30M ~ 1GHz -36dBm
MS allocated 1G ~ 1710MHz -30dBm
Channel 1710M ~ 1785MHz -36dBm
1G ~ 4GHz -30dBm
Radiated 1785M ~ 4GHz -30dBm
1 Spurious 30M ~ 880MHz -57dBm 30M ~ 880MHz -57dBm
Emission 880M ~ 915MHz -59dBm 880M ~ 915MHz -59dBm
915M ~ 1000Mz -57dBm 915M ~ 1000MHz -57dBm
Idle Mode
1G ~ 1.71GHz -47dBm 1G ~ 1.71GHz -47dBm
1.71G ~ 1.785GHz -53dBm 1.71G ~ 1.785GHz -53dBm
1.785G ~ 4GHz -47dBm 1.785G ~ 4GHz -47dBm
2 Frequency Error ±0.1ppm ±0.1ppm
±5(RMS) ±5(RMS)
3 Phase Error
±20(PEAK) ±20(PEAK)
3dB below reference sensitivity 3dB below reference sensitivity
Frequency Error Under RA250: ±200Hz RA250: ±250Hz
4 Multipath and Interference HT100: ±100Hz HT100: ±250Hz
Condition TU50: ±100Hz TU50: ±150Hz
TU3: ±150Hz TU1.5: ±200Hz
0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB
200kHz -30dB 200kHz -30dB
250kHz -33dB 250kHz -31dB
Due to 400kHz -60dB 400kHz -33dB
modulation 600 ~ 1800kHz -66dB 600 ~ 1800kHz -60dB
Output RF
5 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -60dB
Spectrum
3000 ~ 6000kHz -71dB 6000kHz -73dB
6000kHz -77dB
400kHz -19dB 400kHz -22dB
Due to
600kHz -21dB 600kHz -24dB
Switching
1200kHz -21dB 1200kHz -24dB
transient
1800kHz -24dB 1800kHz -27dB
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2. PERFORMANCE
No Item GSM DCS
Frequency offset 800kHz
Intermodulation product should
7 Intermodulation attenuation
be Less than 55dB below the
level of Wanted signal
Power control Power Tolerance Power control Power Tolerance
Level (dBm) (dB) Level (dBm) (dB)
5 33 ±3 0 30 ±3
6 31 ±3 1 28 ±3
7 29 ±3 2 26 ±3
8 27 ±3 3 24 ±3
9 25 ±3 4 22 ±3
10 23 ±3 5 20 ±3
8 Transmitter Output Power 11 21 ±3 6 18 ±3
12 19 ±3 7 16 ±3
13 17 ±3 8 14 ±3
14 15 ±3 9 12 ±4
15 13 ±3 10 10 ±4
16 11 ±5 11 8 ±4
17 9 ±5 12 6 ±4
18 7 ±5 13 4 ±4
19 5 ±5 14 2 ±5
15 0 ±5
9 Burst timing Mask IN Mask IN
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2. PERFORMANCE
2) Transmitter-WCDMA Mode
No Item Specification
Class3: +24dBm(+1/-3dB)
1 Maximum Output Power
Class4: +21dBm(±2dB)
2 Frequency Error ±0.1ppm
3 Open Loop Power control in uplink ±9dB@normal, ±12dB@extreme
Adjust output(TPC command)
cmd 1dB 2dB 3dB
+1 +0.5/1.5 +1/3 +1.5/4.5
4 Inner Loop Power control in uplink 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5
-1 -0.5/-1.5 -1/-3 -1.5/-4.5
group(10equal command group)
+1 +8/+12 +16/+24
5 Minimum Output Power -50dBm(3.84MHz)
Qin/Qout:DPCCH quality levels
6 Out-of-synchronization handling of output power Toff@DPCCH/lor:-22->-28dB
Ton@DPCCH/lor:-24->-18dB
7 Transmit OFF Power -56dBm(3.84M)
±25us
8 Transmit ON/OFF Time Mask
PRACH, CPCH, uplink compressed mode
±25us
power varies according to the data rate
9 Change of TFC
DTX: DPCH off
(minimize interference between UE)
10 Power setting in uplink compressed ±3dB(after 14slots transmission gap)
11 Occupied Bandwidth(OBW) 5MHz(99%)
-35-15*(f-2.5)dBc@f=2.5~3.5MHz, 30k
-35-1*(f-3.5)dBc@f=3.5~7.5MHz, 1M
12 Spectrum emission Mask
-39-10*(f-7.5)dBc@f=7.5~8.5MHz, 1M
-49 dBc@f=8.5~12.5MHz, 1M
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2. PERFORMANCE
No Item Specification
33dB@5MHz, ACP>-50dBm
13 Adjacent Channel Leakage Ratio(ACLR)
43dB@10MHz, ACP>-50dBm
-36dBm@f=9~150KHz, 1k BW
-36dBm@f=150KHz~30MHz, 10k
-36dBm@f=30~1000MHz, 100k
Spurious Emissions -30dBm@f=1~12.75GHz, 1M
14
*: additional requirement -41dBm*@1893.5~1919.6MHz, 300k
-67dBm*@925~935MHz, 100k
-79dBm*@935~960MHz, 100k
-71dBm*@1805~1880MHz, 100k
-31dBc@5MHz, Interferer -40dBc
15 Transmit Intermodulation
-41dBc@10MHz, Interferer -40dBc
17.5% (>-20dBm)
16 Error Vector Magnitude(EVM)
(@12.2k, 1DPDCH+1DPCCH)
-15dB@SF=4, 768kbps, multi-code
17 Transmit OFF Power
transmission
3)Receiver - GSM Mode
No Item GSM DCS
1 Sensitivity (TCH/FS Class II) -105dBm -105dBm
Co-Channel Rejection
2 C/Ic=7dB C/Ic=7dB
(TCH/FS Class II, RBER, TUhigh/FH)
3 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB
Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB
Wanted Signal: -98dBm Wanted Signal: -96dBm
4 Intermodulation Rejection 1'st interferer: -44dBm 1'st interferer: -44dBm
2'st interferer: -45dBm 2'st interferer: -44dBm
Blocking Response Wanted Signal: -101dBm Wanted Signal: -101dBm
5
(TCH/FS Class II, RBER) Unwanted Signal: Depend on freq. Unwanted Signal: Depend on freq.
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2. PERFORMANCE
4) Receiver - WCDMA Mode
No Item Specification
18 Reference Sensivitivity Level -106.7dBm(3.84M)
-25dBm(3.84MHz)
19 Maximum Input Level -44dBm/3.84MHz(DPCH_Ec)
UE@+20dBm output power(class3)
33dB
20 Adjacent Channel Selectivity(ACS)
UE@+20dBm output power(class3)
-56dBm/3.84MHz@10MHz
21 In-band Blocking UE@+20dBm output power(class3)
-44dBm/3.84MHz@15MHz
UE@+20dBm output power(class3)
-44dBm/3.84MHz@f=2050~2095 &
2185~2230MHz, band a)
UE@+20dBm output power(class3)
-30dBm/3.84MHz@f=2025~2050 &
22 Out-band Blocking 2230~2255MHz, band a)
UE@+20dBm output power(class3)
-15dBm/3.84MHz@f=1~2025 &
2255~12500MHz, band a)
UE@+20dBm output power(class3)
-44dBm CW
23 Spurious Response
UE@+20dBm output power(class3)
-46dBm CW@10MHz &
24 Intermodulation Characteristic -46dBm/3.84MHz@20MHz
UE@+20dBm output power(class3)
-57dBm@f=9KHz~1GHz, 100k BW
25 Spurious Emissions -47dBm@f=1~12.75GHz, 1M
-60dBm@f=1920~1980MHz, 3.84MHz
-60dBm@f=2110~2170MHz, 3.84MHz
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2. PERFORMANCE
2.4 Current Consumption
(VT test : Speaker off, LCD backlight On)
Stand by Voice Call VT
WCDMA 120Hours=10mA 140Min=514mA 100Min=720mA
(DRX=1.28) (Tx=12dBm) (Tx=12dBm)
GSM 150Hours=8mA 180Min=400mA
(paging=9period) (Tx=Max)
2.5 RSSI
TBD
GSM WCDMA(TBD)
BAR 4 3 -91 ±2dBm
BAR 3 2 -96 ±2dBm
BAR 2 1 -101 ±2dBm
BAR 1 0 -106 ±2dBm
2.6 Battery Bar
Indication Voltage
BAR 4 3 (68%) 3.87 ±0.03V
BAR 3 2 (47%) 3.77 ±0.03V
BAR 2 1 (26%) 3.72 ±0.03V
BAR 1 Icon Blinking (5%) 3.50 ±0.03V
3.50 ±0.03V(Talk: 1min. interval) -5%
Low voltage, warning message
3.46 ±0.03V(Standby: 3min. Inverval) -3%
3.10 ±0.03V (WCDMA Talk)
Power OFF
3.20 ±0.03V (else)
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2. PERFORMANCE
2.7 Sound Pressure Level
No Test Item Specification
NOM
1 Sending Loudness Rating (SLR) 8±3dB
MAX
NOM -1±3dB
2 Receiving Loudness Rating (RLR)
MAX -13±1dB
NOM
3 Side Tone Masking Rating (STMR) 17dB over
MAX
NOM
4 Echo Loss (EL) MS 40dB over
MAX
5 Sending Distortion (SD) refer to TABLE 30.3
6 Receiving Distortion (RD) refer to TABLE 30.4
NOM
7 Idle Noise-Sending (INS) -64dBm0p under
MAX
NOM -47dBPA under
8 Idle Noise-Receiving (INR)
MAX -36dBPA under
A NOM
9 Sending Loudness Rating (SLR) 8±3dB
C MAX
O NOM -1±3dB
10 Receiving Loudness Rating (RLR)
U MAX -12±3dB
S NOM
11 Side Tone Masking Rating (STMR) 25dB over
T MAX
I HEAD NOM
12 Echo Loss (EL) 40dB over
C SET MAX
13 Sending Distortion (SD) refer to TABLE 30.3
14 Receiving Distortion (RD) refer to TABLE 30.4
NOM
15 Idle Noise-Sending (INS) -55dBm0p under
MAX
NOM -45dBPA under
16 Idle Noise-Receiving (INR)
MAX -40dBPA under
TDMA NOISE SEND
GSM
.GSM: Power Level: 5 REV.
MS
DCS: Power Level: 0 SEND
DCS
(Cell Power: -90 ~ -105dBm) REV.
17 -62dBm under
.Acoustic(Max Vol.) SEND
GSM
MS/HEADSET SLR: 8±3dB REV.
Headset
MS/HEADSET RLR: -13±1dB/-15dB SEND
DCS
(SLR/RLR: mid-Value Setting) REV.
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2. PERFORMANCE
2.8 Charging
· Normal mode: Complete Voltage: 4.2V
Charging Current: 600mA
· Await mode: In case of During a Call, should be kept 3.9V
(GSM: It should be kept 3.9V in all power level
WCDMA: It will not be kept 3.9V in some power level)
Extend await mode: At Charging prohibited temperature(-20C under or 60C over)
(GSM: It should be kept 3.7V in all power level
WCDMA: It will not be kept 3.7V in some power level)
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3. TECHNICAL BRIEF
3. Technical Brief
3.1 Digital Baseband(DBB) & Multimedia Processor
3.1.1 General Description
A. Features
· CPU ARM946 running at 104 MHz
- 32 kB Instruction Cache, 16 kB Data Cache, 128 kB Instruction TCM and 128 kB Data TCM
- 8 channel DMAC
· DSP C55x (LEAD3) Megastar (MGS3_2.0B) running at 170 MHz
- 144 kWord ROM, 32 kWord DARAM, 32 kWord SARAM
- 7 channel DMAC
- Dedicated API channel to DSP memory (not locked up to other DMA channels)
· UMTS Access
- Support for WCDMA/GSM Dual Mode
- GSM/GPRS network signaling (from Layer 1 to 3)
- WCDMA Ciphering and Integrity
- High Speed Serial Link (HSSL) to the WCDMA Modem (at Layer 1)
- GSM AMR
- Multislot Class 8
- HSCSD 14.4 kb/s
· MMI
- Keypad Interface
- Tone Generator Interface
- Camera Data and Programmable Display Interfaces
- Enhanced graphics support for QCIF display
· Operation and Services
- I2CTM Interface
- SIM Interfaces
- General Purpose I/O (GPIO) Interface
- External Memory Interface that supports FLASH, SRAM and PSRAM
- JTAG
- RTC
- ETM (in Prototype Package)
· Data Communication
- IrDA ® (SIR)
- UARTs (ACB, EDB (RS232))
- Slave USB
· Package
- 12 by 12 mm 289 pin FPBGA Production Package
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3. TECHNICAL BRIEF
3.1.2 Hardware Architecture
The hardware structure is delivered as five separate hardware macros to the top-level design, also
depicted in Figure.
Figure. Simplified Block Diagram
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3. TECHNICAL BRIEF
A. Block Diagram
Figure. Simplified Block Diagram
B. CPU Hardware Subsystem
The CPU subsystem incorporates:
· CPU Sub chip
· Backplane
· JTAG
· DMA Controller
· System Buffer RAM
· Boot ROM
· External Memory Interface (EMIF) for connection to external SRAM and Flash memories.
The bus architecture is built on the ARM AMBA standard with multi-layer AHB (Advanced High-speed
Bus) and APB (Advanced Peripheral Bus) for the peripheral buses.
There are two AHB busses, the CPU AHB and the DMA AHB.
Clocks to the CPU subsystem are distributed from the system control (SYSCON) backplane clocking.
The reset lines are all asynchronously asserted low and synchronously negated high.
The CPU subsystem has separate clocking and reset for the ARM946, AHB system, EMIF and DMAC.
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3. TECHNICAL BRIEF
C. Peripheral Hardware Subsystem
There are 29 peripherals within the peripheral hardware subsystem. With the exception of the USB,
all hardware peripheral blocks are APB slave peripherals. From an architecture-hierarchy perspective,
the SYSCON block is an APB slave on the slow APB bridge, but resides at the top level of the ASIC.
The APB provides a simple interface to support low-performance peripherals.
Within the peripheral subsystem, there are four separate APB busses with AHB to APB (AHB2APB)
bridges to the multi-layer AHB.
D. DSP Hardware Subsystem
The DSP subsystem provides support for processor intensive activity, such as voice coding and
multimedia application support. The DSP subsystem includes the standard C55xTM Core (LEAD3)
from Texas Instruments with associated memory system and peripherals.
E. GAM Hardware Subsystem
The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of
visual imagery and the transfer of this data to the display. GAM also provides support for the camera
module. The visual data could be graphics, still images or video.
The GAM subsystem consists of five modules:
· GRAM - graphics memory (160 kB).
· GAMCON . GAM controller.
· GRAPHCON . graphics controller.
· PDI/SSI - programmable display interface for parallel/serial displays.
· CDI - camera data interface.
F. GSM Hardware Subsystem
The GSM subsystem is a stand-alone sub-chip incorporating GSM modem and interface to GSM radio
together with memory control (MEMSYS) and internal RAM (IRAM).
The hardware peripheral blocks are RXIF, FCHDET, CRYPTO, EQU, NODI, 4 x CHD, GPRS
CRYPTO, GPRS CRC24, CHE, DIRMOD, CLKCON, SERCON, TIMGEN, MEMSYS and IRAM.
The peripherals are accessible to the AHB (CPU-only) by an asynchronous I/O bridge.
The dual port IRAM is accessible to the AHB (CPU and DMA) by a synchronous AHB slave interface.
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3. TECHNICAL BRIEF
G. System Control Subsystem
The system controller subsystem (SYSCON) is primarily responsible for generating clock signals and
distributing the clock and reset signals within the ASIC and certain external devices. The GSM core,
GAM and DSP subsystems include their own system controllers that are sourced from SYSCON.
SYSCON consists of analog and digital PLL clocks and a clock squarer. The block is a slave
peripheral on the slow APB bus under control of the CPU.
The programming of SYSCON controls the fundamental modes of operation within the ASIC.
Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control
registers. SYSCON also controls the requesting protocol through which different sub-blocks in
Ericsson DB 20000 can request clocks derived from the system clock.
The system controller also stores the chip-ID number in a read only register.
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3. TECHNICAL BRIEF
3.1.3 External memory interface
There are four independent chip selects (CS0, CS1, CS2, CS3) provided for external memories and
each has an address range of 256 Mb.
RF calibration data, Audio parameters and battery calibration data etc are stored in flash memory
area.
A. U8100 & U8110
· 384Mb flash memory + 64Mb PSRAM
· 4-CS(Chip Select) are used
Interface Spec.
Read Access Time Write
Device Part Name Maker Access
Async Page Burst Time
13.5 ns
MCP S71WS256HC0BAW00 AMD 56 ns at 54MHz 56 ns
13.5 ns
FLASH Am29BDS128HD9VKI AMD 56 ns at 54MHz 70 ns
PSRAM S71WS256HC0BAW00 AMD 70 ns 20 ns 70 ns
Table External memory interface for U8100 & U8110
B. U8120
· 512Mb flash memory + 64Mb PSRAM
· 3-CS(Chip Select) are used
Interface Spec.
Read Access Time Write
Device Part Name Maker Access
Async Page Burst Time
14 ns
MCP RD38F4050L0YTQ0 Intel 85 ns 25 ns at 54MHz 85 ns
14 ns
FLASH NZ48F4000L0YBQ0 Intel 85 ns 25 ns at 54MHz 85 ns
10 ns
PSRAM RD38F4050L0YTQ0 Intel 85 ns 25 ns at 66MHz 85 ns
Table External memory interface for U8120
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3. TECHNICAL BRIEF
3.1.4 RF Interface
A. MARITA Interface
Marita controls GSM RF part using these signals through GSM RF chip-Ingela.
· RFCLK, RFDAT, RFSTR : Control signals for Ingela
· TXON, RXON : Control signals for TX and RX part of Ingela
· PCTL : Control signal for GSM TX PAM
· BANDSEL0 : Band selection signal for GSM or DCS
· ANTSW[0:3] : Control signals for antenna switch
· DCLK, IDATA, QDATA : GSM/DCS RX Data
· DIRMOD[A:D] : GSM/DCS TX Data
Figure. Schematic of MARITA RF Interface
B. WANDA Interface
Wanda controls WCDMA RF part using these signals through W-CDMA RF chip-Wopy & Wivi.
Figure. Schematic of WANDA RF Interface
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3. TECHNICAL BRIEF
Figure. Schematic of WANDA RF Interface
· RADIO_CLK, RADIO_DAT, RADIO_STR : Control signals for Wivi & Wopy
· RXIA, RXIB, RXQA, RXQB : WCDMA RX Data
· TXIA, TXIB, TXQA, TXQB : WCDMA TX Data
· HSSLRX_D, HSSLRX_CLK : Marita & Wanda Communication Signal
· HSSLTX_D, HSSLTX_CLK : Marita & Wanda Communication Signal
- 27 -
3. TECHNICAL BRIEF
3.1.5 SIM Interface
SIMDAT0, SIMCLK0, SIMRST0 ports are used to communicate DBB(MARITA) with ABB(VINCENNE)
and filter.
SIM (Interface between DBB and ABB)
SIMDAT0 SIM card bidirectional data line
SIMCLK0 SIM card reference clock
SIMRST0 SIM card async/sync reset
Table. SIM Interface
MARITA VDIG SIMVCC
VINCENNE
15K
10K VDD
DAT
SIMDAT0 SDAT SIMDAT
CLK CARD
SIMCLK0 SCLK SIMCLK
RST
SIMRST0 SRST SIM RST
Figure. SIM Interface
3.1.6 UART Interface
UART signals are connected to MARITA GPIO through IO connector
UART0
Resource Name Note
GPIO10 UARTRX0 Transmit Data
GPIO11 UARTTX0 Receive Data
UART1
GPIO14 UARTRX1 Transmit Data (UART1)
GPIO15 UARTTX1 Receive Data (UART1)
GPIO16 UARTRTS1 Request To Send
GPIO17 UARTCTS1 Clear To Send
Table. UART Interface
- 28 -
3. TECHNICAL BRIEF
3.1.7 GPIO (General Purpose Input/Output) map
In total 40 allowable resources. This model is using 25 resources.
GPIO Map, describing application, I/O state, and enable level are shown in below table.
IO # Application IO Resource Inactive State Active State
GPIO00 Not used
GPIO01 BL_PWL O GPIO Low High
GPIO02 7C_LED_VDD_EN O GPIO Low High
GPIO03 PULSESKIP (Not used) I GPIO
GPIO04 CAMERA_DET I GPIO High Low
GPIO05 GPIO05 (Not used) O
GPIO06 AMPCTR O GPIO Low High
GPIO07 TGBUZZ (Not used) O GPIO Low High
GPIO10 UARTRX0 I UART0 High Low
GPIO11 UARTTX0 O UART0 High Low
GPIO12 Not used
GPIO13 Not used
GPIO14 UARTRX1 I UART1 High Low
GPIO15 UARTTX1 O UART1 High Low
GPIO16 UARTRTS1 I UART1 High Low
GPIO17 UARTCTS1 O UART1
GPIO20 CAM_REG_EN O GPIO Low High
GPIO21 CAM_FLASH_ON O GPIO Low High
GPIO22 TP2125 (Not used)
GPIO23 CAM_FLASH_SHOT O GPIO Low High
GPIO24 Not used
GPIO25 Not used
GPIO26 Not used
GPIO27 Not used
GPIO30 Not used
GPIO31 Not used
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3. TECHNICAL BRIEF
IO # Application IO Resource Inactive State Active State
GPIO32 KEY_LED_ONOFF O GPIO Low High
GPIO33 Not used
GPIO34 Not used
GPIO35 LCDVSYNCI (Not used) I GPIO Low High
GPIO36 SPKMUTE O GPIO LOW (Ear piece) HIGH (Speaker)
GPIO37 Not used
GPIO40 USBSENSE I GPIO Low High
GPIO41 Not used
GPIO42 BL_EN O GPIO Low High
GPIO43 FOLDER_DET I GPIO High Low
GPIO44 EN_LED_R O GPIO Low High
GPIO45 EN_LED_G O GPIO Low High
GPIO46 EN_LED_B O GPIO Low High
GPIO47 IRDA_REG_CTRL O GPIO Low High
Table. MARITA GPIO Map Table
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3. TECHNICAL BRIEF
3.1.8 USB
The USB block supports the implementation of a "full-speed" device fully compliant to USB 2.0
standard. It provides an interface between the CPU (embedded local host) and the USB wire, and
handles USB transactions with minimal CPU intervention.
The USB specification allows up to 15 pairs of endpoints. Data for each endpoint is buffered in RAM
within the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO register
access. High-speed (high throughput) endpoints can use DMA while slower endpoints can use FIFO
register access.
The USB block can request up to six DMA channels, three for IN endpoints and three for OUT
endpoints.
USB Function Note
USBDP USB differential (+) line
USBDM USB differential (-) line
USBSENSE (GPIO40) USB detection (input)
USBPUEN USB pull-up control
VDDUSB Power supply for MARITA USB block
Table. USB Signal Interface of MARITA
Figure. Schematic of MARITA USB block
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3. TECHNICAL BRIEF
USB regulator input voltage is 5V and uses external USB device power through IO Connector.
Output voltage is 3.3V and supply to MARITA USB block.
USB is detected by MARITA GPIO40(USBSENES).
· VUSB / (10K + 51K) = VUSBSENSE / 51K
Figure. Schematic of USB Regulator
Figure. Schematic of USB filter
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3. TECHNICAL BRIEF
3.1.9 IrDA Interface
MARITA supports FIR, MIR and SIR mode.
In this model, the IrDA block supports SIR (Standard IrDA) mode.
SIR supports data rates up to 115,200 bps, including 9,600/19,200/38,400/57,600 bps.
In this mode, IrDA uses eight data bits per character and one stop bit.
IrDA supports a protocol defined by the IrDA Association.
Figure. Schematic of MARITA IrDA Interface
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3. TECHNICAL BRIEF
3.1.10 Folder ON/OFF Operation
There is a magnet to detect the folder status, opened or closed.
If a magnet is close to the hall-effect switch (U1 on keypad), the voltage at pin2 of U1 goes to 0V.
Otherwise, 2.8V.
This folder signal is delivered to MARITA GPIO43.
VCAM
R3206
100K
CAMERA_DET
A3212ELH 1
OUT 2
N3200
VDD
C3204
0.1u C3205
GND
3
10p
Figure. Schematic of MARITA IrDA Interface
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3. TECHNICAL BRIEF
3.1.11 Power On Sequence
1 User press END key and ONSWAn signal is changed to Low.
2 VINCENNE initiate the internal oscillator and power up the regulators.
3 VINCENNE generate a power for MARITA.
4 VINCENNE release the power reset signal(PWRRSTn) and generate an interrupt(IRQ0n) to
MARITA.
VINCENNE 3 Power for
MARITA
MARITA
2
1 Press END key
4 PWRRSTn
PWRRST 4 IRQ0n RESPOW_N
1 ONSWAn IRQ0_N
IRQ
ONSWA
RESETB RESOUT0_N
Figure. Power On Sequence
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3. TECHNICAL BRIEF
3.1.12 Key Pad
There are 26 buttons and 3 side keys in Figure 3-xx.Shows the Keypad circuit.`END' Key is connected
ONSWAn from Vincenne.
KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4
KEYOUT0 SIDE1 SIDE2 SIDE3
KEYOUT1 1 4 7 * UP
KEYOUT2 2 5 8 0 DOWN
KEYOUT3 3 6 9 # RIGHT
KEYOUT4 SEND CLEARER BACK GAME LEFT
KEYOUT5 MENU SEARCH MULTI CAM OK
Table Key Matrix Mapping Table
Figure. Power On Sequence
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3. TECHNICAL BRIEF
3.2 GAM Hardware Subsystem
Figure. GAM Subsystem Functional Block Diagram
3.2.1 General Description
The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of
visual imagery and the transfer of this data to the display. GAM also provides support for the camera
module. The visual data could be graphics, still images or video. The GAM subsystem consists of five
modules:
· GRAM - graphics memory (160 kB).
· GAMCON . GAM controller.
· GRAPHCON . graphics controller.
· PDI/SSI - programmable display interface for parallel/serial displays.
· CDI - camera data interface.
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3. TECHNICAL BRIEF
3.2.2 Block Description
GAM Controller(GAMCON)
The GAM Controller (GAMCON) is responsible for clock gating and distribution within the GAM
module. GAMCON receives the HCLK from SYSCON and distributes to GRAPHCON, GRAM, PDI and
CDI. GAMCON also distributes the GAM reset signal to GRAPHCON, GRAM, PDI and CDI. The reset
signals CIRES_N and PDIRES_N are distributed from GAMCON to the camera and display module
respectively, see Figure. The CIPCLK is used to clock the received data into the camera data
interface. The CIPCLK can be in the range of 100 kHz to 16 MHz.
Graphics RAM (GRAM) Block
GAM includes 160 kB of graphics memory (GRAM) in order to support display screen sizes of QCIF +
alfa display size and three frame buffers when decoding QCIF video.
The GRAM can be accessed in 8, 16 or 32-bit mode. Write access takes a single AHB clock cycle.
Non-sequential read and the first access of a sequential read access takes two AHB clock cycles.
Subsequent sequential read access take a single AHB clock cycle.
The GRAM contains both frame buffer and temporary data. There are three image areas with one
used for normal MMI graphics and the other two areas used for still images, video frames or camera
frames. The three image areas can be combined into one frame buffer.
GRAM is required to transfer a VGA (640 by 480 pixels) image from the camera data interface (CDI)
over DMA at 100 MBit/s, within a 50 ms timeframe. The GRAM is used as a buffer, but the average
transfer bandwidth required is approximately 3 Mword/s (32-bit word), that is 12 MByte/s.
Graphics Controller (GRAPHCON) Block
GRAPHCON is controlled by the application CPU and can perform operations on pixels and image
areas. Images can be moved and merged with other images and text.
The GRAPHCON block receives graphical objects from GRAM and performers the appropriate
graphical manipulation. The resulting data is transfers to the display interface (PDI). GRAPHCON can
receive images from the camera data interface (CDI) and send them to the PDI automatically.
GRAPHCON performs conversion from YUV to RGB and can scale (zoom) still or video images.
Programmable Display Interface (PDI) Block
The programmable display interface (PDI) is designed to interface both parallel and serial display
modules. The display data is transferred from the 32 word FIFO on GAMCON to the display module
via the PDI block. The PDI block is built around a micro controller and executes 16-bit instruction
words to individually control the I/O ports. It has a 128 byte program memory, programmable by the
CPU, which can store up to 64 instructions.
The CPU transfers all set-up and control data to the display. Data is transferred to PDI as 32-bit words,
which in turn writes 8-bit data to the display. The programmable PDI block is configured at the
software build stage, to support either parallel interface such as PPI or serial interface such as SSI or
I2C.
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3. TECHNICAL BRIEF
Camera Data Interface (CDI) Block
The camera data interface (CDI) block is designed to support a range of still image camera modules.
An 8-bit parallel bus supports data transfer from the camera module to the CDI.
The pixel clock is an output clock from the camera module to the CDI and qualifies