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PIC16C84
8-Bit CMOS EEPROM Microcontroller
High Performance RISC CPU Features
· Only 35 single word instructions to learn · All instructions single cycle (400 ns @ 10MHz) except for program branches which are two-cycle · Operating speed: DC - 10MHz clock input DC - 400 ns instruction cycle · 14-bit wide instructions · 8-bit wide data path · 1K x 14 EEPROM program memory · 36 x 8 general purpose registers (SRAM) · 64 x 8 on-chip EEPROM data memory · 15 special function hardware registers · Eight-level deep hardware stack · Direct, indirect and relative addressing modes · Four interrupt sources: - External RB0/INT pin - TMR0 timer overflow - PORTB<7:4> interrupt on change - Data EEPROM write complete · 1,000,000 data memory EEPROM ERASE/WRITE cycles · EEPROM Data Retention > 40 years
Pin Diagram
PDIP, SOIC
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3
·1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C84
CMOS Technology
· Low-power, high-speed CMOS EEPROM technology · Fully static design · Wide operating voltage range: - Commercial: 2.0V to 6.0V - Industrial: 2.0V to 6.0V · Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 60 µA typical @ 2V, 32 kHz - 26 µA typical standby current @ 2V
Peripheral Features
· 13 I/O pins with individual direction control · High current sink/source for direct LED drive - 25 mA sink max. per pin - 20 mA source max. per pin · TMR0: 8-bit timer/counter with 8-bit programmable prescaler
Special Microcontroller Features
· · · · · · · · Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Code protection Power saving SLEEP mode Selectable oscillator options Serial In-System Programming - via two pins
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PIC16C84
Table of Contents
1.0 General Description ............................................................................................................................................ 3 2.0 PIC16C84 Device Varieties ................................................................................................................................ 5 3.0 Architectural Overview........................................................................................................................................ 7 4.0 Memory Organization ....................................................................................................................................... 11 5.0 I/O Ports............................................................................................................................................................ 19 6.0 Timer0 Module and TMR0 Register.................................................................................................................. 25 7.0 Data EEPROM Memory.................................................................................................................................... 31 8.0 Special Features of the CPU ............................................................................................................................ 35 9.0 Instruction Set Summary ...................................................................................................................................51 10.0 Development Support ........................................................................................................................................63 11.0 Electrical Characteristics for PIC16C84............................................................................................................ 67 12.0 DC & AC Characteristics Graphs/Tables for PIC16C84 ................................................................................... 77 13.0 Packaging Information .......................................................................................................................................91 Appendix A: Feature Improvements ...........................................................................................................................95 Appendix B: Compatibility...........................................................................................................................................95 Appendix C: What's New ............................................................................................................................................96 Appendix D: What's Changed.....................................................................................................................................96 Appendix E: PIC16C84 to PIC16F83/F84/CR83/CR84 Considerations .....................................................................77 Appendix F: PIC16/17 Microcontrollers ......................................................................................................................99 Index............................................................................................................................................................................ 111 PIC16C84 Product Identification System .................................................................................................................... 115
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30445B-page 2
© 1996 Microchip Technology Inc.
PIC16C84
1.0 GENERAL DESCRIPTION
The PIC16C84 is a low-cost, high-performance, CMOS, fully-static, 8-bit microcontroller. All PIC16/17 microcontrollers employ an advanced RISC architecture. PIC16CXX devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with a separate 8-bit wide data bus. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set is used to achieve a very high performance level. PIC16CXX microcontrollers typically achieve a 2:1 code compression and up to a 2:1 speed improvement (at 10 MHz) over other 8-bit microcontrollers in their class. The PIC16C84 has 36 bytes of RAM, 64 bytes of Data EEPROM memory, and 13 I/O pins. A timer/counter is also available. The PIC16CXX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake the chip from sleep through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock-up. The PIC16C84 EEPROM program memory allows the same device package to be used for prototyping and production. In-circuit reprogrammability allows the code to be updated without the device being removed from the end application. This is useful in the development of many applications where the device may not be easily accessible, but the prototypes may require code updates. This is also useful for remote applications where the code may need to be updated (such as rate information). Table 1-1 lists the features of the PIC16C84, and Appendix F: lists the features of all of the Microchip microcontrollers. A simplified block diagram of the PIC16C84 is shown in Figure 3-1. The PIC16C84 fits perfectly in applications ranging from high speed automotive and appliance motor control to low-power remote sensors, electronic locks, security devices and smart cards. The EEPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, security codes, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC16C84 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, serial communication, capture and compare, PWM functions and co-processor applications). The serial in-system programming feature (via two pins) offers flexibility of customizing the product after complete assembly and testing. This feature can be used to serialize a product, store calibration data, or program the device with the current firmware before shipping.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A: for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to the PIC16C84 (Appendix B:).
1.2
Development Support
The PIC16CXX family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A "C" compiler and fuzzy logic support tools are also available.
© 1996 Microchip Technology Inc.
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TABLE 1-1:
h
as
Fl
DS30445B-page 4 Clock
n (M ) Hz
PIC16C84
Memory
em
e yt s)
Peripherals
Features
F
q re
ue
n
cy
o
fO
pe
ra
tio
or
y
Pr
or y (b
r og
am
M
M
er
In t
y (b
M
ru er
te
o
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s)
l du
u So
e(
rc
s)
es
PIC16C8X FAMILY OF DEVICES
M RO M
a M
um xim
EE
O PR
Da
ta
M
em
Da
Ti
ta
m
EE
I/O Pi
Vo lta ge
O PR
ns
R an
ge
o (V
lts
)
Pa
a ck
ge
s
PIC16C84 PIC16F84(1) 10 10 10 10 -- -- 512 36 64 TMR0 4 512 -- -- 36 64 TMR0 4 -- -- 1K 68 64 TMR0 4 13 13 13 1K -- -- 68 64 TMR0 4 13 PIC16CR84(1) PIC16F83(1) PIC16CR83(1)
10
--
1K
--
36
64
TMR0
4
13
2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales office for availability of these devices.
© 1996 Microchip Technology Inc.
PIC16C84
2.0 PIC16C84 DEVICE VARIETIES
2.2
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in this section. When placing orders, please use the "PIC16C84 Product Identification System" at the back of this data sheet to specify the correct part number. There are two device "types" as indicated in the device number. 1. C, as in PIC16C84. These devices have EEPROM program memory and operate over the standard voltage range. LC, as in PIC16LC84. These devices have EEPROM program memory and operate over an extended voltage range.
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices have all EEPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. For information on submitting a QTP code, please contact your Microchip Regional Sales Office.
2.
2.3
When discussing memory maps and other architectural features, the use of C also implies the LC versions.
Serialized Quick-Turnaround-Production (SQTP SM ) Devices
2.1
Electrically Erasable Devices
These devices are offered in the lower cost plastic package, even though the device can be erased and reprogrammed. This allows the same device to be used for prototype development and pilot programs as well as production. A further advantage of the electrically erasable version is that they can be erased and reprogrammed in-circuit, or by device programmers, such as Microchip's PICSTART® Plus or PRO MATE® II programmers.
Microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. For information on submitting a SQTP code, please contact your Microchip Regional Sales Office.
© 1996 Microchip Technology Inc.
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PIC16C84
NOTES:
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PIC16C84
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture. This architecture has the program and data accessed from separate memories. So the device has a program memory bus and a data memory bus. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory (accesses over the same bus). Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. PIC16CXX opcodes are 14-bits wide, enabling single word instructions. The full 14-bit wide program memory bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (400 ns @ 10 MHz) except for program branches. The PIC16C84 addresses 1K x 14 program memory. All program memory is internal. PIC16CXX devices can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. An orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16C84 has 36 x 8 SRAM and 64 x 8 EEPROM data memory. PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register), and the other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram for the PIC16C84 is shown in Figure 3-1, its corresponding pin description is shown in Table 3-1.
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PIC16C84
FIGURE 3-1: PIC16C84 BLOCK DIAGRAM
13 EEPROM/ROM Program Memory 1K x 14 Program Counter Data Bus 8 EEPROM Data Memory
8 Level Stack (13-bit)
RAM File Registers 36 x 8
EEDATA
EEPROM Data Memory 64 x 8
Program Bus 14 Instruction reg 5 Direct Addr
7
RAM Addr
EEADR
Addr Mux 7 Indirect Addr TMR0
FSR reg RA4/T0CKI STATUS reg 8
Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer W reg ALU
MUX I/O Ports
RA3:RA0 RB7:RB1
Timing Generation
RB0/INT
OSC2/CLKOUT OSC1/CLKIN
MCLR
VDD, VSS
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© 1996 Microchip Technology Inc.
PIC16C84
TABLE 3-1:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C8X PINOUT DESCRIPTION
DIP No. 16 15 SOIC No. 16 15 I/O/P Type I O Buffer Type Description
ST/CMOS (1) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR
4
4
I/P
ST
RA0 RA1 RA2 RA3 RA4/T0CKI
17 18 1 2 3
17 18 1 2 3
I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST Can also be selected to be the clock input to the TMR0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD Legend: I= input
6 7 8 9 10 11 12 13 5 14
6 7 8 9 10 11 12 13 5 14
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL TTL TTL TTL TTL TTL TTL/ST (2) TTL/ST (2) -- --
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = Input/Output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
© 1996 Microchip Technology Inc.
DS30445B-page 9
PIC16C84
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)
PC PC+1 PC+2
Internal phase clock
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
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© 1996 Microchip Technology Inc.
PIC16C84
4.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16C84. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the "core" are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory, but is indirectly mapped. That is an indirect address pointer specifies the address of the data EEPROM memory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. More details on the EEPROM memory can be found in Section 7.0.
FIGURE 4-1: PROGRAM MEMORY MAP AND STACK
PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1
· · ·
13
Stack Level 8 Reset Vector Peripheral Interrupt Vector
0000h 0004h
4.1
Program Memory Organization
3FFh
The PIC16CXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16C84, only the first 1K x 14 (0000h-03FFh) are physically implemented (Figure 4-1). Accessing a location above the physically implemented address will cause a wraparound. For example, locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h will be the same instruction. The reset vector is at 0000h and the interrupt vector is at 0004h.
User Memory Space
1FFFh
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PIC16C84
4.2 Data Memory Organization FIGURE 4-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 36 General Purpose registers (SRAM) 2Fh 30h Mapped (accesses) in Bank 0 AFh B0h EEDATA EEADR PCLATH INTCON EECON1 EECON2(1) PCLATH INTCON Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB Indirect addr.(1) OPTION PCL STATUS FSR TRISA TRISB
REGISTER FILE MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 4-2 shows the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file ("F"), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 4.5). Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The first twelve locations of each Bank are reserved for the Special Function Registers. The remainder are General Purpose Registers implemented as static RAM. 4.2.1 GENERAL PURPOSE REGISTER FILE
All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4.5). The GPR addresses in bank 1 are mapped to addresses in bank 0. As an example, addressing location 0Ch or 08h will access the same GPR. 4.2.2 SPECIAL FUNCTION REGISTERS
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory location; read as '0'. Note 1: Not a physical register.
The Special Function Registers (Figure 4-2 and Table 4-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature.
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PIC16C84
TABLE 4-1: REGISTER FILE SUMMARY
Value on Power-on Reset Value on all other resets (Note3)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 0Ah 0Bh EECON1 EECON2 PCLATH INTCON INDF OPTION PCL STATUS (2) FSR TRISA TRISB Uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 ---- ---1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---- ---EEIF WRERR WREN WR RD ---0 x000 ---- ------0 0000 INTF RBIF 0000 000x ---- ---1111 1111 0000 0000 000q quuu uuuu uuuu ---1 1111 1111 1111 ---- ------0 q000 ---- ------0 0000 0000 000u EEDATA EEADR PCLATH INTCON INDF TMR0 PCL STATUS FSR PORTA PORTB
(2)
Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of the Program Counter (PC) IRP RP1 RP0 TO PD Z DC C
---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
---- ---uuuu uuuu 0000 0000 000q quuu uuuu uuuu ---u uuuu uuuu uuuu ---- ---uuuu uuuu uuuu uuuu ---0 0000 0000 000u
Indirect data memory address pointer 0 -- RB7 -- RB6 -- RB5 RA4/T0CKI RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0/INT
---x xxxx xxxx xxxx ---- ---xxxx xxxx xxxx xxxx
Unimplemented location, read as '0' EEPROM data register EEPROM address register -- GIE -- EEIE -- T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF INTF RBIF
---0 0000 0000 000x
Low order 8 bits of Program Counter (PC) IRP RP1 RP0 TO
Indirect data memory address pointer 0 -- -- -- PORTA data direction register
PORTB data direction register Unimplemented location, read as '0' -- -- --
EEPROM control register 2 (not a physical register) -- GIE -- EEIE -- T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred to PCLATH. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
© 1996 Microchip Technology Inc.
DS30445B-page 13
PIC16C84
4.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 9-2) because these instructions do not affect any status bit. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C84 and should be programmed as cleared. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. Note 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specified bit(s) will be updated according to device logic
FIGURE 4-3:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 R-1 R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
TO
PD
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 0 = Bank 0, 1 (00h - FFh) 1 = Bank 2, 3 (100h - 1FFh) The IRP bit is not used by the PIC16C8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 3 (180h - 1FFh) Each bank is 128 bytes. Only bit RP0 is used by the PIC16C8X. RP1 should be maintained clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (for ADDWF and ADDLW instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note:For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
DS30445B-page 14
© 1996 Microchip Technology Inc.
PIC16C84
4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. When the prescaler is assigned to the WDT (PSA = '1'), TMR0 has a 1:1 prescaler assignment.
FIGURE 4-4:
R/W-1 RBPU bit7
OPTION REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to TMR0
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
© 1996 Microchip Technology Inc.
DS30445B-page 15
PIC16C84
4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
FIGURE 4-5:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 EEIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Note: For the operation of the interrupt structure, please refer to Section 8.5. EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT Interrupt Enable bit 1 = Enables the RB0/INT interrupt 0 = Disables the RB0/INT interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 overflow interrupt flag bit 1 = TMR0 has overflowed (must be cleared in software) 0 = TMR0 did not overflow INTF: RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred 0 = The RB0/INT interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS30445B-page 16
© 1996 Microchip Technology Inc.
PIC16C84
4.3 Program Counter: PCL and PCLATH
.
Note: The Program Counter (PC) is 13-bits wide. The low byte is the PCL register, which is a readable and writable register. The high byte of the PC (PC<12:8>) is not directly readable nor writable and comes from the PCLATH register. The PCLATH (PC latch high) register is a holding register for PC<12:8>. The contents of PCLATH are transferred to the upper byte of the program counter when the PC is loaded with a new value. This occurs during a CALL, GOTO or a write to PCL. The high bits of PC are loaded from PCLATH as shown in Figure 4-6.
The PIC16C84 ignores the PCLATH<4:3> bits, which are used for program memory pages 1, 2 and 3 (0800h - 1FFFh). The use of PCLATH<4:3> as general purpose R/W bits is not recommended since this may affect upward compatibility with future products.
4.4
Stack
FIGURE 4-6:
PCH 12 PC 5
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 INST with PCL as dest PCLATH<4:0> 8 ALU result
The PIC16C84 has an 8 deep x 13-bit wide hardware stack (Figure 4-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The entire 13-bit PC is "pushed" onto the stack when a CALL instruction is executed or an interrupt is acknowledged. The stack is "popped" in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a push or a pop operation. Note: There are no instruction mnemonics called push or pop. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.
PCLATH PCH 12 11 10 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCL 8 7 0 GOTO, CALL
PCLATH
The stack operates as a circular buffer. That is, after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). If the stack is effectively popped nine times, the PC value is the same as the value from the first pop. Note: There are no status bits to indicate stack overflow or stack underflow conditions.
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 word block). Refer to the application note "Implementing a Table Read" (AN556). 4.3.2 PROGRAM MEMORY PAGING
The PIC16C84 has 1K of program memory. The CALL and GOTO instructions have an 11-bit address range. This 11-bit address range allows a branch within a 2K program memory page size. For future PIC16CXX program memory expansion, there must be another two bits to specify the program memory page. These paging bits come from the PCLATH<4:3> bits (Figure 4-6). When doing a CALL or a GOTO instruction, the user must ensure that these page bits (PCLATH<4:3>) are programmed to the desired program memory page. If a CALL instruction (or interrupt) is executed, the entire 13-bit PC is "pushed" onto the stack (see next section). Therefore, manipulation of the PCLATH<4:3> is not required for the return instructions (which "pops" the PC from the stack)
© 1996 Microchip Technology Inc.
DS30445B-page 17
PIC16C84
4.5 Indirect Addressing; INDF and FSR Registers EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
NEXT
EXAMPLE 4-1:
· · · ·
INDIRECT ADDRESSING
CONTINUE
movlw movwf clrf incf btfss goto :
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h · Increment the value of the FSR register by one (FSR = 06) · A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-7. However, IRP is not used in the PIC16C84.
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 (FSR) 0
RP1 RP0
6
from opcode
bank select
location select
bank select
location select
00 00h
01
10 not used
11 00h not used
0Bh 0Ch Data Memory 2Fh 30h 7Fh Bank 0 Bank 1 Bank 2 Bank 3 7Fh Addresses map back to Bank 0
DS30445B-page 18
© 1996 Microchip Technology Inc.
PIC16C84
5.0 I/O PORTS
EXAMPLE 5-1:
CLRF PORTA
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by setting output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA4 as outputs TRISA<7:5> are always read as '0'.
The PIC16C84 has two ports, PORTA and PORTB. Some port pins are multiplexed with an alternate function for other features on the device.
5.1
PORTA and TRISA Registers
BSF MOVLW
STATUS, RP0 0x0F
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedence mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. The RA4 pin is multiplexed with the TMR0 clock input.
MOVWF
TRISA
FIGURE 5-2:
Data bus WR PORT
BLOCK DIAGRAM OF PIN RA4
D
Q Q
CK
N Data Latch VSS
D Q Q
RA4 pin
WR TRIS
CK
TRIS Latch
FIGURE 5-1:
Data bus WR Port
BLOCK DIAGRAM OF PINS RA3:RA0
RD TRIS Q VDD
Q
Schmitt Trigger input buffer
D
D EN EN
CK
Q
P RD PORT
Data Latch N D WR TRIS Q VSS CK Q TTL input buffer I/O pin TMR0 clock input Note: I/O pin has protection diodes to VSS only.
TRIS Latch
Note:
RD TRIS Q D
For crystal oscillator configurations operating below 500 kHz, the device may generate a spurious internal Q-clock when PORTA<0> switches state. This does not occur with an external clock in RC mode. To avoid this, the RA0 pin should be kept static, i.e. in input/output mode, pin RA0 should not be toggled.
EN RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
© 1996 Microchip Technology Inc.
DS30445B-page 19
This document was created with FrameMaker 4 0 4
PIC16C84
TABLE 5-1:
Name RA0 RA1 RA2 RA3 RA4/T0CKI
PORTA FUNCTIONS
Bit0 bit0 bit1 bit2 bit3 bit4 Buffer Type TTL TTL TTL TTL ST Function
Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type. Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset ---x xxxx ---1 1111 Value on all other resets ---u uuuu ---1 1111
05h 85h
PORTA TRISA
-- --
-- --
-- --
RA4/T0CKI TRISA4
RA3 TRISA3
RA2 TRISA2
RA1 TRISA1
RA0 TRISA0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30445B-page 20
© 1996 Microchip Technology Inc.
PIC16C84
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' on any bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. A '0' on any bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins have a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The pins value in input mode are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of the pins are OR'ed together to generate the RB port change interrupt. This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Read (or write) PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition, and allow the RBIF bit to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression (see AN552 in the Embedded Control Handbook). Note 1: If a change on the I/O pin should occur when a read operation of PORTB is being executed (start of the Q2 cycle), the RBIF interrupt flag bit may not be set. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 5-3:
BLOCK DIAGRAM OF PINS RB7:RB4
VDD
FIGURE 5-4:
BLOCK DIAGRAM OF PINS RB3:RB0
VDD weak P pull-up Data Latch D CK TRIS Latch D Q Q I/O pin(2)
RBPU(1) Data Latch D CK TRIS Latch D WR TRIS CK Q Q
weak P pull-up
RBPU(1)
Data bus WR Port
Data bus I/O pin(2) WR Port
TTL Input Buffer
WR TRIS
CK
TTL Input Buffer
RD TRIS
Latch Q D EN
RD TRIS Q RD Port D EN
RD Port Set RBIF
RB0/INT From other RB7:RB4 pins Q D RD Port EN RD Port Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION register). 2: I/O pins have diode protection to VDD and VSS. Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION register). 2: I/O pins have diode protection to VDD and VSS.
© 1996 Microchip Technology Inc.
DS30445B-page 21
PIC16C84
EXAMPLE 5-2:
CLRF PORTB
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; Initialize PORTB by setting output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
TABLE 5-3:
Name RB0/INT
PORTB FUNCTIONS
Bit bit0 Buffer Type TTL I/O Consistency Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(1) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. (1) RB7 bit7 TTL/ST Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger. Note 1: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset xxxx xxxx 1111 1111 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
06h 86h 81h
PORTB TRISB OPTION
RB7 TRISB7 RBPU
RB6 TRISB6 INTEDG
RB5 TRISB5 T0CS
RB4 TRISB4 T0SE
RB3 TRISB3 PSA
RB2 TRISB2 PS2
RB1 TRISB1 PS1
RB0/INT TRISB0 PS0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30445B-page 22
© 1996 Microchip Technology Inc.
PIC16C84
5.3
5.3.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (i.e., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch is unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (i.e., BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output current may damage the chip.
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-5). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such that the pin voltage stabilizes (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. Example 5-3 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port.
EXAMPLE 5-3:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp ppp 11pp ppp BCF PORTB, 6 ; 10pp ppp 11pp ppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp ppp 11pp ppp BCF TRISB, 6 ; 10pp ppp 10pp ppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).
FIGURE 5-5:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 MOVF PORTB,W NOP NOP PC + 2 PC + 3
Note: This example shows as write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25 TCY - TPD) where:TCY = instruction cycle TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
Instruction fetched RB7:RB0
MOVWF PORTB write to PORTB
Port pin sampled here Instruction executed MOVWF PORTB write to PORTB MOVF PORTB,W NOP NOP
© 1996 Microchip Technology Inc.
DS30445B-page 23
PIC16C84
NOTES:
DS30445B-page 24
© 1996 Microchip Technology Inc.
PIC16C84
6.0 TIMER0 MODULE AND TMR0 REGISTER
edge select bit, T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 Module and the Watchdog Timer. The prescaler assignment is controlled, in software, by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 Module. The prescaler is not readable or writable. When the prescaler (Section 6.3) is assigned to the Timer0 Module, the prescale value (1:2, 1:4, ..., 1:256) is software selectable.
The Timer0 module timer/counter has the following features: · · · · · · 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module (Figure 6-1) will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode TMR0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the T0 source
6.1
TMR0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing enable bit T0IE (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 Module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt (Figure 6-4) cannot wake the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 6-1:
TMR0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 PSout Sync with Internal clocks (2 cycle delay) Set bit T0IF on Overflow 8 TMR0 register PSout
RA4/T0CKI pin T0SE
Programmable Prescaler 3 PS2, PS1, PS0 T0CS
0
PSA
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2:
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC Instruction Fetch T0
PC-1
PC MOVWF TMR0
PC+1
PC+2
PC+3
PC+4 MOVF TMR0,W
PC+5 MOVF TMR0,W
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
TMR0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Instruction Executed
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
© 1996 Microchip Technology Inc.
DS30445B-page 25
This document was created with FrameMaker 4 0 4
PIC16C84
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction Fetch TMR0 T0 PC-1 PC MOVWF TMR0 PC+1 PC+2 PC+3 PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 6-4:
TMR0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) TMR0 timer T0IF bit 4 (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle Interrupt Latency(2) PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. 4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit. The TMR0 register will roll over 3 Tosc cycles later.
DS30445B-page 26
© 1996 Microchip Technology Inc.
PIC16C84
6.2 Using TMR0 with External Clock
6.2.2 TMR0 INCREMENT DELAY When an external clock input is used for TMR0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of the TMR0 register after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 Module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.
6.3
Prescaler
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of pin RA4/T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (plus a small RC delay) and low for at least 2Tosc (plus a small RC delay). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by an asynchronous ripple counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (plus a small RC delay) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the AC Electrical Specifications of the desired device.
An 8-bit counter is available as a prescaler for the Timer0 Module, or as a postscaler for the Watchdog Timer (Figure 6-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 Module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 Module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 Module, all instructions writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1, BSF 1,x ....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Ext. Clock Input or Prescaler Out (Note 2) Ext. Clock/Prescaler Output After Sampling Increment TMR0 (Q4) TMR0 T0 T0 + 1 T0 + 2 (Note 3) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
© 1996 Microchip Technology Inc.
DS30445B-page 27
PIC16C84
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
Data Bus CLKOUT (= Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
1 0 M U X SYNC 2 Cycles
8 TMR0 register
T0CS
PSA
Set bit T0IF on overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT time-out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS30445B-page 28
© 1996 Microchip Technology Inc.
PIC16C84
6.3.1 SWITCHING PRESCALER ASSIGNMENT
EXAMPLE 6-1:
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). Note: To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be taken even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.
CHANGING PRESCALER (TIMER0WDT)
;Bank 0 ;Clear TMR0 ; and Prescaler ;Bank 1 ;Clears WDT ;Select new ; prescale value ;Bank 0
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION STATUS, RP0
EXAMPLE 6-2:
CLRWDT BSF MOVLW
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ; prescaler ;Bank 1 ;Select TMR0, new ; prescale value ' and clock source ; ;Bank 0
STATUS, RP0 b'xxxx0xxx'
MOVWF BCF
OPTION STATUS, RP0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on Power-on Reset xxxx xxxx INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TRISA1 RBIF PS0 TRISA0 0000 000x 1111 1111 ---1 1111 Value on all other resets uuuu uuuu 0000 0000 1111 1111 ---1 1111
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h 0Bh 81h 85h
TMR0 INTCON OPTION TRISA
Timer0 module's register GIE RBPU -- EEIE INTEDG -- T0IE T0CS --
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
© 1996 Microchip Technology Inc.
DS30445B-page 29
PIC16C84
NOTES:
DS30445B-page 30
© 1996 Microchip Technology Inc.
PIC16C84
7.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are: · · · · EECON1 EECON2 EEDATA EEADR When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory.
7.1
EEADR
The EEADR register can address up to a maximum of 256 bytes of data EEPROM. Only the first 64 bytes of data EEPROM are implemented. The upper two bits are address decoded. This means that these two bits must always be '0' to ensure that the address is in the 64 byte memory space.
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16C84 devices have 64 bytes of data EEPROM with an address range from 0h to 3Fh. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write-time will vary with voltage and temperature as well as from chip to chip. Please refer to AC specifications for exact limits.
FIGURE 7-1:
U -- bit7 U --
EECON1 REGISTER (ADDRESS 88h)
U -- R/W-0 EEIF R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-x RD bit0 R W S U = Readable bit = Writable bit = Settable bit = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:5 bit 4
Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR reset or any WDT reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software). 0 = Does not initiate an EEPROM read
bit 3
bit 2
bit 1
bit 0
© 1996 Microchip Technology Inc.
DS30445B-page 31
This document was created with FrameMaker 4 0 4
PIC16C84
7.2 EECON1 and EECON2 Registers 7.4 Writing to the EEPROM Data Memory
EECON1 is the control register with five low order bits physically implemented. The upper-three bits are non-existent and read as '0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset during normal operation. In these situations, following reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDATA and EEADR registers. Interrupt flag bit EEIF is set when write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the Data EEPROM write sequence. To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte.
EXAMPLE 7-2:
BSF BCF BSF MOVLW MOVWF MOVLW MOVWF BSF BSF
DATA EEPROM WRITE
; ; ; ; ; ; ; ; ; ; Bank 1 Disable INTs. Enable Write Write 55h Write AAh Set WR bit begin write Enable INTs.
Required Sequence
STATUS, RP0 INTCON, GIE EECON1, WREN 55h EECON2 AAh EECON2 EECON1,WR INTCON, GIE
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. Note: The data EEPROM memory E/W cycle time may occasionally exceed the 10 ms specification (typical). To ensure that the write cycle is complete, use the EE interrupt or poll the WR bit (EECON1<1>). Both these events signify the completion of the write cycle.
7.3
Reading the EEPROM Data Memory
To read a data memory location, the user mus