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US4RSM
NSC1
Circuit Diagram of System Blocks
(Version 4.03 Edit 3)
Original 10/98 Updated 11/99
3/A31
US4RSM
NSC1
Circuit Diagram of Power Supply (Version 04.03
Edit 5)
4
5
Test points
Test points 11 12 13 14 15 6 7 8 9 10
16 20
17
18
19
Original 10/98 Updated 11/99
3/A32
US4RSM
NSC1
Circuit Diagram of CTRLU Block (Version 04.03 Edit 3)
TP3
1 Test points 2
Original 10/98 Updated 11/99
3/A33
US4RSM
NSC1
Circuit Diagram of Audio
(Version 4.03 Edit 6)
Test points 21 22 23 24 test point
25
26
27
test points
Original 10/98 Updated 11/99
3/A34
US4RSM
NSC1
Circuit Diagram of Transmitter (Version 4.3 Edit 5)
TP33
TP34
Original 10/98 Updated 11/99
3/A35
US4RSM
NSC1
Circuit Diagram of Receiver (Version 4.3
Edit 03)
Original 10/98 Updated 11/99
3/A36
US4RSM
NSC1
Circuit Diagram of Synthesizer (Version 4.3
Edit 3)
TP
TP
Original 10/98 Updated 11/99
3/A37
US4RSM
NSC1
Circuit Diagram of RF Block (Version
4.3 Edit 2)
Original 10/98 Updated 11/99
3/A38
US4RSM
NSC1
Circuit Diagram of RFBB Interface (Version 4.03 Edit 03)
Original 10/98 Updated 11/99
3/A39
US4RSM
NSC1
Layout Diagram 1/2 of US4RSM
TOP
(Layout version 04)
NOTE: Layout diagram has also upper band (TDMA1900) components included, which are not in actual US4U PCB. Notice this also in testpoints.
testpoint J200 J201 J202 J203 TP1, D202 pin 78 TP2, D202 pin 77
name
condition Only for R&D use Only for R&D use Only for R&D use Only for R&D use
dclevel
aclevel
HOOKINT HEADSETINT RSENSE VOUT VCTCXO CTL CTL
Remote controlheadset Headset connected False transmission indicator VOUT detection VOUT detection power on active state ch 300 active state ch 1000
pulse active 2.8 V, nonactive 0 V pulse active 0 V, nonactive 2.8 V Irregular from 0 V to 2.8 V min 0V, typ 3.6 V, max 5.2 V min 0V, typ 3.6 V, max 5.2 V typ. 0.8 V 1.2 Vpp siniwave 19.44 MHz typ. 2.2 V typ. 2.2 V
TP3, D202 pin 117 TXF TP4, R153 TP5, R153 TP30, G850 pin 3 TP31, G820 pin 3 TP32, G860 pin 3
Original 10/98 Updated 11/99
3/A310
US4RSM
NSC1
Layout Diagram 2/2 of US4RSM
(Layout version 04)
testpoint TP6, N150 pin 11 TP7, N150 pin 15 TP8, N150 pin 4 TP9, N150 pin 9 TP10, N150 pin 25 TP11, N150 pin 20 TP12, N150 pin 19
name VR5 VR4 VR3 VR2 VR1 VR7
condition supply for TX
dclevel 2.8 V min 2.7 V / max 2.85 V
aclevel
testpoint TP19, N150 pin 52 TP20, N150 pin 48 TP21, N250 pin 1 TP22, N250 pin 54 TP23, N250 pin 2
name
condition/type
dclevel pulse active 2.8 V, nonactive 0 V pulsed DC (0V/2.8 V) pulse active 2.8 V, nonactive 0 V pulse active 2.8 V, nonactive 0 V
aclevel
regulated supply for 2.8 V min 2.7 V / max 2.85 V RX regulated supply for 2.8 V min 2.7 V / max 2.85 V TX regulated supply for 2.8 V min 2.7 V / max 2.85 V SYNT regulated supply for 2.8 V min 2.7 V / max 2.85 V VCTCXO regulated supply for 2.8 V min 2.7 V / max 2.85 V TX 2.8 V min 2.7 V / max 2.85 V
CCON- Charger interrupt TINT SLCLK 32.768 kHz, power on
RFCEN active state RFCSE active state TTLED RFC 19.44 MHz sinewave
0.2Vpp1V pp sinewave pulsed DC (0V/2.8V) pulsed DC (0V/2.8V) 0 2.3 V, typ. 1.15 V (room temp) @level 10 typ.ca 0.5 V pulse @level 2 typ.ca 1.7 V pulse 0.4 V 2.2 V 0 V 1.5 V typ. nominal 2.8 V
TP24, N250 pin 63 TP25, N250 pin 64 TP26, N250 pin 13 TP27, N250 pin 15 TP33, R939 TP34, R220 TP35, N702 pins 9,11,12.13,14 NOTE:
VR7BA VR7 regulator exSE ternal transistor base current VREF VBB
COB9.72 MHz, active BACLK state ADATA AFC TXC DETO VAPC VR8 VR 12 active state Autom.Freq.control TX power control voltage active state active state power on
TP13, N150 pin 13 TP14, N150 pin 55
ref.voltage for N150 1.5 V +/ 1.5% regulated supply for 2.8 V min 2.7 V / max 2.85 V BaseBand regulated supply for 2.8 V min 2.7 V / max 2.85 V COBBA regulated supply to 2GHz PLL 5.0 V min 4.8 V / max 5.2 V
TP15, N150 pin 22 VR6 TP16, N150 pin 32 TP17, N150 pin 36 V5V VSIM
regulated supply for 3.0 V min 2.8 V / max 3.2 V flashing RESET Power up/ down reset state 0 V, normal state 2.8 V
Layout diagram has also upper band (TDMA1900) components included, which are not in actual US4U PCB. Notice this also in testpoints.
TP18, N150 pin 54 PURX Original 10/98 Updated 11/99
3/A311
US4RSM
NSC1
Circuit Diagram of System Blocks
(Version 06.43 Edit 10)
Original 10/98 Updated 11/99
3/A312
US4RSM
NSC1
Circuit Diagram of Power Supply (Version 06.43
Edit 9)
TP4
TP5
TP11
TP12
TP13
TP14
TP15
TP6
TP7
TP8
TP9
TP10
TP16 TP20
TP17
TP18
TP19
Original 10/98 Updated 11/99
3/A313
US4RSM
NSC1
Circuit Diagram of CTRLU Block (Version 06.43 Edit 10)
TP3
TP1
TP2
Original 10/98 Updated 11/99
3/A314
US4RSM
NSC1
Circuit Diagram of Audio
(Version 06.43 Edit 7)
TP21
TP22
TP23
TP24
TP25 TP26 TP27
Original 10/98 Updated 11/99
3/A315
US4RSM
NSC1
Circuit Diagram of Transmitter (Version 06.43
Edit 11)
TP33
TP34
Original 10/98 Updated 11/99
3/A316
US4RSM
NSC1
Circuit Diagram of Receiver (Version 06.43.
Edit 7)
Original 10/98 Updated 11/99
3/A317
US4RSM
NSC1
Circuit Diagram of Synthesizer (Version 06.43
Edit 6)
TP
TP
Original 10/98 Updated 11/99
3/A318
US4RSM
NSC1
Circuit Diagram of RF Block (Version
06.43 Edit 4)
Original 10/98 Updated 11/99
3/A319
US4RSM
NSC1
Circuit Diagram of RFBB Interface (Version 06.43 Edit 7)
Original 10/98 Updated 11/99
3/A320
US4RSM
NSC1
Layout Diagram 1/2 of US4RSM
(Layout version 06)
testpoint J200 J201 J202 J203 TP1, D202 pin 78 TP2, D202 pin 77
name
condition Only for R&D use Only for R&D use Only for R&D use Only for R&D use
dclevel
aclevel
HOOKINT HEADSETINT RSENSE VOUT VCTCXO CTL CTL
Remote controlheadset Headset connected False transmission indicator VOUT detection VOUT detection power on active state ch 300 active state ch 1000
pulse active 2.8 V, nonactive 0 V pulse active 0 V, nonactive 2.8 V Irregular from 0 V to 2.8 V min 0V, typ 3.6 V, max 5.2 V min 0V, typ 3.6 V, max 5.2 V typ. 0.8 V 1.2 Vpp siniwave 19.44 MHz typ. 2.2 V typ. 2.2 V
TP3, D202 pin 117 TXF TP4, R153 TP5, R153 TP30, G850 pin 3 TP31, G820 pin 3 TP32, G860 pin 3
NOTE: Layout diagram has also upper band (TDMA1900) components included, which are not in actual US4U PCB. Notice this also in testpoints.
Original 10/98 Updated 11/99
3/A321
US4RSM
NSC1
Layout Diagram 2/2 of US4RSM
(Layout version 06)
testpoint TP6, N150 pin 11 TP7, N150 pin 15 TP8, N150 pin 4 TP9, N150 pin 9 TP10, N150 pin 25 TP11, N150 pin 20 TP12, N150 pin 19
name VR5 VR4 VR3 VR2 VR1 VR7
condition supply for TX
dclevel 2.8 V min 2.7 V / max 2.85 V
aclevel
testpoint TP19, N150 pin 52 TP20, N150 pin 48 TP21, N250 pin 1 TP22, N250 pin 54 TP23, N250 pin 2
name
condition/type
dclevel pulse active 2.8 V, nonactive 0 V pulsed DC (0V/2.8 V) pulse active 2.8 V, nonactive 0 V pulse active 2.8 V, nonactive 0 V
aclevel
regulated supply for 2.8 V min 2.7 V / max 2.85 V RX regulated supply for 2.8 V min 2.7 V / max 2.85 V TX regulated supply for 2.8 V min 2.7 V / max 2.85 V SYNT regulated supply for 2.8 V min 2.7 V / max 2.85 V VCTCXO regulated supply for 2.8 V min 2.7 V / max 2.85 V TX 2.8 V min 2.7 V / max 2.85 V
CCON- Charger interrupt TINT SLCLK 32.768 kHz, power on
RFCEN active state RFCSE active state TTLED RFC 19.44 MHz sinewave
0.2Vpp1V pp sinewave pulsed DC (0V/2.8V) pulsed DC (0V/2.8V) 0 2.3 V, typ. 1.15 V (room temp) @level 10 typ.ca 0.5 V pulse @level 2 typ.ca 1.7 V pulse 0.4 V 2.2 V 0 V 1.5 V typ. nominal 2.8 V
TP24, N250 pin 63 TP25, N250 pin 64 TP26, N250 pin 13 TP27, N250 pin 15 TP33, R939 TP34, R220 TP35, N702 pins 9,11,12.13,14 NOTE:
VR7BA VR7 regulator exSE ternal transistor base current VREF VBB
COB9.72 MHz, active BACLK state ADATA AFC TXC DETO VAPC VR8 VR 12 active state Autom.Freq.control TX power control voltage active state active state power on
TP13, N150 pin 13 TP14, N150 pin 55
ref.voltage for N150 1.5 V +/ 1.5% regulated supply for 2.8 V min 2.7 V / max 2.85 V BaseBand regulated supply for 2.8 V min 2.7 V / max 2.85 V COBBA regulated supply to 2GHz PLL 5.0 V min 4.8 V / max 5.2 V
TP15, N150 pin 22 VR6 TP16, N150 pin 32 TP17, N150 pin 36 V5V VSIM
regulated supply for 3.0 V min 2.8 V / max 3.2 V flashing RESET Power up/ down reset state 0 V, normal state 2.8 V
Layout diagram has also upper band (TDMA1900) components included, which are not in actual US4U PCB. Notice this also in testpoints.
TP18, N150 pin 54 PURX
Original 10/98 Updated 11/99
3/A322