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To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.

Renesas Technology Corp. Customer Support Dept. April 1, 2003

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

DESCRIPTION
The M37220M3-XXXSP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 42-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy programming. The M37220M3-XXXSP has a PWM output function and a OSD display function, so it is useful for a channel selection system for TV.

PIN CONFIGURATION (TOP VIEW)

HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

P52/R P53/G P54/B P55/OUT P20/SCLK P21/SOUT P22/SIN P10 P11 P12 P13 P14 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P33 OSC2/P34 VCC

M37220M3-XXXSP

FEATURES

Number of basic instructions ..................................................... 71 Memory size
ROM ........................................................ 12 K bytes RAM ......................................................... 256 bytes ROM for display......................................... 4 K bytes RAM for display .......................................... 80 bytes The minimum instruction execution time .......................................... 0.5s (at 8 MHz oscillation frequency) Power source voltage .................................................. 5 V 10 % Power dissipation ............................................................. 165 mW (at 8 MHz oscillation frequency, V CC=5.5V, at CRT display) Subroutine nesting ....................................... 96 levels (maximum) Interrupts ....................................................... 13 types, 13 vectors 8-bit timers .................................................................................. 4 Programmable I/O ports (Ports P0, P1, P2, P30P3 2) .............. 27 Input ports (Ports P33, P34) ......................................................... 2 Output ports (Ports P52P5 5) ...................................................... 4 12 V withstand ports ....................................................................6 LED drive ports ........................................................................... 4 Serial I/O ............................................................ 8-bit ! 1 channel A-D comparator (6-bit resolution) ................................ 6 channels D-A converter (6-bit resolution) ................................................... 2 PWM output circuit ......................................... 14-bit ! 1, 8-bit ! 6



Outline 42P4B

CRT display function
Number of display characters ................ 24 characters ! 2 lines (16 lines maximum) Kinds of characters ..................................................... 128 kinds Dot structure .......................................................... 12 ! 16 dots Kinds of character sizes .................................................. 3 kinds Kinds of character colors (It can be specified by the character) maximum 7 kinds (R, G, B) Kinds of raster colors (maximum 7 kinds) Display position Horizontal .................................................................. 64 levels Vertical .................................................................... 128 levels Bordering (horizontal and vertical)

APPLICATION
TV

SIN SCLK SOUT

PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

P0 (8)

INT3

P1 (8) P3 (3)

P2 (8)

INT2 INT1

OUT B G R
16 17 26 27

10 9 8 7 6 5 4 3

28 29 30 31 32 33 34 35

15 14 13 12 11 36 37 38

39 40 41 42

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

I/O port P0

I/O port P1

I/O port P2

D-A

I/O ports P30P32

Output ports P52P55

VSYNC HSYNC
2 1

2
VCC VSS CNVSS
18 24 23 21 22

FUNCTIONAL BLOCK DIAGRAM of M37220M3-XXXSP
Input ports P33, P34 Clock input for display Clock output for display OSC1 OSC2

Clock input Clock output XIN XOUT ( ) Timing output
25

Reset input RESET

19

20

Clock generating circuit
TIM2 TIM3

Data bus

Timer count source selection circuit Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8) Control signal Instruction decoder Instruction register (8) CRT circuit Timer 4 T4 (8)

RAM 256 bytes
Program counter

Program counter

ROM 12 K bytes

PCH (8) PCL (8)

Address bus

8-bit arithmetic and logical unit Index register Y (8) Stack pointer S (8)

Accumulator A (8)

Processor status register PS (8)

Index register X (8)

A-D comparator
14-bit PWM circuit

D-A converter

SI/O(8)

8-bit PWM circuit

P5 (4)

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

FUNCTIONS
Parameter Number of basic instructions Instruction execution time Clock frequency Memory size ROM RAM CRT ROM CRT RAM Input/Output ports P0 P10P1 7 P20, P2 1 P22P2 7 P30, P3 1 P32 P33, P3 4 P52P5 5 Serial I/O A-D comparatpr D-A converter PWM output circuit Timers Subroutine nesting Interrupt I/O I/O I/O I/O I/O I/O Input Output Functions 71 0.5 s (the minimum instruction execution time, at 8 MHz oscillation frequency) 8 MHz (maximum) 12K bytes 256 bytes 4K bytes 80 bytes 8-bit ! 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) 8-bit ! 1 (CMOS input/output structure, can be used as A-D input pins, INT input pin) 2-bit ! 1 (CMOS input/output or N-channel open-drain output structure, can be used as serial output pins) 6-bit ! 1 (CMOS input/output structure, can be used as serial input pin, external clock input pins) 2-bit ! 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins, D-A conversion output pins) 1-bit ! 1 (N-channel open-drain output structure) 2-bit ! 1 (can be used as CRT display clock I/O pins) 4-bit ! 1 (CMOS output structure, can be used as CRT output pins) 8-bit ! 1 6 channels (6-bit resolution) 2 (6-bit resolution) 14-bit ! 1, 8-bit ! 6 8-bit timer ! 4 96 levels (maximum) External interrupt ! 3, Internal timer interrupt ! 4, Serial I/O interrupt ! 1, CRT interrupt ! 1, X IN/4096 interrupt ! 1, V SYNC interrupt ! 1, BRK interrupt ! 1 2 built-in circuits (externally connected a ceramic resonator or a quartzcrystal oscillator) 5 V 10 % CRT ON CRT OFF In stop mode Operating temperature range Device structure Package CRT display function Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of character colors Display position (horizontal, vertical) 165 mW typ. (at oscillation frequency fCPU = 8 MHz, fCRT = 8 MHz) 110 mW typ. (at oscillation frequency fCPU = 8 MHz) 1.65 mW (maximum) 10 C to 70 C CMOS silicon gate process 42-pin shrink plastic molded DIP 20 characters ! 2 lines (maximum 16 lines by software) 12 ! 16 dots 128 kinds 3 kinds Maximum 7 kinds (R, G, B); can be specified by the character 64 levels (horizontal) ! 128 levels (vertical)

Clock generating circuit Power source voltage Power dissipation

3

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

PIN DESCRIPTION
Pin VCC, VSS Name Power source Input/ Output Functions Apply voltage of 5 V 10 % (typical) to VCC, and 0 V to VSS.

CNVSS RESET

CNVSS Reset input Input

This is connected to VSS. To enter the reset state, the reset input pin must be kept at a "L" for 2 s or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this "L" condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the X IN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. The note out of this Table gives a full of port P0 function. Pins P00P05 are also used as PWM output pins PWM0PWM5 respectively.The output structure is N-channel open-drain output. Pins P06, P0 7 are also used as external interrupt input pins INT2, INT1 respectively. Pins P06 is also used as an analog interrupt input pin A-D4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P15P1 7 are also used as an analog input pins A-D1 to A-D3. Pin P15 is also used as an external interrupt input pins INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P23, P2 4 is also used an external clock input pins TIM3, TIM2 respectively. Pins P21, P2 2 are also used serial I/O data input/output pins SOUT, SIN respectively. The output structure is N-channel open-drain output. Pin P20 is also used serial I/O syncronizing clock input/output pin S CLK. The output structure is N-channel open-drain output. Ports P30P32 are a 3-bit I/O port and have basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected as the ports P30 and P31. The output structure of port P32 is N-channel open-drain output. Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively. Pins P3 0, P3 1 are also used as D-A conversion output pins DA1, DA2 respectively. Ports P33, P3 4 are a 2-bit input port. Pin P33 is also used as CRT display clock input pin OSC1. Pin P34 is also used as CRT display clock output pin OSC2.The output structure is CMOS output.

XIN XOUT P00/PWM0 P05/PWM5, P06/INT2/ A-D4, P07/INT1

Clock input Clock output I/O port P0 PWM output External interrupt input Analog input I/O port P1 Analog input External interrupt input I/O port P2 External clock input Serial I/O data input/output Serial I/O synchronizing clock input/ output

Input Output I/O Output Input Input I/O Input Input I/O Input I/O I/O

P10P14 , P15/A-D1 INT3, P16/A-D2, P17/A-D3 P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25P2 7

P30/A-D5/ DA1, P31/A-D6/ DA2, P32 P33/OSC1, P34/OSC2

I/O port P3

I/O

Analog input D-A conversion output Input port P3 Clock input for CRT display Clock output for CRT display

Input Output Input Input Output

4

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

PIN DESCRIPTION (continued)
P52/R, P53/G, P54/B, P55/OUT HSYNC VSYNC D-A Output port P5 CRT output HSYNC input VSYNC input DA output Output Output Input Input Output Ports P5 2P55 are a 4-bit output port. The output structure is CMOS output. Pins P52P55 are also used as CRT output pins R, G, B, OUT respectively. The output structure is CMOS output. This is a horizontal synchronizing signal input for CRT display. This is a vertical synchronizing signal input for CRT display. This is an output pin for 14-bit PWM.

Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input ("0") or an output ("1"). The pins programmed as "1" in the direction register are output pins. When pins are programmed as "0," they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output "L" voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.

5

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The M37220M3-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User's Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used.

CPU Mode Register
The CPU mode register contains the stack page selection bit. The CPU mode register is allocated at address 00FB 16.

7 1 1 1 1 1

0 0 0

CPU mode register (CPUM : address 00FB16) Fix these bits to "0."

Stack page selection bit (Note) 0 : Zero page 1 : 1 page

Fix these bits to "1." Note : Please beware of this bit when programming because it is set to "1" after the reset release.

Fig. 1. Structure of CPU mode register

6

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MEMORY Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.

Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.

Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.

RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.

ROM
ROM is used for storing user programs as well as the interrupt vector area.

Special Page
The 256 bytes from addresses FF0016 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.

RAM for Display
RAM for display is used for specifying the character codes and colors to display.

ROM for Display
ROM for display is used for storing character data.

000016 Zero page RAM (256 bytes) 00C016 SFR area 00FF16 ROM for display (4 K bytes)

1000016

10FFF16

013F16 Not used RAM for display (Note) (80 bytes) 060016 06B316 Not used Not used

D00016

ROM (12 K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area

Special page 1FFFF16

Note : Refer to Table 8. Contents of CRT display RAM.

Fig. 2. Memory map

7

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

sSFR area (addresses C016 to DF16)
: Nothing is allocated : Fix this bit to "0" (do not write "1") 0 : "0" immediately after reset 1 : "1" immediately after reset ? : undefined immediately after reset

Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16

Register

b7

Bit allocation

b0 b7

State immediately after reset

b0

Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3)

0 0

0 0

0 0

Port P5 (P5) Port P5 direction register (D5) Port P3 output mode control register (P3S) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN)
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 PN4 PN3 PN2 DA2S DA1S P31S P30S

0 0 0 0

0 0 0 0

? 0 0 ?

0

0

0

Serial I/O mode register (SM) Serial I/O regsiter (SIO) DA1 conversion register (DA1) DA2 conversion register (DA2)

SM6 SM5

SM3 SM2 SM1 SM0

0 0 0

0 0 0

0 ? ?

DA15 DA14 DA13 DA12 DA11 DA10 DA25 DA24 DA23 DA22 DA21 DA20

? 0016 ? 0016 ? 0016 ? ? 0 0 ? ? ? ? 0 0 ? 0 0 ? ? ? ? ? ? ? ? 0016 0 0 ? ? ? ? ? 0 0 ? ? ? ? ?

? 0

? 0

? 0

? 0 0 ?

? 0 0 ?

? 0 0 ?

0

0

0

0 ? ?

0 ? ?

0 ? ?

Fig. 3. Memory map of SFR (special function register) (1)

8

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

sSFR area (addresses E016 to FF16)
: Nothing is allocated : Fix this bit to "0" (do not write "1") : Fix this bit to "1" (do not write "0") 0 : "0" immediately after reset 1 : "1" immediately after reset ? : undefined immediately after reset

Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16

Register

b7

Bit allocation

b0 b7

State immediately after reset 0 ? ? 0 0 0 0 0 0 0 0 ? ? 0 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 ? ? ? ? 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0

b0

Horizontal position register (HR) Vertical register 1 (CV1) Vertical register 2 (CV2) Character size register (CS) Border selection register (MD) Color register 0 (CO0) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) CRT control register (CC) CRT port control register (CRTP) CRT clock selection register (CK) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 1 (TM1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer 12 mode register (T12M) Timer 34 mode register (T34M) PWM5 register (PWM5)

HR5 HR4 HR3 HR2 HR1 HR0
CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20

0 0 0 0 0 0 0 0 0 0

0 ? ? ? ? 0 0 0 0 0

CS21 CS20 CS11 CS10 MD20 CO05 CO15 CO25 CO35 CO03 CO02 CO01 CO13 CO12 CO11 CO23 CO22 CO21 CO33 CO32 CO31 MD10

CC2 CC1 CC0

OP7 OP6 OP5 OUT

R/G/B VSYC HSYC

CK1 CK0
ADM4 ADM2 ADM1 ADM0

ADC5 ADC4 ADC3 ADC2 ADC1 ADC0

0 0 0

0 0 0

0 0 0

T12M4 T12M3 T12M2 T12M1 T12M0 T34M5 T34M4 T34M3 T34M2 T34M1 T34M0

0 0

0 0

0 0

Interrupt input polarity register (RE) Test register (TEST) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)

RE5 RE4 RE3 CK0

0
CM2

0 1 0 0 0 0

0 1 0 0 0 0

IT3R

VSCR CRTR TM4R TM3R TM2R TM1R

MSR CK0
IT3E

S1R 1T2R 1T1R

VSCE CRTE TM4E TM3E TM2E TM1E

MSE

S1E 1T2E 1T1E

1 0 0 0 0

? 0016 0 0 ? 0 0 0 FF16 0716 FF16 0716 0 0 0 0 ? ? ? CK0 0 0 0016 1 1 0 0 CK0 0 0 0 0 0 0

0 0 0

0 0 0

0 0 0

0 0

0 0

0 0

0 1 0 0 0 0

0 0 0 0 0 0

? 0 0 0 0 0

Fig. 4. Memory map of SFR (special function register) (2)

9

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

INTERRUPTS
Interrupts can be caused by 13 different sources consisting of 3 external, 9 internal, and 1 software sources. Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, (1) The contents of the program counter and processor status register are automatically stored into the stack. (2) The interrupt disable flag I is set to "1" and the corresponding interrupt request bit is set to "0." (3) The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to "1." All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figure 5 shows the structure of the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is "1," interrupt request bit is "1," and the interrupt disable flag is "0." The interrupt request bit can be set to "0" by a program, but not set to "1." The interrupt enable bit can be set to "0" and "1" by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 6 shows interrupt control.

Interrupt Causes
(1) VSYNC and CRT interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The CRT interrupt occurs after character block display to the CRT is completed. (2) INT1, INT2, INT3 interrupts With an external interrupt input, the system detects that the level of a pin changes from "L" to "H" or from "H" to "L," and generates an interrupt request. The input active edge can be selected by bits 3, 4 and 5 of the interrupt input polarity register (address 00F916 ) : when this bit is "0," a change from "L" to "H" is detected; when it is "1," a change from "H" to "L" is detected. Note that all bits are cleared to "0" at reset. (3) Timer 1, 2, 3 and 4 interrupts An interrupt is generated by an overflow of timer 1, 2, 3 or 4. (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) XIN/4096 interrupt This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM output control register 1 to "0." (6) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).

Table 1. Interrupt vector addresses and priority Interrupt source Reset CRT interrupt INT2 interrupt INT1 interrupt Timer 4 interrupt XIN/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt INT3 interrupt BRK instruction interrupt Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 Vector addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF9 16, FFF816 FFF5 16, FFF416 FFF3 16, FFF216 FFF1 16, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE9 16, FFE816 FFE5 16, FFE416 FFDF16, FFDE16 Active edge selectable Non-maskable (software interrupt) Active edge selectable Active edge selectable Non-maskable Remarks

10

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

7

0 Interrupt request register 1 (IREQ1 : address 00FC16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CRT interrupt request bit VSYNC interrupt request bit INT3 interrupt request bit

7 0

0 Interrupt request register 2 (IREQ2 : address 00FD16) INT1 interrupt request bit INT2 interrupt request bit Serial I/O interrupt request bit XIN/4096 interrupt request bit Fix this bit to "0."

0 : No interrupt request issued 1 : Interrupt request issued

7

0 Interrupt control register 1 (ICON1 : address 00FE16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CRT interrupt enable bit VSYNC interrupt enable bit INT3 interrupt enable bit

7 0 0 0 0

0 Interrupt control register 2 (ICON2 : address 00FF16) INT1 interrupt enable bit INT2 interrupt enable bit Serial I/O interrupt enable bit Fix this bit to "0." XIN/4096 interrupt enable bit Fix these bits to "0."

0 : Interrupt disabled 1 : Interrupt enabled

7 0 0 0

0 Interrupt input polarity register (RE : address 00F916) Fix these bits to "0." INT1 polarity switch bit 0 : Positive polarity 1 : Negative polarity INT2 polarity switch bit 0 : Positive polarity 1 : Negative polarity INT3 polarity switch bit 0 : Positive polarity 1 : Negative polarity Fix this bit to "0."

Fig. 5. Structure of interrupt-related registers

11

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Interrupt request bit Interrupt enable bit

Interrupt disable flag I

BRK instruction Reset

Interrupt request

Fig. 6. Interrupt control

12

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

TIMERS
The M37220M3-XXXSP has 4 timers: timer 1, timer 2, timer 3, and timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F0 16 to 00F316). The count value is decremented by 1. The timer interrupt request bit is set to "1" by a timer overflow at the next count pulse after the count value reaches "00 16".

(1) Timer 1
Timer 1 can select one of the following count sources: f(X IN)/16 f(X IN)/4096 The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00F4 16). Timer 1 interrupt request occurs at timer 1 overflow.

At reset, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716 " in timer 4. The f(XIN)/16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set bit 0 of the timer 34 mode register (address 00F516) to "0" before the execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. The structure of timer-related registers is shown in Figure 7.



(2) Timer 2
Timer 2 can select one of the following count sources: f(X IN)/16 Timer 1 overflow signal External clock from the P24/TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00F4 16). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.



(3) Timer 3
Timer 3 can select one of the following count sources: f(X IN)/16 External clock from the HSYNC pin External clock from the P23/TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00F516) Timer 3 interrupt request occurs at timer 3 overflow.



(4) Timer 4
Timer 4 can select one of the following count sources: f(X IN)/16 f(X IN)/2 Timer 3 overflow signal The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address 00F5 16). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.



13

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

7 0

0 Timer 12 mode register (T12M : address 00F416)

7

0 Timer 34 mode register (T34M : address 00F516)

Timer 1 count source selection bit 0 : f(XIN)/16 1 : f(XIN)/4096

Timer 3 count source selection bit 0 : f(XIN)/16 1 : External clock

Timer 2 count source selection bit 0 : Internal clock 1 : External clock from P24/TIM2 pin

Timer 4 internal count source selection bit 0 : Timer 3 overflow 1 : f(XIN)/16

Timer 1 count stop bit 0 : Count start 1 : Count stop

Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 4 count stop bit 0 : Count start 1 : Count stop

Timer 2 count stop bit 0 : Count start 1 : Count stop

Timer 2 internal count source selection bit 0 : f(XIN)/16 1 : Timer 1 overflow

Timer 4 count source selection bit 0 : Internal clock 1 : f(XIN)/2

Fix this bit to "0."

Timer 3 external count source selection bit 0 : External clock from P23/TIM3 pin 1 : External clock from HSYNC pin

Fig. 7. Structure of timer-related registers

14

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Data bus

8

1/4096

Timer 1 latch (8) 8

XIN

1/2

1/8 T12M0 T12M2

Timer 1 (8) 8 T12M4 8

Timer 1 interrupt request

Timer 2 latch (8) 8 P24/TIM2 T12M1 T12M3 8 8 FF16 P23/TIM3 T34M5 Timer 3 latch (8) 8 Timer 3 (8) T34M0 T34M2 8 8 0716 Timer 4 latch (8) 8 Timer 4 (8) T34M4 T34M3 8 Timer 4 interrupt request Timer 3 interrupt request Timer 2 (8) Timer 2 interrupt request

HSYNC

Reset STP instruction

Selection gate : Connected to black colored side at reset T34M1 T12M : Timer 12 mode register T34M : Timer 34 mode register

Notes 1 : "H" pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2 : When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3 : In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used

Fig. 8. Timer block diagram

15

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

SERIAL I/O
The M37220M3-XXXSP has a built-in serial I/O which can either transmit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 9. The synchronizing clock I/O pin (SCLK), and data I/O pins (SOUT , SIN) also function as port P2. Bit 2 of the serial I/O mode register (address 00DC16) selects whether the synchronizing clock is supplied internally or externally (from the P20/SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) is divided by 4, 16, 32, or 64. Bit 3 selects whether port P2 is used for serial I/O or not. To use the P22/SIN pin as the SIN pin, set the bit 2 of the port P2 direction register (address 00C516) to "0." The operation of the serial I/O function is described below. The function of the serial I/O differs depending on the clock source; external clock or internal clock.

Data bus XIN 1/2 1/2 Frequency divider
1/4 1/8 1/16

SM2
S

SM1 SM0

Synchronization circuit

Selection gate : Connected to black colored side at reset. SM : Serial I/O mode register

P20 latch P20/SCLK SM3 P21 latch P21/SOUT SM3 P22/SIN SM6 SM5: LSB MSB (Note) Serial I/O shift register (8) (Address 00DD16) 8 Serial I/O counter (8) Serial I/O interrupt request

Note: When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register.

Fig. 9. Serial I/O block diagram

16

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Internal clock--the serial I/O counter is set to "7" during write cycle into the serial I/O register (address 00DD16), and transfer clock goes "H" forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes "0" and the transfer clock stops at "H." At this time the interrupt request bit is set to "1." External clock--when an external clock is selected as the clock source, the interrupt request is set to "1" after the transfer clock has counted 8 times. However, transfer operation does not stop, so control the clock externally. Use the external clock of 1MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 11. When using an external clock for transfer, the external clock must be held at "H" for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions as SEB and CLB instructions. 2: When an external clock is used as the synchronizing clock, write transmit data to the serial I/O register at "H" of the transfer clock input level.

7 0

0 Serial I/O mode register (SM : address 00DC16) Internal synchronizing clock selection bits b1 b0 0 0 : f(XIN)/4 0 1 : f(XIN)/16 1 0 : f(XIN)/32 1 1 : f(XIN)/64 Synchronizing clock selection bit 0 : External clock 1 : Internal clock Serial I/O port selection bit 0 : P20, P21 functions as port 1 : SCLK, SOUT Fix this bit to "0." Transfer direction selection bit 0 : LSB first 1 : MSB first Serial input pin selection bit 0 : Input signal from SIN pin 1 : Input signal from SOUT pin

Fig. 10. Structure of serial I/O mode register

Synchroninzing clock

Transfer clock Serial I/O register write signal Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7

(Note)

Interrupt request bit is set to "1" Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Fig. 11. Serial I/O timing (for LSB first)

17

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Serial I/O Common Transmission/Reception Mode
By writing "1" to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 12 shows signals on serial I/O common transmission/reception mode. Note: When receiving the serial data after writing "FF16" to the serial I/O register.

P20/SCLK

Clock

P21/SOUT "1" Serial I/O shift register (8) P22/SIN "0" SM6

SM: Serial I/O mode register

Fig. 12. Signals on serial I/O common transmission/reception mode

18

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

PWM OUTPUT FUNCTION
The M37220M3-XXXSP is equipped with a 14-bit PWM (DA) and six 8-bit PWMs (PWM0PWM5). DA has a 14-bit resolution with the minimum resolution bit width of 0.25s (for f(XIN) = 8 MHz) and a repeat period of 4096s. PWM0PWM5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4s (for f(XIN) = 8 MHz) and repeat period of 1024s. Figure 13 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0PWM5 using f(XIN) divided by 2 as a reference signal.

(4) Operating of 14-bit PWM
As with 8-bit PWM, set the bit 0 of the PWM output control register 1 (address 00D516) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. Next, select the output polarity by bit 2 of the PWM output control register 2 (address 00D6 16). Then, the 14-bit PWM outputs from the D-A output pin by setting bit 1 of the PWM output control register 1 to "0" (at reset, this bit already set to "0" automatically) to select the DA output. The output example of the 14-bit PWM is shown in Figure 15. The 14-bit PWM divides the data of the DA latch into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data "D H." A "H" level area with a length ! DH ("H" level area of fundamental waveform) is output every short area of "t" = 256 = 64s ( is the minimum resolution bit width of 0.25s). The "H" level area increase interval (tm) is determined with the low-order 6-bit data "DL ." The "H" level are of smaller intervals "tm" shown in Table 2 is longer by than that of other smaller intervals in PWM repeat period "T" = 64t. Thus, a rectangular waveform with the different "H" width is output from the D-A pin. Accordingly, the PWM output changes by unit pulse width by changing the contents of the DA-H and DA-L registers. A length of entirely "H" output cannot be output, i. e. 256/ 256.

(1) Data Setting
When outputting DA, first set the high-order 8 bits to the DA-H register (address 00CE16 ), then the low-order 6 bits to the DA-L register (address 00CF16). When outputting PWM0PWM5, set 8-bit output data in the PWMi register (i means 0 to 5; addresses 00D016 to 00D416, 00F616 ).

(2) Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. Also, data transfer from the DA register (addresses 00CE16 and 00CF16) to the 14-bit PWM circuit is executed at writing data to the DA-L register (address 00CF16 ). Reading from the DA-H register (address 00CE16) means reading this transferred data. Accordingly, it is possible to confirm the data being output from the D-A output pin by reading the DA register.

(5) Output after Reset
At reset, the output of port P00P05 is in the high-impedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.

(3) Operating of 8-bit PWM
The following is the explanation about PWM operation. At first, set the bit 0 of PWM output control register 1 (address 00D516) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. PWM0PWM5 are also used as pins P00P0 5 respectively. For PWM0PWM5, set the corresponding bits of the port P0 direction register to "1" (output mode). And select each output polarity by bit 3 of the PWM output control register 2(address 00D616 ). Then, set bits 2 to 7 of the PWM output control register 1 to "1" (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 14 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses relative to the weight of each bit (bits 0 to 7) are output inside the circuit during 1 cycle. Refer to Figure 14 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 14 (b). 256 kinds of output ("H" level area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely "H" output cannot be output, i.e. 256/256.

19

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Table 2. Relation between the low-order 6-bit data and high-level area increase interval Low-order 6 bits of data Area longer by than that of other tm (m = 0 to 63) 000000 000001 000010 000100 001000 010000 100000
LSB

Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................ 57, 59, 61, 63

Data bus

DA-H register (Address : 00CE16) b7 DA latch (14 bits)
MSB 8 6 6 14 LSB

b0

DA-L register (Note) (Address : 00CF16)

PN2 14-bit PWM circuit

PN4 PW1

DA D-A

XIN

1/2 PW0

PWM timing generating circuit

PWM register (Address : 00D016)

b7
8

b0

PN3 8-bit PWM circuit

P00 PW2 P01

D00

PWM0

D01

PWM1

PWM1 register (Address : 00D116)

PW3 P02 D02 PWM2

Selection gate : Connected to black colored side when reset. Pass gate Inside of with the others. is as same contents

PWM2 register (Address : 00D216)

PW4 P03 PW5 P04 PW6 P05 PW7 D05 PWM5 D04 PWM4 D03 PWM3

PWM3 register (Address : 00D316)

P0 : Port P0 register D0 : Port P0 direction register PW : PWM output control register 1 PN : PWM output control register 2

PWM4 register (Address : 00D416)

PWM5 register (Address : 00F616)

Note: The DA-L register also functions as the low-order 6 bits of the DA latch.
Fig. 13. PWM block diagram

20

13 5 7 9

20

30

40

50

60

70

80

90

100

110

120

130

140

150

160

170

180

190

200

210

220

230

240

250 255

Bit 7
50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254

Fig. 14. 8-bit PWM timing
52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 56 88 120 152 184 216 232 200 168 136 104 72 248 80 112 144 176 208 240 96 160 224 64 192 128

2

6 10

14

18

22 26 30

34

38

42 46

Bit 6

4

12

20

28

36

44

Bit 5

8

24

40

Bit 4

16

48

Bit 3

32

Bit 2

Bit 1

Bit 0

(a) Pulses showing the weight of each bit

0016 (0)

0116 (1)

1816 (24)

FF16 (255)

t T = 256 t PWM output t = 4 s T = 1024 s f(XIN) = 8 MHz (b) Example of 8-bit PWM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP

21

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Set "2C16" to DA-H register.

Set "2816" to DA-L register.

b7 b6 b5 b4 b3 b2 b1 b0 [DA-H 0 0 1 0 1 1 0 0 DH register] At writing of DA-L b13 [DA latch] 0 0 1 0 1 1 0 b6 b5
0

b7 b6 b5 b4 b3 b2 b1 b0 [DA-L register]
Undefined

1

0

1

0

0

0

DL

At writing of DA-L b0 0 1 0 0 0

1

These bits decide "H" level area of fundamental waveform.
"H" level area of fundamental waveform

These bits decide smaller interval "tm" in which "H" leval area is ["H" level area of fundamental waveform + ].

=

Minimum resolution bit width 0.25s

!

High-order 8-bit value of DA latch

Fundamental waveform

Waveform of smaller interval "tm" specified by low-order 6 bits 0.25 s!44 0.25 s!45 0.25 s 14-bit PWM output 2C 2B 2A ... 03 02 01 00 8-bit counter FF FE FD ... D6 D5 D4 D3 ... 02 01 00

14-bit PWM output 2C 2B 2A ... 03 02 01 00 8-bit counter FF FE FD ... D6 D5 D4 D3 ... 02 01 00

Fundamental waveform of smaller interval "tm" which is not specified by low-order 6 bits is not changed. 0.25 s!44 = 0.25 s

14-bit PWM output t0 DA latch of Low-order 6-bit output Repeat period T = 4096 s t1 t2 t3 t4 t5 t59 t60 t61 t62 t63

Fig. 15. 14-bit PWM output example (f(XIN)= 8 MHz)

22

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

7

0 PWM output control register 1 (PW: address 00D516) DA, PWM count source selection bit 0 : Count source supply 1 : Count source stop DA/PN4 output selection bit 0 : DA output 1 : PN4 output P00/PWM0 output selection bit 0 : P00 output 1 : PWM0 output P01/PWM1 output selection bit 0 : P01 output 1 : PWM1 output P02/PWM2 output selection bit 0 : P02 output 1 : PWM2 output P03/PWM3 output selection bit 0 : P03 output 1 : PWM3 output P04/PWM4 output selection bit 0 : P04 output 1 : PWM4 output P05/PWM5 output selection bit 0 : P05 output 1 : PWM5 output

7

0 PWM output control register 2 (PN: address 00D616)

DA output polarity selection bit 0 : Positive polarity 1 : Negative polarity PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity DA general-purpose output bit 0 : Output "L" 1 : Output "H"

Fig. 16. Structure of PWM-related registers

23

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

A-D COMPARATOR
A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 19. The reference voltage "Vref" for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 00EF16). The comparison result of the analog input voltage and the reference voltage "Vref" is stored in bit 4 of the A-D control register 1 (address 00EE16). For A-D comparison, set "0" to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to Vref to be compared to the bits 0 to 5 of the A-D control register 2. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ! 8).

7

0

A-D control register 2 (AD2: address 00EF16)

D-A converter set bits Refer to Table 3.

Fig.18. Structure of A-D control register 2

7

0

A-D control register 1 (AD1: address 00EE16)

Table 3. Relation between contents of A-D control register 2 and reference voltage "Vref" Bit 5 0 0 0
...

Analog input pin selection bits
b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0: Do not set. 1:

A-D control register 2 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 0 0 0 0 0 0 0 0 1
... ... ... ...

Bit 0 0 1 0
...

Reference voltage "Vref" 1/128 VCC 3/128 VCC 5/128 VCC
...

Storage bit of comparison result 0 : Input voltage < reference voltage 1 : Input voltage > reference voltage

1 1 1

1 1 1

1 1 1

1 1 1

0 1 1

1 0 1

123/128 VCC 125/128 VCC 127/128 VCC

Fig. 17. Structure of A-D control register 1

Data bus

A-D control register 1

Bits 0 to 2

Comparator control

P15/A-D1/INT3 P16/A-D2 P17/A-D3 P06/INT2/A-D4 P30/A-D5/DA1 P31/A-D6/DA2

A-D control register 1 Analog signal switch Comparator Bit 4 Bit 5 Bit 4

A-D control register 2 Bit 3 Bit 2 Bit 1 Bit 0

Switch tree

Resistor ladder

Fig. 19. A-D comparator block diagram

24

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

D-A CONVERTER
The M37220M3-XXXSP has 2 D-A converters with 6-bit resolution. D-A converter block diagram is shown in Figure 22. D-A conversion is performed by setting the value in the DA conversion register. The result of D-A conversion is output from the DA pin by setting "1" to the DA output enable bit of the port P3 output mode control register (bits 2 and 3 at address 00CD16). The output analog voltage V is determined with the value n (n: decimal number) in the DA conversion register. V = VCC ! n (n = 0 to 63) 64

7

0
Port P3 output mode control register (P3S: address 00CD16) P30 output structure selection bit 0 : CMOS output 1 : N-channel open-drain output

P31 output structure selection bit 0 : CMOS output 1 : N-channel open-drain output DA1 output enable bit 0 : P30 input/output 1 : DA1 output DA2 output enable bit 0 : P31 input/output 1 : DA2 output

The DA output does not build in a buffer, so connect an external buffer when driving a low-impedance load.

Fig.21. Structure of port P3 output mode register

7

0

Table 4. Relation between contents of D-A conversion register and output voltage
DA1 conversion register (DA1: address 00DE16) DA2 conversion register (DA2: address 00DF16) DA conversion set bits Refer to Table 4. Fix this bit to "0."

0

Bit 5 0 0 0 ...

D-A conversion register Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 0 0 0 0 0 0 0 0 1 ... ... ... ...

Bit 0 0 1 0 ...

Output voltage "V" 0/64 V CC 1/64 V CC 2/64 V CC ... 61/64 VCC 62/64 VCC 63/64VCC

Fig. 20 Structure of D-A converter register

1 1 1

1 1 1

1 1 1

1 1 1

0 1 1

1 0 1

Data bus

DA1 conversion register 6 (address 00DE16)

DA2 conversion register 6 (address 00DF16)

Resistor ladder DA1 output enable bit P30/A-D5/DA1

Resistor ladder DA2 output enable bit P31/A-D6/DA2

Fig. 22. D-A converter block diagram

25

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

CRT DISPLAY FUNCTIONS
12 dots

(1) Outline of CRT Display Functions
Table 5 outlines the CRT display functions of the M37220M3-XXXSP. The M37220M3-XXXSP incorporates a CRT display control circuit of 20 characters ! 2 lines. CRT display is controlled by the CRT control register. Up to 128 kinds of characters can be displayed. The colors can be specified for each character and up to 4 kinds of colors can be displayed on one screen. A combination of up to 7 colors can be obtained by using each output signal (R, G, and B). Characters are displayed in a 12 ! 16 dots configuration to obtain smooth character patterns (refer to Figure 23). The following shows the procedure how to display characters on the CRT screen. Write the display character code in the display RAM. Specify the display color by using the color register. Write the color register in which the display color is set in the display RAM. Specify the vertical position by using the vertical position register. Specify the character size by using the character size register. Specify the horizontal position by using the horizontal position register. Write the display enable bit to the designated block display flag of the CRT control register. When this is done, the CRT display starts according to the input of the VSYNC signal. The CRT display circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 24 shows the structure of the CRT display control register. Figure 25 shows the block diagram of the CRT display control circuit.

16 dots

Fig. 23. CRT display character configuration

7

0

CRT control register (CC: address 00EA16)

Table 5. Outline of CRT display functions Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of colors Color Coloring unit Display expansion Raster coloring Functions 24 characters ! 2 lines 12 ! 16 dots (refer to Figure 23) 128 kinds 3 kinds 1 screen: 4 kinds, maximum 7 kinds A character Possible (multiline display) Possible (maximum 7 kinds)
All-blocks display control bit (Note) 0 : All-blocks display off 1 : All-blocks display on Block 1 display control bit 0 : Block 1 display off 1 : Block 1 display on Block 2 display control bit 0 : Block 2 display off 1 : Block 2 display on Note: Display is controlled by logical product (AND) between the all-blocks diplay control bit and each block display control bit.

Fig. 24. Structure of CRT control register

26

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

OSC1

OSC2

HSYNC VSYNC

(Address 00EA16) CRT control register (Addresses 00E116, 00E216) Display oscillation circuit

Vertical position registers

(Address 00E416) Character size register Display position control circuit (Address 00E016) Horizontal position register (Address 00E516) Border selection register

Display control circuit

RAM for display 9 bits ! 20 ! 2 (Addresses 00E616 to 00E916)

ROM for display 12 bits ! 16 ! 128

Color registers

Shift register 12 bits

Shift register 12 bits

(Address 00EC16) Output circuit CRT port control register Data bus R G B OUT

Fig. 25. Block diagram of CRT display control circuit

27

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

(2) Display Position
The display positions of characters are specified in units called a "block." There are 2 blocks, block 1 and block 2. Up to 20 characters can be displayed in each block (refer to (4) Memory for display). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4TC (TC = oscillating cycle for display). The display position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines.

Block 2 is displayed after the display of block 1 is completed (refer to Figure 26 (a)). Accordingly, if the display of block 2 starts during the display of block 1, only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed (refer to Figure 26 (b)). The vertical position can be specified from 128-step positions (4 scanning lines per a step) for each block by setting values "0016" to "7F16" to bits 0 to 6 in the vertical position register (addresses 00E116 and 00E2 16). Figure 28 shows the structure of the vertical position register.

(HR) CV1 Block 1

CV2 Block 2

(a) Example when each block is separated

CV1 Block 1 CV2 Block 2

No display

CV1 Block 1 (second) No display

(b) Example when block 2 overlaps with block 1

Fig. 26. Display position

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MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, it starts to count the rising edge (falling edge) of HSYNC signal from after about 1 machine cycle of rising edge (falling edge) of V SYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the CRT port control register (address 00EC 16). For details. refer to (8) CRT Output Pin Control. Note: When bits 0 and 1 of the CRT port control register (address 00EC16 ) are set to "1" (negative polarity), the vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer (refer to Figure 27).

7

0 Vertical position registers 1, 2 (CV1 : address 00E116) (CV2 : address 00E216)

Vertical display start positions 128 steps from "0016" to "7F16" Fig. 28. Structure of vertical position register

VSYNC signal input

0.125 to 0.25 [s] ( at f(XIN) = 8MHz)

VSYNC control signal in microcomputer Period of counting HSYNC signal (Note) HSYNC signal input 1 2 3 4 5

The horizontal position is common to all blocks, and can be set in 64 steps (where 1 step is 4TC , TC being the display oscillation period) as values "0016 " to "3F16 " in bits 0 to 5 of the horizontal position register (address 00E016 ). The structure of the horizontal position register is shown in Figure 29.

7

0 Horizontal position register (HR : address 00E016) Horizontal display start positions 64 steps from "0016" to "3F16" (1 step is 4TC)

Not count When bits 0 and 1 of the CRT port control register (address 00EC16) are set to "1" (negative polarity) Note: Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter.

Fig. 29. Structure of horizontal position register

Fig. 27. Supplement explanation for display position

29

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

(3) Character Size
The size of characters to be displayed can be from 3 sizes for each block. Use the character size register (address 00E416) to set a character size. The character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3. Figure 30 shows the structure of the character size register. The character size can be selected from 3 sizes: minimum size, medium size and large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (TC ) in the width (horizontal) direction. The minimum size consists of [1 scanning line] ! [1TC ]; the medium size consists of [2 scanning lines] ! [2TC]; and the large size consists of [3 scanning lines] ! [3TC ]. Table 6 shows the relation between the set values in the character size register and the character sizes.

7

0 Character size register (CS : address 00E416)

Character size of block 1 selection bits 0 0 : Minimum size 0 1 : Medium size 1 0 : Large size 1 1 : Do not set. Character size of block 2 selection bits 0 0 : Minimum size 0 1 : Medium size 1 0 : Large size 1 1 : Do not set. Fig. 30. Structure of character size register

Minimum

Medium

Large

Horizontal display start position Fig. 31. Display start position of each character size (horizontal direction) Table 6. Relation between set values in character size register and character sizes Set values of character size register CSn1 0 0 1 1 CSn0 0 1 0 1 Character size Minimum Medium Large Width (horizontal) direction TC: oscillating cycle for display 1TC 2TC 3TC This is not available Height (vertical) direction scanning lines 1 2 3

Note: The display start position in the horizontal direction is not affected by the character size. In other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to Figure 31).

30

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

(4) Memory for Display
There are 2 types of memory for display : CRT display ROM (addresses 10000 16 to 10FFF 16) used to store character dot data (masked) and CRT display RAM (addresses 060016 to 06B316) used to specify the colors of characters to be displayed. The following describes each type of display memory.

ROM for display (addresses 1000016 to 10FFF16 )
The CRT display ROM contains dot pattern data for characters to be displayed. For characters stored in this ROM to be actually displayed, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the CRT display ROM) into the CRT display RAM. The character code list is shown in Table 7.

The CRT display ROM has a capacity of 4K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 128 kinds of characters. The CRT display ROM space is broadly divided into 2 areas. The [vertical 16 dots] ! [horizontal (left side) 8 dots] data of display characters are stored in addresses 1000016 to 107FF16 ; the [vertical 16 dots] ! [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16 (refer to Figure 32). Note however that the high-order 4 bits in the data to be written to addresses 1080016 to 10FFF16 must be set to "1" (by writing data "FX16").

b7 10XX016 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0

b0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 10XX016 +80016

b7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

b3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0

b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

10XXF16

10XXF16 +80016

Fig. 32. Display character stored data

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MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Table 7. Character code list (partially abbreviated) Character code 0016 Character data storage address Left 8 dots lines Right 4 dots lines 10000 16 1080016 to to 1000F16 1080F 16 10010 16 1081016 to to 1001F16 1081F 16 10020 16 1082016 to to 1002F16 1082F 16 10030 16 10830 16 to to 1003F16 1083F16 : : 107E016 to 107EF16 107F016 to 107FF16 10FE016 to 10FEF16 10FF016 to 10FFF16

RAM for display (addresses 060016 to 06B3 16)
The CRT display RAM is allocated at addresses 060016 to 06B316, and is divided into a display character code specification part and display color specification part for each block. Table 8 shows the contents of the CRT display RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 0600 16 and write the color register No. to the low-order 2 bits (bits 0 and 1) in address 068016. The color register No. to be written here is one of the 4 color registers in which the color to be displayed is set in advance. For details on color registers, refer to (5) Color Registers. The structure of the CRT display RAM is shown in Figure 33.

0116

0216

0316 : 7E16

7F16

Table 8. Contents of CRT display RAM Block Display position (from left) 1st character 2nd character 3rd character : 18nd character 19rd character 20th character Not used 1st character 2nd character 3rd character : 18nd character 19rd character 20th character Character code specification 060016 060116 060216 : 061116 061216 061316 061416 to 061F 16 062016 062116 062216 : 063116 063216 063316 Color specification 068016 068116 068216 : 069116 069216 069316 069416 to 069F 16 06A016 06A116 06A216 : 06B116 06B216 06B316

Block 1

Block 2

32

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Block 1 [Character specification] 1st character : 060016 to 20th character : 061316 Character code Specify 128 characters ("0016" to "7F16") [Color specification] 1st character : 068016 to 20th character : 069316 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Block 2 [Character specification] 1st character : 062016 to 20th character : 063316 Character code Specify 128 characters ("0016" to "7F16") [Color specification] 1st character : 06A016 to 20th character : 06B316 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 1 0 7 0 1 0 7 0

Fig. 33. Structure of CRT display RAM

33

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

(5) Color Registers
The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E916) and then specifying that color register with the CRT display RAM. There are 3 color outputs; R, G and B. By using a combination of these outputs, it is possible to set 23 1 (when no output) = 7 colors. However, since only 4 color registers are available, up to 4 colors can be disabled at one time. R, G and B outputs are set by using bits 1 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Figure 34 shows the structure of the color register. 7 0 Color register 0, 1, 2, 3 (CO0 : address 00E616) (CO1 : address 00E716) (CO2 : address 00E816) (CO3 : address 00E916)

B signal output selection bit 0 : No character is output 1 : Character is output G signal output selection bit 0 : No character is output 1 : Character is output R signal output selection bit 0 : No character is output 1 : Character is output OUT signal output control bit 0 : Character is output 1 : Blank is output Fig. 34. Structure of color registers

34

MITSUBISHI MICROCOMPUTERS

M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

(6) Character Border Function
An border of 1 clock (1 dot) equivalent size can be added to a character to be displayed in both horizontal and vertical directions. The border is output from the OUT pin. In this case, set bit 5 of a color register to "0" (character is output). Border can be specified in units of block by using the border selection register (address 00E5 16). Figure 35 shows the structure of the border selection register. Table 9 shows the relationship between the values set in the bor