Text preview for : Force 1030-00003-4.pdf part of Force 1030-00001 Force 1030-00001 DVB Receiver
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5
4
3
2
1
PCB1
Revision list:
99.07.02 First release of partlist 99.07.05 Complex 27Mhz circuit replaced by oscillator
#1030-19003
D D
BC847
1 1
B E
C
Transistor Footprint
GND1
C
gnholed
C
MT1 1
MT3 1
1 MountingHole
1 MountingHole
TH1 1
TH2 1
TH3 1
FM1 1 1
FM2 1 1
1 Toolinghole
1 Toolinghole
1 Toolinghole
Fiducial
Fiducial
B
B
PINS FOR MAC MODULES
MT4 1 MT5 1 MT6 1 MT7 1
1
1
1
1
HFC2580-Hole
HFC2580-Hole
HFC2580-Hole
HFC2580-Hole
A
A
All information contained on this drawing is copyright of FORCE Electronics A/S Denmar k. Legal actions will be taken against any company u sing or copying the design/ideas or information contai ned on this drawing without prior written permiss ion.
Mechanical
5 4 3 2
Title 1030 Mechanical Parts Document Number Size 1030-00003-4 A3 Date: Thursday, January 20, 2000
1
Sheet
1
Rev 1.0 of
9
5
4
3
2
1
Micro&Mac
Scart
FRONTEND-CA
D
BBVIDEO
BBVIDEO
BBVIDEO
I2CSCL I2CSDA /D_WAIT D_RD/WR /D_CS2 /INT0 -RESET3.3V CLK 27MHZ TSCA_CLK TSCA_START TSCA_VALID TSCA_D[0..7] DA[2..23] DD[0..7] /D_BE2 /D_BE3 /RESET5V
C
MACPAL ROUT GOUT BOUT MACYOUT MACCOUT MacLeftAudio MacRightAudio
MACPAL ROUT GOUT BOUT MACYOUT MACCOUT MacLeftAudio MacRightAudio
MACPAL ROUT GOUT BOUT MACYOUT MACCOUT MacLeftAudio MacRightAudio
D
/D_WAIT D_RD/WR /D_CS2 /INT0 -RESET3.3V CLK 27MHZ TSCA_CLK TSCA_START TSCA_VALID TSCA_D[0..7] DA[2..23] DD[0..7] /D_BE2 /D_BE3 /RESET5V
/D_WAIT D_RD/WR /D_CS2 /INT0 -RESET3.3V CLK 27MHZ TSCA_CLK TSCA_START TSCA_VALID TSCA_D[0..7] DA[2..23] DD[0..7] /D_BE2 /D_BE3 /RESET5V YDIG CDIG CVBSDIG RDIG GDIG BDIG FBL DIG-AUD-R DIG-AUD-L YDIG CDIG CVBSDIG RDIG GDIG BDIG FBL DIG-AUD-R DIG-AUD-L YDIG CDIG CVBSDIG RDIG GDIG BDIG FBL DIG-AUD-R DIG-AUD-L
C
SmartCardIf
50HZ 50HZ 50HZ Vpp low -Power A -Power B Vpp A Vpp B Card I/O A Card Clock A Card Reset A Vpp low -Power A -Power B Vpp A Vpp B Card I/O A Card Clock A Card Reset A 50HZ Vpp low -Power A -Power B Vpp A Vpp B Card I/O A Card Clock A Card Reset A
I2CSCL I2CSDA
I2CSCL I2CSDA
I2CSCL I2CSDA
IR RX SCART
IR RX SCART
IR RX SCART
SCTX SCRX
SCTX SCRX
SCTX SCRX
B
B
Card I/O B Card Clock B Card Reset B Card det A Card det B
Card I/O B Card Clock B Card Reset B Card det A Card det B 50HZ
Card I/O B Card Clock B Card Reset B Card det A Card det B 50HZ
Power 50HZ
A
A
All information contained on this drawing is copyright of FORCE Electronics A/S Denmar k. Legal actions will be taken against any company u sing or copying the design/ideas or information contai ned on this drawing without prior written permiss ion.
" ÃH6DI
5 4 3 2
Title DVB Receiver Document Number Size 1030-00003-4 A3 Date: Thursday, January 20, 2000
1
Sheet
2
Rev 1.0 of
9
5
4
3
2
1
6 TSCA_D[0..7]
TSCA_D[0..7] U1 TSCA_D7 TSCA_D6 TSCA_D5 TSCA_D4 TSCA_D3 TSCA_D2 TSCA_D1 TSCA_D0 3.3V C1 100nF 20 10 18 16 14 12 9 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 MIBPB7 MIBPB6 MIBPB5 MIBPB4 MIBPB3 MIBPB2 MIBPB1 MIBPB0 /BYPSSA C2 100nF TSCA_D7 TSCA_D6 TSCA_D5 TSCA_D4 TSCA_D3 TSCA_D2 TSCA_D1 TSCA_D0 3.3V 18 16 14 12 9 7 5 3 20 10
U2 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244
D
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G
2 4 6 8 11 13 15 17 1 19 /INPUTA
MDOAD7 MDOAD6 MDOAD5 MDOAD4 MDOAD3 MDOAD2 MDOAD1 MDOAD0 MDOAD[0..7]
D
U3 MIBPB7 MIBPB6 MIBPB5 MIBPB4 MIBPB3 MIBPB2 MIBPB1 MIBPB0 /INPUTA 2 4 6 8 11 13 15 17 1 19 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LVX244 1 19 MIBPCLK MIBPSTRT MIBPVAL /INPUTA /BYPSSA MDIAD[0..7] MOCLKA MOSTRTA MOVALA MDOAD0 MDOAD1 MDOAD2 MDOAD3 MDOAD4 MDOAD5 MDOAD6 MDOAD7 MDOAD[0..7] 3.3V 20 10 C7 100nF U9 TS2997 TS2996 TS2995 TS2994 TS2993 TS2992 TS2991 TS2990 2 4 6 8 11 13 15 17 1 19 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LVX244 20 10 C11 100nF 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 18 16 14 12 9 7 5 3 20 10 MIBPB7 MIBPB6 MIBPB5 MIBPB4 MIBPB3 MIBPB2 MIBPB1 MIBPB0 3.3V C9 MIBPB7 MIBPB6 MIBPB5 MIBPB4 MIBPB3 MIBPB2 MIBPB1 MIBPB0 3.3V C10 18 16 14 12 9 7 5 3 20 10 U10 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244 MICLKB MISTRTB MIVALB MDIBD0 MDIBD1 MDIBD2 MDIBD3 MDIBD4 MDIBD5 MDIBD6 MDIBD7 MDIBD[0..7] MOCLKB MOSTRTB MOVALB MDOBD0 MDOBD1 MDOBD2 MDOBD3 MDOBD4 MDOBD5 MDOBD6 MDOBD7 MDOBD[0..7] /REGB /CE1B /OEB /WEB /IORD B /IOWRB /IRQB R6 10K 5V 5V Q1 SI443 1DY 1 2 3 R7 47K S1 S2 S3 G D4 D3 D2 D1 8 7 6 5 5VPCCARDB DBLPCMCIA 129 75 110 77 83 112 113 128 84 REG CE1 CE2 OE WE/PGM IORD IOWR INP_ACK IREQ 125 131 130 132 133 134 105 106 107 108 109 MOCLK MOSTRT MOVAL MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 88 114 87 115 116 117 118 121 122 123 124 MICLK MISTRT MIVAL MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 MDOBD7 MDOBD6 MDOBD5 MDOBD4 MDOBD3 MDOBD2 MDOBD1 MDOBD0 /REGA /CE1A /OEA /WEA /IORD A /IOWR A /IRQA 61 7 42 9 15 44 45 60 16 68 35 34 1 REG CE1 CE2 OE WE/PGM IORD IOWR INP_ACK IREQ GND GND GND GND 57 63 62 64 65 66 37 38 39 40 41 MOCLK MOSTRT MOVAL MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 18 16 14 12 9 7 5 3 3.3V 20 10 MDIAD[0..7] C3 100nF MDIAD7 MDIAD6 MDIAD5 MDIAD4 MDIAD3 MDIAD2 MDIAD1 MDIAD0 U4 MICLKA MISTRTA MIVALA MDIAD0 MDIAD1 MDIAD2 MDIAD3 MDIAD4 MDIAD5 MDIAD6 MDIAD7 20 46 19 47 48 49 50 53 54 55 56 MICLK MISTRT MIVAL MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 PCMDA[0..7]
U5 6 TSCA_CLK 6 TSCA_START 6 TSCA_VALID 18 16 14 12 9 7 5 3 3.3V C4 100nF 20 10 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 MOCLKA MOSTRTA MOVALA
PCMCIA_A
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CD1 CD2
30 31 32 2 3 4 5 6 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 36 67 43 59
PCMDA0 PCMDA1 PCMDA2 PCMDA3 PCMDA4 PCMDA5 PCMDA6 PCMDA7
U6 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 3.3V MAA[0..14] 20 10 C5 100nF 18 16 14 12 9 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 /D_BE2 /D_BE3 DA2 DA3 DA4 DA5 DA6 DA7 /CS_PCCA
MIBPB[0..7] U8 2 4 6 8 11 13 15 17 /INPUTA /INPUTB
C
MOVALB MOSTRTB MOCLKB
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LVX244 U11
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND
18 16 14 12 9 7 5 3
MIVALA MISTRTA MICLKA
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14
5V R1 10K
U7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 /CDA /WAITA C6 100nF 3.3V 20 10 18 16 14 12 9 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244
C
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G
2 4 6 8 11 13 15 17 1 19
DA8 DA9 DA10 DA11 DA12 DA13 DA14
1 19
VTG_SENSE WAIT
DA[2.. 14] /CS_PCCA
VPP1 VPP2 RESET IOCS16
18 52 58 33
/CS_PCCA /RESETPCCA 5VPCCARDB C8 100nF
MISTR 4 TS299CLK 4 TS299START 4 TS299VALID R126 0
R157 DUMMY
2 4 6 8 11 13 15 17 /BYPSSB /INPUTB 1 19
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LVX244
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND
18 16 14 12 9 7 5 3
MICLKB MISTRTB MIVALB 3.3V
R2 10K 5V
/BYPSSB
/INPUTB
VCC VCC
51 17
100nF 100nF
PCMDB[0..7]
PCMCIA_B
4 TS299[0..7] TS2997 TS2996 TS2995 TS2994 TS2993 TS2992 TS2991 TS2990 2 4 6 8 11 13 15 17 1 19
TS299[0..7] U13 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LVX244 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 18 16 14 12 9 7 5 3 20 10 MDIBD7 MDIBD6 MDIBD5 MDIBD4 MDIBD3 MDIBD2 MDIBD1 MDIBD0 3.3V C13 100nF
MDIBD[0..7]
D0 D1 D2 D3 D4 D5 D6 D7
98 99 100 70 71 72 73 74
PCMDB0 PCMDB1 PCMDB2 PCMDB3 PCMDB4 PCMDB5 PCMDB6 PCMDB7 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 MAB14
U12 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 3.3V MAB[0..14] 18 16 14 12 9 7 5 3 20 10 C12 100nF 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 /D_BE2 /D_BE3 DA2 DA3 DA4 DA5 DA6 DA7 /CS_PCCB
/INPUTB
U15 6 CLK 27MHZ 6 /RESET5V
B
U32 SI0 SI1 SO0 SO1 SO2 SO3 WAIT_A CE1_A REG_A OE_A WE_A IORD_A IOWR_A AOE_A DOE_A D0_A D1_A D2_A D3_A D4_A D5_A D6_A D7_A SI2 SI3 SO4 SO5 SO6 SO7 WAIT_B CE1_B REG_B OE_B WE_B IORD_B IOWR_B AOE_B DOE_B 17 18 19 20 21 44 45 64 40 62 41 60 61 24 39 56 55 54 53 51 50 49 48 47 46 43 38 36 37 10 35 7 3 6 5 4 9 8 /CDA /CDB PCCARDON /BYPSSA /INPUTB /WAITB /REGB /OEB R144 39 /IRQA /IRQB 2 4 6 8 11 13 15 17 /AOE_A /AOE_B 1 19 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 18 16 14 12 9 7 5 3 20 10 /RESETPCCA /CS_PCCA
59 58 R127 22 67 66 65 13 11 14 16 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DA16 DA17 77 76 75 74 71 70 69 68 15 1 78 79 80 33 73 2 12 23 32 42 52 63 72
TSSTR TSCK CK TEST MODE CPU IRQ ACK CS RW HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 SEL0 SEL1 HA0 HA1 HA2 VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CD1 CD2 VTG_SENSE WAIT VPP1 VPP2 RESET IOCS16
97 96 95 94 93 92 91 90 80 79 76 78 89 81 82 104 135
5V R3 10K MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 MAB14 /CDB 3.3V 20 10 C15 100nF 18 16 14 12 9 7 5 3
U14 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 DA8 DA9 DA10 DA11 DA12 DA13 DA14 DA[2.. 14] /CS_PCCB
3.3V
10K R4 4.7K
/BYPSSB /INPUTA /WAITA /REGA /OEA
/RESETPCCB /CS_PCCB
B
3.3V C112 100nF
111 127 86 120 126 101
/WAITB /CS_PCCB
6 6 6 6 6
/INT0 /D_WAIT /D_CS2 D_RD/ WR DD[0..7 ]
R141 /CE1A 74LVX244 /WEA 39 /IORD A /IOWR A /AOE_A PCMDA[0..7] R142 39 R143 39 PCMDA0 PCMDA1 PCMDA2 PCMDA3 PCMDA4 PCMDA5 PCMDA6 PCMDA7
/RESETPCCB
136 103 102 69
GND GND GND GND
5VPCCARDB VCC VCC 119 85
C16 100nF
6 /D_BE2 6 /D_BE3 6 DA[2.. 23]
DA2 5V
C17 100nF
C18 100nF
/CE1B /WEB /IORD B /IOWRB
A
A
/AOE_B PCMDB[0..7]
4,5,6 ,8 4,5,6 ,8 4,5,6 ,8 4,5,6 ,8
I2CSCL I2CSDA I2CSCL I2CSDA
4,6 -RESET3.3V 4,6 -RESET3.3V CXD1957Q
D0_B D1_B D2_B D3_B D4_B D5_B D6_B D7_B MISTR
25 26 27 28 29 30 31 34 57 MISTR
R145 39 R146 39
PCMDB0 PCMDB1 PCMDB2 PCMDB3 PCMDB4 PCMDB5 PCMDB6 PCMDB7
All information contained on this drawing is copyr ightof FORCE Electronics A/S Denmar k. Legal actions will be taken against any company using or copying the design/ideas or information contained on this drawing without prior written permission .
4
Title LNB inte rface
86
5 4 3 2
Document Number Size 1030-00003-4 A2 Date : Thursday, Ja nuary 20, 2000
1
Rev 1.0 Sheet 3 of 9
5
4
3
2
1
D
D
J1 5,6,8 3 TS299[0..7] TS299[0..7] TS2990
C
I2CSDA I2CSCL
5,6,8
TS2991 TS2992 TS2993 TS2994 TS2995 TS2996 TS2997 3 TS299CLK 3 TS299START 3 TS299VALID 6 -RESET3.3V 5 BBVIDEO 5V 3.3V
B
12V 22V 30V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 IDCBOXHEADER40
C
B
JP5 3.3V 5V 12V 22V 30V 1 2 3 4 5 6 1 2 3 4 5 6 POWER PINHEADER
A
A
All information contained on this drawing is copyright of FORCE Electronics A/S Denmar k. Legal actions will be taken against any company u sing or copying the design/ideas or information contai ned on this drawing without prior written permiss ion.
Frontend Interface
5 4 3 2
Title Frontend Interface Document Number Size 1030-00003-4 A3 Date: Thursday, January 20, 2000
1
Sheet
4
Rev 1.0 of
9
5
4
3
2
1
D
D
5V JP6 4 3 2 1 4 3 2 1
12V
POWER PLUG 4_S
J6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 IDCBOXHEADER40 I2CSCL I2CSDA -EXTRESET IMDAT IMIO IMCLK TSYNC BDAT BCLK BBVIDEO 4 MACPAL ROUT GOUT BOUT 8 8 8 8 4,6,8 4,6,8 6 6 6 6 6 6 6
C
C
MACYOUT 8 MACCOUT 8 MacLeftAudio 8 MacRightAudio 8
B
B
MAC5VOFF
6
A
A
All information contained on this drawing is copyright of FORCE Electronics A/S Denmar k. Legal actions will be taken against any company u sing or copying the design/ideas or information contai ned on this drawing without prior written permiss ion.
H68
5 4 3 2
Title Mac section Document Number Size 1030-00003-4 A3 Date: Thursday, January 20, 2000
1
Sheet
5
Rev 1.0 of
9
5
4
3
2
1
SCRX SCTX
J7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 IDCBOXHEADER26 R134 SLCT PE TBUSY -TACK PBIT7 PBIT6 PBIT5 PBIT4 PBIT3 -SLIN PBIT2 -INIT PBIT1 -ERR PBIT0 -TAFD -TSTB
R56 D4 1 2 3 4 5 7 I/O I/O I/O I/O I/O I/O 1 2 3 4 5 6 H 6 5V U21 2 10K
5V -RESET3.3V 4 R59 10K 3 Vout 1 /RESET5V 2 6 74LVX02 74LVX02 BSE1 BSE2 2 U16C 8 10 -JTAGRST 9 74LVX02 2 CLK 27MHZ 3.3V 50HZINT 5V
D
/RESET5V 3 -RESET3.3V U16A U16B 1 5 4 R65 10K X1 3 OUT GND 27MHz X3 3 OUT GND DUMMY 3 CLK 27MHZ V CONT VCC 1 4 3.3V V CONT VCC 1 4 3.3V C45 100nF R67 4.7K 27MHZ PWM 3.3V
DO NOT MOUNT
L
8
10uF
DALC112S1 R69 39 PDO7 PDO6 PDO5 PDO4 PDO3 PDO2 PDO1 PDO0
3
Vss TC54-4.6V
RESET1 DUMMY
+
Vin
C44
R71 39
SP1 DUMMY
SP2 DUMMY
Leaded and SMD type Mount only ONE
D
3 TSCA_D[0..7] C113 68pF C114 68pF 7 5 4 3 2 1 3 TSCA_START 3 TSCA_VALID 3 TSCA_CLK
TSCA_D[0..7] R139 DUMMY SPEED1 SPEED0
C49 27pF X2
C50 27pF
R74 0
R75 0 + C52 100nF C51 10uF
L2 22uH
3.3V
I/O I/O I/O I/O I/O I/O
R131 TSCA_D7 TSCA_D6 TSCA_D5 TSCA_D4 TSCA_D3 TSCA_D2 TSCA_D1 TSCA_D0
D8 DALC112S1
6 5 4 3 2 1
5V 1K 7 5 4 3 2 1
C115 68pF
H
L
PDO[0..7]
TRIGIN TRIGOUT
32.768kHz
3.3V C53 100nF H17 R19 R20 F4 K4 P4 U5 D6 U9 D10 D14 U13 E17 J17 N17 U17 G1 W6 A8 U24 C54 100nF C55 100nF C56 100nF C57 100nF C58 100nF C59 100nF C60 100nF
5V 5V D7 DALC112S1 JP3 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 H L /RI INTCTS INTRTS -EXTRESET CD DTR INTTXD INTRXD 5V R78 DUMMY 9 9 9 9 9 9 9 SCRX L3 DUMMY C62 C61 + DUMMY DUMMY 8 8 SCRX SCTX SCTX 1 H1 DUMMY 1 H2 R149 5V PANEL IR RX R84 2.7K 4,5,8 I2CSCL 4,5,8 4,5,8 I2CSCL 5 IMIO I2CSDA I2CSDA 11 7 RDCU1 DCU1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IDCBOXHEADER20 RDCU2 3.3V 50HZ 13 12 74LVX02 50HZINT 5 BCLK U16D 5 BDAT 0 BCLK INTRXD INTTXD /RI TRIGOUT TRIGIN R86 10K BS1 0 BS2 DUMMY TMS TCK TDI TDO -JTAGRST -TRST R107 10K /D_WAIT D_RD/WR R108 0 3 3 3 3 3 3 3 /D_WAIT D_RD/WR /D_CS2 /D_BE2 /D_BE2 /D_BE3 /D_BE3 /D_RAS0 /D_CAS3 /D_CAS2 /D_CAS1 /D_CAS0 /D_BE3 /D_BE2 /D_BE1 R147 68 K19 K18 J18 G20 E18 F17 F20 F19 D19 D18 E20 E19 G19 G18 H20 H19 H18 F18 K20 G17 MEM_REQ MEM_GRANT MEM_WAIT MEM_RDNOTWR /MEM_RAS_3 /MEM_RAS_2 /MEM_RAS_1 /MEM_RAS_0 /MEM_CAS_3 /MEM_CAS_2 /MEM_CAS_1 /MEM_CAS_0 /MEM_BE_3 /MEM_BE_2 /MEM_BE_1 /MEM_BE_0 5 TSYNC TSYNC 3.3V BSE1 BSE2 3 /INT0 BDAT R140 INTRTS INTCTS R85 2.7K I2CSCL DUMMY R3A 0 5 IMCLK 8 IR RX SCART PANEL IR TX DUMMY 2 R5 DUMMY 9 9 9 9 9 5 9 Card det B Vpp B -Power B Card Reset B Card Clock B -EXTRESET Card I/O B 2 R150 DUMMY 5 MAC5VOFF 27MHZ PWM Card det A Vpp A -Power A Card Reset A Card Clock A Vpp low Card I/O A R136 10K 5% -INIT TBUSY -TACK -ERR SLCT -TAFD PE -TSTB -SLIN C1 E3 E2 D3 D1 D2 E4 H2 C2 V6 U6 Y5 W5 V5 Y4 W4 V4 V9 C4 D5 Y8 W8 W7 V7 Y6 Y3 Y2 W3 Y1 W2 V3 W1 V2 C3 V10 U10 Y9 W9 V8 U8 Y7 L3 A2 B2 B1 A1 L2 A4 B4 A3 B3 W11 Y11 6 5 4 3 2 1
PDO7 PDO6 PDO5 PDO4 PDO3 PDO2 PDO1 PDO0
10K
8
6
V11 Y10 W10
L19 M20 M19 L18
M18 M17 N20 N19 N18 P20 P19 P18
U12
K17 L20
H1 G4 G3 G2 F3 F2 F1 E1
I/O I/O I/O I/O I/O I/O
TSI BYTE CLK TSI BCLK VALID TSI PKT CLK TSI ERROR
7 6 5 4 3 2 1 0
K2 K1 K3
L1
1284_DATA_7 1284_DATA_6 1284_DATA_5 1284_DATA_4 1284_DATA_3 1284_DATA_2 1284_DATA_1 1284_DATA_0
SPEED SEL1 SPEED SEL0
CPURESET CPUAS/TRIGIN ERROUT/TRIGOUT
LP CLOCK IN LP CLOCK OSC RTC VDD
PROC_CLOCK_OUT AUX_CLK_OUT
VCLAMP_1 VCLAMP_2 VCLAMP_3
VCC_VPLL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
CLOCK IN
/RESET
5V
H3 DUMMY AGC
1284_/INIT 1284_BUSY 1284_/ACK 1284_/FAULT 1284_SELECT 1284_/AUTOFD 1284_P_ERROR 1284_/STROBE 1284_/SELECT_IN PIO_07_SC1DETEC PIO_06_SC1DIR PIO_05_SC1CMD PIO_04_SC1RST PIO_03_SC1CLK PIO_02_SC1CLKGE PIO_01_ASC0RXD PIO_00_ASC0TXD PIO_17_PWM_OUT2 PIO_16_ASC1RXD PIO_15_ASC1TXD PIO_14_PWM_OUT1 PIO_13_PWM_OUT0 PIO_12_SSC0SCLK PIO_11_SSC0_MRS PIO_10_SSC0_MTS PIO_27_SC0DETEC PIO_26_SC0DIR PIO_25_SC0CMD PIO_24_SC0RST PIO_23_SC0CLK PIO_22_SC0CLKGE PIO_21_ASC2RXD PIO_20_ASC2TXD PIO_37_1284_OUT PIO_36_COMP_OUT PIO_35_CAPT_IN2 PIO_34_CAPT_IN1 PIO_33_CAPT_IN0 PIO_32_SSC1SCLK PIO_31_SSC1MRST PIO_30_SSC1MTSR PIO_47_TTEXTDAT PIO_46_INT3 PIO_45_INT2 PIO_44_1284HOST PIO_43_1284PERI PIO_42_TTEXTCLK PIO_41_ASC3RXD PIO_40_ASC3TXD INT1 INT0
HEADER10
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND_VPLL
J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 P17
DATA DATA DATA DATA DATA DATA DATA DATA
C63 100nF
C64 100nF
C65 100nF
C66 100nF
C67 100nF
C68 100nF
C69 100nF
C70 100nF
TSI TSI TSI TSI TSI TSI TSI TSI
8
6
L4 C71 100nF C72 + 47uF 1 3 2 4 SDATA LRCK DIG-AUD-R 8 AGND notDEM/SCLK AOUTR MCLK 5 VA+ 8 22uH
3.3V
7
U25
CS4330-KS
AOUTL
DIG-AUD-L 8
Dem. GND Out Vs 5V 2 1 3
P3 PCM_CLK_OUT M1 PCM_LR_CLK N1 PCM_DATA PCM_CLK_IN N3
C73 DUMMY L5 4.7uH C74 R79 390 82pF C75 82pF R80 390 CVBSDIG 8
5
IMDAT
N2 AC3_REQ N4 AC3_PTS_STB
M2 /HSYNC M3 ODD_EVEN R2 CV_OUT R4 Y_OUT R3 C_OUT V_VCC_1 T3 22uH R81 9.1K 1% C77 100nF C78 100nF + C79 220uF C82 DUMMY U3 R_OUT U4 G_OUT U2 B_OUT OSD_ENABLE V_VCC_0 L4 V1 R90 9.1K 1% V_GND_0 U1 SDA[0..11] U15 W15 V15 Y14 W14 V14 U14 Y13 W13 V13 Y12 W12 V12 R18 T20 T19 T18 T17 U20 U19 U18 V20 V19 W20 Y20 W19 Y19 W18 V18 R116 39 C88 DUMMY L10 4.7uH R103 390 C89 82pF C90 82pF R104 390 C91 DUMMY SDD[0..15] L11 4.7uH R109 390 C92 82pF C93 82pF R110 390 BDIG 8 GDIG 8 FBL 8 L8 4.7uH R88 390 C83 82pF C84 82pF R89 390 CDIG 8 C76 L6 3.3V C80 82pF DUMMY L7 4.7uH R82 390 C81 82pF R83 390
C
6
P2 I_REF_YC P1 V_REF_YC
YDIG
8
C
IR RX IN
V_GND_1
R1
4,5,8 I2CSDA
C85 DUMMY L9 4.7uH R92 390 C86 82pF C87 82pF R93 390 RDIG 8
DUMMY
10K
T2 I_REF_RGB T1 V_REF_RGB
OS_LINK_OUT OS_LINK_IN SD_AD_12 SD_AD_11 SD_AD_10 SD_AD_9 SD_AD_8 SD_AD_7 SD_AD_6 SD_AD_5 SD_AD_4 SD_AD_3 SD_AD_2 SD_AD_1 SD_AD_0 SD_DQ_15 SD_DQ_14 SD_DQ_13 SD_DQ_12 SD_DQ_11 SD_DQ_10 SD_DQ_9 SD_DQ_8 SD_DQ_7 SD_DQ_6 SD_DQ_5 SD_DQ_4 SD_DQ_3 SD_DQ_2 SD_DQ_1 SD_DQ_0
J20 J19 H4 M4 J2 H3 J4 J3 J1
BOOT_SRC_1 BOOT_SRC_0 TTXT_EVEN/ODD TTXT_HSYNC TMS TCK TDI TDO /T_RST
R98 39
R102 39 R105 39
SDA11 SDA10 SDA9 SDA8 SDA7 SDA6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 SDD15 SDD14 SDD13 SDD12 SDD11 SDD10 SDD9 SDD8 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0
R106 39
R111 39 R112 39 R113 39
3.3V R114 10K R115 10K
Y15 SD_CLOCK_IN U16 SD_CLOCK_OUT Y17 SD_DQ_MU Y18 SD_DQ_ML MEM_ADDR_23 MEM_ADDR_22 MEM_ADDR_21 MEM_ADDR_20 MEM_ADDR_19 MEM_ADDR_18 MEM_ADDR_17 MEM_ADDR_16 MEM_ADDR_15 MEM_ADDR_14 MEM_ADDR_13 MEM_ADDR_12 MEM_ADDR_11 MEM_ADDR_10 MEM_ADDR_9 MEM_ADDR_8 MEM_ADDR_7 MEM_ADDR_6 MEM_ADDR_5 MEM_ADDR_4 MEM_ADDR_3 MEM_ADDR_2 MEM_DATA_31 MEM_DATA_30 MEM_DATA_29 MEM_DATA_28 MEM_DATA_27 MEM_DATA_26 MEM_DATA_25 MEM_DATA_24 MEM_DATA_23 MEM_DATA_22 MEM_DATA_21 MEM_DATA_20 MEM_DATA_19 MEM_DATA_18 MEM_DATA_17 MEM_DATA_16 MEM_DATA_15 MEM_DATA_14 MEM_DATA_13 MEM_DATA_12 MEM_DATA_11 MEM_DATA_10 MEM_DATA_9 MEM_DATA_8 MEM_DATA_7 MEM_DATA_6 MEM_DATA_5 MEM_DATA_4 MEM_DATA_3 MEM_DATA_2 MEM_DATA_1 MEM_DATA_0 Y16 /SD_RAS W16 /SD_CAS V16 /SD_WE W17 /SD_CS_1 V17 /SD_CS_0
SDCLK SDDQMU SDDQML /SDRAS
/D_CS2 /D_CS_ROM /D_OE
B
/MEM_CS2 /MEM_CS_ROM /MEM_OE /SDRAMCS0 CFC YC0 YC1 YC2 YC3 YC4 YC5 YC6 YC7
R117 39
/SDCAS /SDWE /SDCS1 /SDCS0
B
D8 D12 D16 L17 R17 U11 U7 D4
A5 B5 C5 A6 B6 C6 A7 B7 C7 D7 B8 C8 A9 B9 C9 D9 A10 B10 C10 A11 B11 C11 D11 A12 B12 C12 A13 B13 C13 D13 A14 B14
C14 A15 B15 C15 D15 A16 B16 C16 A17 B17 C17 D17 A18 B18 B19 A19 A20 B20 C20 C19 C18 D20
T4
STI5512 U26 U27 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC. NC. 2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49 37 33 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 3.3V R119 47K SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SDA11 21 22 23 24 27 28 29 30 31 32 20 19 15 16 17 18 34 35 14 36 3.3V 1 4 7 10 13 25 26 38 41 44 47 50 AO A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 WE CAS RAS CS CKE CLK DQML DQMU VCC VSSQ VCCQ VSSQ VCCQ VCC VSS VCCQ VSSQ VCCQ VSSQ VSS MB81F161622B DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC. NC. 2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49 37 33 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
3 3
DD[0..7] DA[2..23]
DD[0..31] DA[2..23]
SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SDA11
21 22 23 24 27 28 29 30 31 32 20 19 15 16 17 18
AO A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 WE CAS RAS CS CKE CLK DQML DQMU VCC VSSQ VCCQ VSSQ VCCQ VCC VSS VCCQ VSSQ VCCQ VSSQ VSS
DD31 DD30 DD29 DD28 DD27 DD26 DD25 DD24 DD23 DD22 DD21 DD20 DD19 DD18 DD17 DD16 DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2
3.3V Supported Flash Fujitsu 8Mbit: MBM29LV800TA Fujitsu 16Mbit: MBM29LV160T AMD 8Mbit: AM29LV800B_T AMD 16Mbit: AM29LV160B_T ST: ?
R118 47K
34 35 14 36
3.3V
U28 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DA14 DA15 DA16 DA17 DA18 DA19 DA20 DA21
A
U29 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RY/BY 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 15 DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DA14 DA15 DA16 DA17 DA18 DA19 DA20 DA21 3.3V 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 47 12 11 28 26 37 46 27 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 BYTE RESET WE OE CE VCC VSS VSS AM29LV160B_T DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RY/BY 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 15 14 15 30 31 32 3.3V C102 100nF 1 6 22 23 39 44 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 C96 100nF
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 47 12 11 28 26 37 46 27
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 BYTE RESET WE OE CE VCC VSS VSS
U30 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 18 19 20 21 24 25 26 27 28 29 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 W RAS OE UCAS LCAS VCC VCC VCC VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC. NC. NC. NC. NC. NC. NC. 2 3 4 5 7 8 9 10 35 36 37 38 40 41 42 43 11 12 13 16 17 33 34 DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 3.3V C103 100nF DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 18 19 20 21 24 25 26 27 28 29 14 15 30 31 32 1 6 22 23 39 44
U31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 W RAS OE UCAS LCAS VCC VCC VCC VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC. NC. NC. NC. NC. NC. NC. 2 3 4 5 7 8 9 10 35 36 37 38 40 41 42 43 11 12 13 16 17 33 34 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
1 4 7 10 13 25 26 38 41 44 47 50
C98 100nF
MB81F161622B
5V TP2 C100 + 220uF C101 100nF JP4 PANEL IR TX PANEL IR RX I2CSCL I2CSDA 1 2 3 4 5 6 1 2 3 4 5 6 MS6 TP 1 3.3V
A
VCC
3.3V
-RESET3.3V
NC. NC. NC.
10 13 14
-RESET3.3V
NC. NC. NC.
10 13 14
Testpoint
3.3V
C104 100nF
3.3V
C105 100nF
AM29LV160B_T
KM416V1200CT
KM416V1200CT
All information contained on this drawing is copy FORCE Electronics A/S Den mark. Legal actions will be taken against any company copying the design/ideas or information contained drawing without prior written permi ssion.
right of using or on this
Micro
5 4 3 2 1
Title Micro section Document Number Size 1030-00003-4 Custom Date: Thur sday, January 20, 2000
Rev 1.0 Sheet 6 of
9
5
4
3
2
1
D
D
50HZ
6
30V
JP7 12 11 10 9 8 7 6 5 4 3 2 1 12 11 10 9 8 7 6 5 4 3 2 1
22V
C
C
12V
3.3V 5V
POWER PINHEADER
B
B
A
All information contained on this drawing is copyright of FORCE Electronics A/S Denmark. Legal actions will be taken against any company using or copying the design/ideas or information contained on this drawing without prior written permission.
A
32:(5
5 4 3 2
Title Power Section Document Number Size 1030-00003-4 A4 Date: Thursday, January 20, 2000
1
Sheet
Rev 1.0 7 of
9
5
4
3
2
1
6
FBL
TVScartPin8
D
R148 DUMMY R8 4.7K 12V R9 1K 1 5V R10 2.2K IR RX SCART 6 Q2 BC847 R12 1K R13 220 R15 1K 12V R16 100K R17 1K R18 1K 2 D1 3 R19 220 1N4148 1 3 Q5 BC847 R20 22K 2 R11 2.2K R14 100K C21 4.7nF 3 1 2 Q3 SW-FNC-OUT BC847 TV-AUD-OUT R TV-AUD-IN R TV-AUD-OUT L TV-AUD-IN L J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
D
9V
U17 6 5 6 5 6 5 6 BOUT BDIG GOUT GDIG ROUT RDIG 12 13 2 1 5 3 7 INH X0 X1 Y0 Y1 Z0 Z1 VEE 4053 A B C VSS VDD X Y Z 16 14 15 4 BM GM RM 5V 2 3
7 9
BLUE GREEN RED
11 10 9 8
1 Q4 BC857 AUD-VCR-OUT R AUD-VCR- IN R AUD-VCR-OUT L
R151 DUMMY R152 DUMMY R153 DUMMY 12V
B&O
RGB OUT B RGB OUT G RGB OUT R CVBS OUT FBL OUT
AUD-VCR-IN L VCR-B-IN VCR-FNC-IN VCR-G -IN
9 & 5
C
VCR-R/C- IN R154 DUMMY R155 DUMMY R156 DUMMY C109 470nF C110 470nF C111 470nF VCR-B-IN VCR-G -IN VCR-CVBS-IN VCR-FBL-IN VCR-FNC- IN DEC-B IN DEC-G IN CVBSOUTSW COUTSW YOUTSW C25 A B C VSS 11 10 9 8 10uF + R29 75 1uF 9V DEC-R IN DEC-VID IN DEC-FB IN DEC-FCN I N C23 1uF + 61 59 57 55 53 64 13 15 17 21 51 1 Vin2 B VCR Vin5 G Vin9 R/C Vin13-CVBS/Y FBLK_IN2 FNC_VCR Vin3 B Vin6 G AUX Vin10 R/C Vin14-CVBS/Y FBLK_IN3 FNC_AUX
1
C
C106 470nF
C107 470nF
C108 470nF U18 63 2 4 8 6 10 52 Vin1 B Vin4 G DIG Vin7 R Vin11 CVBS Vin8 C Vin12 Y FBLK_IN1 CXA2125Q
VCR-FBL-IN VCR-CVBS-OUT VCR-CVBS-IN
2 3
Q6 BC847 1 R21 Q7 BC847 3 1 R22 Q8 BC847 3 1 R24 Q9 BC847 3 1 1K 1K 1K
IDCBOXHEADER40
VIDEO
48 47 46 49 50 30 BUB GUB RUB
2 VOUT1 B TV VOUT2 G VOUT3 R VOUT4 CVBS FBLANK FNC
CVBSUB FBLUB R23 100
2
2
J3 AUD-DEC-OUT R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
9V U19 6 5 6 5 6 5 6 MACPAL CVBSDIG MACCOUT CDIG MACYOUT YDIG 12 13 2 1 5 3 7 INH X0 X1 Y0 Y1 Z0 Z1 VEE 4053 VDD X Y Z 16 14 15 4
VCR
VOUT5 C
41 44 12V 1
R25 Q10 BC847 1K
VOUT6 CVBS/Y
AUD-DEC- IN R AUD-DEC-OUT L AUD-DEC-IN L
2 2 3 Q11 BC847 12V R28 1K R26 75 3 39
AUX VOUT7 CVBS
R27 1K
DEC-B IN DEC-FCN I N DEC-G IN
23 C26 + C27 100nF 10u F C28 + C29 100nF 10uF D2 12V C32 47uF C33 22uF 1N4148 + 12V 1 Q16 BC847 C34 2.2uF C35 2.2uF AUD-VCR- IN R AUD-VCR-IN L AUD-DEC- IN R AUD-DEC-IN L TV-AUD-IN R TV-AUD-IN L 27 29 45 16 18 22 24 2 9V 9V 3 5 12 14 43 7 26 3 C30 + C31 100nF 25 38 60 20 58 62 19 56 54
Vin15-CVBS Vin16-CVBS DIG_VCC VID_VCC AUD_VCC VCC_12V VID_BIAS AUD_BIAS
TV SAT
2 3 1 Q12 BC847 R33 1K R30 75
12V 1
9V
DEC-R I N DEC-FB IN
2 3
Q13 BC847 1 R31 22K Q14 BC847 3 2 Q15 BC847 R32 15K DEC-VID IN 1 PHONO L 2 3 PHONO R I2CSDA I2CSCL MONO AUDIO
B
MACORDIG
VREG_BASE VREG_9V DIG_GND VID_GND AUD_GND
R34 1K
R35 75
' ( & 2 ' ( 5
B
+
6 DIG-A UD-R 6 DIG- AUD-L 5 MacLef tAudio 5 MacRightAudio
MONO AUDIO
+ +
Rin1 Lin1 Rin2 Lin2 Rin3 Lin3 Rin4 Lin4 Rin5 Lin5
DIG VCR AUX TV SAT
AUDIO
MONO PHONO_R PHONO_L
33 35 37 40 42 34 36 31 32 28
PHONO R PHONO L TV-AUD-OUT R TV-AUD-OUT L AUD-VCR-OUT R AUD-VCR-OUT L AUD-DEC-OUT R
DEC-VID OUT
TV
RTV LTV
30V 5V
VCRROUT1 LOUT1 AUXROUT2 LOUT2
IDCBOXHEADER40 R36
I2CSDA 4,5,6 4,5,6 I2CSDA I2CSCL I2CSCL 11 9
HW_MUTE SDA SCL
AUD-DEC-OUT L
CVBSUB 1K
CVBSMOD
I2C
LOGIC
R128 10K
9V
R129 DUMMY
A
A
R130 6 SCRX DUMMY
6
SCTX
All information contained on this drawing is copyr ightof FORCE Electronics A/S Denmar k. Legal actions will be taken against any company using or copying the design/ideas or information contained on this drawing without prior written permission .
T86SU
5 4 3 2
Title SCART & Modulator Document Number Size 1030-00003-4 A2 Date : Thursday, Ja nuary 20, 2000
1
Rev 1.0 Sheet 8 of 9
5
4
3
2
1
Vpp = 15V or 5V.
22V U20 1
D
Vpp
Q18 3 BC857 1
Vpp_A
2
Input
5 8
Output Output NC Output NC Output Adjustment 4 LM317LD
2 3 6 7
Vpp 5V R37 301 1% R38 100K R39 4.7K C36 100nF Q19 3 BC857 1 Vcc_A
D
R41 909 1%
R42 10K
R137 10K Q20 BC847 R43 4.7K
R40 100K
C37 100nF
2 3
1
R44 10K 5%
1
Vpp Q23 BC847 R45 2.43K 1%
Q21 3 BC8571
5V Vpp_B
2
Q22 3 BC857 1
Vcc_B
2 3
R46 100K
C38 100nF
R47 100K R48 4.7K
C39 100nF
2
R49 4.7K
R138 10K
R50 10K
2 3
1
Q24 BC847
C
2
C
R51 J4 6 6 6 6 6 Vpp low -Power A -Power B Vpp A Vpp B Vpp low -Power A -Power B Vpp A Vpp B R52 10K 5V 6 6 6 Card I /O A Card Cl ock A Card Re set A Card I/ O A Clock A Card Re set A Vpp_A conIOA 100 conCLKA conRESA Vcc_A Vpp_B conIOB conCLKB conRESB Vcc_B Vcc_A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND Vpp I/O GND clk Res Vcc GND Vpp I/O GND clk Res Vcc ID A ID B
CARD A
CARD B
IDCBOXHEADER16
6 6
Card d et A Card d et B
Det A Det B
B
B
R53 6 6 6 Card I/ O B Card Cl ock B Card Re set B Card I/ O B Card Clo ck B Card Re set B
100 7 5 4 3 2 1 R54 D3 DALC112S1 10K 5V
H
L
I/O I/O I/O I/O I/O I/O
6 5 4 3 2 1
Vcc_B
8
6 5V
A
A
All information contained on this drawing is copyr ightof FORCE Electronics A/S Denmar k. Legal actions will be taken against any company using or copying the design/ideas or information contained on this drawing without prior written permission .
86S9ÃS@69@S
5 4 3 2
Title Smart Card Re ader If. Document Number Size 1030-00003-4 A2 Date : Thursday, Ja nuary 20, 2000
1
Rev 1.0 Sheet 9 of 9