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A
B
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D
E
Page Index ===============
P01-Cover Page P02-Block Diagram P03-Notes List P04-Dothan(1/2) P05-Dothan(2/2)
1 1
P06-Alviso HOST(1/5) P07-Alviso DDR(2/5) P08-Alviso PCI-E(3/5) P09-Alviso POWER(4/5) P10-Alviso POWER(5/5) P11-DDRI-SODIMM0
Compal Confidential
EFL50/ EFT51 Schematics Document
2
P12-DDRI-SODIMM1 P13-DDR Decoupling P14-Clock Generator P15-CRT Conn. P16-VGA / LCD Conn. P17-ICH6(1/4)_HUB,PCI,HOST P18-ICH6(2/4)_CPU,AC97,IDE,LPC P19-ICH6(3/4)_USB,PM,LAN,GPIO P20-ICH6(4/4)_POWER&GND
2
Intel Dothan/ Celeron M/ Alviso GM(PM) / DDR-2 / ICH6-M (Daughter Card: ATi M24P/ M26P) 2005 / 03 / 08 (B-Test EVT) Rev:0.2
3
P21-HDD/CDROM P22-DVI / TV_Out P24-PCMCIA SOCKET P25-TI 1394A TSB43AB21A P26-LAN BCM5788M P27-LAN Magnetic & RJ45/RJ11 P28-Mimi-PCI Slot P29-AC97 Codec_ALC250D P30-Audio Line in Switch P31-AMP & Audio Jack P32-Super IO SMC217 P33-ENE-KB910 P34-MDC / BT / KBD / TP Conn. P35-BIOS & I/O Port & SATA HDD P36-RJ11/LID Switch / Fan / FIR P37-USB2.0 Conn P38-Docking Conn. P39-PWR_OK / RTC P40-DC INTERFACE P41-Screws P42-PWR-DCIN / Precharge P43-PWR-Charger P44-PWR-Battery Select P45-PWR-3V/5V/12V P46-PWR-GMCH_CORE/1.8V/0.9V P47-PWR-1.5V/2.5V P48-PWR-CPU_CORE
3
Conn
P23-PCMCIA ENE CB1410 & CB714
4
P49-PWR-OTP P50-PWR-PIR
Security Classification Issued Date 2005/03/08
4
Compal Secret Data
Deciphered Date 2006/03/08
Title
Cover Sheet
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Rev 0.2 1 of 51
A
B
C
D
E
Compal confidential
Project Code: EFL50/ EFT51 File Name : LA-2761 CRT & TV-OUT
1
Intel Dothan/ Celeron M CPU
page 4,5
Thermal Sensor ADM1032ARM
page 4
Clock Generator ICS954226AGT
page 14
1
page 15
H_A#(3..31)
400 / 533 Mhz
FSB
H_D#(0..63)
Daughter Card Slot PCI-Express x16 ATi M24P/ M26P VGA Board
page 16
PCI-E BUS
page 15
Intel Alviso GM(PM)
PCBGA 1257
page 6,7,8,9,10
DDR-2
Two Channel DDR-2
DDRII-SO-DIMM X2
BANK 0, 1, 2, 3page 11,12,13
DMI LCD CONN
page 16
2
USB 2.0
USB conn x 3 BT Conn
page 37
2
Intel ICH6-M
PCI BUS BroadCOM BCM4401KFB BCM5788M
page 26
USB 2.0
page 34
mBGA-609
AC-LINK
page 17,18,19,20
Audio CKT ALC250-D
page 29
AMP & Audio Jack
page 31
Jack x2
page 36
Mini PCI Socket
page 28
ENE Controller
CB712
page 23,24
1394 Controller TSB43AB21
page 25
MDC Conn.
RJ11 CONN
page 36
page 36
SATA
3
SATA HDD Conn.
page 21
RJ45 CONN
page 27
Slot 0
page 24
3in1 CardReader page 24 Slot
1 394 Conn.
LPC BUS
PATA
page 25
HDD Conn. CDROM Conn.
page 21
Power On/Off CKT.
page 39
SMsC LPC47N217
RTC CKT.
page 39 page 32
ENE KB910Q
page 33
DC/DC Interface CKT.
page 40
Int. KBD Power Circuit DC/DC
page 42~49
4
Docking Conn. PCI-E Bridge RJ45 VGA DVI TV-Out HP-Out/ Line-Out Mic-in/ Line-in SPDIF Parallel Port Serial Port KB/ Mouse (PS/2)
page 39
3
Power OK CKT.
page 39
DOCKING CONN
page 38
Parellel Port
Serial Port
DOCKING CONN
page 38
page 34
Touch Pad CONN.page 34
BIOS
page 35
2006/03/08
Title
4
Button LED
page 38
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date
Block Diagrams
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Rev 0.2 2 of 51
A
B
C
D
E
STATE
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# HIGH LOW LOW LOW LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH LOW
+VALW ON ON ON ON ON
+V ON ON ON OFF OFF
+VS ON ON OFF OFF OFF
Clock ON LOW OFF
1
Voltage Rails
Power Plane VIN
1
Full ON
Description Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU 1.05V switched power rail 0.9V switched power rail for DDR terminator 1.5V always on power rail 1.5V switched power rail 1.8V switched power rail 1.8V power rail for DDR 2.5V switched power rail 3.3V always on power rail 3.3V power rail 3.3V switched power rail 5V always on power rail 5V switched power rail 5V switched power rail for Module Bay 12V always on power rail RTC power S1 N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON S3 N/A N/A O FF O FF O FF ON O FF O FF ON O FF ON ON O FF ON O FF O FF ON ON S4/ S5 N/A N/A O FF O FF O FF ON* O FF O FF O FF O FF ON* O FF O FF ON* O FF O FF ON* ON
S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)
B+ +CPU_CORE +1.05VS +DDRVTT +1.5VALW +1.5VS +1.8VS +DDRVCC +2.5VS +3VALW +3V +3VS +5VALW +5VS +5VMOD +12VALW +RTCVCC
OFF OFF
Board ID / SKU ID Table for AD channel
Vcc Ra / Rc
Board ID
2
0 1 2 3 4 5 6 7
3.3V +/- 5% 100K +/- 5% Rb / Rd 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC
V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V
V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V
V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V
2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table
Board ID 0 1 2 3 4 5 6 7 PCB Revision 0.1 0.2
BTO Option Table
BTO Item UMA Discrete LAN 10/100 LAN GIGA 1 Spindle 2 Spindle 2 Spindle with SATA 2 Spindle with PATA 1 Spindle with SATA 1 Spindle with PATA With Docking Without Docking With 1394 With 1394 4pin With 1394 6pin BOM Structure GM@ PM@ 4401@ 5788@ 1S@ 2S@ 2SS@ 2SP@ 1SS@ 1SP@ WD@ ND@ 1394@ 1394<4>@ 1394<6>@
External PCI Devices
Device C ardBus 1394 SD Mini-PCI LAN
3
IDSEL#
AD20 AD16 AD20 AD18 AD17
REQ#/GNT#
2 0 2 1 3
Interrupts PIRQA/PIRQB PIRQE PIRQA/PIRQB PIRQG/PIRQH PIRQF
3
EC SM Bus1 address
Device
Smart Battery EEPROM(24C16/02) (24C04)
EC SM Bus2 address
Device
ADM1032
SKU ID Table
SKU ID 0 1 2 3 4 5 6 7 SKU
Address
0001 011X b 1010 000X b 1011 000Xb
Address
1001 110X b
ICH6M SM Bus address
Device
4
Address
1101 001Xb 1001 000Xb 1001 010Xb Security Classification Issued Date 2005/03/08
4
Clock Generator (ICS 954226AGT) DDRII DIMM0 DDRII DIMM2
Compal Secret Data
Deciphered Date 2006/03/08
Title
Notes
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Rev 0.2 3 of 51
5
4
3
2
1
JP20A 6 H_A#[3..31] 6 H_REQ#[0..4] 6 H_RS#[0..2] 6 H_D#[0..63] H_A#[3..31] H_REQ#[0..4] H_RS#[0..2] H_D#[0..63] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 6 H_ADSTB#0 6 H_ADSTB#1
C
D
P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 R2 P3 T2 P1 T1 U3 AE5 A16 A15
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#
Dothan
ADDR GROUP
DATA GROUP
REQ0# REQ1# REQ2# REQ3# REQ4# ADSTB0# ADSTB1# ITP_CLK0 ITP_CLK1 BCLK0 BCLK1
H_ADSTB#0 H_ADSTB#1
13 CLK_CPU_BCLK 13 CLK_CPU_BCLK#
CLK_CPU_BCLK CLK_CPU_BCLK#
B15 B14
HOST CLK
6 H_ADS# 6 H_BNR# 6 H_BPRI# 6 H_BR0# 6 H_DEFER# 6 H_DRDY# 6 H_HIT# 6 H_HITM# 6 H_LOCK# 6 H_CPURST#
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRD Y# H_HIT# H_HITM# H_IERR# H_LOCK# H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
N2 L1 J3 N4 L4 H2 K3 K4 A4 J2 B11 H1 K1 L2 M3
ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET# RS0# RS1# RS2# TRDY#
CONTROL GROUP
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 D25 J26 T24 AD20 C23 K24 W25 AE24 C22 L24 W24 AE25
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
+3VS
U29 2200P_0402_50V7K
2
THERMDA THERMDC
2 3 8 7
D+ DSCLK SDATA
VDD1 ALERT# THERM# GND
1 6 4 5
33 EC_SMB_CK2 33 EC_SMB_DA2
EC_SMB_CK2 EC_SMB_DA2
ADM1032ARM_RM8
SMBus Address: 1001110X (b)
+1.05VS
C
ITP_TDI ITP_TDO H_CPURST# ITP_TMS PRO_CHOT# H_PWRGOOD H_IERR#
R53 R383 R382 R54 R386 R56 R380
2 2 2 2 2 2 2
1
150_0402_5%
1 @ 54.9_0402_1% 1 @ 54.9_0402_1% 1 1 1 1
40.2_0402_1% 56_0402_5% 200_0402_5% 56_0402_5%
+3VS
ITP_DBRRESET#
R381
2
1
150_0402_5%
6 H_TRDY#
B
C8 B8 A9 C9
ITP_DBRRESET# H_DBSY# H_DPSLP# H_DPRSTP# H_DPWR# PRO_CHOT# 17 H_PWRGOOD 6,17 H_CPUSLP# H_PWRGOOD H_CPUSLP# ITP_TCK ITP_TDI ITP_TDO TEST1 TEST2 ITP_TMS ITP_TRST# THERMDA THERMDC H_THERMTRIP#
BPM0# BPM1# BPM2# BPM3# DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT# PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#
DINV0# DINV1# DINV2# DINV3# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
6 6 6 6 6 6 6 6 6 6 6 6
ITP_TRST# ITP_TCK TEST1
R384 R385 R55 R401
2 2 2 2
1 1
680_0402_5% 27.4_0402_1%
B
1 @ 1K_0402_5% 1 @ 1K_0402_5%
6 H_DBSY# 17 H_DPSLP# 17 H_DPRSTP# 6 H_DPWR#
A7 M2 B7 G1 C19 A10 B10 B17 E4 A6 A13 C12 A12 C5 F23 C11 B13 B18 A18 C17
MISC
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
TEST2
0415
H_INIT# C685 1 C686 1 C687 1
2 47P_0402_50V8J 2 47P_0402_50V8J 2 47P_0402_50V8J 2 47P_0402_50V8J
THERMAL
THERMDA DIODE THERMDC THERMTRIP#
TYCO_1612365-1_Dothan
LEGACY CPU
A20M# FERR# IGNNE# INIT# LINT0 LINT1
C2 D3 A3 B5 D1 D4 C6 B4
H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI H_STPCLK# H_SMI#
H_A20M# 17 H_FERR# 17 H_IGNNE# 17 H_INIT# 17 H_INTR 17 H_NMI 17 H_STPCLK# 17 H_SMI# 17
H_NMI H_SMI#
H_CPURST# C688 1
STPCLK# SMI#
6,17 H_THERMTRIP#
A
2
1 C402
2
C401 0.1U_0402_16V4Z
1
R379 @ 10K_0402_5%
1
D
A
THERMDA & THERMDC Trace / Space = 10 / 10 mil
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
Dothon Processor in mFCPGA479
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Rev 0.2 4 of 51
5
4
3
2
1
+CPU_CORE JP20B R144 1 R141 1 220U_D2_4VM_R12 1 + C50 220U_D2_4VM_R12 1 + C151
+CPU_CORE JP20C
2 2
@ 54.9_0402_1% @ 54.9_0402_1%
VCCSENSE VSSSENSE
AE7 AF6
VCCSENSE VSSSENSE VCCA0 VCCA1 VCCA2 VCCA3 VCCQ0 VCCQ1 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PSI# VID0 VID1 VID2 VID3 VID4 VID5 GTLREF BSEL0 BSEL1 COMP0 COMP1 COMP2 COMP3
+VCCA
R393 R388 R387 R417
1 1 1 1
30 mils0_0603_5%
2 @ 0_0603_5% 2 @ 0_0603_5% 2 @ 0_0603_5% 2
+1.05VS
VCCA0 F26 VCCA1 B1 VCCA2 N1 VCCA3 AC26
D
1.8V FOR DOTHAN-A
+1.8VS
P23 W4 D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L5 L21 M6 M22 N5 N21 P6 P22 R5 R21 T6 T22 U21 D6 D8 D18 D20 D22 E5 E7 E9 E17 E19 E21 F6 F8 F18
PSI# CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 GTL_REF0
1 R419
2 @ 0_1206_5%
Dothan
POWER, GROUNG, RESERVED SIGNALS AND NC
1.5V FOR DOTHAN-B
+1.5VS
1 R399
+VCCA 2 0_1206_5%
Trace Width>= 40 mils
1
C405 0.01U_0402_16V7K 2
1
C463
2 10U_0805_10V4Z
C
+CPU_CORE
46 PSI# +1.05VS 46 46 46 46 46 46 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5
E1 E2 F2 F3 G3 G4 H4 AD26 C16 C14 P25 P26 AB2 AB1
R422 1K_0402_1%
B
1 R420
2 2K_0402_1%
13 CPU_BSEL0 13 CPU_BSEL1
CPU_BSEL0 CPU_BSEL1 COMP0 COMP1 COMP2 COMP3
B2 C3 E26 AF7 AC1
RSVD RSVD RSVD RSVD RSVD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A2 A5 A8 A11 A14 A17 A20 A23 A26 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1
1
+
1
+
C49 2 220U_D2_4VM_R12
2
C150 2 220U_D2_4VM_R12
2
+CPU_CORE 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 1 1 1 1 1 1 1 C455 C456 C424 C435 C443 C448 C453
2 2 10U_0805_10V4Z
+CPU_CORE
2 2 10U_0805_10V4Z
2 2 10U_0805_10V4Z
2 10U_0805_10V4Z
1
C423
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 1 1 1 1 1 1 C112 C421 C420 C434 C442 C447
2 10U_0805_10V4Z
+CPU_CORE
2
2 2 10U_0805_10V4Z
2 2 10U_0805_10V4Z
2 10U_0805_10V4Z
1
C60
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 1 1 1 1 1 1 C57 C61 C72 C82 C97 C109
2 10U_0805_10V4Z
+CPU_CORE
2
2 2 10U_0805_10V4Z
2 2 10U_0805_10V4Z
2 10U_0805_10V4Z
1
C71
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 1 1 1 1 1 1 C81 C452 C113 C96 C108 C58
2 10U_0805_10V4Z
2
2 2 10U_0805_10V4Z
2 2 10U_0805_10V4Z
2 10U_0805_10V4Z
+CPU_CORE 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 1 1 1 1 1 1 C668 C669 C670 C671 C672 C673
1
C667
F20 F22 G5 G21 H6 H22 J5 J21 K22 U5 V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC9 AC11 AC13 AC15 AC17 AC19 AD8 AD10 AD12 AD14 AD16 AD18 AE9 AE11 AE13 AE15 AE17 AE19 AF8 AF10 AF12 AF14 AF16 AF18
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Dothan
POWER, GROUND
2 10U_0805_10V4Z
2
2 2 10U_0805_10V4Z
2 2 10U_0805_10V4Z
2 10U_0805_10V4Z M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
TYCO_1612365-1_Dothan
2
0331
Vcc-core Decoupling SPCAP,Polymer MLCC 0805 X5R C,uF 3X330uF 35X10uF ESR, mohm 9m ohm/3 5m ohm/35 ESL,nH 3.5nH/4 0.6nH/35
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24
D
C
1
B
TYCO_1612365-1_Dothan
+1.05VS 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
500 mils
R408 1
A
+ C404
1
C63
1
C68
1
C78
1
C90
1
C75
1
C85
1
C43
1
C42
1
C41
1
C98
2 2 2 2
27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1%
COMP0 COMP1
2
2
2
2
2
2
2
2
2
2
2
A
R407 1
50 mils
150U_D2_6.3VM COMP2 COMP3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R424 1 R425 1
Security Classification
Compal Secret Data
2005/03/08 Deciphered Date 2006/03/08
Title
TRACE CLOSELY CPU > 50 mils
COMP0, COMP2 layout : Width 18mils and Space 25mils COMP1, COMP3 layout : Space 25mils
5 4
Issued Date
Dothan Processor in mFCPGA479
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Rev 0.2 5 of 51
5
4
3
2
1
H_RS#[0..2] 4 H_A#[3..31] 4 H_REQ#[0..4] H_A#[3..31]
H_RS#[0..2] 4 CLK_DREF_SSC R114 1 R122 1
+1.5VS
H_REQ#[0..4] U31A
H_D#[0..63]
2 PM@ 0_0402_5% 2 PM@ 0_0402_5%
H_D#[0..63] 4 U31B
CLK_DREF_SSC#
D
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 H_ADSTB#1 CLK_MCH_BCLK# CLK_MCH_BCLK H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_CPURST# H_ADS# H_TRDY# H_DPWR# H_DRD Y# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# CPU_SLP# H_RS#0 H_RS#1 H_RS#2
G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13 A11 A7 D7 B8 C7 A8 B9 E13 AB1 AB2 G4 K1 R3 V3 G5 K2 R2 W4 H8 K3 T7 U5 H10 F8 B5 G6 F7 E6 F6 D6 D4 B3 E7 A5 D5 C6 G8 A4 C5 B4
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
Alviso
C
4 H_ADSTB#0 4 H_ADSTB#1 13 CLK_MCH_BCLK# 13 CLK_MCH_BCLK 4 4 4 4 4 4 4 4 4 4 4 4 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
HPCREQ# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1 HCLKN HCLKP HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDINV#0 HDINV#1 HDINV#2 HDINV#3 HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HEDRDY# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# HRS0# HRS1# HRS2#
4 H_CPURST# 4 H_ADS# 4 H_TRDY# 4 H_DPWR# 4 H_DRDY# 4 H_DEFER# 4 4 4 4 4 4 4 H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY#
B
+1.05VS R120 2 R111 1 R151 2 R145 1
NC
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
E4 E1 F4 H7 E2 F1 E3 D3 K7 F2 J7 J8 H6 F3 K8 H5 H1 H2 K5 K6 J4 G3 H3 J1 L5 K4 J5 P7 L7 J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6 W6 U3 V5 W8 W7 U2 U1 Y5 Y2 V4 Y7 W1 W3 Y3 Y6 W2 J11 C1 C2 T1 L1 D1 P1
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_VREF H_XRCOMP H_XSCOMP H_YRCOMP H_YSCOMP H_XSWING H_YSWING
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 11 M_CLK_DDR0 11 M_CLK_DDR1 12 M_CLK_DDR3 12 M_CLK_DDR4 11 M_CLK_DDR#0 11 M_CLK_DDR#1 12 M_CLK_DDR#3 12 M_CLK_DDR#4
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4
AA31 AB35 AC31 AD35 Y31 AA35 AB31 AC35 AA33 AB37 AC33 AD37 Y33 AA37 AB33 AC37 AM33 AL1 AE11 AJ34 AF6 AC10 AN33 AK1 AE10 AJ33 AF5 AD10
DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3
DMI
DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMITXP0 DMITXP1 DMITXP2 DMITXP3 SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27
G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25
CFG0 MCH_CLKSEL1 MCH_CLKSEL0 CFG5 CFG6 CFG7 CFG9 CFG12 CFG13 CFG16 CFG18 CFG19
MCH_CLKSEL1 13 MCH_CLKSEL0 13
D
+1.05VS CFG0 CFG0 CFG5 CFG6 CFG7 CFG9 R131 1 R132 1 R127 1 R124 1 R117 1 R119 1
2 10K_0402_5% 2 @ 1K_0402_5% 2 @ 1K_0402_5% 2 1K_0402_5% 2 @ 1K_0402_5% 2 @ 1K_0402_5% 2 @ 1K_0402_5% 2 @ 1K_0402_5% 2 @ 1K_0402_5%
CFG/RSVD
CFG12 R125 1 CFG13 R137 1 CFG16 R140 1
DDR MUXING
SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CS0# SM_CS1# SM_CS2# SM_CS3#
CFG[17:3]: internal pull-up
+2.5VS
C
HOST
CFG18 R128 1 CFG19 R135 1
2 @ 1K_0402_5% 2 @ 1K_0402_5%
11 11 12 12 11 11 12 12 R162 1 R163 1
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
DDR_CKE0_DIMMA AP21 DDR_CKE1_DIMMA AM21 DDR_CKE2_DIMMB AH21 DDR_CKE3_DIMMB AK21 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_OCDCOMP0 M_OCDCOMP1 M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_RCOMPN M_RCOMPP SMVREF M_XSLEW M_YSLEW
CFG[19:18]: internal pull-down
BM_BUSY# EXT_TS0# EXT_TS1# THRMTRIP# PWROK RSTIN# J23 J21 H22 F5 AD30 AE29 A24 A23 D37 C37 AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37
PM_BMBUSY# EXT_TS#0 EXT_TS#1 H_THERMTRIP# VGATE PLT_RST# CLK_DREF_96M# CLK_DREF_96M CLK_DREF_SSC CLK_DREF_SSC# PM_BMBUSY# 18 H_THERMTRIP# 4,17 VGATE 13,18,46 PLT_RST# 16,18,20,32,33,41 CLK_DREF_96M# 13 CLK_DREF_96M 13 CLK_DREF_SSC 13 CLK_DREF_SSC# 13 EXT_TS#0 R139 1 EXT_TS#1 R136 1
AN16 AM14 AH15 AG16 AF22 AF16 AP14 AL15 AM11 AN10 AK10 AK11 AF37 AD1 AE27 AE28 AF9 AF10
2 40.2_0402_1% 2 40.2_0402_1% 10mils 11 M_ODT0 11 M_ODT1 12 M_ODT2 12 M_ODT3 2 80.6_0402_1% 2 80.6_0402_1%
SM_OCDCOMP0 SM_OCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT
CLK PM
DREF_CLKN DREF_CLKP DREF_SSCLKP DREF_SSCLKN NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11
+2.5VS
+1.8V
R165 1 R166 1
2 10K_0402_5% 2 10K_0402_5%
10mils
10mils
CFG[2:0] CFG5 CFG6 CFG7
Refer to sheet 6 for FSB frequency select Low = DMI x 2 High = DMI x 4 Low = DDR-II High = DDR-I
B
HVREF HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING
1 2 1 2
24.9_0402_1% 54.9_0402_1% 24.9_0402_1% 54.9_0402_1%
(10mil:20mil)
ALVISO_BGA1257
* *
Low = DT/Transportable CPU High = Mobile CPU
*
+1.8V
CFG9 CFG[13:12]
CFG16 (FSB Dynamic ODT)
H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil
ALVISO_BGA1257 +1.05VS R164 1K_0402_1% R421 221_0603_1%
Low = Reverse Lane High = Normal Operation 00 01 10 11
*
Un-pop for Dothan-A
4,17 H_CPUSLP# H_CPUSLP# R130 1
= Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation (Default)
1
2
2
0_0402_5%
CPU_SLP#
*
1
0.1U_0402_16V4Z C185
SMVREF
Low = Disabled High = Enabled
2
+1.05VS
+1.05VS
R158
1
1
C179 0.1U_0402_16V4Z
* *
1
1
1
H_YSWING R409 221_0603_1%
(12mil:10mil)
C149 0.1U_0402_16V4Z R423 100_0603_1%
1K_0402_1%
2
2
R405 100_0603_1%
A
1
1
2
CFG18 (VCC Select) CFG19 (VTT Select)
Low = 1.05V (Default) High = 1.5V Low = 1.05V (Default) High = 1.2V
(5mil:15mil)
H_VREF
(12mil:10mil)
H_XSWING
2
*
A
2
2
1
1
C138 0.1U_0402_16V4Z
R406 200_0603_1%
1
C459 0.1U_0402_16V4Z
1
R411 100_0603_1%
2
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
2
2
Alviso HOST (1/5)
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
1
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Rev 0.2 6 of 51
5
4
3
2
1
D
D
U31C 11 DDR_A_BS#0 11 DDR_A_BS#1 11 DDR_A_BS#2 11 DDR_A_DM[0..7] DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_CAS# DDR_A_RAS# DDR_A_WE#
AK15 AK16 AL21 AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3 AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5 AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4 AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15 AN15 AP16 AF29 AF28 AP15
SA_BS0# SA_BS1# SA_BS2# SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
11 DDR_A_DQS[0..7]
11 DDR_A_DQS#[0..7]
C
11 DDR_A_MA[0..13]
11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE#
B
SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#
SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63
AG35 AH35 AL35 AL37 AH36 AJ35 AK37 AL34 AM36 AN35 AP32 AM31 AM34 AM35 AL32 AM32 AN31 AP31 AN28 AP28 AL30 AM30 AM28 AL28 AP27 AM27 AM23 AM22 AL23 AM24 AN22 AP22 AM9 AL9 AL6 AP7 AP11 AP10 AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6 AL4 AM3 AK2 AK3 AG2 AG1 AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_D[0..63] 11 12 DDR_B_BS#0 12 DDR_B_BS#1 12 DDR_B_BS#2 12 DDR_B_DM[0..7]
U31D DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_CAS# DDR_B_RAS# DDR_B_WE#
AJ15 AG17 AG21 AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7 AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4 AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5 AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15 AH14 AK14 AF15 AF14 AH16
SB_BS0# SB_BS1# SB_BS2# SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
12 DDR_B_DQS[0..7]
12 DDR_B_DQS#[0..7]
DDR MEMORY SYSTEM A
12 DDR_B_MA[0..13]
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE#
SB_CAS# SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#
DDR SYSTEM MEMORY B
SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63
AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31 AJ31 AK30 AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23 AJ22 AK22 AH24 AH23 AG22 AJ21 AG10 AG9 AG8 AH8 AH11 AH10 AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_D[0..63] 12
C
B
ALVISO_BGA1257
ALVISO_BGA1257
A
A
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
Alviso DDR (2/5)
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Rev 0.2 7 of 51
5
4
3
2
1
+3VS
+2.5VS
1
15,41 PCIE_MTX_C_GRX_N[0..15] R92 GM@ 2.2K_0402_5% 15,41 PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCEI_GTX_C_MRX_N[0..15] PCEI_GTX_C_MRX_P[0..15]
2 G
D
D
Q10
S
15,33 GMCH_ENBKL
GMCH_ENBKL
2
GM@ BSS138_SOT23
15,41 PCEI_GTX_C_MRX_N[0..15] 15,41 PCEI_GTX_C_MRX_P[0..15]
1
3
LBKLT_EN
D
2 R88
1 @ 0_0402_5%
15,41 15,41 13 13 SDVO_SDAT SDVO_SCLK CLK_MCH_3GPLL# CLK_MCH_3GPLL SDVO_SDAT SDVO_SCLK CLK_MCH_3GPLL# CLK_MCH_3GPLL
U31G
MISC
H24 H25 AB29 AC29 A15 C16 A17 J18 B15 B16 B17
SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC
EXP_COMPI EXP_ICOMPO EXP_RXN0/SDVO_TVCLKIN# EXP_RXN1/SDVO_INT# EXP_RXN2/SDVO_FLDSTALL# EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 EXP_RXP0/SDVO_TVCLKIN EXP_RXP1/SDVO_INT EXP_RXP2/SDVO_FLDSTALL EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 EXP_TXN0/SDVOB_RED# EXP_TXN1/SDVOB_GREEN# EXP_TXN2/SDVOB_BLUE# EXP_TXN3/SDVOB_CLKN EXP_TXN4/SDVOC_RED# EXP_TXN5/SDVOC_GREEN# EXP_TXN6/SDVOC_BLUE# EXP_TXN7/SDVOC_CLKN EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 EXP_TXP0/SDVOB_RED EXP_TXP1/SDVOB_GREEN EXP_TXP2/SDVOB_BLUE EXP_TXP3/SDVOB_CLKP EXP_TXP4/SDVOC_RED EXP_TXP5/SDVOC_GREEN EXP_TXP6/SDVOC_BLUE EXP_TXP7/SDVOC_CLKP EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
D36 D34 E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34 D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34 E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36 D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36
PEG_COMP
1 R115
2
24.9_0402_1%
+1.5VS
21 GMCH_TV_COMPS 21 GMCH_TV_LUMA 21 GMCH_TV_CRMA
GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA R143
2
1
4.99K_0603_1%
2 R108
TV_REFSET 1 0_0402_5%
14 GMCH_CRT_CLK 14 GMCH_CRT_DATA 14 GMCH_CRT_B 14 GMCH_CRT_G 14 GMCH_CRT_R
C
GMCH_CRT_CLK GMCH_CRT_DATA GMCH_CRT_B
+2.5VS R97 R98 R100 R99
1 1 1 1
2 2 2 2
4.7K_0402_5% 4.7K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
GMCH_CRT_CLK GMCH_CRT_DATA LCTLB_DATA LCTLA_CLK 15 15 15 15 GMCH_TXCLKGMCH_TXCLK+ GMCH_TZCLKGMCH_TZCLK+ 15 GMCH_ENVDD
LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA GMCH_ENVDD LIBG
E25 F25 C23 C22 F23 F22 F26 C33 C31 F28 F27 B30 B29 C25 C24 B34 B33 B32 A34 A33 B31
LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL
PCI - EXPRESS GRAPHICS
14 GMCH_CRT_VSYNC 14 GMCH_CRT_HSYNC
VGA
2 R121 2 R107 2 R403
1 PM@ 150_0402_5% 1 PM@ 150_0402_5% 1 PM@ 150_0402_5%
GMCH_CRT_G GMCH_CRT_R GMCH_CRT_VSYNC GMCH_CRT_HSYNC 1 2 REFSET R142 255_0402_1%
E24 E23 E21 D21 C20 B20 A19 B19 H21 G21 J20
DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET
PCEI_GTX_C_MRX_N0 PCEI_GTX_C_MRX_N1 PCEI_GTX_C_MRX_N2 PCEI_GTX_C_MRX_N3 PCEI_GTX_C_MRX_N4 PCEI_GTX_C_MRX_N5 PCEI_GTX_C_MRX_N6 PCEI_GTX_C_MRX_N7 PCEI_GTX_C_MRX_N8 PCEI_GTX_C_MRX_N9 PCEI_GTX_C_MRX_N10 PCEI_GTX_C_MRX_N11 PCEI_GTX_C_MRX_N12 PCEI_GTX_C_MRX_N13 PCEI_GTX_C_MRX_N14 PCEI_GTX_C_MRX_N15 PCEI_GTX_C_MRX_P0 PCEI_GTX_C_MRX_P1 PCEI_GTX_C_MRX_P2 PCEI_GTX_C_MRX_P3 PCEI_GTX_C_MRX_P4 PCEI_GTX_C_MRX_P5 PCEI_GTX_C_MRX_P6 PCEI_GTX_C_MRX_P7 PCEI_GTX_C_MRX_P8 PCEI_GTX_C_MRX_P9 PCEI_GTX_C_MRX_P10 PCEI_GTX_C_MRX_P11 PCEI_GTX_C_MRX_P12 PCEI_GTX_C_MRX_P13 PCEI_GTX_C_MRX_P14 PCEI_GTX_C_MRX_P15 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 C422 1 C437 1 C445 1 C451 1 C460 1 C465 1 C469 1 C476 1 C416 0.1U_0402_16V4Z C428 0.1U_0402_16V4Z C440 0.1U_0402_16V4Z C449 0.1U_0402_16V4Z C457 0.1U_0402_16V4Z C462 0.1U_0402_16V4Z C467 0.1U_0402_16V4Z C474 0.1U_0402_16V4Z C413 0.1U_0402_16V4Z C425 0.1U_0402_16V4Z C438 0.1U_0402_16V4Z C446 0.1U_0402_16V4Z C454 0.1U_0402_16V4Z C461 0.1U_0402_16V4Z C466 0.1U_0402_16V4Z C470 0.1U_0402_16V4Z
TV
C
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
R134 R112
B
1 1 1 1 1
2 2
100K_0402_5% 1.5K_0402_1%
LBKLT_EN LIBG GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA
R109 R118 R101
2 PM@ 150_0402_5% 2 PM@ 150_0402_5% 2 PM@ 150_0402_5%
15 GMCH_TXOUT015 GMCH_TXOUT115 GMCH_TXOUT215 GMCH_TXOUT0+ 15 GMCH_TXOUT1+ 15 GMCH_TXOUT2+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+
LADATAN0 LADATAN1 LADATAN2 LADATAP0 LADATAP1 LADATAP2
LVDS
GMCH_TXCLKGMCH_TXCLK+ GMCH_TZCLKGMCH_TZCLK+
LACLKN LACLKP LBCLKN LBCLKP
0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15
B
C418 1 C430 1 C444 1 C450 1 C458 1 C464 1 C468 1 C475 1
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
15 GMCH_TZOUT015 GMCH_TZOUT115 GMCH_TZOUT2+2.5VS +3VS 15 GMCH_TZOUT0+ 15 GMCH_TZOUT1+ 15 GMCH_TZOUT2+
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
C29 D28 C27
LBDATAN0 LBDATAN1 LBDATAN2
GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+
2
R104 GM@ 4.7K_0402_5%
R87 GM@ 4.7K_0402_5% GMCH_LCD_CLK
C28 D27 C26
LBDATAP0 LBDATAP1 LBDATAP2
2
2
G
1
LDDC_CLK
3
S
1
D
1
ALVISO_BGA1257 GMCH_LCD_CLK 15
Q9 GM@ 2N7002_SOT23
A
+2.5VS +3VS
A
2
2
R105 GM@ 4.7K_0402_5%
2
R404 GM@ 4.7K_0402_5% GMCH_LCD_DATA
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
G
LDDC_DATA
3
S
1
D
Alviso PCI-E (3/5)
Size B Date: Document Number
1
1
GMCH_LCD_DATA 15
Q32 GM@ 2N7002_SOT23
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
EFL50 LA-2761
Wednesday, April 20, 2005 Sheet
1
Rev 0.2 8 of 51
5
4
3
2
1
+1.05VS U31F U31E +1.05VS C195 0.1U_0402_16V4Z V1.8_DDR_CAP1 2 1 V1.8_DDR_CAP2 2 V1.8_DDR_CAP5 C189 0.1U_0402_16V4Z 1 2 1 C198 0.1U_0402_16V4Z
4000mA
2.2U_0603_6.3V6K
D
C
T29 R29 N29 M29 K29 J29 V28 U28 T28 R28 P28 N28 M28 L28 K28 J28 H28 G28 V27 U27 T27 R27 P27 N27 M27 L27 K27 J27 H27 K26 H26 K25 J25 K24 K23 K22 K21 W20 U20 T20 K20 V19 U19 K19 W18 V18 T18 K18 K17 AC1 AC2 B23 C35 AA1 AA2
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
F17 E17 D18 C18 F18 E18 H18 G18 D19 H17 B26 B25 A25 A35 B22 B21 A21 B28 A28 A27 AF20 AP19 AF19 AF18 AE37 W37 U37 R37 N37 L37 J37
120mA
1
+
+3VS_TVDAC
+1.05VS
2
C55 TV@150U_D2_6.3VM
POWER
VCCA_TVBG VSSA_TVBG
VCCD_TVDAC VCCDQ_TVDAC VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCA_LVDS VCCHV0 VCCHV1 VCCHV2 VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2 VCCA_SM0 VCCA_SM1 VCCA_SM2 VCCA_SM3 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6
24mA
+1.5VS
60mA 10mA 2mA 60mA
+1.5VS_DDRDLL +2.5VS
+1.5VS_PEG
1500mA
C432 1 0.47U_0603_16V4Z +1.5VS_3GPLL
VCCA_3GPLL0 VCCA_3GPLL1 VCCA_3GPLL2 VCCA_3GBG VSSA_3GBG VCC_SYNC VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC
Y29 Y28 Y27 F37 G37 H20 F19 E19 G19
2
0.15mA
+2.5VS_3GBG
1
+2.5VS C431 70mA 0.47U_0603_16V4Z 2
+1.5VS +1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL +1.5VS_MPLL +1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL +1.5VS_MPLL
VCCD_HMPLL1 VCCD_HMPLL2 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL
ALVISO_BGA1257
K13 J13 K12 W11 V11 U11 T11 R11 P11 N11 M11 L11 K11 W10 V10 U10 T10 R10 P10 N10 M10 K10 J10 Y9 W9 U9 R9 P9 N9 M9 L9 J9 N8 M8 N7 M7 N6 M6 A6 N5 M5 N4 M4 N3 M3 N2 M2 B2 V1 N1 M1 G1
VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51
POWER
1
C163 0.22U_0402_10V4Z 2
1
B
Please Closed to U31-H20
1
+ C663 150U_D2_6.3VM
+2.5VS
C131 0.22U_0402_10V4Z 2 ALVISO_BGA1257
VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCSM52 VCCSM53 VCCSM54 VCCSM55 VCCSM56 VCCSM57 VCCSM58 VCCSM59 VCCSM60 VCCSM61 VCCSM62 VCCSM63 VCCSM64
1
TV@
C664
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z AM37 AH37 1 1 1 1 1 1 C169 C160 C144 C143 AP29 AD28 +1.8V C154 C152 AD27 2 2 2 2 2 2 AC27 10U_1206_16V4Z AP26 2.2U_0603_6.3V6K 0.1U_0402_16V4Z AN26 D AM26 +1.8V AL26 2200mA AK26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AJ26 AH26 1 AG26 1 1 1 1 1 1 1 1 + C174 C188 C172 C177 AF26 AE26 C200 C175 C176 C178 C187 AP25 2 2 2 2 2 2 2 2 330U_D2E_2.5VM 2 AN25 AM25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AL25 AK25 AJ25 AH25 AG25 +2.5VS AF25 VCCHV(Ball A21,B21,B22) AE25 AE24 AE23 AE22 1 1 1 1 1 1 C101 C100 C94 C107 C92 C102 AE21 AE20 AE19 2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z AE18 AE17 AE16 AE15 AE14 VCCA_LVDS (Ball A35) VCCTX_LVDS(Ball A27,A28,B28) C AP13 AN13 +2.5VS AM13 VCCA_CRTDAC(Ball F19,E19) AL13 AK13 AJ13 AH13 1 1 1 1 C91 C133 C126 C103 AG13 AF13 AE13 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K AP12 AN12 AM12 AL12 AK12 VCC_SYNC(Ball H20) AJ12 AH12 AG12 VCCD_TVDAC (Ball D19) +1.5VS AF12 0.1U_0402_16V4Z 0.1U_0402_16V4Z AE12 AD11 AC11 AB11 1 1 1 1 1 1 C199 C93 C104 C120 C122 C140 C134 AB10 0.1U_0402_16V4Z C197 AB9 0.1U_0402_16V4Z 1 AP8 V1.8_DDR_CAP6 2 2 2 2 2 2 4.7U_0805_10V4Z 2 2 1 AM1 V1.8_DDR_CAP4 2 1 AE1 V1.8_DDR_CAP3 B C182 0.1U_0402_16V4Z 0.022U_0402_16V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z
C665
2
2
2
0307
VCCD_LVDS(Ball A25,B25,B26)
+1.05VS R153
VCCDQ_TVDAC (Ball H17)
+1.5VS_DDRDLL +1.5VS_DDRDLL
@ 1000P_0402_50V7K 0.1U_0402_16V4Z +1.5VS_DPLLA
R160 0_0603_5% 1 2
+1.5VS_PEG +1.5VS +1.5VS_PEG
1 1
C153
2
0_0805_5%
950mA
+1.5VS
1
+ C168
60mA
+1.5VS_DPLLA
+1.5VS_DPLLB L15 60mA CHB1608U301_0603 +1.5VS_DPLLB 1 2 +1.5VS
L16 CHB1608U301_0603 1 2 +1.5VS
1
C183
1
C181
1
C186
1
C146
1
C141
1
C157
1
C165
1
C166
1
C158
1
C159
1
C132
2 10U_1206_16V4Z 2
@ 1000P_0402_50V7K
2 0.1U_0402_16V4Z
2 10U_1206_16V4Z
2 4.7U_0805_10V4Z 2
2 4.7U_0805_10V4Z
2
2 470U_D2_2.5VM2 2.2U_0603_6.3V6K
2 2.2U_0603_6.3V6K
2 2.2U_0603_6.3V6K
2 2.2U_0603_6.3V6K
1
C59
1
C70
1
C77
1
C73
1
C87
1
C80
@ 1000P_0402_50V7K
@ 1000P_0402_50V7K
2 10U_1206_16V4Z 2
@ 1000P_0402_50V7K
2 0.1U_0402_16V4Z
2 10U_1206_16V4Z 2
@ 1000P_0402_50V7K
2 0.1U_0402_16V4Z
+1.5VS_3GPLL +1.5VS_3GPLL R159 L24 0.5_0603_1% CHB1608U301_0603 +2.5VS_3GBG 1 2 +3GPLL 1 2 +1.5VS +2.5VS_3GBG +3VS_TVDAC L17 CHB1608U301_0603 1 2
VCCA_TVDAC
VCCA_TVBG (Ball H18)
1
+1.5VS_HPLL
A
60mA
+1.5VS_HPLL
+1.5VS_MPLL L31 60mA CHB1608U301_0603 +1.5VS_MPLL 1 2 +1.5VS
C184
1
C171
1
C170
1 R123
+3VS 2 +2.5VS 0_0603_5%
1
L21 CHB1608U301_0603 1 2 +1.5VS
1
C129 0.1U_0402_16V4Z
1
C65
1
C74
1
C139
1
C123
1
C136
1
C130
C128
2 10U_1206_16V4Z 2 0.1U_0402_16V4Z 2
@ 1000P_0402_50V7K
2
2
@ 1000P_0402_50V7K
2 10U_1206_16V4Z
1000P_0402_50V7K
2
2
2 1000P_0402_50V7K 2 0.1U_0402_16V4Z
2
A
1
C478
1
C481
1
C477
1
C161
1
C167
1
0.1U_0402_16V4Z
0.022U_0402_16V7K
C155
120mA
2 10U_1206_16V4Z 2
@ 1000P_0402_50V7K
2 0.1U_0402_16V4Z
2 10U_1206_16V4Z 2
@ 1000P_0402_50V7K
2 0.1U_0402_16V4Z
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
Alviso POWER (4/5)
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Rev 0.2 9 of 51
5
4
3
2
1
U31H U31I +1.05VS U31J
D
L12 M12 N12 P12 R12 T12 U12 V12 W12 L13 M13 N13 P13 R13 T13 U13 V13 W13 Y12 AA12 Y13 AA13 L14 M14 N14 P14 R14 T14 U14 V14 W14 Y14 AA14 AB14 L15 M15 N15 P15 R15 T15 U15 V15 W15 Y15 AA15 AB15 L16 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16 AB16 R17 Y17 AA17 AB17 AA18 AB18 AA19 AB19 AA20 AB20 R21 Y21 AA21 AB21 Y22 AA22 AB22 Y23 AA23 AB23 Y24 AA24 AB24 Y25 AA25 AB25 Y26 AA26 AB26
VTT_NCTF17 VTT_NCTF16 VTT_NCTF15 VTT_NCTF14 VTT_NCTF13 VTT_NCTF12 VTT_NCTF11 VTT_NCTF10 VTT_NCTF9 VTT_NCTF8 VTT_NCTF7 VTT_NCTF6 VTT_NCTF5 VTT_NCTF4 VTT_NCTF3 VTT_NCTF2 VTT_NCTF1 VTT_NCTF0 VSS_NCTF68 VSS_NCTF67 VSS_NCTF66 VSS_NCTF65 VSS_NCTF64 VSS_NCTF63 VSS_NCTF62 VSS_NCTF61 VSS_NCTF60 VSS_NCTF59 VSS_NCTF58 VSS_NCTF57 VSS_NCTF56 VSS_NCTF55 VSS_NCTF54 VSS_NCTF53 VSS_NCTF52 VSS_NCTF51 VSS_NCTF50 VSS_NCTF49 VSS_NCTF48 VSS_NCTF47 VSS_NCTF46 VSS_NCTF45 VSS_NCTF44 VSS_NCTF43 VSS_NCTF42 VSS_NCTF41 VSS_NCTF40 VSS_NCTF39 VSS_NCTF38 VSS_NCTF37 VSS_NCTF36 VSS_NCTF35 VSS_NCTF34 VSS_NCTF33 VSS_NCTF32 VSS_NCTF31 VSS_NCTF30 VSS_NCTF29 VSS_NCTF28 VSS_NCTF27 VSS_NCTF26 VSS_NCTF25 VSS_NCTF24 VSS_NCTF23 VSS_NCTF22 VSS_NCTF21 VSS_NCTF20 VSS_NCTF19 VSS_NCTF18 VSS_NCTF17 VSS_NCTF16 VSS_NCTF15 VSS_NCTF14 VSS_NCTF13 VSS_NCTF12 VSS_NCTF11 VSS_NCTF10 VSS_NCTF9 VSS_NCTF8 VSS_NCTF7 VSS_NCTF6 VSS_NCTF5 VSS_NCTF4 VSS_NCTF3 VSS_NCTF2 VSS_NCTF1 VSS_NCTF0 VCC_NCTF10 VCC_NCTF9 VCC_NCTF8 VCC_NCTF7 VCC_NCTF6 VCC_NCTF5 VCC_NCTF4 VCC_NCTF3 VCC_NCTF2 VCC_NCTF1 VCC_NCTF0
ALVISO_BGA1257
VCCSM_NCTF31 VCCSM_NCTF30 VCCSM_NCTF29 VCCSM_NCTF28 VCCSM_NCTF27 VCCSM_NCTF26 VCCSM_NCTF25 VCCSM_NCTF24 VCCSM_NCTF23 VCCSM_NCTF22 VCCSM_NCTF21 VCCSM_NCTF20 VCCSM_NCTF19 VCCSM_NCTF18 VCCSM_NCTF17 VCCSM_NCTF16 VCCSM_NCTF15 VCCSM_NCTF14 VCCSM_NCTF13 VCCSM_NCTF12 VCCSM_NCTF11 VCCSM_NCTF10 VCCSM_NCTF9 VCCSM_NCTF8 VCCSM_NCTF7 VCCSM_NCTF6 VCCSM_NCTF5 VCCSM_NCTF4 VCCSM_NCTF3 VCCSM_NCTF2 VCCSM_NCTF1 VCCSM_NCTF0 VCC_NCTF78 VCC_NCTF77 VCC_NCTF76 VCC_NCTF75 VCC_NCTF74 VCC_NCTF73 VCC_NCTF72 VCC_NCTF71 VCC_NCTF70 VCC_NCTF69 VCC_NCTF68 VCC_NCTF67 VCC_NCTF66 VCC_NCTF65 VCC_NCTF64 VCC_NCTF63 VCC_NCTF62 VCC_NCTF61 VCC_NCTF60 VCC_NCTF59 VCC_NCTF58 VCC_NCTF57 VCC_NCTF56 VCC_NCTF55 VCC_NCTF54 VCC_NCTF53 VCC_NCTF52 VCC_NCTF51 VCC_NCTF50 VCC_NCTF49 VCC_NCTF48 VCC_NCTF47 VCC_NCTF46 VCC_NCTF45 VCC_NCTF44 VCC_NCTF43 VCC_NCTF42 VCC_NCTF41 VCC_NCTF40 VCC_NCTF39 VCC_NCTF38 VCC_NCTF37 VCC_NCTF36 VCC_NCTF35 VCC_NCTF34 VCC_NCTF33 VCC_NCTF32 VCC_NCTF31 VCC_NCTF30 VCC_NCTF29 VCC_NCTF28 VCC_NCTF27 VCC_NCTF26 VCC_NCTF25 VCC_NCTF24 VCC_NCTF23 VCC_NCTF22 VCC_NCTF21 VCC_NCTF20 VCC_NCTF19 VCC_NCTF18 VCC_NCTF17 VCC_NCTF16 VCC_NCTF15 VCC_NCTF14 VCC_NCTF13 VCC_NCTF12 VCC_NCTF11
AB12 AC12 AD12 AB13 AC13 AD13 AC14 AD14 AC15 AD15 AC16 AD16 AC17 AD17 AC18 AD18 AC19 AD19 AC20 AD20 AC21 AD21 AC22 AD22 AC23 AD23 AC24 AD24 AC25 AD25 AC26 AD26 L17 M17 N17 P17 T17 U17 V17 W17 L18 M18 N18 P18 R18 Y18 L19 M19 N19 P19 R19 Y19 L20 M20 N20 P20 R20 Y20 L21 M21 N21 P21 T21 U21 V21 W21 L22 M22 N22 P22 R22 T22 U22 V22 W22 L23 M23 N23 P23 R23 T23 U23 V23 W23 L24 M24 N24 P24 R24 T24 U24 V24 W24 L25 M25 N25 P25 R25 T25 U25
+1.8V
+1.05VS
C
B
Y1 D2 G2 J2 L2 P2 T2 V2 AD2 AE2 AH2 AL2 AN2 A3 C3 AA3 AB3 AC3 AJ3 C4 H4 L4 P4 U4 Y4 AF4 AN4 E5 W5 AL5 AP5 B6 J6 L6 P6 T6 AA6 AC6 AE6 AJ6 G7 V7 AA7 AG7 AK7 AN7 C8 E8 L8 P8 Y8 AL8 A9 H9 K9 T9 V9 AA9 AC9 AE9 AH9 AN9 D10 L10 Y10 AA10 F11 H11 Y11
VSS271 VSS270 VSS269 VSS268 VSS260 VSS259 VSS258 VSS257 VSS256 VSS255 VSS254 VSS253 VSS252 VSS251 VSS250 VSS249 VSS248 VSS247 VSS246 VSS245 VSS244 VSS243 VSS242 VSS241 VSS240 VSS239 VSS238 VSS237 VSS236 VSS235 VSS234 VSS233 VSS232 VSS231 VSS230 VSS229 VSS228 VSS227 VSS226 VSS225 VSS224 VSS223 VSS222 VSS221 VSS220 VSS219 VSS218 VSS217 VSS216 VSS215 VSS214 VSS213 VSS212 VSS211 VSS210 VSS209 VSS208 VSS207 VSS206 VSS205 VSS204 VSS203 VSS202 VSS201 VSS200 VSS199 VSS198 VSS197 VSS196
VSSALVDS VSS195 VSS194 VSS193 VSS192 VSS191 VSS190 VSS189 VSS188 VSS187 VSS186 VSS185 VSS184 VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130
B36 AA11 AF11 AG11 AJ11 AL11 AN11 B12 D12 J12 A14 B14 F14 J14 K14 AG14 AJ14 AL14 AN14 C15 K15 A16 D16 H16 K16 AL16 C17 G17 AF17 AJ17 AN17 A18 B18 U18 AL18 C19 H19 J19 T19 W19 AG19 AN19 A20 D20 E20 F20 G20 V20 AK20 C21 F21 AF21 AN21 A22 D22 E22 J22 AH22 AL22 H23 AF23 B24 D24 F24 J24 AG24 AJ24
VSS
AL24 AN24 A26 E26 G26 J26 B27 E27 G27 W27 AA27 AB27 AF27 AG27 AJ27 AL27 AN27 E28 W28 AA28 AB28 AC28 A29 D29 E29 F29 G29 H29 L29 P29 U29 V29 W29 AA29 AD29 AG29 AJ29 AM29 C30 Y30 AA30 AB30 AC30 AE30 AP30 D31 E31 F31 G31 H31 J31 K31 L31 M31 N31 P31 R31 T31 U31 V31 W31 AD31 AG31 AL31 A32 C32 Y32 AA32 AB32
VSS267 VSS266 VSS265 VSS264 VSS263 VSS262 VSS261 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68
VSS
VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
AC32 AD32 AJ32 AN32 D33 E33 F33 G33 H33 J33 K33 L33 M33 N33 P33 R33 T33 U33 V33 W33 AD33 AF33 AL33 C34 AA34 AB34 AC34 AD34 AH34 AN34 B35 D35 E35 F35 G35 H35 J35 K35 L35 M35 N35 P35 R35 T35 U35 V35 W35 Y35 AE35 C36 AA36 AB36 AC36 AD36 AE36 AF36 AJ36 AL36 AN36 E37 H37 K37 M37 P37 T37 V37 Y37 AG37
D
C
NCTF
B
ALVISO_BGA1257
ALVISO_BGA1257
+1.05VS
+1.5VS
1
C?
1
C?
1
C?
1
C689
1
C690
1
C691
1
C692
1
C693
1
C694
2 0.1U_0603_16V7K
2 0.1U_0603_16V7K
2 0.1U_0603_16V7K
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
+1.05VS
A
V25 W25 L26 M26 N26 P26 R26 T26 U26 V26 W26
A
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
Alviso POWER (5/5)
Size B Date: Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4 3 2
EFL50 LA-2761
Wednesday, April 20, 2005 Sheet
1
Rev 0.2 10 of 51
5
5
4
3
2
1
+1.8V +1.8V @680P_0402_50V7K C658 1 +1.8V @680P_0402_50V7K C659 1
+1.8V
+DIMM_VREF
+1.8V 7 DDR_A_D[0..63] DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..13] DDR_A_DQS#[0..7]
JP31 DDR_A_D0 DDR_A_D1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 @680P_0402_50V7K DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 C273 DDR_A_D4 DDR_A_D5 4.7U_0805_10V4Z DDR_A_DM0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_D14 DDR_A_D15 M_CLK_DDR0 6 M_CLK_DDR#0 6 1
R228 1K_0402_1%
7 DDR_A_DM[0..7] 7 DDR_A_DQS[0..7] 7 DDR_A_MA[0..13] 7 DDR_A_DQS#[0..7]
1
0.1U_0402_16V4Z
1 C272 2
2
2
Layout Note: Place near DIMM
2
2
1
D
+1.8V @680P_0402_50V7K C660 1
+1.8V C661 1
R226 1K_0402_1%
+1.8V
D
2
C310 4.7U_0805_10V4Z
1
C312 4.7U_0805_10V4Z
1
C313 4.7U_0805_10V4Z
1
C311 4.7U_0805_10V4Z
1
C314 4.7U_0805_10V4Z 0.1U_0402_16V4Z 1 2
1
2
2
2
2
2
2
2
+1.8V @ @ @ 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 1 1 1 1 1 1 1 C292 C293 C294 C295 C296 C297 C298
+1.8V @680P_0402_50V7K C662 1 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27
C
DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2 10U_0805_10V4Z @
2
2 2 10U_0805_10V4Z @
2 2 10U_0805_10V4Z @
2 10U_0805_10V4Z @
1
1
1
C260
C277
C276
C275
2
2
2
0304 EMI
+0.9VS DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
6 DDR_CKE0_DIMMA 7 DDR_A_BS#2
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1 DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35
DDR_CKE1_DIMMA 6
1
1
1
1
1
1
1
1
1
1
1
1
1
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13 DDR_A_BS#1 7 DDR_A_RAS# 7 DDR_CS0_DIMMA# 6 M_ODT0 6
2 C303
2 C302
2 C301
2 C300
2 C299
2 C321
2 C317
2 C316
2 C305
2 C304
2 C318
2 C319
2 C320
7 DDR_A_BS#0 7 DDR_A_WE# 7 DDR_A_CAS# 6 DDR_CS1_DIMMA# 6 M_ODT1
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
Layout Note: Place these resistor closely DIMM0,all trace length<750 mil
+0.9VS R269 1 R254 1 R253 1 R268 1 R267 1 R252 1 R251 1 R273 1 R270 1 R255 1 R256 1 R271 1 R257 1 R272 1 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% DDR_A_MA0 DDR_A_MA1 DDR_A_MA3 DDR_A_MA6 DDR_A_MA7 DDR_A_MA9 DDR_A_MA12 DDR_A_MA13 DDR_A_BS#1 DDR_A_WE# DDR_A_CAS# DDR_CS0_DIMMA# DDR_CS1_DIMMA# M_ODT0
DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 R242 1 R243 1 2 10K_0402_5% 2 10K_0402_5% M_CLK_DDR1 6 M_CLK_DDR#1 6 DDR_A_MA2 DDR_A_MA4 DDR_A_MA5 DDR_A_MA8 DDR_A_MA10 DDR_A_MA11 DDR_A_BS#0 DDR_A_BS#2 R264 1 R263 1 R247 1 R246 1 R248 1 R262 1 R249 1 R245 1
2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5%
B
DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49
B
DDR_A_RAS# R265 1 DDR_CKE0_DIMMA R244 1 DDR_CKE1_DIMMA R261 1 M_ODT1 R250 1
Layout Note: Place these resistor closely DIMM0,all trace length Max=1.3"
DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 12,13,38 D_CK_SDATA 12,13,38 D_CK_SCLK
A
D_CK_SDATA D_CK_SCLK +3VS 1 2 C278 0.1U_0402_16V4Z
A
P-TWO_A5640C-A0G16-N
Address: 1001 000X b
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
DDRII- SODIMM SLOT0
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
R ev 0.2 11 of 51
A
B
C
D
E
+1.8V +1.8V +1.8V +DIMM_VREF 7 DDR_B_D[0..63] JP26 0.1U_0402_16V4Z DDR_B_D0 DDR_B_D1 DDR_B_DQS#0 DDR_B_DQS0
1
DDR_B_D[0..63] DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..13] DDR_B_DQS#[0..7] C323 4.7U_0805_10V4Z 1 C325 4.7U_0805_10V4Z 1 C322 4.7U_0805_10V4Z 1 C324 4.7U_0805_10V4Z 1 C326 4.7U_0805_10V4Z 1
DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 2S@
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
7 DDR_B_DM[0..7] 1 C251 7 DDR_B_DQS[0..7] 7 DDR_B_MA[0..13] 7 DDR_B_DQS#[0..7]
DDR_B_D4 DDR_B_D5 C252 DDR_B_DM0 4.7U_0805_10V4Z DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR_B_DM1 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_D14 DDR_B_D15
1
2
2
2
2
2
2
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout Note: Place near DIMM
+1.8V
1
1
1
1
1
C262
C261
C263
C264
C265
M_CLK_DDR3 6 M_CLK_DDR#3 6
2
2
2
2
2
1 C289 0.1U_0402_16V4Z
1 C288 0.1U_0402_16V4Z
1 C286 0.1U_0402_16V4Z
1 C287 0.1U_0402_16V4Z
2 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 6 DDR_CKE2_DIMMB 7 DDR_B_BS#2 DDR_CKE2_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS3_DIMMB# M_ODT3 DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35
3
2
2
2
DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDR_CKE3_DIMMB
+1.8V
1 C250 0.1U_0402_16V4Z
1 C249 0.1U_0402_16V4Z
1 C248 0.1U_0402_16V4Z
1 C247 0.1U_0402_16V4Z
1 C246 0.1U_0402_16V4Z
1 C245 0.1U_0402_16V4Z
1 C274 0.1U_0402_16V4Z
1 C291 0.1U_0402_16V4Z
1 C290 2 0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
2
+0.9VS DDR_CKE3_DIMMB 6 +1.8V 1 1 + 2 C258 2 + C328 150U_D2_6.3VM 1 C306 150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 DDR_B_MA13 DDR_B_BS#1 7 DDR_B_RAS# 7 DDR_CS2_DIMMB# 6 M_ODT2 6
1
1
1
1
1
1
1
1
1
1
1
1
2 C282
2 C285
2 C284
2 C259
2 C283
2 C253
2 C254
2 C255
2 C256
2 C280
2 C281
2 C257
2
7 DDR_B_BS#0 7 DDR_B_WE# 7 DDR_B_CAS# 6 DDR_CS3_DIMMB# 6 M_ODT3
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 M_CLK_DDR4 M_CLK_DDR#4 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 R222 1 R223 1 2 10K_0402_5% 2 10K_0402_5% DDR_B_RAS# DDR_CS2_DIMMB# R231 1 R232 1 M_CLK_DDR4 6 M_CLK_DDR#4 6 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA8 DDR_B_BS#0 DDR_B_MA10 M_ODT3 DDR_CS3_DIMMB# DDR_B_BS#2 DDR_CKE2_DIMMB R203 1 R202 1 R205 1 R204 1 R207 1 R206 1 R209 1 R208 1 R229 1 R230 1
+0.9VS 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% R211 1 R210 1 R213 1 R212 1 R215 1 R214 1 R233 1 R234 1 R235 1 R236 1 R237 1 R238 1 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% 2 56_0402_5% DDR_B_MA9 DDR_B_MA12 DDR_B_MA1 DDR_B_MA3 DDR_B_CAS# DDR_B_WE# DDR_CKE3_DIMMB DDR_B_MA11 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1
Layout Note: Place these resistor closely DIMM0,all trace length<750 mil
3
DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49
DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 11,13,38 D_CK_SDATA 11,13,38 D_CK_SCLK
4
Layout Note: Place these resistor closely DIMM0,all trace length Max=1.3"
2 56_0402_5% 2 56_0402_5%
R239 1 R240 1
2 56_0402_5% 2 56_0402_5%
M_ODT2 DDR_B_MA13
D_CK_SDATA D_CK_SCLK +3VS 1 C244 0.1U_0402_16V4Z 2
+3VS
4
SUPER_AKH-110A-092-3
Address: 1001 010X b
Security Classification Issued Date 2005/03/08
Compal Secret Data
Deciphered Date 2006/03/08
Title
DDRII-SODIMM SLOT1
Size Document Number Custom EFL50 LA-2761 Date: Wednesday, April 20, 2005 Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFO