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KE-42TS2U/42TS2E
PANEL MODULE SERVICE MANUAL
PDP Module Name

FPF42C128127UB-73

UC Model AEP Model UK Model HK Model

FLAT PANEL COLOR TV

Contents
Outline
1.1 Out view 1.2 Feature 1.3 Specification 1.3.1 Functional specification 1.3.2 Display quality 1.3.3 Interface specification

Notes on safe handling of the plasma display
2.1 Notes to follow during servicing

Name and Function
3.1 Configuration 3.2 Block Diagrams 3.2.1 Signal Diagrams 3.3.2 Power Diagrams 3.3 Function 3.5 Protection function

Problem analysis
4.1 Outline of Repair Flow 4.2 Outline of PDP Module Repair Flow 4.3 Checking the Product Requested for Repair 4.4 Operation Test Procedure 4.5 Fault Symptom 4.6 Failure analysis procedure 4.6.1 Procedure of no screenPower supply 4.6.2 Vertical lineVertical bar analysis procedure 4.6.3 Horizontal lineHorizontal bar 4.7 Failure Analysis Using a personal computer 4.7.1 Connection a Computer 4.7.2 Preparation a Computer 4.7.3 Problem Analysis procedure

DISASSEMBLE AND ASSEMBLING 5.1 Disassemble Diagrams
5.2 5.3 5.4 5.5 5.6 5.7 5.8 X-SUS CIRCUIT BOARD REMOVING MANUAL Y-SUS CIRCUIT BOARD REMOVING MANUAL ADDRESS-BUS Left CIRCUIT BOARD REMOVING MANUAL ADDRESS-BUS Right CIRCUIT BOARD REMOVING MANUAL LOGIC CIRCUIT BOARD REMOVING MANUAL CIRCUIT BOARD REMOVING MANUAL Panel chassis Replacement Procedure

Checking and adjustment
6.1 CheckAdjustment list 6.2 CheckAdjustment 6.2.1 CheckAdjustment Procedure 6.2.2 Parameter adjustment 6.2.3 Operation and performance check 6.2.4 Heat-running test 6.2.5 LOGIC CIRCUIT BOARD Data transfer 6.2.6 Accumulation time reset 6.2.7 Shipment setting

The parts Information

Out line
The module is a plasma display module which can be designed in there is no fan in addition to a general feature of the plasma display such as a flat type, lightness, and high-viewing-angle and terrestrial magnetism. Out view 994 921.6

585 522.24

Pixel pitch(horizontal) 0.90mm

Sub- pixel pitch(horizontal) 0.30mm

R G B R G B R G B R G B R G B R G B Pixelpitch(Vertical) R G B R G B R G B R G B R G B R G B 0.51 mm R G B R G B R G B R G B R G B R G B

Feature For high definition television by ALIS method For FAN Less design(Low consumption electric power Flat typeLightness Customizing of module equipped with communication function

1

Specification Functional specification
Item Externals Display panel Module size Weight Display size Resolution Pixel pitch Sub pixel pitch Grayscale(standard) White(display load Ratio 100%) White(display load Ratio 1%, standard) (x,y)white 10% NO 1 2 3 4 5 6 9 11 12 x 994×585×66mm 18kg 921.60×522.24mm (42inch: 16:9) 1024×1024 pixel 0.90(H)×0.51(V)mm 0.30(H)×0.51(V)mm RGB each color 256 Grayscale 140cd/ 700cd/ Specification x x (1000) cd/

Color BrightNess

Chromaticity Coordinates Contrast Data signal

14

(0.300,0.290) 400:1 LVDS(8bit) 52MHz 50KHz(LVDS) 50Hz±1.960±1.7Hz(LVDS) 100-120/200-240VAC 4.5/2.0A 50/60Hz 1W 25dB(A)orless 045 045 2085%RH(no condensation) 2080%RH(no condensation)

+3.3/+5/+75-90/+50 -70VDC 0.05/6/4/2A

(0.300,0.300) (1000:1)

Contrast in Darkroom60Hz 15 Video signal 16 (RGB each color) Dot clockmax 17 Horizontal Sync Signalmax 18 Vertical Sync Signal 19 Input voltage/current 20 Standby electric powermax Shade noise at 18dB(A) or less Temperature(operation) Temperature(storage) Humidity(operation) Humidity(storage) 21 22 23 24 25 26

Sync Signal Powersupply

Noise Guarantee environment

It is made to give priority when there is a delivery specification according to the customer.


Non-lighting cell defect

Display quality specification
Item Total numbersubpixel Densitysubpixel/c SizeH×Vsubpixel Total number(subpixel) Densitysubpixel/c Flickering lighting cell defectsub pixel/c Flickering non-extinguishing cell defect Twice or more bright point White block of 10% load [9 point] In area adjacent 20mm [White] White block of 10% load [9 point] NO 1 2 3 4 5 6 7

Specification
x 15 or less 2 or less However,1 continuousness or less 1×2 or less, Or 2×1 or less 6 or lesseach color 2 or less Each color 2 cells max However,1 continuousness or less 5 or less Number on inside of Non-extinguishing cell defect 20 or less 10 or less Average±0.015 Average±0.015 x x

Non-extinguis hing cell defect Flickering cell defect

High intensity cell defect Brightness variation

8 9 10 11





Color variation

It is made to give priority when there is a delivery specification according to the customer.

2

Interface Specification No . Item
Signal Name
Number of signals I/O

Form

Content of definition
Differential serial data signal.

Reflection signal Timing Signal

RXIN0RXIN0+ RXIN1RXIN1+ RXIN2RXIN2+ RXIN3RXIN3+

1 1 1 1 1 1 1 1

Input

LVDS Different ial

Input video and timing signals after differential serial conversion using a dedicated transceiver. The serial data signal is transmitted seven times faster than the base signal



Display data Clock RXCLKINRXCLKIN+ 1 1 Input LVDS Different ial

Differential clock signal.
Input the clock signal after differential conversion using a dedicated transceiver.

Power down Signal Communication

PDWN

1

Input

SDA SCL

1 1

I/O I/O

CPUGO Communi cation/ Control Control

1

Input

The clock signal is transmitted at the same speed as the base signal. Low :LVDS receiver outputs are all L. LVTTL High:Input signals are active. I2C bus serial data communication signal. LVTTL (I2C) Communication with the control MPU of this product is enabled. Low power consumption mode of the control MPU LVTTL of this product is released.
"High" LVTTL

PDPGO

1

Input

This product started.

is

IRQ

1

Output

LVTTL

(CPUGO="High" Effective) It changes into "Low" "High" when this product enters the undermentioned state. Vcc/Va/Vs output decrease Circuit abnormality detection

3

LVDS Signal Definition and Function
A video signal (display data signal and control signal) is converted from parallel data to serial data with the LVDS transmitter and further converted into four sets of differential signals before input to this product. These signals are transmitted seven times faster than dot clock signals. The dot clock signal is converted into one set of differential signals by the transmitter before input to this product. The LVDS signal definition and function are summarized below:

Signal name

Symbol

Number of signals

Signal definition and function Display data signal Display data signal Display data signalSync SignalControl signal Display data signalControl signal Clock signal

RXIN0RXIN0+

RXIN1RXIN1+ Video signal Timing signal Transmission line RXIN2RXIN2+





RXIN3RXIN3+



Clock transmission line RXCLKINRXCLKIN+



4

Video Signal Definition and Function The table below summarizes the definitions and functions of input video signals before LVDS conversion. Number of signal s 8 8 8

Item

Signal name

Input/ output

Signal definition and function Display data signal R7/G7/B7 is the highest intensity bit. R0/G0/B0 is the lowest intensity bit. Display data timing signal: Data are read when DCLK is low. DCLK is continuously input.

Original Display signal (before LVDS transmit tance)

Video signal (digital RGB)

DATA-R DATA-G DATA-B

Input

Data Clock Horizontal sync signal

DCLK _____ Hsync

Input

Regulates one horizontal line of data: Begins control of the next screen when Hsync is lowered. Screen starts up control timing signal: Begins control of the next screen when Vertical sync _____ 1 Input Vsync is lowered. signal Vsync Input the same frequency in both odd-numbered and even-numbered fields. This signal specifies the display field. H: Odd-numbered field Parity signal PARITY 1 Input L: Even-numbered field Parity signal should be alternated in every Vsync cycle. Display period timing signal. H indicates the display period and L indicates the non display period. Note: Set this timing properly like followings, as is used internally for signal processing. Set the blanking period so that the number of effective display data items in one horizontal period is 852. Blanking 1 Input Set the number of blanking signals in signal BLANK one vertical period to 512, which is one half the number of effective scan lines. If the BLANK changes when the Vsync frequency is switched, the screen display may be disturbed or brightness may change. The screen display is restored to the normal state later when the BLANK length is constant again. This product does not correspond to the progressive display mode by the parity signal fixation. When the parity signal is fixed, this product is reversed arbitrarily internally and used. 1 Input

5

Connector

Specifications The connector specification is shown below. Please do not connect anything with the terminal NC. Signal connector CN1: DF13-20DP-1.25 V (tin-plated) (Maker: HIROSE DENKI)
Pin No. Signal name Pin No. Signal name

1 3 5 7 9 11 13 15 17 19

RXIN0RXIN0+ RXIN1RXIN1+ RXIN2RXIN2+ RXCLKINRXCLKIN+ RXIN3RXIN3+

2 4 6 8 10 12 14 16 18 20

GND SCL GND SDA GND CPUGO PDPGO IRQ PDWN GND

[Conforming connector]

Housing: DF13-20DS-1.25C Contact: DF13-2630SCF

Power Source ConnectorsOnly UB-01 Type Power input connector Power supply output connector for system CN61:B06P-VH CN62:B03P-VH (Maker: JST) (Maker: JST)
Pin No. Symbol Pin No. Symbol






AC(L) N.C AC(N) N.C N.C F.G



V N.C GND

[Conforming connector] Housing:VHR-03N(or M) Contact:SVH-21T-P1.1

[Conforming connector] Housing:VHR-06N(or M) Contact:SVH-21T-P1.1

Power supply output connector for system CN63:B5B-XH-A (Maker: JST)
Pin No. Symbol



Vpr1 N.C. Vpr2 N.C. GND

[Conforming connector] Housing:XHP-5 Contact:SXH-001T-P0.6

6

Power Source Connectors (a)Power supply output
connector for system

(b)Power supply output CN23: B10P-VH(JST)
Pin No. Symbol

(c)Power supply output
connector for system

connector for system

CN6: B6B-PH-SM3-TB(JST)
Pin No. Symbol

CN33: B9PS-VH(JST)
Pin No. Symbol

1 2 3 4 5 6

Vpr2 N.C. GND GND N.C. Vcc

1 2 3 4 5 6 7 8 9 10

Va N.C. Vcc GND GND GND N.C. Vs Vs Vs

1 2 3 4 5 6 7 8 9

Vcc GND GND GND GND N.C. Vs Vs Vs

[Conforming connector] HousingPHR-6 ContactSPH-002T-P0.5L

[Conforming connector] HousingVHR-10N ContactSVH-21T-P1.1 (d)Power supply output (e)Power supply output connector for system connector for system

[Conforming connector] HousingVHR-9N ContactSVH-21T-P1.1

CN42: S7B-PH-SM3-TB(JST)
Pin No. Symbol

CN52: S7B-PH-SM3-TB(JST)
Pin No. Symbol

1 2 3 4 5 6 7

Va N.C. N.C. GND GND N.C. Vcc

1 2 3 4 5 6 7

Va N.C. N.C. GND GND N.C. Vcc

[Conforming connector] HousingPHR-7 ContactSPH-002T-P0.5L (f)Power supply output connector for system
Pin No. Symbol

[Conforming connector] HousingPHR-7 ContactSPH-002T-P0.5L

CN7: 00 6200 520 330 000 [ZIF Right Angle Connector](kyousera elco)
Pin No. Symbol

1 2 3 4 5 6 7 8 9 10

N.C. N.C. N.C. N.C. GND VSAGO GND VCEGO GND PFCGO

11 12 13 14 15 16 17 18 19 20

GND Vra GND Vrs GND Iak GND Vak GND Vsk

7

2.
2. 1

Notes on safe handling of the plasma display
Notes to follow during servicing
The work procedures shown with the Note indication are important for ensuring the safety of the product and the servicing work. Be sure to follow these instructions. Before starting the work, secure a sufficient working space. At all times other than when adjusting and checking the product, be sure to turn OFF the main POWER switch and disconnect the power cable from the power source of the display (jig or the display itself) during servicing. To prevent electric shock and breakage of PC board, start the servicing work at least 30 seconds after the main power has been turned off. Especially when installing and removing the power supply PC board and the SUS PC board in which high voltages are applied, start servicing at least 2 minutes after the main power has been turned off. While the main power is on, do not touch any parts or circuits other than the ones specified.

The high voltage power supply block within the PDP module has a floating ground. If any connection other than the one specified is made between the measuring equipment and the high voltage power supply block, it can result in electric shock or activation of the leakage-detection circuit breaker.
When installing the PDP module in, and removing it from the packing carton, be sure to have at least two persons perform the work while being careful to ensure that the flexible printed-circuit cable of the PDP module does not get caught by the packing carton. When the surface of the panel comes into contact with the cushioning materials, be sure to confirm that there is no foreign matter on top of the cushioning materials before the surface of the panel comes into contact with the cushioning materials. Failure to observe this precaution may result in the surface of the panel being scratched by foreign matter. When handling the circuit PC board, be sure to remove static electricity from your body before handling the circuit PC board. Be sure to handle the circuit PC board by holding the such large parts as the heat sink or transformer. Failure to observe this precaution may result in the occurrence of an abnormality in the soldered areas. Do not stack the circuit PC boards.

Failure to observe this precaution may result in problems resulting from scratches on the parts, the deformation of parts, and short-circuits due to residual electric charge.
Routing of the wires and fixing them in position must be done in accordance with the original routing and fixing configuration when servicing is completed.

All the wires are routed far away from the areas that become hot (such as the heat sink). These wires are fixed in position with the wire clamps so that the wires do not move, thereby ensuring that they are not damaged and their materials do not deteriorate over long periods of time. Therefore, route the cables and fix the cables to the original position and states using the wire clamps.
Perform a safety check when servicing is completed.

Verify that the peripherals of the serviced points have not undergone any deterioration during servicing. Also verify that the screws, parts and cables removed for servicing purposes have all been returned to their proper locations in accordance with the original setup.

8

Name and Function
Configuration

Product label Panel chassis Serial Id label

Y-SUS board

PSU board *1 X-SUS board Signal cable Signal cable Signal cable

Scan module

Ps cable

ADM1

ADM2

ADM3

ADM4

ADM5

ADM6

ADM7

ADM8

XBB

PSU Signal
Address module(ADM)

ABUSL board LOGIC board ABUSR board

The figure shows the article number in the parts information table of clause 7.
*1:Power supply(jig)

9

Block Diagrams signal Diagrams Y-SUS B.
Y-SUS EVEN SW Y-SCAN EVEN SW Y-SUS ODD SW Y-SCAN ODD SW POS /NEG RESET SW

S D M

X B B

X-SUS B X-SUS
EVEN SW X-SCAN EVEN SW

S D M
ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7 ADM8

X B B

X-SUS ODD SW X-SCAN ODD SW POS RESET

ABUSL B
CN51

ABUSR B.
CN41

CN31

CN21

TIMMING

LOGIC B.
CN2

CN3

SCAN CONTROLLER OSC
24MHz

DATA PROCESSOR
comp. RGB GAIN DITHER /ERR

DATA CONVERTER
CN5

SIGNAL INPUT

CN1 LVDS

SUB FIELD PRC.

MEMORY CONTROLLER

CN4
V-SYNC cont.

MPU
OSC 40MHz OSC 80MHz

FRAME MEMORY

2C
Analog Sw

. ailure DET.
FLASH

EEPROM
APC cont.

OSC 10MHz

D/A

Vrs Vra Vrw Vrx

CN7 CN69 PFCgo Vsago Vcego

PSU B. *1

*1:Power supply(jig)
10

Y-SUS B.
Y-SUS EVEN SW Y-SCAN EVEN SW Y-SUS ODD SW Y-SCAN ODD SW POS/NEG RESET SW

Power Diagrams
S D M X B B

X-SUS B X-SUS
EVEN SW X-SCAN EVEN SW

S D M
ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7 ADM8

X B B

X-SUS ODD SW X-SCAN ODD SW POS RESET SW

ABUSL B
Vcc 5V Va 60V Vcc 5V

ABUSR B.
Va 60V

Va
Vx Vw Vb 180V ­5V

CN32

CN52

CN42

CN22 Vxwgo

45V

DC/DC CONVERTER
Vs 60V

YFVCC1 YFVCC2
5V 5V

FVE5H
18V

YFVE1
18V

YFVE2
18V

VE
17V

D/A
CPUgo PDPgo

Vra Vrs Vrw Vrx

XFVCC1
5V

XFVCC2
5V

XFVE1
18V

XFVE2
18V

VE
17V

DC/DC CONVERTER
Vcc 5V Vs 80V


Vcc 5V Vpr2 3.3V

RST

rst

DC/DC CONVERTER
Vcc 5V Vs 80V

LOGIC B.
CN33 CN6

CN23

10A AC100 240V

PFC
CN61

380V

Va Vsago Vcc Vcego Vs

55V CN65

5V

CN68 80V CN67

Servce SW PFCgo 5/3.3V

Vpr2 Vpr1
Vsago

3.3V 5V

CN66

control

Vsago Vcego

PFCgo

CN64

PSU B. *1

Vra

*1:Power supply(jig)

11

Function Logic board Function Data Processor adjustment NTSC/EBU formatColor matrixSwitch RGB gain ControlWhite balance adjustmentAmplitude limitation Error Diffusion Technology(Grayscale adjustment) Dither(Grayscale adjustment) Burn-in Pattern generation Data Converter Quasi out-line adjustment (luminous pattern control) Scan Controller Address driver control signal generator scan driver control signal generator X/Y sustain control signal generator Waveform ROM Waveform Pattern for drive / Timing memory MPU Synchronous detection System control Driving voltage Minute adjustment Abnormal watch (breakdown detection)/abnormal processing Is(sustain) current control (sustain pulse control) Ia(address) current control (sub-field control) External communication control Flash memory (firmware) EEPROM Control parameter memory The accumulation energizing time (Every hour). Abnormal status memory (16 careers)

12

Sub Data Address bit 00 7-0 7

Symbol

Item address MAP VERsion update of ERRor Flag

Function Indicates the version number of the address map. Indicates that an error has occurred. It can be cleared with the ErrRST setting. If this flag is set, · Error code is written. · Cannot enter the PDP-ON mode. Indicates that the drive hours are counted. Indicates that shutdown of the AC power is detected and the PDP has executed the OFF-sequence. It can be cleared with the PSDRST setting. Indicates status of the module. Indicates error code. The error codes of as many as 16 errors in the past can be retrieved with the ERRS setting. . Same error code is not stored

Setting [hex] RANGE 00 ~ FF INITIAL value 01 UB0x/5x 02 UB7x

MAPVER ERRF

0: Not updated 1: Updated

0

01

6

OHRF

update of Operation HouRs Flag Power Shut Down Flag CoNDition Code

0: Not updated 1: Updated 0: Not detected 1: Detected Refer to 4.11.2.6 condition codes.

0

5 4-0

PSDF CNDC

0 irregular

02

7-0

ERRC

ERRor Code

00~FF

00

continuously.

03 04

7-0 7-0

OHRH OHRL

Operation HouRs Higher bits Operation HouRs Lower bits

Indicates the higher 8 bits of the module driving hours. Indicates the lower 8 bits of the module driving hours. It selects the built-in test pattern signals of this display. This setting is valid when the PATON setting is 1.

00~FF 00~FF 0: The single color display is switched every 2 seconds. A total of 8 colors are displayed. 1: All white (Different from actual white.) 0: Displaying the input signal 1: Displaying the built-in pattern 0: Blank 1: Displaying the input signal 0~1 0~1

00 00

20

7

PATSEL

Selecting patterns

0

6

PATON

Built-in pattern display is set to ON. Address data enable DiSPlay PaRiTy

Display of the built-in pattern signal in this product is turned ON/OFF.

0

5 4 3

ADEN -

The black screen is displayed. 0 is set when the input video signal has disturbance. Be sure to use the display with the setting fixed to 0. Be sure to use the display with the setting fixed to 1. Input reflection polarity setting

1 0 1UB0x/5x

3

DSPPRT

0:Emits light by 1UB7x LOW 1:Emits light by High 0: Power OFF 1: Power ON

2

IFON

Interface power supply ON

Switches the interface power ON/OFF. Use this item when you want turn ON the main power of the interface side only when the PDPON is set to 0. This setting is invalid when PDPON is set to 1.

0

13

Sub Data Address bit 1

Symbol

Item High voltage power supply ON

Function Switches ON/OFF the high voltage power supply of PDP. Be sure to use the display with the setting fixed to 1.

Setting [hex] RANGE 0: Power OFF 1: Power ON 0~1 0~7 0~7 0: Luminance has priority. 1: Gradation has priority INITIAL value 0 1 1UB0x/5x 0UB7x

PDPON

0
7-5 7-6 Color correction mode Dynamic Color Balance

Be sure to use the display with the setting fixed to 0. Be sure to use the display with the setting fixed to 0. Selecting the color correction modes. Valid when the CCFON setting is 1

4

CCFMD

0UB7x

3

DCBON

Tracking correction of white balance between the high luminance and the low luminance. When a picture with high luminance/small area is displayed for about 3 minutes or longer, the number of pulses is reduced to about 20% at a maximum. This item can be used to reduce panel temperature/extend useful life when the display is used to show a still image. Be sure to use the display with the setting fixed to 0. Whether the register value is reflected to the operating status of this product, selected by this item. The following switch is executed.

0: OFF 1: ON

0

21

2

HAON

Heat APC function

0: OFF 1: ON

0

1

-

-

0~1

0

0

DSETEN

Data set enable

0: The received register value is reflected from the next field. 1: The received register value is stored so that the DSET setting is reflected from the next field. (DSET setting: Setting bit 0 of address FF) Color collection process is turned ON/OFF. Color collection process is switched. This item is valid when CCFON setting is 1. Be sure to use the display with the setting fixed to 0. Reverse correction level is set. The setup 7 is the test mode. Do not select the setup 7.

0: Invalid 1: Valid

1

7

CCFON

Color correction Color correction format -

0: OFF 1: ON 0: NTSC 1: EBU 0~7 0: OFF 1: 1.0 th power 2: 2.2 nd power 3: 2.4 th power 4: 2.6 th power 5: 2.8 th power 6: USER 7: TEST

0

6

CCFORM

0

5-3 22

-

0

2-0

GAMSEL

Selecting the reverse correction

When the setup 6 is selected, setting of the addressed in the range of 31~51 become valid.

2

14

Sub Data Address bit

Symbol

Item

Function Peak luminance is adjusted.

Setting [hex] RANGE 00~FF 00~FF 00~FF 00~FF 0: Normal 1: IRQ signal clear 0: Normal 1: ERRF flag clear 0~1 0: Normal 1: OHRF flag clear 0: Normal 1: PSDF flag clear 0: Latest error 1: Previous error 2: | E: F: Oldest error 0~3 When password is set 0:OFF 1:ON 0-3 INITIAL value

23 24 25 26

7-0 7-0 7-0 7-0 7

CONTrast R-RATIO G-RATIO B-RATIO IRQRST

Peak luminance R ratio G ratio B ratio Clearing the IRQ output signal

When the display picture load is heavy, the peak luminance is automatically limited. White balance is adjusted. Use the display with at least one item being set to FF (hex). This item implements control to return the IRQ signal from "HIGH" to "Low" level when an error occurs. When this item is set to 1, the IRQ signal is returned to "Low" level. This item implements control to return the ERRF flag to 0 when an error occurs. When this item is set to 1, this setting automatically returns to 0 after returning the ERRF flag to 0. Be sure to use the display with the setting fixed to 0. The control by which the OHRF flag is returned to 0 is done. This setting automatically returns to the state of 0 after returning 0 the ERRF flag when this setting is set to one. This item exercise control to return the PSDF flag to 0 when this machine performs the OFF sequence at AC power shutdown. When this item is set to 1, this setting automatically returns to 0 after returning the PSDF flag to 0. When this setting is changed and the ERRC setting is read out, the error contents (as many as 16 errors) of the module that have occurred in the past can be checked. If more than 16 errors have occurred, the error code is updated starting from the oldest error. Be sure to use the display with the setting fixed to 0. The PWMAX setting is switched to constant brightness (peak electric power) control. The password setting is necessary to turn on this setting. Be sure to use the display with the setting fixed to 0. Sets the maximum power consumption. Set this item in accordance with the status of the machine. Make sure that the respective parts' temperature/panel temperature stays within the specifications. If the setting is set to 3, power consumption increases to a level exceeding the standard consumption. Be sure to execute the heat dissipation design so that respective parts' temperature/panel temperature stay within the specifications. PWMP= Setting of the maximum 0 electric power.

FF FF FF FF 0

6

ERRRST

Clearing the ERRF flag Clearing the OHRF flag

0

5 5 27 4

OHRRST

0UB0x/5x

0UB7x

PSDRST

Clearing the PSDF flag

0

3-0

ERRS

Error code selection

0

28

7-6 7 6

PWMP -

Power Maximam peek control -

0UB0x/5x 0UB7x 0UB7x

5-4

PWMAX

Maximum power consumption

0: -20W 1: -10W 2: ±0W 3: +10W

2UB0x/5x

5-4

PWMAX

Maximum power consumption

0: 0W 1: +20W 2: +30W 3:+40W

0UB7x

15

Sub Data Address bit

Symbol

Item PWMP= 1

Function Setting of peak electric power. Electric power by which electric power is permitted in addition to improve practical brightness to the maximum electric power set 3:+10W Be sure to use the display with the setting fixed to 0. Password of peak electric power setting.The password is described to the delivery specifications. When the password setting is normally done, the reading value of the real thing ground becomes 51. The maximum electric power setting: The maximum over electric power from +10W Time which can operate by the maximum over electric power (*10sec) Sets the input level that implements the forced 0 [LSB] output. Reverse coefficient value is set. Input Output value of 8 [LSB] Reverse coefficient value is set. Input Output value of 16 [LSB] Reverse coefficient value is set. Input Output value of 24 [LSB] When the amount of an over electric power becomes PsTPW× PsTTM or less at PWMP=1, the control by which brightness is lowered is done.

Setting [hex] RANGE 0: -40W 1: -20W 2: ±0W 3: +20W 0~F 51: Permission of PWMP ON Another: Prohibition 0 INITIAL value

3-0 29 7-0

-

Password of peak electric power setting

PWM PASS

FFUB7x

2C

7-0

PsTPW

Ps-Tank PoWer

00-FF

1EUB7x

2D

7-0

PsTTM

Ps-Tank TiMe Reverse correction DC Reverse coefficient 01 Reverse correction 02 Reverse correction 03

00-FF

3CUB7x

31 32 33 34 35 36 37

7-0 7-2 1-0 7-0 7-3 2-0 7-0 7-4 3-0 7-0 7-4

GAM00 GAM01[9: 8] GAM01[7: 0] GAM02[10: 8] GAM02[7: 0] GAM03[11:8] GAM03 [7: 0] GAM04[11:

00~FF 00~FF 00~FF 00~FF 00~FF 00~FF 00~FF

1F 00 04 00 24 00 58

Reverse correction 04

Reverse coefficient value is set. Input Output value of 32 [LSB] 00~FF 00

38

3-0 7-0 7-5

8]
GAM04[7: 0] GAM05[12:

39

00~FF Reverse correction 05 00~FF Reverse coefficient value is set. Input Output value of 40 [LSB] 00~FF Reverse correction 06 Reverse coefficient value is set. Input Output value of 48 [LSB] 00~FF 00~FF

A7

3A

4-0 7-1 0 7-5

01

8]
GAM05[7: 1] GAM06[12:

3B

12

3C 3D

4-0 7-1

01 9A

8]
GAM06[7: 1]

16

Sub Data Address bit 0 7-5 3E 4-0 7-2 1-0 7-5 40 4-0 7-2 1-0 7-6 42 5-0 7-4 3-0 7-6 44 5-0 7-4 3-0 7-6 46 5-0 7-4 3-0 7-6 48 5-0 7-4 3-0 7-6 4A 5-0 7-4 3-0 7-6 4C 5-0 7-4 3-0 7-6 4E 4F 5-0 7-4 -

Symbol

Item Reverse correction 07 Reverse correction 08 Reverse correction 09 Reverse correction 10 Reverse correction 11 Reverse correction 12 Reverse correction 13 Reverse correction 14 Reverse correction 15 -

Function

Setting [hex] RANGE INITIAL value

GAM07[12:

8]
GAM07[7: 2] GAM08[12:

Reverse coefficient value is set. Input Output value of 56 [LSB] -

00~FF

02

3F

00~FF

40

00~FF Reverse coefficient value is set. Input Output value of 64 [LSB] 00~FF Reverse coefficient value is set. Input Output value of 80 [LSB] 00~FF Reverse coefficient value is set. Input Output value of 96 [LSB] Reverse coefficient value is set. Input Output value of 112 [LSB] Reverse coefficient value is set. Input Output value of 128 [LSB] Reverse coefficient value is set. Input Output value of 160 [LSB] Reverse coefficient value is set. Input Output value of 192 [LSB] Reverse coefficient value is set. Input Output value of 224 [LSB] 00~FF 00~FF 00~FF 00~FF 00~FF 00~FF 00~FF 00~FF

03

8]
GAM08[7: 2] GAM09[13:

41

04

04

8]
GAM09[7: 4] GAM11[13:

43

00~FF

F0

07

8]
GAM11[7: 4] GAM11[13:

45

60

0A

8]
GAM11[7: 4] GAM12[13:

47

00~FF

50

0D

8]
GAM12[7: 4] GAM13[13:

49

00~FF

D0

16

8]
GAM13[7: 4] GAM14[13:

4B

00~FF

A0

21

8]
GAM14[7: 4] GAM15[13:

4D

00~FF

E0

2F 90

8]
GAM15[7: 4]

17

Sub Data Address bit 3-0 7 50 6-0 7-5 4-0 7-0 -

Symbol

Item Reverse correction 16 USER Vrs -

Function

Setting [hex] RANGE INITIAL value

GAM16[14:

8]
GAM16[7: 5] UVrs

Reverse coefficient Input Output value of 256 [LSB] Setting Vrs voltage equation: Vrs=2.99*UVrs/255 Setting Vra voltage Standard Standard

00~FF

40

51

00~FF

00 Adjusted in factory Adjusted in factory 0

E5 E6

00~AA

7-0

UVra

USER Vra

equation: Vra=2.99*UVra/255

00~AA

7-3





Be sure to use the display with the setting fixed to 0.
Resetting the UVrs, UVra in both of register and EEPROM to the initial value by setting RCLVr to 1. This setting automatically returns to 0 after resetting the UVrs,Uvra. Storing the UVrs,UVra in register to

0

0:Normal 1: UVrs,UVra initialized 0

2

RCLVr

UVrs/UVra RECALL

FE

0:Normal 1: UVrs,UVra stored EEPROM 0 0 in 0

1

EWRVr

UVrs/UVra Write

EEPROM by setting EWRVr to 1. This setting automatically returns to 0 after resetting the UVrs,UVra.

0





Be sure to use the display with the setting fixed to 0. Be sure to use the display with the setting fixed to 0.
When the DSETEN setting is 1, setting this bit causes all the register setups that

7-1





0

0

FF 0 DSET Data setup

have been set up to now, to be reflected to the operation status of this product. They are reflected from the next field after this bit is accepted.

0: Normal 1: Execute 0

18

3.3.2 Function of X-SUS Board
(1) DC/DC power supply block Vs (+60V) Vw (+185V)/Vx (+45V) Vcc (+5V) XFvcc (+5V, floating)/XFve (+18V, floating)/Ve (+17V)/Vb(-5) (2) X switching block Switching during address period Switching during sustain period Switching during reset period (3) Current detector block Isx (sustain) current detection

3.3.3

Function of Y-SUS Board
Vcc (+5V) Y Fvcc (+5V, floating)/Y Fve (+18V, floating)/Ve (+17V)

(1) DC/DC power supply block

(2) Switching block Switching during address period Switching during sustain period Switching during reset period (3) Current detector block Isy (sustain) current detection Isp (SDM) current detection

3.3.4

Function of PSU Board
AC100­200 Vpr1 (+5V)/Vpr2 (+3.3v)

(1) Standby power supply block

(2) PFC block (AD/DC power supply block) AC100­200 +380V (3) AD/DC power supply block +380V Vcc (+5V) / Vs (+80V)/Va (+60V) (4) Current detection block Ia (address) current detection (5) Abnormal voltage monitoring Vs excess voltage monitoring Va excess voltage monitoring

19



Protection function
Reactivation condition when State of protection operation ×:State change There is no change at the blank. abnormal content is excluded AC PFCgo Vau State Vw, Vx Vs Va Vex Vey Vcc Re-turni Reset Vpr x ng on Stopno latch × × × × × × × Delay Latch × × × × × × × Stopno latch × × × × × × × Delay Latch × × × × × × × Latch × × × × × × × Latch × × × × × × × Delay Latch × × × × × × × Latch × × × × × × × Latch × × × × × × × Delay Latch × × × × × × × Stopno latch × × × × × × × Voltage pendency × × × × × × × no latch Latch Delay Latch Latch Delay Latch Delay Latch Latch Voltage pendency no latch Latch × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×

Abnormality part

Vw

Overvoltage Overcurrent Overvoltage

Vx
Overcurrent Overvoltage

Vs

Low voltage Overcurrent Overvoltage

Va

Low voltage Overcurrent

Vex Vey

Overvoltage Overcurrent Overvoltage

Vcc
Overcurrent Overvoltage

Vpr1
Overcurrent

Vpr2

Overcurrent Overvoltage

Vaux

Overcurrent (Note 2)

PSU Heat sink

Temperature

20

4.
4. 1

Problem Analysis
Outline of Repair Flow
Client
Client claim

Repair product and Claim contents match Y Product block/PDP module block Locating cause of problem Y Is PDP module block Defective ? Y Is the Panel defective ? Y N PDP module sent to factory N N

Recheck the problem description

Product manufacturer (Repair center)

Product problem analysis/Repair

PC board replacement/Parts replacement

Operation normal ?

Y

Repair product and claim contents match

N

Recheck problem description

Is the panel faulty?

Y

Panel replacement/IC module replacement

Repair center

N PC board unacceptable (NG) ? N Processing to prevent recurrence Y Heat run Y PC board replacement/Parts replacement

Packing/Shipment

Operation normal ?

N

Installation in product

Product manufacturer (Repair center)

N

Product runs normally ? Y Return of repaired product

Client

End of repair

21

4.2

Outline of PDP Module Repair Flow
Receipt of returned product (Chapter 4.3)

Does ID of returned product agree with ID of actual Yes Appearance check Yes Appearance unacceptable (NG) ? Yes Repair of appearance requested ? Yes

No

Repair description and returned product rechecked.

No

No 4

Perform operation test (Chapter 4.4).

Repair defective spots Problem recurred ? 2 Yes Check description of repair request. No

Contents match ? Yes

No

Problem symptom nonrecurrence analysis mode

3

1

5

22

1

Fault mode classification (Chapter 4.5)

Fault analysis (Chapter 4.6)

Repair of faulty spots (Chapter 5)

Replace LOGIC PC board or panel chassis ?

Yes

No 3

Adjustment (Chapter 6)

Perform operation test (Chapter 4.4)

Problem repaired?

No

Yes Warranty test (Running)

End of repair

Shipment

23

5

Problem symptom nonrecurrence analysis mode/Shipment process mode

Implement module tapping

No

Problem recurs ?

Yes

Perform running test (Burn-in pattern) No

Problem recurs ?

Turn off the main power

Yes

2

3

24

4.3

Checking the Product Requested for Repair Check the serial ID number of the product requested for repair before starting the problem analysis and repair. Structure of serial ID number is shown below. (1) Checking serial ID number of PDP module (14 digits) The serial ID number of the product that is brought in for service and that of the completed panel chassis has the structure as shown below.
The serial ID number is shown on the bar code label that is attached to the rear of the chassis (aluminum).

N7A 1 01 001A1

Module product label

01 ~ 99 A ~ Z (excluding I and O) Lot No.: 001 ~ 999 A ~ Z (excluding I and O) 1~3 Production week code: 01 ~ 53 Production year (low digit): 0 ~ 9 Product code: N7A model 42 H1/2 type Serial ID label of panel chassis

01A

Version No.:

The module serial ID number and the serial ID number of the completed chassis (product requested for repair) are usually the same when the product is brought in for repair for the first time. (2) Checking serial ID number of constituent PC boards (12 digits) The serial ID number of the module constituent PC boards has the following structure. The serial ID number is shown on the bar code label that is attached to each PC board. Cs 1 01 00001 1A Version No.: 1 ~ 9 , a~z A ~ Z (excluding I and O) Lot No.: 00001 ~ Z9999 Production week code: 01 ~ 53 Production year (low digit): 0 ~ 9 Product code: Cs:X-SUS board : Ct:Y-SUS board : CR : ABUSR board : CS : ABUSL board : Cv:LOGIC board : CU : PSU board

25

4.4

Operation Test Procedure (1) Prepare the test equipment and the module requested for repair. (2) Affix to the stand (jig) the module requested for repair. (3) Connect LOGIC board connector CN1 of the module to the Interface board (jig)CN5 with the dedicated signal cable.

(4) Connect the AC power cable to CN61 on the PSU board of the module requested for repair. (5) Turn on the AC power to the interface board (jig). (6) Select the signal used when a problem occurs, or an all white (7) Set the PDP go switch on the Interface board (jig) to ON. (The main power of the module is turned on.)

Check Fault Symptom

CN1

CN5 PDP go Switch ON OFF

26

4.5 NO

Fault Symptom Fault contents Entire screen does not light.

Fault status

1

After momentarily going on, the screen becomes black immediately or after a few seconds. (Main power is turned off.) Screen lights dimly even on the back screen.

2

Suspected Analysis fault procedure location and measure X-SUS Refer to Y-SUS PSU Chapter Panel chassis 4.6.1 LOGIC ABUSL ABUSR LOGIC Replace LOGIC board Panel chassis LOGIC Refer to Chapter 4.6.2 Replace panel chassis Refer to Chapter 4.6.2 Refer to Chapter 4.6.2 Replace panel chassis

3

Vertical line

Single vertical line (of different color)

4

Vertical line from the middle of effective scan area (Vertical line of different color) Bar width of 1/7 of horizontal size or in multiples of 1/7, is displayed. Abnormal display. Bar width of 3/7 or 4/7 of the screen width, is displayed. Abnormal display. (Vertical line of different color) Horizontal Single horizontal line (No light) or single horizontal line line does not light among the effective scanning area. Single horizontal line does not light. Every other line(No light) Entire screen Vertical bar

Panel chassis

5

Panel chassis ABUSL ABUSR LOGIC
Above boards are connected.

6

ABUSL ABUSR LOGIC

Above boards are connected.

7

Panel chassis

8

X-SUS Y-SUS

Replace X-SUS Y-SUS board

27

NO

Fault contents

Fault status

Suspected fault location Panel chassis

Analysis procedure and measure Replace panel chassis

9

Horizontal Bar width of 1/8 or multiples of 1/8 of the bar screen height, is displayed. Abnormal (Screen does not light) Bar width of 1/2 of the screen height. Abnormal display (Screen does not light) Fixed display contents are always displayed.

10

Panel chassis Y-SUS X-SUS
Above boards are connected.

Refer to Chapter 4.6.3

11 Image sticking

ABCDEF

12 Stains

Oval-shaped points having abnormal luminance are scattered in the upper or lower part of screen.

Perform all white heat run. After judgment, replace panel chassis Panel chassis Perform all white heat run. After judgment, replace panel chassis

Panel chassis

13 Twinkle

The entire screen momentarily becomes brighter or darker.

14 Flicker

The entire screen flickers continuously.

Poor connector contact
CN2,3,21,31

connector / cable re-co nnection or Cable exc hange

15 Luminanc Screen is too dark or too e is abnor bright. (Out of mal specifications) 16 Chromina Colors cannot be displayed nce is ab correctly. normal
28

LOGIC

Replace LOGIC board

17 Sync is disturbed

LOGIC

Replace LOGIC board Replace LOGIC board Replace LOGIC board

18 Picture distorted

LOGIC

19 Steps of gradatio n are skipped 20 Abnormal sound

Luminance linearity is poor.

LOGIC

PSU X-SUS Y-SUS
(Core is broken, or transformer is abnormal.)

21

Control on Contrast, color temperature external adjustment and cannot be communic changed. ation is abnormal

LOGIC

Locate cause of abnormality from listening and viewing. Replace the cause of problem. Replace LOGIC board

29

4.6 4.6.1

Problem Analysis Procedure "The entire screen does not light. Main power is turned off Problem analysis procedure " The entire screen does not light. (Main power is turned off.)

PC for analysis Connected?

Y

Analysis using PC Chapter 4.7

N
Remove CN6 (LOGIC)

Turn on AC power.

PSU board Vpr2 (3.3V) exists?

N

PSU board is defective. STANDBY power supply has abnormality.

Y
Turn off AC power. Connect CN 6 (LOGIC). Turn on AC power

PSU board Vpr2 (3.3V) exists?

N

LOGIC board is defective.

Y
Turn off the AC power. Remove the following power connectors (4 locations): CN 23 (X-SUS CN 33 (Y-SUS) CN 42 (ABUSR) CN 52 (ABUSL) STANDBY power supply (MPU power supply) system has short-circuit.

Turn off the AC power.

End of analysis

1

30

1

X-SUS board CN23 3 4 pins or CN23

Y

6 8 pins

X-SUS board is defective. Switching circuit (power supply) has a short-circuit.

CN23 3 : Vcc 4 : GND 6 : GND 8 : Vs

are shorted.

N

CN33 1 : Vcc 2 : GND 5 : GND 7 : Vs

Y-SUS board CN33 1 2 pins or CN33 7 5 pins are shorted.

Y

N

Remove SDM from the following (2) connectors. CN 34 CN 35

* Refer to Chapter 5.3 for SDM removal. procedure.

Y-SUS board CN33 1 2 pins or CN33 7 5 pins are shorted.

N

SDM is defective (Panel chassis is defective.)

Y

SDM chip/Flexible shorted Y-SUS board is defective. Switching circuit (power supply) has short-circuit.

ABUSL board CN52

1 4 pins or CN52 5 7 pins
are shorted.

Y
Remove ADM from the following (2) connectors. CN 53 CN 54 CN 55 CN 56

CN52 1 : Va 4 : GND 5 : GND 7 : Vcc

* Refer to Chapter 5.4 for ADM removal. procedure.

CN52

ABUSL board 1 4 pins or

N

CN52

5 7
are shorted.

pins

ADM is defective (Panel chassis is defective.) ADM chip/Flexible shorted

Y
ABUSL board is defective.

2

Power supply circuit has a short-circuit.
End of analysis

31

2

CN42 1 : Va 4 : GND 5 : GND 7 : Vcc

ABUSL board CN42 1 4 pins or CN42 5 7 pins are shorted.

Y

N

Remove ADM from the following (4) connectors. CN 43 CN 44 CN 45 CN 46

* Refer to Chapter 5.5for ADM removal. procedure.

ABUSL board CN42 CN42

1 4 pins or 5 7 pins
are shorted.

N

ADM is defective (Panel chassis is defective.)

ADM chip/Flexible shorted

Y

ABUSR board is defective.

Power supply circuit has short-circuit.

Turn on AC power. Turn on the Jig PDP go switch.

End of analysis

PSU board Vcc (5V) exists?

N

LOGIC board is defective.

Y

Control logic power system has short-circuit.
Turn off the AC power.

End of analysis 3

32

3

Turn off the AC power. Connect CN 42(ABUSR). Turn on AC power.

PSU board Vcc (5V) exists ?

N

ABUSR board is defective.

Y
Turn off the AC power. Connect CN 52(ABUSL). Turn on AC power.

Logic buffer circuit has abnormality.

PSU board Vcc (5V) exists ?

N

ABUSL board is defective.

Y
Turn off the AC power. Connect CN 23(X-SUS). Turn on AC power.

Logic buffer circuit has abnormality.

PSU board Vcc (5V) exists ?

N

X-SUS board is defective.

Y
Turn off the AC power. Connect CN 33(Y-SUS). Turn on AC power.

DC/DC power supply circuit or control logic circuit has abnormality.

N
PSU board Vcc (5V) exists ?

Y-SUS board is defective.

Y
Turn off the AC power.

DC/DC power supply circuit or control logic circuit has abnormality. Turn off the AC power.

Remove ADM 1 ­ 8 End of analysis 4

33

4

Turn on AC power.

PSU board Va (60) exists ?

N

ADM is defective (Panel chassis is defective.)

Y

ADM chip operation is abnormal.

Turn off the AC power. ABUSR board Disconnect connector CN42. Turn on AC power.

PSU board Va (60) exists ?

Y

ABUSR board is defective. Power supply system (capacitor, etc.,) has abnormality.

N
Turn off the AC power.

ABUSL board Disconnect connector CN52.

Turn on AC power.

PSU board Va (60) exists ?

Y

ABUSR board is defective. Power supply system (capacitor, etc.,) has abnormality.

N

Turn off the AC. power

End of analysis 5

34

5 PSU board (Va block) is defective. (Panel chassis is defective.)

PSU board Vs(80V) exists

Y

N
Turn off the AC. power Turn off the AC power.

End of analysis Connect SDM/Y-SUS board Disconnect connector.

Measure resistance of SDM power line (Between A1-A2 , B1-B2, C1-C2 and D1-D2.)

SDM power supply line is shorted.

Y

SDM is faulty. (Panel chassis is defective.) SDM chip is shorted. Turn on AC power.

N N

Turn off the AC power.

N

PSU board Vs /Vccis output

Y
Turn off the AC power.

6

A2
35

A1

B1 B2

C1 C2

D1

D2

6

Disconnect connection from XBB/X-SUS board.

Measure resistance of XBB line. (Between A1-B1,B1-A2, A2-B2 ,B2-A3,A3-B3,B3-A4,A4-B4)

XBB line has short-circuit.

Y

XBB is faulty (Panel chassis is defective.) X-SUS board is defective.

N

Y-SUS board is defective. X-SUS board is defective.

End of analysis

A1

B1

A2

B2

A3

B3

A4

B4

36

4. 6. 2 "Vertical line/Vertical bar" Problem analysis procedure Vertical line/Vertical bar

LOGIC ~ ABUS board signal cable has abnormal appearance?

Y

Signal cable is defective.

N
ADM flexible has abnormal appearance?

Y

N
Turn on the main power.

ADM is defective. (Panel chassis is defective.)

Y
One vertical line

End of analysis Tap lightly on ADM flexible heat-melted junction.

N
Any changes?

Y

Heat-melted junction is defective (Panel chassis is defective.)

N

Turn off the main power.

Panel address has open circuit or ADM IC chip is defective.(Panel chassis is defective.)

End of analysis

1

37

1

Bar of 1/2 width on the left does not light?

Y Y

N

Voltage exists at ABUSL board CN 52.

LOGIC board is defective.

N
Turn off the main power. Disconnect CN52 from ABUSL board. Turn on the main power.

Voltage exists at PSU Side?

Y

ABUSL board is defective.

N

Bar of 1/2 width in right does not light?

Y

PSU cable is defective. Connector has poor connection (LOGIC board is defective.)

N

Voltage exists at ABUSR board CN42?

Y

LOGIC board is defective.

N
Turn off the main power. Disconnect CN42 from ABUSL board. Turn on the main power.

Voltage exists at PSU Side?

Y

ABUSR board is defective.

N

PSU cable is defective. Connector has poor connection. (PSU board is defective.)

2

Turn off the main power.

End of analysis

38

2

Vertical line of different color?

Y Y

N

Exists in left 1/2 area.

N

Turn off the main power. Replace ABUSL board (Backup part). Turn on the main power.

Normal?

Y

ABUSL board is defective.

N
Turn off the main power. Replace LOGIC board (Backup part) Turn on the main power.

Y
Normal? LOGIC board is defective.

N
Turn off the main power. Replace LOGIC ~ ABUSL signal cable. Turn on the main power.

Normal?

Y

Signal cable is defective.

N
ADM is defective. (Panel chassis is defective.)

Turn off the main power.

End of analysis

3

4

39

3

4

Turn off the main power. Replace ABUSR board (Backup part). Turn on the main power.

Y
Normal?

ABUSR board is defective.

N
Turn off the main power. Replace LOGIC board (Backup part). Turn on the main power.

Y
Normal? LOGIC board is defective.

N
Turn off the main power. Replace signal cables LOGIC ~ ABUSR. Turn on the main power.

Y
Normal?

Signal cable is defective.

N
ADM is defective. (Panel chassis is defective.)

Panel is defective. (Panel chassis is defective.) Turn off the main power.

End of analysis

40

4.6.3

"Horizontal bar"

Problem analysis procedure

Horizontal bar

Turn off the main power. Replace X-SUS board (Backup parts). Turn on the main power.

Y

N
Normal?

Y

X-SUS board is defective.

N
Turn off the main power. Replace X-SUS0 board (Defective product). Replace Y-SUS board (Backup parts) Turn on the main power.

Normal?

Y

Y-SUS board is defective.

N

Panel chassis is defective.

Turn off the main power.

End of analysis

41

4.7 4.7.1

Problem Analysis Using a Personal Computer Connecting a computer
(1) (2) (3) Set the module in accordance with Chapter 4.4. Connect the RS-232C terminal of the computer to the RS-232C terminal of the interface board. Turn on the main power to the interface board.(Red LED goes on.)

4.7.2

Preparing a computer
(1) (2) (3) Turn on the main power to the computer.

POWER indicator (red LED)

Set the PDPgo switch on the interface board to ON and turn on the main power to the module. For computer running DOS/V: C : „ >FHPH2 For computer running WINDOWS: Start menu Run FHPH2

(4)

The following menu screen appears.

42H2 Main menu ** Module information menu POWER ON menu Problem analysis menu Voltage adjustment menu Accumulated power-on time menu Logic board change menu EXIT

42

*1: *2:

Use COM1: for the computer's communication port. Set the communication setup as follows. Speed: 9600 bps Data: 7 bits Parity: none Stop bit: 1 bit In Windows, restart the computer after setting the communication setup.

*3:

If the program starts up while the module standby power is not yet turned on, the menu screen will not be displayed.

4.7.3

Problem Analysis Procedure
(1) Select the problem analysis menu from the main menu using the key or key and press key to start the program.

42H2 Main menu Module information menu POWER ON menu ** Problem analysis menu Voltage adjustment menu Accumulated power-on time menu Logic board change menu EXIT

43

(2)

Check the error code (hexadecimal number) from the Latest error code read-out menu and locate the faulty position from the following table.

42H2

Problem analysis menu :** :** :** :** :** :** :** :** :** :** :** :** :** :** :** :** :** (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) The state of the module is shown. The latest error code is shown.

**_Condition code Latest error code Previous error Code 2nd previous error code 3rd previous error code 4th previous error code 5th previous error code 6th previous error code 7th previous error code 8th previous error code 9th previous error code 10th previous error code 11th previous error code 12th previous error code 13th previous error code 14th previous error code 15th previous error code Error code clear / execute RETURN EXIT

A past error code is shown in order. new the

All error code is cleared to 0.

Example of displaying breakdown analysis
(3) Select RETURN using the key or key and press key to start the program, then the screen returns to the menu screen. * When EXIT is selected, the screen returns to the WINDOWS or DOS screen.



44

Error code table
ERR code
00 04 06 18 19 1C 1D 1E 1F 24 25 26 28 29 2A 2C 2D 30 31 34 35 39 3B 44 45 46 4C 4D 50 51 54 55 59 5B 5D 61 62 64 65 66 68 69 6A 6C 6D X-SUS Y-SUS X-SUS X-SUS Y-SUS PSU Y-SUS X-SUS

Detect position (board)
LOGIC LOGIC

Contents
(1) STANDBY power is stopped 3.3V power voltage has dropped 3.3V power startup is faulty Internal I2C_SCL1_LOW level Internal I2C_ACK does not respond EEPROM initial setting is defective EEPROM write-down is defective EEPROM user initial setting is defective EEPROM factory setting reading is defective Vex power voltage has decreased Vex power voltage is excessive Vex power startup is faulty. Vx power voltage has dropped Vx power voltage is excessive Vx power startup is faulty. Vpx voltage has dropped Vpx voltage is excessive Vpx1 voltage has dropped Vpx1 voltage is excessive Vpx2 voltage has dropped Vpx2 voltage is excessive PSU LOGIC X-SUS LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC X-SUS X-SUS X-SUS X-SUS X-SUS X-SUS X-SUS X-SUS X-SUS X-SUS X-SUS X-SUS

Suspected faulty board (In the order of higher probability of defect)
(2) (3) (4) (5) (6) (7)

Remarks

PSU temperature has probably increased PSU Y-SUS ADM1 - 8 PSU ABUS-L ABUS-R LOGIC

LOGIC

LOGIC LOGIC

LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC Panel Panel LOGIC LOGIC LOGIC

Vs power current is excessive (during X-SUS operation) Vs power current is excessive (during startup) X-SUS Vey power voltage has dropped Vey power voltage is excessive Vey power startup is faulty. Vpy voltage has dropped Vpy voltage is excessive Vpy1 voltage has dropped Vpy1 voltage is excessive Vpy2 voltage has dropped Vpy2 voltage is excessive Y-SUS Y-SUS Y-SUS Y-SUS Y-SUS Y-SUS Y-SUS Y-SUS Y-SUS

LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC Panel Panel SDM LOGIC Y-SUS X-SUS Y-SUS X-SUS X-SUS Y-SUS LOGIC PSU Y-SUS LOGIC LOGIC LOGIC Panel LOGIC

Vs power current is excessive (during Y-SUS operation) Vs power current is excessive (during startup) Y-SUS Vs power current is excessive (during Y-SUS operation) Vs power voltage is excessive PSU Vs power startup is faulty. Vex and Vpy power voltage has dropped Vex and Vey power voltage is excessive Vex and Vey power startup is faulty. Vw power voltage has dropped Vw power voltage is excessive Vw power startup is faulty. Vpx and Vpy voltage has dropped Vpx and Vpy voltage is excessive X-SUS LOGIC X-SUS LOGIC Y-SUS X-SUS Y-SUS LOGIC LOGIC

X-SUS X-SUS X-SUS

LOGIC Y-SUS Y-SUS

45

ERR code
81 82 99 9B 9D A5 A9 AD B1 B5 B9 BD C5 E2 FC

Detect position (board)
PSU

Contents
(1) Va power voltage is excessive Va power startup is faulty. PSU

Suspected faulty board (In the order of higher probability of defect)
(2) LOGIC LOGIC ABUS-L ABUS-R LOGIC LOGIC LOGIC (3) (4) (5) (6) (7)

Remarks

ADM1 - 8 PSU

Va power current is excessive (during ADM1 - 8 ABUS-L ABUS-R PSU operation) Va power current is excessive (during startup) ADM1 - 8 ABUS-L ABUS-R PSU Va power current is excessive (during ADM1 - 8 ABUS-L ABUS-R PSU operation) ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7 ADM8 LOGIC PSU ADM1 has abnormal heat generation. ADM2 has abnormal heat generation. ADM3 has abnormal heat generation. ADM4 has abnormal heat generation. ADM5 has abnormal heat generation. ADM6 has abnormal heat generation. ADM7 has abnormal heat generation. ADM8 has abnormal heat generation. 5V power startup is faulty. Detection error of Vs and Va voltage. ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7 ADM8 X-SUS PSU PSU PSU PSU PSU PSU PSU PSU PSU Y-SUS LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC PANEL

Excess current is detected in ACCC operation. It can possibly occur depending on screen display.

PSU ABUS-L ABUS-R LOGIC

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5

Disassembling and Reassembling
Unless otherwise specified, use the torque screwdriver for screw tightening, following the tightening torques below. Screw size M3 M4 Tightening torque 0.69±0.049Nm (7±0.5kg·cm) 1.18±0.098Nm (12±1.0kg·cm)

5.1

Exploded View
2 6

8

3

10

5 7 12 9 1 11 4

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5.2 Note

X-SUS Circuit Board Removal/Installation Procedure
When removing the circuit board after the main power is turned on/off, wait for at least one minute before starting to remove the circuit board. If the circuit board removal is started immediately after turning off the main power, it can result in electric shock or damage to the circuit due to residual electric charge.

Remove the circuit board following the steps below. To install the circuit board, reverse the removal procedure. (1) (2) (3) (4) Remove the fixing screws (M3×8) at 9 locations. Release the lock of the FPC connector (CN21) and disconnect the signal cable. Disconnect the cables from the VH connectors (CN22, CN23). Pull out the XSUS board horizontally and disconnect the connectors (CN24, CN25). (4)CN25

(3)CN22

(3)CN23
Pull out

(4)CN24

(2)CN21
Pull out

Note * On handling the FPC connector
To release the lock, release it by gently flipping it with the nail of the thumb or forefinger. Never pinch the lock lever with fingers or hook on it (especially with a fingernail). Doing so might damage the lock lever.

48

(5)

Remove the X-SUS board. Make sure that you do not to hold the heat sink when removing the Y-SUS board.

2

49

5.3

Y-SUS Circuit Board Removal/Installation Procedure
one minute before starting to remove the circuit board. If the circuit board removal is started immediately after turning off the main power, it can result in electric shock or damage to the circuit due to residual electric charge. Remove the circuit board by following the steps below. To install the circuit board, reverse the removal procedure. (1) (2) (3) (4) Remove the fixing screws (M3×8) at 9 locations. Release the lock of the FPC connector (CN31) and disconnect the signal cable. Disconnect the cables from the VH connectors (CN32, CN33). Pull out the YSUS board horizontally and disconnect the connectors (CN34, CN35).

Note When removing the circuit board after the main power is turned on/off, wait for at least

(4)CN35 (3)CN32 (3)CN33

Pull out

(2)CN31 (4)CN34

Pull out

* On handling the FPC connector To release the lock, release it by gently flipping it with the nail of the thumb or forefinger. Never pinch the lock lever with fingers or hook onto it (especially with fingernails). Doing so might damage the lock lever.

50

(5)Remove the Y-SUS board. Make sure that you do not to hold the heat sink when removing the Y-SUS board.

3

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5.4 Note

ABUS-L Circuit Board Removal/Installation Procedure
When removing the circuit board after the main power is turned on/off, wait for at least one minute before starting to remove the circuit board. If the circuit board removal is started immediately after turning off the main power, it can result in electric shock or damage of the circuit due to residual electric charge.

Remove the circuit board by following the steps below. To install the circuit board, reverse the removal procedure. (1) (2) (3) Disconnect the connector CN52 from the ABUS-L board. Raise the lock of the FPC connectors CN53, CN54, CN55 and CN56 to release it and remove the ADM flexible board. Release the lock of the FPC connector CN51 and disconnect the signal cable (FPC).

(1)CN52

(3)CN51

(2)CN56 (2)CN55 (2)CN54 (2)CN53 Note * On handling the FPC connector To release the lock, release it by pulling up the lever. Never pinch the lock lever with the fingers or push hard on it without a cable in it. Doing so might damage the lock lever.

52

(4) Remove the screws (M3X8) fixing the ADM at the 8 locations. (5) (6) Remove the screws (M3X8) fixing the ABUS-L board at the 3 locations. Remove the ABUS-L board

ADM(4 locations)
(7) When installing the ABUS-Lboard, place it so that the ABUS-Lboard is locked by the tabs for fixing it in position (at 3 locations).

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5.5

ABUS-R Circuit Board Removal/Installation Procedure
before starting to remove the circuit board. If the circuit board removal is started immediately after turning off the main power, it can result in electric shock or damage of the circuit due to residual electric charge.

Note When removing the circuit board after the main power is turned on/off, wait for at least one minute

Remove the circuit board by following the steps below. To install the circuit board, reverse the removal procedure. (1) Disconnect the connector CN42 on the ABUS-R board. (2) Raise the lock of the FPC connectors CN43, CN44, CN45, CN46 to release it and disconnect the ADM flexible board. (3) Release the lock of the FPC connector CN41 and disconnect the signal cable (FPC).

(3)CN41

(1)CN42

(2)CN46 (2)CN45 (2)CN44 Note (2)CN43

* On handling the FPC connector To release the lock, release it by pulling up the lever. Never pinch the lock lever with the fingers or push hard on it without a cable in it. Doing so might damage the lock lever.
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(4) Remove the screws (M3X8) fixing the ADM at the 8 locations. (5) Remove the screws (M3X8) fixing the ABUS-R board at the 3 locations. (6) Remove the ABUS-R board.

5

ADM(4 locations)

(7) When installing the ABUS-R board, place it so that the ABUS-R board is locked by the tabs for fixing it in position (at 3 locations).

55

5.6

LOGIC Board Removal/Installation Procedure
Remove the circuit board by following the steps below. To install the circuit board, reverse the removal procedure. (1) (2) (3) Disconnect the EH connector CN6. Release the lock of the FPC connectors CN2, CN3, CN4, CN5 and disconnect the signal cable (FPC). Slide the lock of the FPC connector CN7 toward the PSU board side, then press it down toward the front and remove the PSU signal cable.

3 CN7

1 CN6 2 CN2

2 CN3

Note

2 CN5

2 CN4

* On handling the FPC connector To release the lock, release it by gently flipping it. Never pinch the lock lever with the fingers or hook onto it (especially with fingernails). Doing so might damage the lock lever.

56

(4) (5)

Remove the screws (M3×8) fixing the LOGIC board in position at 2 locations. Remove the LOGIC board.

1

(6)

When installing the LOGIC board, place it so that the LOGIC board is locked by the tabs for fixing it in position (at 3 locations).

57

5.7

PSU Board Removal/Installation Procedure
before starting to remove the circuit board. If the circuit board removal is started immediately after turning off the main power, it can result in electric shock or damage to the circuit due to residual electric charge. Remove the circuit board by following the steps below. To install the circuit board, reverse the removal procedure. (1) Release the lock of the cable clamp (large) .(At 4 locations) (2) Disconnect the X-SUS board connector CN23. (3) Disconnect the Y-SUS board connector CN33. (4) Disconnect the ABUSR board connector CN42. (5) Disconnect the ABUSL board connector CN52. (6) Remove the wires (4), (5) from the cable clamp (small) . (7) Disconnect the LOGIC board connector CN6. (8) Disconnect the PSU signal cable from the PSU board connector CN69 side.

Note When removing the circuit board after the main power is turned on/off, wait for at least two minute

(8)CN69

(3)CN33

(2)CN23

(1) Cable clamps

(7)CN6

(4 locations)

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(4)CN52

(6) Cable clamps (2 locations)

(4)CN42

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(9) (10)

Remove the screws (M3×8) fixing the PSU board in position. (9 locations) Use cutting pliers to cut the nylon bands tying the following 5 power cables. CN64 (PSU) ~ CN32 (Y-SUS) CN65 (PSU) ~ CN23 (X-SUS) CN66 (PSU) ~ CN42 (ABUSR) CN67 (PSU) ~ CN52 (ABUSL) : : : :

(11)

CN22 (X-SUS) ~ CN32 (Y-SUS) : Remove the PSU board.

6

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5.8

Panel Chassis Replacement Procedure
(1) Remove the 6 types of printed-circuit board (X-SUS, Y-SUS, ABUSL, ABUSR, LOGIC, PSU) that are installed in the panel module. For the removal procedure, refer to Section 5.2 to 5.7. * Before removing the above 6 types of board, be sure to remove both ends of the single power cable (BLU) and those of the five FPC cables (WHT) that are used to connect the circuit boards.

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(2) (3)

***Install the printed-circuit board that was removed in step (1) and fix it in position. (Refer to the exploded view shown in Section 5.1.) Print the serial ID number of the product to be repaired on the product label which is prepared separately. Attach the product label to the panel chassis on top of the Y-SUS board (See the photo).

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(4) When the installation of the board is complete, route the wires as shown below.
Pass the CN52 cable (RED/ BLK) under the signal cable. Route it on top of the PSU signal cable.

Enlarge

Pass the CN42 cable (YEL/BLK) under the signal cable.

CN63

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6
6.1

Operation Check and Adjustment Method
List of Check and Adjustment Items
Adjustment position Check and adjustment When PDP panel is replaced When X-SUS board is replaced When Y-SUS board is replaced Required timing When LOGIC board is replaced When ABUS board is replaced When PSU board is replaced Jig/tools Labor Labor (persons) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 required Time (minutes) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Adjustment item (Minor item) Is detection adjustment Ve voltage adjustment Vw voltage adjustment Ve voltage adjustment Is detection adjustment PFC voltage adjustment Vs adj1 Vs adj2 Va adj2 Vs f min Vpr adj Vcc f min Vcc adj Va adj1 Vaa Va f min Vs voltage adjustment Va voltage adjustment Vw voltage adjustment Vx voltage adjustment (Name of the part)

Adjustment item (Major item) VR adjustment

Parameter adjustment

X-SUS board VR1 X-SUS board VR4 X-SUS board VR3 Y-SUS board VR1 Y-SUS board VR2 PSU board RV301 PSU board RV801 PSU board RV802 PSU board RV803 PSU board RV901 PSU sub-board RV201 PSU sub-board RV150 PSU sub-board RV270 PSU sub-board RV860 PSU sub-board RV861 PSU sub-board RV950 LOGIC board(Vsvolt) LOGIC board(Vavolt) LOGIC board(Vwvolt) LOGIC board(Vxvolt)

Be sure to keep the default setup set at the factory. (Do not change the VR control settings.)

Digital voltmeter , screwdriver





Error history clear Default setting Accumulated power-on time clear

LOGIC board (EEPROM) LOGIC board (EEPROM)



Interface board, personal computer, Digital voltmeter Interface board, personal computer

: Check, adjustment, or setup

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6.2 6.2.1

Check and Adjustment Method Check and adjustment procedure
Check and adjustment

Was LOGIC board replaced?

Y
Logic board data transfer (Section 6.2.5)

N

Was Panel chassis replaced?

Y
Parameter adjustment (Section 6.2.2)

N

Operation/performance check (Section 6.2.3)

No abnormality?

N

Y
Burn-in mode setting (Section 6.2.4)

Heat run (Section 6.2.4)

Abnormal

Y

N
Was Panel chassis replaced?

Y

Accumulated power-on time reset (Section 6.2.6)

N

Default setup (Error history clear) (Section 6.2.7)

End

Re-analysis To Section 4.2

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6.2.2
Item 1

Parameter adjustment
Adjustment items Vs voltage adjustment Measurement point PSU board TP5 Adjustment value (conditions) Voltage setting label indication value* ±1% (all black) Remarks

List of parameter adjustment items

2

Va

voltage adjustment

PSU board TP4

Voltage setting label indication value* ±1% (all black)

3

Vw voltage adjustment

X-SUS board connector CN26 6-pin

Voltage setting label indication value* ±1% (all black)

4

Vx

voltage adjustment

X-SUS board connector CN26 1-pin

Voltage setting label indication value* ±1% (all black)

*: Voltage setting label shows the following messages at the top left of the back of the chassis. < LOT > Vs = . V Va = . V Vw = . V Vx = . V

CN26(Vx) TP5(Vs) CN26(Vw)

TP4(Va) TP6(GND)

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(1)

From the main menu, select the voltage adjustment menu with the key or key and press the key.
42H2 Main menu Module information menu Power ON menu Problem analysis menu ** Voltage adjustment menu Accumulated power-on time menu Logic board change menu EXIT

(2)

From the voltage adjustment menu, adjust parameters in the order starting from Vs, Va, Vw, and Vx. Select parameter with the key or key and adjust the parameter with the key (increment) or key (decrement). The adjustment values are shown on the voltage label that is attached to the panel chassis.
42H2 Voltage adjustment menu ** Voltage adjustme