Text preview for : Mainboard_Foxconn_Model-748A01.pdf part of some brands - algumas marcas some schematic motherboards notebooks downloaded from www.freeservicemanuals.net. alguns esquemas placa-mae e notebook baixados de www.freeservicemanuals.net.
Back to : Notebook_MB schematic.par | Home
5
4
3
2
1
Foxconn Precision Co.Inc. 748A01
D
Date:2004/03/ 01
D
PAGE INDEX 01. 02 . 0 3. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. Index Page Topology Reset Map Clock Dist ribution Power Deli very Map C PU-1 C PU-2 C PU-3 ISL6563 V CCP ISL6563 V CCP 748-1(Host /AGP) 748-2 Mem ory 748-3 MuTI OL/Other 748-4 Pow er 2.5V_DDR & 1.25V_VTT SB1.8V & SB 3V & 5V_DUAL 1D8V_VCC & VDDQ Hardware T rap* Main Clock Generator Clock Buffe r-1(3DDR/MIX) DDR/MIX DI MM1,2 DDR/MIX DI MM3 SSTL-2 Term ination Res AGP.SCH 25. 26. 27. 28. 29. 30. 31 . 32. 33. 3 4. 35. 36. 37. 38. 39 . 40. 41. 42. 43. 44. 45. 46. 47. 48. SIS964-PCI, IDE, MUTIOL SIS964-LPC /MII/GPIO SIS964-USB , SATA SIS964-PO WER PCI 1&2.S CH PCI 3&4.S CH PCI5.SCH VT6307 USB Header & 1394 Port LAN POWER RTL8110S/R TL8100C LAN & USB PORT IDE.SCH AC97 CODEC .SCH AC97 I/O ITE8705 Keyboard M ouse.SCH FAN HW Mon itor BIOS/FLOP PY COM/PRT P ORT Power BTN/R TC Batt.SCH Power Conn ector GPIO Sett ing Change li st
C
C
B
B
A
A
TECHNOLOGY COPR.
Title
Index
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
1
of
48
5
4
3
2
1
AMD K7
D D
Host Bus
AGP SLOT
DDR SDRAM
SiS748
CHANNEL A CHANNEL B
MuTIOL 1G
PCI Slot 1
C
Gigabit LAN RJ45 LAN PHY AC'97 Audio Codec Audio I/O SATA1,2
C
PCI Slot 2 PCI Slot 3 PCI Slot 4 PCI Slot 5
ATA 66/100/133
SiS964
PS/2 Back Panel LPC Bus USB 0 USB 1
IDE 1 IDE 2
B
KEYBOARD /MOUSE
Front Panel
B
USB 4 USB 5 USB 6 USB 7 USB 3
Media Interface
FAN 1
FAN CONTROL
USB 2
VOLTAGE MONITOR
FAN 2 FAN 3 ISA Bus ISA ROM
LPC Super I/O
TEMPERATURE MONITOR
A
A
IR
PARALLEL
FLOPPY
TECHNOLOGY COPR.
Title
Topology
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
2
of
48
5
4
3
2
1
D
D
C
C
B
B
A
TECHNOLOGY COPR.
Title
A
Reset Map
Document Number Re v
748A01
Date: Sunday, September 05, 2004 Sheet 3 of 48
A
5
4
3
2
1
5
4
3
2
1
D
D
C
C
B
B
A
A
TECHNOLOGY COPR.
Title
Clock Distribution
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
4
of
48
5
4
3
2
1
D
D
C
C
B
B
A
A
TECHNOLOGY COPR.
Title
Power Delivery Map
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
5
of
48
8
11 SDATAINCLKJ[0..3] 11 SDATAOUTCLKJ[0..3] 11 SADDINJ[2..14] 11 SADDOUTJ[2..14] 11 SDATAJ[0..63]
7
SDATAINCLKJ[0..3] SDATAOUTCLKJ[0..3]
6
5
4
3
L1 ADINCLKJ
2
L2 L0603 4.7nH 2
1
L0603 4.7nH 2 SADDINCLKJ SADDINCLKJ 11
1
1
10/10 SADDINJ[2..14] THERMDA SADDOUTJ[2..14] THERMDC SDATAJ[0..63] THERMDA THERMDC 40,42 42
* 4.7nH
U1A VCCP ADINCLKJ R1 680 +/-5% SADDINJ0 SADDINJ1 SADDINJ2 SADDINJ3 SADDINJ4 SADDINJ5 SADDINJ6 SADDINJ7 SADDINJ8 SADDINJ9 SADDINJ10 SADDINJ11 SADDINJ12 SADDINJ13 SADDINJ14 SADDOUTCLKJ
BC1 2.7pF 50V, NPO, +/-0.25pF C0603
C
B
RSTCLK CLKIN SDATAIN_VALID# SDATAOUT_VALID# NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 NC44 NC45 NC46 NC47 NC48 NC49 NC50 NC51 NC52 NC53 NC54 NC55 NC57 NC58 NC59 NC60 NC61 NC62 NC63 NC64 NC65 NC66 NC67 NC68 SYSFILLVALID#
AN19 AN17 AN33 AL31 AJ31
SOCKETA SDATAINVALJ
* *
SDATAJ0 SDATAJ1 SDATAJ2 SDATAJ3 SDATAJ4 SDATAJ5 SDATAJ6 SDATAJ7 SDATAJ8 SDATAJ9 SDATAJ10 SDATAJ11 SDATAJ12 SDATAJ13 SDATAJ14 SDATAJ15 SDATAJ16 SDATAJ17 SDATAJ18 SDATAJ19 SDATAJ20 SDATAJ21 SDATAJ22 SDATAJ23 SDATAJ24 SDATAJ25 SDATAJ26 SDATAJ27 SDATAJ28 SDATAJ29 SDATAJ30 SDATAJ31 SDATAJ32 SDATAJ33 SDATAJ34 SDATAJ35 SDATAJ36 SDATAJ37 SDATAJ38 SDATAJ39 SDATAJ40 SDATAJ41 SDATAJ42 SDATAJ43 SDATAJ44 SDATAJ45 SDATAJ46 SDATAJ47 SDATAJ48 SDATAJ49 SDATAJ50 SDATAJ51 SDATAJ52 SDATAJ53 SDATAJ54 SDATAJ55 SDATAJ56 SDATAJ57 SDATAJ58 SDATAJ59 SDATAJ60 SDATAJ61 SDATAJ62 SDATAJ63
AA35 W37 W35 Y35 U35 U33 S37 S33 AA33 AE37 AC33 AC37 Y37 AA37 AC35 S35 Q37 Q35 N37 J33 G33 G37 E37 G35 Q33 N33 L33 N35 L37 J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15 E9 A13 C9 A9 C21 A21 E19 C19 C17 A11 A17 A15
F8 F30 G11 G13 G19 G21 G27 G29 G31 H6 H8 H10 H28 H30 H32 J5 J31 K8 K30 L31 N31 Q31 S7 S31 U7 U31 W7 W31 Y5 Y31 AA31 AC31 AD8 AD30
D
SYSDATA#0 SYSDATA#1 SYSDATA#2 SYSDATA#3 SYSDATA#4 SYSDATA#5 SYSDATA#6 SYSDATA#7 SYSDATA#8 SYSDATA#9 SYSDATA#10 SYSDATA#11 SYSDATA#12 SYSDATA#13 SYSDATA#14 SYSDATA#15 SYSDATA#16 SYSDATA#17 SYSDATA#18 SYSDATA#19 SYSDATA#20 SYSDATA#21 SYSDATA#22 SYSDATA#23 SYSDATA#24 SYSDATA#25 SYSDATA#26 SYSDATA#27 SYSDATA#28 SYSDATA#29 SYSDATA#30 SYSDATA#31 SYSDATA#32 SYSDATA#33 SYSDATA#34 SYSDATA#35 SYSDATA#36 SYSDATA#37 SYSDATA#38 SYSDATA#39 SYSDATA#40 SYSDATA#41 SYSDATA#42 SYSDATA#43 SYSDATA#44 SYSDATA#45 SYSDATA#46 SYSDATA#47 SYSDATA#48 SYSDATA#49 SYSDATA#50 SYSDATA#51 SYSDATA#52 SYSDATA#53 SYSDATA#54 SYSDATA#55 SYSDATA#56 SYSDATA#57 SYSDATA#58 SYSDATA#59 SYSDATA#60 SYSDATA#61 SYSDATA#62 SYSDATA#63
D
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34
SYSADDINCLK# SYSADDIN#0 SYSADDIN#1 SYSADDIN#2 SYSADDIN#3 SYSADDIN#4 SYSADDIN#5 SYSADDIN#6 SYSADDIN#7 SYSADDIN#8 SYSADDIN#9 SYSADDIN#10 SYSADDIN#11 SYSADDIN#12 SYSADDIN#13 SYSADDIN#14 SYSADDOUTCLK#
AJ33 AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 E3 J1 J3 C7 A7 E5 A5 E7 C1 C5 C3 G1 E1 A3 G5 G3 W33 J35 E27 E15 AE35 C37 A33 C11 U37 Y33 L35 E33 E25 A31 C13 A19 AL19 AL17
R2 680 +/-5%
SOCKETA-1
SADDOUTCLKJ 11
VID[4:0]
VCC_CORE
VID[4:0]
VCC_CORE
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
1.850 1.825 1.800 1.775 1.750 1.725 1.700 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 NO CPU
SYSADDOUT#0 SYSADDOUT#1 SYSADDOUT#2 SYSADDOUT#3 SYSADDOUT#4 SYSADDOUT#5 SYSADDOUT#6 SYSADDOUT#7 SYSADDOUT#8 SYSADDOUT#9 SYSADDOUT#10 SYSADDOUT#11 SYSADDOUT#12 SYSADDOUT#13 SYSADDOUT#14 SYSDATAINCLK#0 SYSDATAINCLK#1 SYSDATAINCLK#2 SYSDATAINCLK#3 SYSDATAOUTCLK#0 SYSDATAOUTCLK#1 SYSDATAOUTCLK#2 SYSDATAOUTCLK#3 SYSCHECK#0 SYSCHECK#1 SYSCHECK#2 SYSCHECK#3 SYSCHECK#4 SYSCHECK#5 SYSCHECK#6 SYSCHECK#7 RSTCLK# CLKIN#
SADDOUTJ2 SADDOUTJ3 SADDOUTJ4 SADDOUTJ5 SADDOUTJ6 SADDOUTJ7 SADDOUTJ8 SADDOUTJ9 SADDOUTJ10 SADDOUTJ11 SADDOUTJ12 SADDOUTJ13 SADDOUTJ14 DAINCLKJ0 DAINCLKJ1 DAINCLKJ2 DAINCLKJ3 SDATAOUTCLKJ0 SDATAOUTCLKJ1 SDATAOUTCLKJ2 SDATAOUTCLKJ3 VCCP VCCP
C
R3 60.4 +/-1% R0603 R5 301 +/-1% R0603
R4 60.4 +/-1% R0603
600 0.1uF BC2 680pF 50V, NPO, +/-5% BC3 C0603 680pF 50V, NPO, +/-5% C0603
B
CK_133M_CPUJ 19 CK_133M_CPU 19 SDATAINVALJ 11
R6 270 +/-5% R0603
R7 270 +/-5% R0603
AE31 AF6 AF8 AF10 AF28 AF30 AF32 AG5 AG19 AG21 AG23 AG25 AH8 AH30 AJ7 AJ9 AJ11 AJ15 AJ17 AJ19 AJ27
Close to S748 L3 DAINCLKJ0 1 L4 L0603 10nH L0603 10nH M_DAINCLKJ0 1 2 2 SDATAINCLKJ0 BC4 4.7pF 50V, NPO, +/-0.25pF C0603 L5 DAINCLKJ2 1
FSB_Sense[1] FSB1 FSB1
L0603 10nH 2
A
10nH
L7 DAINCLKJ1 1
*
*
L9 DAINCLKJ3 1
L6 L0603 10nH 1 2 SDATAINCLKJ2 BC5 4.7pF 50V, NPO, +/-0.25pF C0603
AK8 AL7 AL9 AL11 AL25 AL27 AM8 AN7 AN9 AN11 AN25 AN27
19,26
A
TECHNOLOGY COPR.
Title
L8 L0603 10nH L0603 10nH M_DAINCLKJ1 1 2 2 SDATAINCLKJ1 BC6 4.7pF 50V, NPO, +/-0.25pF C0603
*
L10 L0603 10nH L0603 10nH 2 M_DAINCLKJ3 1 2 SDATAINCLKJ3 BC7 4.7pF 50V, NPO, +/-0.25pF C0603
*
CPU-1
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 6 of 48
A
8
7
6
FSB_Sense[0] FSB0 FSB0 19,26
5
4
3
VCCP R8 100 +/-5% R0603 PLLBYPASSCLKJ PLLBYPASSCLK R14 100 +/-5% R0603 VCCP
2
VCCP R10 100 +/-5% R0603 K7CLKOUTJ R16 100 +/-5% R0603
1
VCCP R11 100 +/-5% R0603
VCCP *After Model 6,VCC_Z/VSS_Z is NC R12 0 AC7 VCC_Z DUMMY BC8 0.1uF DUMMY R13 0 AE7 VSS_Z DUMMY
G7 G9 G15 G17 G23 G25 N7 Q7 Y7 AA7 AG7 AG9 AG15 AG17 AG27 AG29 AG31
D
TRSTJ TDI TCK TMS DBREQJ SCANCLK1 SCANCLK2 SCANSHIFTEN SCANINTEVAL PLLTESTJ PLLMON1 PLLMON2 PLLBYPASSJ PLLBYPASSCLKJ PLLBYPASSCLK
U3 U5 U1 Q1 Q3 AA1 AA3 S1 S5 Q5 S3 AC3 AN13 AL13 AJ25 AL15 AN15
NMI SMI# A20M# FERR INTR INIT# IGNNE# STPCLK# FLUSH#
AN3 AN5 AE1 AG1 AL1 AJ3 AJ1 AC1 AL3
NMI SMIJ A20MJ FERR INTR INITJ IGNNEJ STPCLKJ FLUSHJ
KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 KEY7 KEY8 KEY9 KEY10 KEY11 KEY12 KEY13 KEY14 KEY15 KEY16 KEY17
NMI SMIJ A20MJ INTR INITJ IGNNEJ STPCLKJ
26 26 26 26 26 26 26
R9 100 +/-5% R0603 K7CLKOUT R15 100 +/-5% R0603
C
ZP ZN VREFSYS *After Model 6,SYSVERFMODE is NC SYSVREFMODE VCCP
SYSVREFMODE
RESET#
CPURSTJ
11
VCCP FERR
C
DBREQJ R28 PLLTESTJ R29 TRSTJ TDI TCK TMS
510 510
*
B
BC9 VREFSYS 0.1uF 25V, Y5V, +80%/-20% BC10 C0603 R30 0.33uF/NC 100 +/-1% C0603 R0603
R27 100 +/-1% R0603
*
*
BC11 47nF PLLMON1 C0603 PLLMON2
1 3 5 7
*
RN1
510 2 4 6 8
E
GND
A
*
1
1
2
*
R17 100 +/-5% R0603
D
TRST# TDO TDI TCK TMS DBRDY DBREQ# SCANCLK1 SCANCLK2 SCANSHIFTEN SCANINTEVAL PLLTEST# PLLMON1 PLLMON2 PLLBYPASS# PLLBYPASSCLK# PLLBYPASSCLK
CONNECT PROCRDY CLKFWDRESET PIC#1 PIC#0 PICCLK K7CLKOUT K7CLKOUT# COREFBCOREFB+ FID0 FID1 FID2 FID3
AL23 AN23 AJ21 N5 N3 N1 AL21 AN21 AG13 AG11 W1 W3 Y1 Y3
CONNECT P ROCRDY CLKFWDRST PICD1 PICD0 PICCLK0 K7CLKOUT K7CLKOUTJ 15MIL COREFBJ COREFB FI D0 FI D1 FI D2 FI D3
CONNECT PROCRDY CLKFWDRST PICD1 PICD0 PICCLK0
11 11 11 26 26 19
3D3V_SYS R18 330 +/-5% R0603 PICD0 R21 1K +/-5% R0603 PICD1
3D3V_SYS R19 330 +/-5% R0603 PICCLK0 R22 1K +/-5% R0603
3D3V_SYS R20 330 +/-5% R0603
COREFB
9
R23 1K +/-5% R0603
VCCA
FID[0..3]
18 9 9 9 9 9 VCCP
C
AJ23
VCCA
SOCKETA-2
AE5 AC5 W5 AA5 ZP ZN VREFSYS
VID0 VID1 VID2 VID3 VID4 AMDPIN ANALOG PWROK
L1 L3 L5 L7 J7 AH6 AJ13 AE3 AG3
VID0 VID1 VID2 VID3 VID4
VID0 VID1 VID2 VID3 VID4
R25 150 Change Component +/-5% R0603 600 have vccp pull up
PWRGOOD CPURSTJ
FERRJ PWRGOOD 46
26
B
Q1 MMBT3904
U1B SOCKETA
R31 R33
CIS 56 RN2 56 680 40.2 680 2 4 6 8 8P4R0603 ZP SYSVREFMODE SCANCLK2 SCANINTEVAL SCANCLK1 SCANSHIFTEN 270 2 4 6 8 56 270 DUMMY
B
PLLBYPASSJ R35 ZN SMIJ INITJ FLUSHJ NMI INTR IGNNEJ A20MJ STPCLKJ R38
1 3 5 7
*
R32 R34
1 3 5 7 1 3 5 7
*
RN62
VREFMODE=Low=No voltage scaling
3D3V_SYS
A individual power plane, Isolate withVCCA digital power.
U2 AME8800
*
RN63 +/-5%
2 4 6 8
8P4R0603
COREFBJ
R36
10K
3
BC12 1uF
V_IN
V_OUT
2
BC13 10uF C0805
R47 BC14
10 +/-5% R0603
K7_PLL_PGD
46
CPURSTJ COREFB
680 +/-5% R49 R50
100 10K
600 NC
*
BC15 10nF
*
39pF
*
39pF BC16
*
BC17 39pF 50V, NPO, +/-5% C0603
A
TECHNOLOGY COPR.
JP18
Title
2
1
SHORT Document Number
SocketA-2
R ev
748A01
Date: Sunday, September 05, 2004 Sheet 7 of 48
A
8
VCCP U1C
7
6
5
4
3
2
1
D
C
B
A
AB30 AB32 AB34 AB36 AD2 AD4 AD6 AF14 AF18 AF22 AF26 AF34 AF36 AH10 AH14 AH18 AH2 AH22 AH26 AH4 AJ5 AK10 AK14 AK18 AK22 AK26 AK30 AK34 AK36 AL5 AM10 AM14 AM18 AM2 AM22 AM26 AM30 AM34 B12 B16 B20 B24 B28 B32 B36 B4 B8 D12 D16 D2 D20 D24 D28 D32 D4 D8 F12 F16 F20 F24 F28 F32 F34 F36 H12 H16 H2 H20 H24 H4 K32 K34 K36 M2 M4 M6 M8 P30 P32 P34 P36 R2 R4 R6 R8 T30 T32 T34 T36 V2 V4 V6 V8 X30 X32 X34 X36 Z2 Z4 Z6 Z8
VCC_CORE1 VCC_CORE2 VCC_CORE3 VCC_CORE4 VCC_CORE5 VCC_CORE6 VCC_CORE7 VCC_CORE8 VCC_CORE9 VCC_CORE10 VCC_CORE11 VCC_CORE12 VCC_CORE13 VCC_CORE14 VCC_CORE15 VCC_CORE16 VCC_CORE17 VCC_CORE18 VCC_CORE19 VCC_CORE20 VCC_CORE21 VCC_CORE22 VCC_CORE23 VCC_CORE24 VCC_CORE25 VCC_CORE26 VCC_CORE27 VCC_CORE28 VCC_CORE29 VCC_CORE30 VCC_CORE31 VCC_CORE32 VCC_CORE33 VCC_CORE34 VCC_CORE35 VCC_CORE36 VCC_CORE37 VCC_CORE38 VCC_CORE39 VCC_CORE40 VCC_CORE41 VCC_CORE42 VCC_CORE43 VCC_CORE44 VCC_CORE45 VCC_CORE46 VCC_CORE47 VCC_CORE48 VCC_CORE49 VCC_CORE50 VCC_CORE51 VCC_CORE52 VCC_CORE53 VCC_CORE54 VCC_CORE55 VCC_CORE56 VCC_CORE57 VCC_CORE58 VCC_CORE59 VCC_CORE60 VCC_CORE61 VCC_CORE62 VCC_CORE63 VCC_CORE64 VCC_CORE65 VCC_CORE66 VCC_CORE67 VCC_CORE68 VCC_CORE69 VCC_CORE70 VCC_CORE71 VCC_CORE72 VCC_CORE73 VCC_CORE74 VCC_CORE75 VCC_CORE76 VCC_CORE77 VCC_CORE78 VCC_CORE79 VCC_CORE80 VCC_CORE81 VCC_CORE82 VCC_CORE83 VCC_CORE84 VCC_CORE85 VCC_CORE86 VCC_CORE87 VCC_CORE88 VCC_CORE89 VCC_CORE90 VCC_CORE91 VCC_CORE92 VCC_CORE93 VCC_CORE94 VCC_CORE95 VCC_CORE96 VCC_CORE97 VCC_CORE98 VCC_CORE99 VCC_CORE100 VCC_CORE101
SOCKETA
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102
AB2 AB4 AB6 AB8 AD32 AD34 AD36 AF12 AF16 AF2 AF20 AF24 AF4 AH12 AH16 AH20 AH24 AH28 AH32 AH34 AH36 AK12 AK16 AK2 AK20 AK24 AK28 AK32 AK4 AK6 AM12 AM16 AM20 AM24 AM28 AM32 AM36 AM4 AM6 B10 B14 B18 B2 B22 B26 B30 B34 B6 D10 D14 D18 D22 D26 D30 D34 D36 D6 F10 F14 F18 F2 F22 F26 F4 F6 H14 H18 H22 H26 H34 H36 K2 K4 K6 M30 M32 M34 M36 P2 P4 P6 P8 R30 R32 R34 R36 T2 T4 T6 T8 V30 V32 V34 V36 X2 X4 X6 X8 Z30 Z32 Z34 Z36
High Frequency Decoupling Capacitors
VCCP
D
BC18 4.7uF C1206 4.7uF C1206 4.7uF/NC C1206 4.7uF C1206 BC19 4.7uF C1206 4.7uF/NC C1206 4.7uF/NC C1206 4.7uF/NC C1206 BC20 10uF C1206 10uF C1206 10uF/NC C1206 10uFNC C1206
*
*
BC21
BC22
BC23
*
*
BC24
BC25
BC26
*
*
BC27
BC28
BC29
*
*
CPR#
CPR#(AK6): CPU_PRESENCE# is connected to VSS on the processor package. If pulled-up on the motherboard, CPU_PRESENCE# may be used to detect the presence or absence of a processor.
High Frequency Decoupling Capacitors
VCCP
*
*
*
*
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
BC50
0.22uF
BC51
0.22uF/NC
*
BC46
0.22uF
BC47
0.22uF/NC
BC48
0.22uF/NC
BC49
*
BC42
0.22uF
BC43
0.22uF/NC
BC44
0.22uF/NC
BC45
*
BC38
0.22uF
BC39
0.22uF/NC
BC40
0.22uF/NC
BC41
*
BC34
0.22uF
BC35
0.22uF/NC
BC36
0.22uF/NC
BC37
*
BC30
0.22uF
BC31
0.22uF/NC
BC32
0.22uF/nc
BC33
0.22uF/NC
SOCKETA-3
0.22uF/NC
0.22uF/NC
0.22uF/NC
0.22uF/NC
B
A
TECHNOLOGY COPR.
Title
SocketA-3
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 8 of 48
A
5
4
3
2
1
D
ISL6563CR FOR K7 POWER
3D3V_SYS 5V_SYS R51 2 +/-5% R0603 5V_SYS VIN
D
5V_SYS
*
Choke COIL 0.7uH L11
*
D
16
1 3 5 7
8
5V_SYS 7 7 7 7 7 VID4 VID3 VID2 VID1 VID0 PWMOK R537 5V_SYS 3.3K/NC +/-5% R0603 R59 7 COREFB 1K R0603 +/-5% R56
*
U3
C
R536 2K/NC +/-5% R0603 46 PWMOK
22 23 24 1 2 3 10
BC72 0.1uF_NC R58 BC75
VCC
VID4 VID3 VID2 VID1 VID0 DACSEL/VID5 SSEND
PVCC
UGATE1 PHASE1
19 18
R53
*
S
BC71
*
R54
AOD412 0 G R0805 +/-5%
D
0.1uF
21
10nF 2K BC73
LGATE1 ENLL
3
1
3
1
3
EC4
EC5
1
17
R1151
*
*
0.1uF_NC
2.2
FB OFS
BOOT2
R1152
2.2
5V_SYS
R60
150K_NC
9
R62 10K +/-5% R0603
*
0.1uF R61
D
6
11
BC76 AOD412 1
Q4
*
BC77 10uF 6.3V, X5R, +/-20% C1206 Choke COIL 0.7uH L13
UGATE2 PHASE2 ISEN
12 13
G S
R63 5V_SYS
B
7
10K R0603 +/-5%
R64
AOD412
D
Q5 R65 2.2 +/-5% R0805
VRM10
GND
4
LGATE2 PGND
ISL6563CR
3
1
3
EC8
1
15 14
0 R0805 +/-5%
G S
*
2
25
BC78 10nF
JP17
2
1
Seperated from GND Pad
SHORT
BOTTOM PAD CONNECT TO GND
A
2
5
4
3
*
*
*
10K R0603 +/-5%
R57 10K/NC +/-5% R0603
S
2
2
5
COMP
BOOT1
20
VIN BC74 10nF
2
*
AOD412 1 R0805 +/-5%
*
R52 1K +/-5% R0603
RN3 1K
BC853 0.1uF
BC68 10uF C1206
*
*
BC69 10uF C1206
BC834 10uF/NC 6.3V, X5R, +/-20% C1206
*
2 4 6 8
EC1 1500uF 16V,+/-20% CE50D100H300
*
EC2 1500uF 16V,+/-20% CE50D100H300
*
VIN EC3 1500uF 16V,+/-20% CE50D100H300
BC854 0.1uF
*
Q2
BC70 10uF 6.3V, X5R, +/-20% C1206
G
Choke COIL 0.7uH L12 VCCP
C
Q3 R55 2.2 +/-5% R0805 EC6
2200uF 6.3V 2200uF 6.3V 2200uF 6.3V/NC
EC9
B
2200uF 6.3V 2200uF 6.3V
A
TECHNOLOGY COPR.
Title
VCCP
Document Number Re v
748A01
Date:
2
A
Sheet
1
Sunday, September 05, 2004
9
of
48
5
4
3
2
1
D
D
H4 Mounting Hole mh40x80_8 H1 FMARK FD40 H2 FMARK FD40 H3 FMARK FD40
H5 Mounting Hole mh40x80_8
H6 Mounting Hole mh40x80_8
H7 Mounting Hole mh40x80_8
H8 Mounting Hole mh40x80_8
H9 Mounting Hole mh40x80_8
6 5
6 5
6 5
6 5
6 5
7 8 9 1
4 3 2
7 8 9 1
4 3 2
7 8 9 1
4 3 2
7 8 9 1
4 3 2
7 8 9 1
4 3 2
7 8 9 1
6 5 4 3 2
C
C
B
B
A
A
TECHNOLOGY COPR.
Title
VRD DRIVER
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
10
of
48
3D3V_SYS Place near the 748 chip. BC80 0.1uF CPUCLKAVDD BC81 10nF 25V, Y5V, +80%/-20% C0603 CPUCLKAVSS
8
7
6 SDATAJ[0..63] SDATAJ[0..63]
6
SDATAJ[0..63]
5
4
3
2
AAD[0..31] SBAJ[0..7] AC-BE[0..3]
1
AAD[0..31] SBAJ[0..7] AC-BE[0..3] ST[0..2] ADSTBF[0..1] ADSTBS[0..1] 24 24 24 24 24 24
*
3D3V_SYS
*
S2KCOMPND
C0603
S2KCOMPPD
ST[0..2] SDATAJ0 SDATAJ1 SDATAJ2 SDATAJ3 SDATAJ4 SDATAJ5 SDATAJ6 SDATAJ7 SDATAJ8 SDATAJ9 SDATAJ10 SDATAJ11 SDATAJ12 SDATAJ13 SDATAJ14 SDATAJ15 SDATAJ16 SDATAJ17 SDATAJ18 SDATAJ19 SDATAJ20 SDATAJ21 SDATAJ22 SDATAJ23 SDATAJ24 SDATAJ25 SDATAJ26 SDATAJ27 SDATAJ28 SDATAJ29 SDATAJ30 SDATAJ31 SDATAJ32 SDATAJ33 SDATAJ34 SDATAJ35 SDATAJ36 SDATAJ37 SDATAJ38 SDATAJ39 SDATAJ40 SDATAJ41 SDATAJ42 SDATAJ43 SDATAJ44 SDATAJ45 SDATAJ46 SDATAJ47 SDATAJ48 SDATAJ49 SDATAJ50 SDATAJ51 SDATAJ52 SDATAJ53 SDATAJ54 SDATAJ55 SDATAJ56 SDATAJ57 SDATAJ58 SDATAJ59 SDATAJ60 SDATAJ61 SDATAJ62 SDATAJ63 ADSTBF[0..1] ADSTBS[0..1]
C PUPHYAVDD
JP3
C0603
S2KCOMPND
S2KCOMPPD
SHORT
VDDREFA VSSREFA VDDREFB VSSREFB HSTLVREFA HSTLVREFB
M27 M29 A23 C23 L29 B23 W29
VDDREFA VSSREFA VDDREFB VSSREFB
SDATA#0 SDATA#1 SDATA#2 SDATA#3 SDATA#4 SDATA#5 SDATA#6 SDATA#7 SDATA#8 SDATA#9 SDATA#10 SDATA#11 SDATA#12 SDATA#13 SDATA#14 SDATA#15 SDATA#16 SDATA#17 SDATA#18 SDATA#19 SDATA#20 SDATA#21 SDATA#22 SDATA#23 SDATA#24 SDATA#25 SDATA#26 SDATA#27 SDATA#28 SDATA#29 SDATA#30 SDATA#31 SDATA#32 SDATA#33 SDATA#34 SDATA#35 SDATA#36 SDATA#37 SDATA#38 SDATA#39 SDATA#40 SDATA#41 SDATA#42 SDATA#43 SDATA#44 SDATA#45 SDATA#46 SDATA#47 SDATA#48 SDATA#49 SDATA#50 SDATA#51 SDATA#52 SDATA#53 SDATA#54 SDATA#55 SDATA#56 SDATA#57 SDATA#58 SDATA#59 SDATA#60 SDATA#61 SDATA#62 SDATA#63
2
1
C25 F24 E24 D25 C26 F23 A27 C27 A25 D23 F22 C24 D26 B25 D24 B27 F26 E26 D27 D29 E28 E29 F29 F27 G24 F25 C29 C28 G26 H25 G29 G27 J25 K25 L24 K27 M26 L28 L25 L27 J24 J26 H27 J27 J29 J28 M24 L26 N26 R25 R26 P27 T26 R27 T24 T29 N27 N24 N25 N28 P25 R29 N29 R24
E18
D17
D
*
BC83 0.1uF
*
BC84 10nF 25V, Y5V, +80%/-20% C0603 CPUPHYAVSS
D
AGP3.0 = 50 ohm VDDQ
HSTLVREFA HSTLVREFB CPUCLK SDATAINVAL# CPURST# PROCRDY CONNECT CLKFWDRST SADDINCLK# SADDOUTCLK# SDATAINCLK#0 SDATAINCLK#1 SDATAINCLK#2 SDATAINCLK#3 SDATAOUTCLK#0 SDATAOUTCLK#1 SDATAOUTCLK#2 SDATAOUTCLK#3 SADDIN#2 SADDIN#3 SADDIN#4 SADDIN#5 SADDIN#6 SADDIN#7 SADDIN#8 SADDIN#9 SADDIN#10 SADDIN#11 SADDIN#12 SADDIN#13 SADDIN#14 SADDOUT#2 SADDOUT#3 SADDOUT#4 SADDOUT#5 SADDOUT#6 SADDOUT#7 SADDOUT#8 SADDOUT#9 SADDOUT#10 SADDOUT#11 SADDOUT#12 SADDOUT#13 SADDOUT#14 CPUAVDD CPUAVSS CPUPHYAVDD AAD0 AAD1 AAD2 AAD3 AAD4 AAD5 AAD6 AAD7 AAD8 AAD9 AAD10 AAD11 AAD12 AAD13 AAD14 AAD15 AAD16 AAD17 AAD18 AAD19 AAD20 AAD21 AAD22 AAD23 AAD24 AAD25 AAD26 AAD27 AAD28 AAD29 AAD30 AAD31 SBA7 SBA6 SBA5 SBA4 SBA3 SBA2 SBA1 SBA0 ST0 ST1 ST2 CPUPHYAVSS
19 CK_133M_S748 6 7 7 7 7 SDATAINVALJ CPURSTJ PROCRDY CONNECT CLKFWDRST SDATAINVALJ CPURSTJ P ROCRDY CONNECT CLKFWDRST SADDINCLKJ SADDOUTCLKJ SDATAINCLKJ0 SDATAINCLKJ1 SDATAINCLKJ2 SDATAINCLKJ3
AC/BE3# AC/BE2# AC/BE1# AC/BE0# AREQ# AGNT# AFRAME# AIRDY# ATRDY# ADEVSEL# ASERR# ASTOP# APAR# RBF# WBF# GC_DET#/AGP8XDET# PIPE#/DBI_HI DBI_LO SB_STBF SB_STBS
B7 C5 C3 H5 D15 E16 F6 A4 E5 D6 B4 A3 B2 C14 B13 C15 A13 D13 A12 B11 E1 F2 B8 A7 C16 J3 J1 A16 B16 B15 A15 H1 J2
AC-BE3 AC-BE2 AC-BE1 AC-BE0 AREQ AGNT AFRAME AIRDY ATRDY ADEVSEL ASERR ASTOP APAR RBF W BF GCDETJ DBI_HI DBI_LOW GCDETJ DBI_HI DBI_LOW SBSTBF SBSTBS ADSTBF0 ADSTBS0 ADSTBF1 ADSTBS1 AGPCLK0 AGPRCOMP AGPRCOMN A1XAVDD A1XAVSS A4XAVDD A4XAVSS AVREFGC 24 CK_66M_S748 19 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
AGPRCOMN
R68 49.9 +/-1% R0603 R69 43.2 +/-1% R0603
E20 D18 D19 C19 F18 A22 U29 A26 E27 K29 P29 A24 G28 H29 R28 F21 D21 B21 E22 F20 D22 C20 C21 D20 C22 A20 A21 F19 U24 T27 W24 U25 U27 W26 U28 V25 W27 V27 U26 Y25 V29 Y26 Y27 B19 A19
AGPRCOMP
6 SADDINCLKJ 6 SADDOUTCLKJ
HOST
C
6 SDATAINCLKJ[0..3]
SDATAOUTCLKJ0 SDATAOUTCLKJ1 SDATAOUTCLKJ2 SDATAOUTCLKJ3 SADDINJ2 SADDINJ3 SADDINJ4 SADDINJ5 SADDINJ6 SADDINJ7 SADDINJ8 SADDINJ9 SADDINJ10 SADDINJ11 SADDINJ12 SADDINJ13 SADDINJ14 SADDOUTJ2 SADDOUTJ3 SADDOUTJ4 SADDOUTJ5 SADDOUTJ6 SADDOUTJ7 SADDOUTJ8 SADDOUTJ9 SADDOUTJ10 SADDOUTJ11 SADDOUTJ12 SADDOUTJ13 SADDOUTJ14 CPUCLKAVDD CPUCLKAVSS C PUPHYAVDD
C
6 SDATAOUTCLKJ[0..3] Put near 748 chip VCCP R70 62 +/-1% R0603 CK_133M_S748
748-1
AGP
AD_STBF0 AD_STBS0 AD_STBF1 AD_STBS1 AGPCLK AGPRCOMP AGPRCOMN A1XAVDD A1XAVSS A4XAVDD A4XAVSS AGPVREF AGPVSSREF
6 SADDINJ[2..14]
*
BC859 3.3pF/NC
3D3V_SYS A1XAVDD BC85 0.1uF C0603 A1XAVSS BC86 10nF C0603 JP4 2 SHORT 3D3V_SYS A4XAVDD BC88 0.1uF C0603 BC89 10nF C0603 JP5 2 SHORT 1D8V_VCCNB 1D8V_VCCNB VDDREFB BC100 0.1uF BC101 10nF/NC C0603 VSSREFB JP9 VDDREFA BC103 0.1uF BC104 10nF/NC C0603 VSSREFA
B
6 SADDOUTJ[2..14]
B
*
*
Place near the 748 chip. VCCP R73 S2KCOMPND 33 +/-5% R0603 R74 S2KCOMPPD 33 +/-5% R0603 VCCP
CPUPHYAVSS
1
U4A 748
SBAJ7 SBAJ6 SBAJ5 SBAJ4 SBAJ3 SBAJ2 SBAJ1 SBAJ0
AAD0 AAD1 AAD2 AAD3 AAD4 AAD5 AAD6 AAD7 AAD8 AAD9 AAD10 AAD11 AAD12 AAD13 AAD14 AAD15 AAD16 AAD17 AAD18 AAD19 AAD20 AAD21 AAD22 AAD23 AAD24 AAD25 AAD26 AAD27 AAD28 AAD29 AAD30 AAD31
ST0 ST1 ST2
H2 J6 G1 H4 J4 G3 F3 G4 E2 E4 D2 G6 F5 D3 C1 D4 D7 B5 E7 F8 A6 C6 E8 F9 C8 D9 E10 C9 F11 A9 B10 D10
E11 F12 C11 A10 C12 D12 E13 F14
F15 A14 E14
VCCP
*
R76 100 +/-1% R0603
*
A
R77 100 +/-1% R0603
*
BC91 10nF/NC C0603 15 mil trace
*
BC92 10nF/NC C0603 15 mil trace
A4XAVSS
1
A
HSTLVREFA R81 100 +/-1% R0603 2 JP6 SHORT
HSTLVREFB R80 100 +/-1% R0603
*
1
BC95 10nF C0603
*
1
BC97 10nF C0603 JP8
TECHNOLOGY COPR.
Title
*
*
*
*
C0603
C0603
HOST & AGP
Document Number R ev
2
JP7 SHORT
2
1
SHORT
2
1
SHORT
748A01
Date: Sunday, September 05, 2004 Sheet 11 of 48
A
8
MD[0..63] DQM[0..7] DQS[0..7]
7
MD[0..63] DQM[0..7] DQS[0..7] 21,22,23 21,22,23 21,22,23
6
MAA[0..14] MAA[0..14]
5
21,22,23
4
3
2
1
CSAJ[0..5]
CSAJ[0..5] U4B MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 DQM0 DQS0 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 DQM1 DQS1 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 DQM2 DQS2 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 DQM3 DQS3 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 DQM4 DQS4 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 DQM5 DQS5 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 DQM6 DQS6 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 DQM7 DQS7
21,22,23 10 mil wire
D
C
B
AD25 AH28 AD24 AH26 AF27 AG25 AF26 AG27 AJ26 AJ27 AE25 AE23 AG24 AH23 AF24 AH25 AE22 AD21 AD22 AJ24 AH22 AG22 AF20 AH20 AE20 AF21 AE19 AJ20 AG21 AJ21 AE16 AH17 AF15 AJ15 AF17 AD16 AG15 AH16 AG16 AJ17 AJ12 AF12 AG10 AF11 AG12 AD12 AE11 AH10 AH11 AJ11 AJ6 AF6 AE7 AH4 AH7 AG7 AG6 AF5 AJ5 AH5 AD7 AE5 AE4 AF2 AG4 AF3 AG3 AD6 AH2 AG1 AC2 AE1 AB3 AD3 AE2 AC6 AD5 AC4 AB5 AD1
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 DQM0 CSB#0/DQS0 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 DQM1 CSB#1/DQS1 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 DQM2 CSB#2/DQS2 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 DQM3 CSB#3/DQS3 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 DQM4 CSB#4/DQS4 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 DQM5 CSB#5/DQS5 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 DQM6 CSB#6/DQS6 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 DQM7 CSB#7/DQS7
748
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15 RAMRWA# SRASA# SCASA# Reserved
AE13 AJ14 AH14 AE14 AD15 AD18 AJ18 AF18 AG18 AH19 AF14 AE10 AD13 AG19 AD19 AF23 AF9 AG9 AJ9 AE17
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MWAJ RASAJ CASAJ
D
RASAJ MWAJ CASAJ
RASAJ MWAJ CASAJ
21,22,23 21,22,23 21,22,23
C
748-2
CS0# CS1# CS2# CS3# CS4# CS5# AD9 AD10 AJ8 AE8 AF8 AH8
CSAJ0 CSAJ1 CSAJ2 CSAJ3 CSAJ4 CSAJ5
DDRVREFA DDRVREFB DLLAVDD DLLAVSS SDRCLKI FWDSDCLKO DDRAVDD DDRAVSS CKE0 CKE1 CKE2 CKE3 CKE4 CKE5 S3AUXSW# DDRCOMP DDRCOMN
AJ23 AJ3 AA29 AA28 AG13 AH13 Y29 Y28 AA6 AB6 AA5 AA3 AB4 AA4 Y6 AB2 AB1
DDRCOMP DDRCOMN
DDRVREFA DDRVREFB DLLAVDD DLLAVSS 2D5V_DDR FWDSDCLKO DDRAVDD DDRAVSS CKE0 CKE1 CKE2 CKE3 CKE4 CKE5 DDRCOMN R83 40.2 DDRCOMP R84 40.2 +/-1% +/-1%
B
CKE0 CKE1 CKE2 CKE3 CKE4 CKE5
21 21 21 21 22 22
FWDSDCLKO
Put near 748 chip. R86 22 R0603 +/-5%
SDCLKO_DDR 20
2D5V_DDR
2D5V_DDR
* *
A
DDRVREFA ( 10-mil trace ) 25-mil clearance or shielded by VSS trace and VDD trace BC106 0.1uF/NC C0603 R88 150 +/-1% R0603 DDRVREFB ( 10-mil trace ) 25-mil clearance or shielded by VSS trace and VDD trace
*
BC107 0.1uF/NC C0603
R87 150 +/-1% R0603 DDRAVDD
BC105 10pF 50V, NPO, +/-5% C0603
3D3V_SYS DLLAVDD
3D3V_SYS
A
*
BC108 0.1uF C0603
R92 150 +/-1% R0603
*
BC109 0.1uF C0603
R91 150 +/-1% R0603 DDRAVSS
*
BC110 0.1uF C0603
*
BC111 10nF C0603 DLLAVSS
*
BC113 0.1uF C0603
*
BC114 10nF C0603 Title
TECHNOLOGY COPR.
748-MEM
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 12 of 48
A
8
7
6
5
4
NB Hardware Trap Table
3
2
1
A0/A1 CPUDLLENN TMODE0 TMODE1 CPUCLK SDCLK PLL/DLL Circuit Enable MuTIOL ( ASL ) DBI Mode MuTIOL ( ASL ) initialize Mode P748 Debug Mode Selection MuTIOL type (verision 1 , 2)
ON/1 DISABLE DISABLE Packet ENABLE Ver. 1
OFF/0 ENABLE ENABLE Series DISABLE Ver. 2
Default OFF OFF OFF OFF OFF
D
The differences between the traces of MuTIOL Strobes and Data should be smaller than 0.05" 19 25 25 25 25 ZSTB0 ZSTBJ0 ZSTB1 ZSTBJ1 ZCLK0 ZSTB0 ZSTBJ0 ZSTB1 ZSTBJ1 Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS ZCMPJN ZCMPJP ZVREF ZCLK0
U4C 748
TMODE2 TRAP4
D
W1 U1 V2 P2 R1 Y2 Y1 AA1 AA2 W2 W4 W3 W6 V3
ZCLK ZSTB0 ZSTB0# ZSTB1 ZSTB1# Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS ZCMP_N ZCMP_P ZVREF AUXOK ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZAD16 ZUREQ ZDREQ TESTMODE0 TESTMODE1 TESTMODE2 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 ENTEST DLLEN# DRAM_SEL PCIRST# PWROK B18 A18 F17 E17 C17 B17 A17 F16 D16 C18 Y4 W5 Y5 Y3
TMODE0 TMODE1 TMODE2 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 ENTEST DLLENJ DRAM_SEL R94 TRAP0 TRAP1 TRAP2 TRAP3 18 18 18 18 R1160 DUMMY 3D3V_SB 0 PCIRSTJ2 PWRGD_NB BC116 1uF C0603 dummy PWRGD_NB AUXOK 46 26,45 25,37 DLLENJ 0 R1145 4.7K/NC +/-5% R0603
748-3
MuTIOL
3D3V_SYS
C
25 25 ZUREQ ZDREQ ZUREQ ZDREQ
C
*
*
BC117 1uF C0603 dummy
ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZAD16
V4 T2 U5 T5 U3 T4 R3 T6 P6 P1 R5 P4 N2 N5 N3 N6 V6
The differences between the traces of MuTIOL Strobes and Data should be smaller than 0.05" 25 ZAD[0..16] ZAD[0..16]
NB Hardware Trap
PULL LOW
TMODE0 TMODE1 TMODE2 TRAP4 R1144
3D3V_SYS
1 3 5 7
*
RN75
2 4 6 8
4.7K DUMMY 4.7K DUMMY
B
NB Hardware Trap has internal pull-low in SiS748 chip for DRAM_SEL,CPUDLLENN,TMODE0,TMODE1,TMODE2 signals.
B
Place near 748 chip.
1D8V_VCCNB R95 56 +/-5% R0603 ZCMPJN
3D3V_SYS BC833 10uF C1206
FB52
3D3V_SYS
2
1
*
2
FB L0603 47 Ohm JP14
*
Z4XAVDD BC121 BC120 0.1uF 10nF
*
*
JP15
BC123 10nF C0603
*
Z1XAVDD BC124 0.1uF C0603 Z1XAVSS
R96 150 +/-1% R0603
*
BC118 0.1uF C0603
ZVREF R98 49.9 +/-1% R0603 JP16 2 1 SHORT
A
1
SHORT
C0603 C0603 Z4XAVSS
2
1
SHORT
*
BC126 0.1uF C0603 R99 56 +/-5% R0603 ZCMPJP Title
A
TECHNOLOGY COPR.
MuTIOL
Document Number Re v
748A01
Date: Sunday, September 05, 2004 Sheet 13 of 48
A
8
7
6
5
4
3
2
1
8
7
6
5
4
3
3D3V_SYS
1D8V_VCCNB BC127 10uF 1uF/NC BC130 1uF 0.1uF/NC 0.1uF BC134 C1206 VCCP
2
1
BC128 VDDQ VDDQ BC129 U4D 1D8V_VCCNB 10uF C1206 10uF/NC C1206 1uF/NC 1uF 0.1uF 0.1uF/NC VDDQ BC131 0.1uF 0.1uF BC132 BC136 BC139 2D5V_DDR
* * * * *
* * * * *
10uF C1206 1uF/NC 0.1uF 0.1uF/NC 0.1uF
* * * * * *
D
BC133 BC137 BC140 BC142 BC144
H8 H9 J8 K10 K11 K13 K14 L10 L11 L12 L13 L14 L15 M10 M11 N11
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDDZ VDDZ VDDZ VDDZ VDDZ IVDD VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM PVDDM PVDDM PVDDM PVDDM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
T10 R11 R10 P11 P10 W20 T11 U10 U11 U19 U20 V10 V11 V19 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Y10 Y13 Y14 Y16 Y17 Y20 AA8 AA22 AB8 AB9 AB21 AB22 W9 Y11 AA13 AA17 P12 P13 P14 P15 P16 R12 R13 R14 R15 R16 T12 T13 T14 T15 T16 U12 U13 U14 U15 U16 U17 U18 V12 V13 V14 V15 V16 V17 V18 M12 M13 M14 M15 N12 N13 N14 N15
2D5V_DDR
* * * * * * * *
BC153 BC156 BC158 BC160 BC161
0.1uF/NC 1uF 1uF 0.1uF 0.1uF
BC155 BC157 BC159
* * * *
K1 K2 K3 K4 K5 K6 L1 L2 L3 L4 L5 L6 M1 M2 M3 M4 M5 M6
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
1D8V_VCCNB
1D8V_VCCNB
C
K12 K15 K16 K18 K20 L20 M20 N10
IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD
N1 P3 R2 T1 T3 U2 V1
2D5V_DDR
VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ
748-5
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM
A5 A8 A11 B3 B6 B9 B12 B14 C2 C4 C7 C10 C13 D1 D5 D8 D11 D14 E3 E6 E9 E12 E15 F1 F4 F7 F10 F13 G2 G5 H3 H6 J5 AC1 AC3 AC5 AD2 AD4 AD8 AD11 AD14 AD17 AD20 AD23 AE3 AE6 AE9 AE12 AE15 AE18 AE21 AE24 AF1 AF4 AF7 AF10 AF13 AF16 AF19 AF22 AF25 AG2 AG5 AG8 AG11 AG14 AG17 AG20 AG23 AG26 AG28 AH3 AH6 AH9 AH12 AH15 AH18 AH21 AH24 AH27 AJ4 AJ7 AJ10 AJ13 AJ16 AJ19 AJ22 AJ25
VSSZ VSSZ VSSZ VSSZ VSSZ VSSZ VSSZ
BC135
* *
U4E
N4 P5 R4 R6 U4 U6 V5
BC138 BC141 BC143
D
BC145 BC147 BC150
1uF/NC BC146 10uF C1206 10uF/NC C1206 VCCP BC149 10uF/NC C1206 1uF/NC 0.1uF 0.1uF/NC 0.1uF 1uF/NC 0.1uF/NC
*
*
BC148
BC152
*
748-4
Power(inside)
C
*
IVDD IVDD IVDD IVDD IVDD
BC165
Y12 Y15 Y18 Y19
VCCP
AB13 AB17 H21 H22 J22 K17 K19 L16 L17 L18 L19 M19 N19 N20 P19 P20 R19 R20 T19 T20 H16 J16 T9
IVDD IVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD VDD3.3 VDD3.3 AUX1.8 AUX3.3
748
. Power (outside)
VDDQ BC170 0.1uF-BOT
BC166
B
1D8V_VCCNB BC172 BC174 BC176 0.1uF-BOT
*
*
*
0.1uF-BOT
*
0.1uF-BOT
V20
*
Y24 AA24 AA25 AA26 AA27 AB24 AB25 AB26 AB27 AB28 AB29 AC24 AC25 AC26 AC27 AC28 AC29 AD26 AD27 AD28 AD29 AE26 AE27 AE28 AE29 AF28 AF29 AG29
VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM VDDM
Place these capacitors under 748 solder side. 2D5V_DDR VDDQ BC164 0.1uF-BOT BC163 0.1uF-BOT
B
0.1uF-BOT
E19 E21 E23 E25 G25 H24 H26 K24 K26 M25 P24 P26 T25 V24 V26 W25
A
T18 T17 R18 R17 P18 P17 N18 N17 N16 M18 M17 M16
*
*
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BC673 10uF C1206
BC188 10nF C0603
U9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BC186
**
3D3V_SB
BC184
*
1D8V_SB
BC182
*
0.1uF-BOT 0.1uF-BOT 0.1uF-BOT
3D3V_SYS
B20 B22 B24 B26 B28 D28 F28 H28 K28 M28 P28 T28 V28 W28
S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD S2KOVDD
*
BC178
VCCP BC180 0.1uF-BOT
*
VCCP
*
0.1uF-BOT
0.1uF-BOT
748
A
TECHNOLOGY COPR.
Title
748-POWER
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 14 of 48
A
5
4
3
2
1
3D3V_SYS 12V_SYS 3D3V_SB
*
D
BC778 0.1uF 25V, Y5V, +80%/-20% C0603
EC78 1000uF
*
CE35D80H200 3D3V_SB
D
6.3V, +/-20%
4
R1132 270 +/-1% R0603
U26A
D
Q54
3 2
R1134 1K +/-1% R0603
+ -
3D3V_SYS
1
LM324 R1133
G S
SDU3055L2 R1135 169 +/-1% R0603 2D5V_DDR BC779 0.1uF 25V, Y5V, +80%/-20% C0603
11
D
1K R0603 +/-5%
4
U26B
Q50
*
5 6
R1136 205 +/-1% R0603
+ -
6.3V, +/-20%
1000uF 6.3V, +/-20% 6.3V, +/-20%
11
LM324
R522 R0603
1K
S
EC79 1000uF
*
EC14
*
EC15 1000uF
*
*
2.598 EC68 1000uF/NC 6.3V, +/-20% CE35D80H200
7
G
SDU3055L2
1D8V_VCCSB BC678 0.1uF 25V, Y5V, +80%/-20% C0603 EC59 1000uF 6.3V, +/-20% CE35D80H200
CE35D80H200 CE35D80H200 CE35D80H200
*
*
1.8V--SB
C C
3D3V_SB
1D5V_AGP POWER FOR NB/AGP
3D3V_SYS R1137 340 +/-1% R0603 EC60 1000uF/NC 6.3V, +/-20% CE35D80H200 3D3V_SYS
4
U26C
*
Q51
10 9
R1138 301 +/-1% R0603
+ -
8
LM324 R526
G S
D
SDU3055L2
3D3V_SB
11
VDDQ 1K R0603 +/-5% R1139 150 +/-1% R0603
*
4
U26D
B
*
BC679 0.1uF
*
EC61 1000uF 6.3V, +/-20% CE35D80H200
EC58 1000uF 6.3V, +/-20% CE35D80H200
B
D
Q55
12 13
R1141 205 +/-1% R0603
+ -
14
R1140 LM324
G
1K R0603
SDU3055L2
11
S
1D8V_VCCNB BC780 0.1uF 25V, Y5V, +80%/-20% C0603 EC80 1000uF 6.3V, +/-20% CE35D80H200
*
2D5V_DDR 3D3V_SYS
*
1.9V--NB U6 BC190 0.1uF 25V, Y5V, +80%/-20% C0603
1 1
BC191 1uF/NC
VIN
R109 1K
VCNTL VCNTL VCNTL VCNTL VOUT
8 7 6 5 4 2
*
2
1
DDR_VTT
2
A
3
REFEN
GND
*
2
BC193 R110 RT9173 0.1uF/NC 25V, Y5V, +80%/-20% C0603 1K
*
EC17 470uF 6.3V, +/-20% CE25D60H110
*
EC18 470uF/NC 6.3V, +/-20% CE25D60H110
*
BC192 0.1uF 25V, Y5V, +80%/-20% C0603
A
1
TECHNOLOGY COPR.
Title
2.5V_DDR & 1.25_VTT
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
15
of
48
5
4
3
2
1
SB1.8V
D
3D3V_SB
Vref=1.25V
1D8V_SB
D
3
2
1
U7 AME1117
Vin
4 Vout
4
*
BC194 10uF 10V, Y5V, +80%/-20% C1206
ADJ
+ -
Vref
R111 750 +/-1% R0603
*
EC21 470uF 6.3V, +/-20% CE25D60H110
*
BC195 0.1uF 25V, Y5V, +80%/-20% C0603
R113 330 +/-1% R0603
C
C
5V_SB
U36
3
VIN ADJ
AIC1086CE/NC VOUT 2
3D3V_SB
1
ADJ
SB3.3V
5V_SB
Vref=1.25V
3D3V_SB
B
B
3
2
1
U8 AME1117
Vin
4 Vout
*
4
EC19 22uF 50V, +/-20% CE20D50H110
*
BC196 10uF/NC C1206
ADJ
+ Vref ADJ
R112 196 +/-1% R0603
*
EC20 470uF 6.3V, +/-20% CE25D60H110
*
BC197 0.1uF/NC 25V, Y5V, +80%/-20% C0603
R114 330 +/-1% R0603
A
A
TECHNOLOGY COPR.
Title
SB1.8V & SB3V & 5V_DUAL
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
16
of
48
5
4
3
2
1
CNR1 3D3V_SYS ATTACH R1166 FOR NO CNR SKU
D
R1165 1K +/-5% R0603
R1166 R1167 10K +/-5% R0603
3D3V_SYS 0/NC
-12V_SYS
5V_SB
D22
1
2
1N4148W
AC_RESETJ
CODEC_RSTJ 38
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30
3 2 1
3 2 1
PRI_DNJ
C
J9
RESERVED RESERVED RESERVED GND RESERVED RESERVED GND LAN_TXD1 LAN_RSTSYNC GND LAN_RXD2 LAN_RXD0 GND RESERVED +5VDUAL USB_OC# GND -12V +3.3VD GND EE_DOUT EE_SHCLK GND SMB_A0 SMB_SCL PRIMARY_DN# GND AC97_SYNC AC97_SD_OUT AC97_BITCLK
CNR
RESERVED RESERVED GND RESERVED RESERVED GND LAN_TXD2 LAN_TXD0 GND LAN_CLK LAN_RXD1 RESERVED USB+ GND USB+12V GND +3.3VDUAL +5VD GND EE_DIN EE_CS SMB_A1 SMB_A2 SMB_SDA AC97_RESET# AC97_SD_IN2 AC97_SD_IN1 AC97_SD_IN0 GND
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
D
12V_SYS
3D3V_SB
5V_SYS
B E
Q56 MMBT3904
HEADER_1X3
SMA0 19,20,21,22,26 SMB_CLK_MAIN 26,38 SYNC 26,38 SDATO 26,38 BIT_CLK
C
SMA1 SMA2 SMB_DATA_MAIN 19,20,21,22,26 AC_RESETJ 26 SDATI2 26 SDATI1 26 SDATI0 26,38
PRI_DNJ
R1170 10K
R1171 10K/NC
R1172 10K
R1173 10K/NC
C
2-3 1-2
ENABLE CNR AUDIO ENABLE PRIMARY AUDIO
5V_SYS
R1174 10K
R1175 10K
R1176 10K
B
SMA0 SMA1 SMA2
B
R1177 10K/NC
A
A
TECHNOLOGY COPR.
Title
EMPTY
Document Number Re v
748A01
Date:
5 4 3 2
A
Sheet
1
Sunday, September 05, 2004
17
of
48
8
7
6
5
4
3
2
1
D
D
GPIO4 GPIO3 GPIO1 GPIO0
26 26 26 26 26 SPKR( LPC addr mapping) SDATO( Trap mode) 0 disable ROM enable enable 1 enable PCI AD disable disable Default R409 un-stuff R410 un-stuff R411 un-stuff NONE internal pull-low (30~50K Ohm) yes yes NO yes
C
GPIO7
C
OC4-( SB debug mode) SYNC( PCICLK PLL)
RN76 0/NC 3D3V_SYS
2 4 6 8
1 3 5 7
*
R1157 0/NC +/-5% R0603 FID[0..3]
FID[0..3] 2D5V_DDR
7
2 4 6 8
3D3V_SB RN70 10K 8P4R0603 +/-5% max R152 10K +/-5% R0603 2.625v
1 3 5 7
*
B
D
Q22 RN72
2 4 6 8
NB Hardware Trap has internal pull-low in SiS748 chip FOR TRAP[0..3]. RN71 680 8P4R0603 +/-5% 11.0 11.5 12.0 12.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5
B
1 3 5 7
*
(FID3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
(FID2) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
(FID1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
(FID0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
13 13 13 13
TRAP0 TRAP1 TRAP2 TRAP3
D
TRAP0 TRAP1 TRAP2 TRAP3
1 3 5 7
*
G 2N7002 2 4 6 8 S
F ID0
1K +/-5% 8P4R0603
Q23
G 2N7002 S
F ID1
D
Q24
G 2N7002 S
A
D
Q25
F ID2
A
TECHNOLOGY COPR.
G 2N7002 S
F ID3
Title
Hardware Trap
Document Number Re v
748A01
Date: Sunday, September 05, 2004 Sheet 18 of 48
A
8
7
6
5
4
3
2
1
8
7
3D3V_SYS
6
5
4
3
2
1
2D5V_DDR
Main Clock Generator
FB5 FB L0805 60 Ohm U11 ICS952703 CLK_3V BC215 0.1uF C0603 BC216 0.1uF C0603 BC220 0.1uF C0603 BC217 0.1uF C0603 BC221 0.1uF C0603 BC222 0.1uF C0603 Damping Resistors Place near to the Clock Outputs SATA FOR SRC
2
D
FB6 FB L0805 60 Ohm
1
2
CLK_2.5V BC686 BC225 10uF 0.1uF 16V, X5R, +/-10% C1206 C0603
*
*
*
*
*
*
*
*
1 11 13 19 28 29
VDDREF VDDZ VDDPCI VDDPCI_1 AVDD48 VDDAGP
D
R161 R162 22 22 R1161 49.9 +/-1% R0603 R1162 49.9 +/-1% R0603 CK_100M_SATA 27 CK_100M_SATAJ 27
1
SRCCLKT SRCCLKC
43 42
5 8 18 24 25 32
GNDREF GNDZ GNDPCI GNDPCI_1 GND48 GNDAGP
CPUCLK_0T CPUCLK_0C CPUCLK_1T IOAPIC1 IOAPIC0 AGPCLK0 AGPCLK1
38 37 40 47 46 31 30 9 10 14 15 16 17 20 21 22 23 2 3 4 27 26
FS2 FS3
R163 R164 R165 R166 R167 R168 R169 R170 R171 RN64 7 5 3 1 33 +/-5% FS0 FS1 R181 R182 R183 R187 R185
10 10 0 10 10 22 22 22 22
CPUCLK0 CPUCLK-0 748CCLK PICCLK0 PICCLK1 AGPCLK0 AGPCLK1 ZCLK0 ZCLK1
CK_133M_CPU 6 CK_133M_CPUJ 6 CK_133M_S748 11 PICCLK0 PICCLK1 7 26 CPU SB
CK_66M_S748 11 CK_66M_AGP NB&SB 24 ZCLK0 ZCLK1 13 25
*
C
BC230 0.1uF C0603
*
BC231 0.1uF C0603
CLK_2.5V
48 39 45 41
VDDAPIC GNDCPU GNDAPIC GNDSRC *FS2/PCICLK_F0 *FS3/PCICLK_F1 PCICLK0 PCICLK1 PCICLK2 *(PCI_STOP#)PCICLK3 *(CPU_STOP#)PCICLK4 *(PD#)PCICLK5 **FS0/REF0 **FS1/REF1 **Mode/REF2 12_48MHz/SEL12_48#MHz* 24_48MHz/SEL24_48#MHz**~
8 6 4 2
8P4R0603
R180 475 +/-1% R0603 R53 SATA FOR SRC
34
IREF
33 33 33/NC 22 22
OSCI VOSCI REFCLK2 USB12M SIO48M
3D3V_SYS FB7 2
SCLK SDATA 1 36 VDDA
12 33
SMB_CLK_MAIN SMB_DATA_MAIN
SMB_CLK_MAIN 17,20,21,22,26 SMB_DATA_MAIN 17,20,21,22,26
R1164 Frequency Selection R188 10K +/-5% R0603 DUMMY 3D3V_SYS 10K +/-5% R0603 DUMMY
FB L0805 60 Ohm
*
BC245 0.1uF C0603
*
BC246 1nF 25V, NPO, +/-5% C0603
35
GNDA
R186 10K +/-5% R0603 DUMMY
X1
B
3D3V_SYS R190 10K +/-5% R0603 R191 10K FS3 J8 SB--GPIO FS1 BC861 22pF 50V, NPO, +/-5% C0603
X2
*
REFCLK2
BC684
10pFC0603 DUMMY
6
*
7
1
2
BC248 33pF 50V,NPO,+/-5% C0603
7,26
FSB0
FSB0
1 2
Header_1X2 3D3V_SYS 3D3V_SYS R193 10K +/-5% R0603 R197 10K FS2 R189 10K +/-5% R0603 FS0 R192 10K +/-5% R0603 DUMMY
X1 XTAL-14.318MHz BC247 33pF 50V,NPO,+/-5% C0603
*
*
FSB_Sense[1] FSB_Sense[0] Bus Frequency 1 0 RESERVED 1 1 133 MHz 0 1 166 MHz 0 0 200 MHz
FS3 FS2 FS1 FS0
0 1 1
0
CPU SRC ZCLK AGP PCI
200.01 100.00 133.34 66.67 33.33 166.65 100.00 133.32 66.66 33.33 133.34 100.00 133.34 66.67 33.33
100.00 100.00 133.34 66.67 33.33
0 0 1
1
0 0 0
0
1 1 1
1
A
6,26
FSB1 SB--GPIO
FSB1
Title
CLK 952703
Document Number Re v
748A01
Date: Sunday, September 05, 2004 Sheet 19 of 48
8
7
6
5
4
3
2
*
*
7 5 33 3 1 RN65
CK_33M_SIO 40 CK_33M_1394 32 CK_33M_PCI5 31 CK_33M_PCI2 29 8 6 4 2 CK_14M_S964 26 CK_14M_AUDIO 38
CK_33M_PCI1 CK_33M_PCI3 CK_33M_PCI4 CK_33M_S964
29 30 30 25
CK_48M_SIO
40 BC860 10pF C0603 DUMMY
*
44
VDDSRC
ZCLK0 ZCLK1
BC856 10pF C0603 DUMMY
*
C
CK_12M_USB
27
B
A
TECHNOLOGY COPR.
A
1
8
7
6
5
4
3
2
1
Clock Buffer ( FOR 3 DDR SDRAM DIMMS )
D
1. 2. 3. 4. 5.
Cypress CY28351C ICS 93735 Hitachi CDCV851 Phaselink 102-08 Realtek RTM 680-648
DDRCLK[0..8] DDRCLKJ[0..8]
DDRCLK[0..8] 21,22 DDRCLKJ[0..8] 21,22
D
CBVDD U34 ICS 93705 CBVDD 2D5V_DDR
FB50 FB L0805 60 Ohm
15 4 11 21 28 34 38 45
VDDI2C VDD VDD VDD VDD VDD VDD VDD
2
By-Pass Capacitors Place near to the Clock Buffer
C
17,19,21,22,26 SMB_CLK_MAIN 17,19,21,22,26 SMB_DATA_MAIN 12 SDCLKO_DDR
17
SMB_CLK_MAIN SMB_DATA_MAIN SDCLKO_DDR
AGND SCLK SDATA CLK_IN
14
FB_OUT
CLK_IN# FB_IN FB_OUT FB_OUT#
35
33 32
BFB_OUT
R1131
22
FB_OUT
FB_IN# GND GND GND GND GND GND GND GND GND GND
1 7 8 18 24 25 31 41 42 48
2D5V_DDR
FB51
2
1
FB L0805 60 Ohm
CBVDD
*
BC772 BC774 10nF 0.1uF 25V, Y5V, +80%/-20% C0603 C0603
*
*
A
BC775 10nF C0603
*
BC776 0.1uF C0603
*
BC777 0.1uF C0603
*
FB_OUT
*
DDRCLKJ1
BC770
10pFC0603 DUMMY
BC771
*
DDRCLKJ4
*
B
*
DDRCLKJ0 DDRCLKJ7 BC768
*
DDRCLKJ3
BC766
10pFC0603 DUMMY BC767 10pFC0603 DUMMY
*
36
DDRCLKJ6
*
DDRCLKJ2
BC764
C0603 DUMMY BC765 10pFC0603 DUMMY
*
DDRCLKJ5
*
DDRCLKJ8
BC762
*
DDRCLK1
BC761
10pFC0603 DUMMY
10pFC0603 DUMMY 10pF BC763 10pFC0603 DUMMY
*
DDRCLK4
*
13
DDRCLK7
BC759
10pFC0603 DUMMY BC760 10pFC0603 DUMMY
*
12 37
CLK#0 CLK#1 CLK#2 CLK#3 CLK#4 CLK#5 CLK#6 CLK#7 CLK#8 CLK#9
2 6 9 19 23 47 43 40 30 26
DDRCLKJ3 DDRCLKJ6 DDRCLKJ2 DDRCLKJ5 DDRCLKJ8 DDRCLKJ0 DDRCLKJ4 DDRCLKJ1 DDRCLKJ7
DDRCLK0
*
DDRCLK3
BC757
10pFC0603 DUMMY BC758 10pFC0603 DUMMY
*
C0603
DDRCLK6
*
*
BC754 0.1uF
*
BC755 10nF 25V, Y5V, +80%/-20% C0603
AVDD
DDRCLK2
BC753
10pFC0603 DUMMY BC756 10pFC0603 DUMMY
*
16
CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9
3 5 10 20 22 46 44 39 29 27
DDRCLK3 DDRCLK6 DDRCLK2 DDRCLK5 DDRCLK8 DDRCLK0 DDRCLK4 DDRCLK1 DDRCLK7
1
DDRCLK5
*
DDRCLK8
BC751
10pFC0603 DUMMY BC752 10pFC0603 DUMMY
C
10pFC0603 DUMMY BC769 10pFC0603 DUMMY
B
27pFC0603
A
TECHNOLOGY COPR.
Title
Clock Buffer
Document Number Re v
748A01
Date: Sunday, September 05, 2004 Sheet 20 of 48
A
8
7
6
5
4
3
2
1
8
2D5V_DDR
7
7 38 46 70 85 108 120 148 168
6
D DRVREF 184 DIMM1 DDR_DIMM MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 DDRVREF 22
5
4
2D5V_DDR
3
D DRVREF 7 38 46 70 85 108 120 148 168 184 DIMM2 DDR_DIMM
2
1
82
1
VDDSPD/VCC3
VDDID
VREF/NC
VDD VDD VDD VDD VDD VDD VDD VDD VDD
MD[0..63]
12,22,23
82
VDDSPD/VCC3
D
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180 12,22,23 MAA[0..14] MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA13 MAA14 MAA11 MAA12 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 8.2K CSAJ0 CSAJ1 48 43 41 130 37 32 125 29 122 27 141 118 115 167 59 52 113 97 107 119 129 149 159 169 177 140 157 158 71 163 RASAJ CASAJ MWAJ DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 154 65 63 5 14 25 36 56 67 78 86 47 21 111 16 17 137 138 76 75
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 NC/A12 NC/A13 BA0 BA1 NC/BA2 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 DQMB8 CS0 CS1 NC/CS2 NC/CS3 RAS CAS WE DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
VDD 3.3V 3.3V 2.5V 2.5V 1.8V
VDDQ 3.3V 2.5V 2.5V 1.8V 1.8V
VDDID OPEN VSS OPEN VSS OPEN
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 9 10 101 102 103 173
VREF/NC
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDID
1
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA13 MAA14 MAA11 MAA12 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 R226 12,23 12,23 CSAJ2 CSAJ3 8.2K CSAJ2 CSAJ3 48 43 41 130 37 32 125 29 122 27 141 118 115 167 59 52 113 97 107 119 129 149 159 169 177 140 157 158 71 163 154 65 63 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 5 14 25 36 56 67 78 86 47 21 111 16 17 137 138 76 75
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 NC/A12 NC/A13 BA0 BA1 NC/BA2 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 DQMB8 CS0 CS1 NC/CS2 NC/CS3 RAS CAS WE DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
VDD 3.3V 3.3V 2.5V 2.5V 1.8V
VDDQ 3.3V 2.5V 2.5V 1.8V 1.8V
VDDID OPEN VSS OPEN VSS OPEN
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 9 10 101 102 103 173
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
D
PIN 92
PIN 184
PIN 92
C
PIN 184
12,22,23 DQM[0..7]
C
PIN 53
PIN 145
PIN 53 PIN 52
2D5V_DDR
PIN 52
PIN 144
2D5V_DDR
R225 12,23 CSAJ0 12,23 CSAJ1
12,22,23 DQS[0..7]
12,22,23 RASAJ 12,22,23 CASAJ 12,22,23 MWAJ
RASAJ CASAJ MWAJ
B
12 12 20 20 20 20 20 20 CKE0 CKE1 DDRCLK1 DDRCLKJ1 DDRCLK0 DDRCLKJ0 DDRCLK2 DDRCLKJ2 CKE0 CKE1 DDRCLK1 DDRCLKJ1 DDRCLK0 DDRCLKJ0 DDRCLK2 DDRCLKJ2
PIN 144
PIN 145
B
FRONT PIN 1
VOLTAGE KEY
CKE0 CKE1 CK0/(NC) CK0/(NC) CK1(CK0) CK1(CK0) CK2/(NC) CK2/(NC)
CK0/(NC) CK0/(NC) CK1(CK0) CK1(CK0) CK2/(NC) CK2/(NC) VDDQ= 2.5V
1 .8V FRONT VIEW 3 .3V
VOLTAGE KEY
20 20 20 20 20 20
DDRCLK4 DDRCLKJ4 DDRCLK3 DDRCLKJ3 DDRCLK5 DDRCLKJ5
DDRCLK4 DDRCLKJ4 DDRCLK3 DDRCLKJ3 DDRCLK5 DDRCLKJ5
VDDQ= 2.5V R227 8.2K
1 .8V FRONT VIEW
3 .3V
181 182 183 17,19,20,22,26 SMB_CLK_MAIN 17,19,20,22,26 SMB_DATA_MAIN SMB_CLK_MAIN SMB_DATA_MAIN WP 92 91 90
SA0 SA1 SA2 SCL SDA WP
NC NC/ (RESET) NC NC NC/ (FETEN) NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2D5V_DDR
181 182 183 92 91 90
SA0 SA1 SA2 SCL SDA WP
BACK93 PIN
CKE0 CKE1
12 12
CKE2 CKE3
CKE2 CKE3
FRONT PIN 1
BACK93 PIN
17,19,20,22,26 SMB_CLK_MAIN 17,19,20,22,26 SMB_DATA_MAIN 22 WP
WP
NC NC/ (RESET) NC NC NC/ (FETEN) NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176
A
A
TECHNOLOGY COPR.
Title
DDR Slot 1 / 2
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 21 of 48
A
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OK
2D5V_DDR DDRVREF DDRVREF 21
7 38 46 70 85 108 120 148 168
184
DIMM3 DDR_DIMM MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
82
1
D
VDDSPD/VCC3
VREF/NC
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDID
MD[0..63]
12,21,23
DDRVREF GEN. & DECOUPLING
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180
12,21,23 MAA[0..14] MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA13 MAA14 MAA11 MAA12 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 8.2K CSAJ4 CSAJ5
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 NC/A12 NC/A13 BA0 BA1 NC/BA2 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 DQMB8 CS0 CS1 NC/CS2 NC/CS3 RAS CAS WE DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
VDD 3.3V 3.3V 2.5V 2.5V 1.8V
VDDQ 3.3V 2.5V 2.5V 1.8V 1.8V
VDDID OPEN VSS OPEN VSS OPEN
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 9 10 101 102 103 173
D
2D5V_DDR
R228 75 +/-5% R0603
*
BC288 10nF C0603
*
BC289 10nF C0603
*
BC290 10nF C0603
*
BC291 10nF C0603 DDRVREF 21
DDRVREF R229 75 +/-5% R0603
*
BC292 10nF C0603
*
BC293 10nF C0603
*
BC294 10nF C0603
*
BC295 10nF C0603
C
12,21,23 DQM[0..7]
48 43 41 130 37 32 125 29 122 27 141 118 115 167 59 52 113 97 107 119 129 149 159 169 177 140 157 158 71 163
PIN 92
PIN 184
close to resistor divider
close to DIMM1 VREF pin
close to DIMM2 VREF pin
close to DIMM3 VREF pin
C
PIN 53
DIMM DECOUPLING
2D5V_DDR
PIN 52
PIN 144
PIN 145
2D5V_DDR
R1063 12,23 CSAJ4 12,23 CSAJ5
BC296
BC297
*
*
12,21,23 RASAJ 12,21,23 CASAJ 12,21,23 MWAJ 12,21,23 DQS[0..7]
*
*
B
*
*
*
*
VOLTAGE KEY
20 20 20 20 20 20
DDRCLK7 DDRCLKJ7 DDRCLK6 DDRCLKJ6 DDRCLK8 DDRCLKJ8
DDRCLK7 DDRCLKJ7 DDRCLK6 DDRCLKJ6 DDRCLK8 DDRCLKJ8
16 17 137 138 76 75
CK0/(NC) CK0/(NC) CK1(CK0) CK1(CK0) CK2/(NC) CK2/(NC)
VDDQ= 2.5V
1. 8V FRONT VIEW 3. 3V
BC312
0.1uF/NC
BC313
*
CKE0 CKE1
BACK93 PIN
12 12
CKE4 CKE5
CKE4 CKE5
FRONT PIN 1
21 111
BC308
0.1uF/NC
BC309
0.1uF/NC
BC310
*
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
5 14 25 36 56 67 78 86 47
BC302
0.1uF/NC
0.1uF/NC
BC304
*
0.1uF/NC
RASAJ CASAJ MWAJ
154 65 63
BC299
0.1uF/NC
BC300
0.1uF/NC
BC301
*
0.1uF
0.1uF
BC298
0.1uF
0.1uF/NC
*
*
BC305 0.1uF
BC306
0.1uF
BC307
*
BC303
B
0.1uF
0.1uF/NC
0.1uF/NC
*
*
2D5V_DDR
R1064
8.2K
181 182 183 92 91 90
SA0 SA1 SA2 SCL SDA WP
17,19,20,21,26 SMB_CLK_MAIN 17,19,20,21,26 SMB_DATA_MAIN 21 WP
A
SMB_CLK_MAIN SMB_DATA_MAIN WP
NC NC/ (RESET) NC NC NC/ (FETEN) NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
*
BC311
0.1uF/NC
A
TECHNOLOGY COPR.
Title
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176
DDR SLOT3
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 22 of 48
A
8
12,21,22 RASAJ 12,21,22 MWAJ 12,21,22 CASAJ MD[0..63] DQM[0..7] DQS[0..7] RASAJ MWAJ CASAJ
7
6
5
4
3
2
1
SSTL-2 Termination Resistors
12,21,22 12,21,22 12,21,22 MD/DQM(/DQS) MA/Control CS CKE (Note: The termination resistors are only for DDR application) DDR SSTL-2 SSTL-2 SSTL-2 LV-CMOS/OD 2.5V Rs 10/0 10/0 10/0 Rtt 33/47 22/33 22/33
MD[0..63] DQM[0..7] DQS[0..7]
OK
MAA[0..14] CSAJ[0..5]
MAA[0..14] CSAJ[0..5]
12,21,22 12,21,22
D
D
Pullup resistance can reswap by layout result. DDR_VTT
DECOUPLING CAPACITOR FOR SSTL-2 END TERMIANTION VTT ISLAND 0603 Package placed within 350mils of VTT Termination R-packs DDR_VTT DUMMY ONE HALF DEPEND ON LAYOUT
RN6 33 MD12 MD8 MD3 MD7 MD6 MD2 DQM0 DQS0
2 4 6 8
*
RN7
33
1 3 5 7 2 4 6 8
MD27 MD31 MD26 MD30 RN8 33
*
*
*
*1 3
5 7
MD37 MD33 MD36 MD32 MD38 MD34 DQM4 DQS4
*
*
*
MD1 MD5 MD4 MD0
2 4 6 8
*1 3
5 7 2 4 6 8
RN12 33
*
*
*
C
DQM1 DQS1 MD13 MD9 RN14 33 MD11 MD10 MD15 MD14 DQS2 MD21 MD17 MD16 RN17 33 MD22 MD18 DQM2 MD25 MD29 MD28 MD24 DQM3 DQS3 MD19 MD23 MD20
*1 3
5 7
MD44 MD40 MD35 MD39 MD45 MD41 MD59 MD63
2 4 6 8
*1 3
5 7
BC326 33 33 33 33 RN16 33
*
RN13 33
2 4 6 8
*1 3
5 7
BC322
0.1uF/NC
BC323
0.1uF
BC324
0.1uF/NC
BC325
*
0.1uF
RN10 33
2 4 6 8
*1 3
5 7
RN11 33
BC318
0.1uF/NC
BC319
0.1uF/NC
BC320
0.1uF/NC
BC321
*
0.1uF
RN9 33
2 4 6 8
*
1 3 5 7
BC314 0.1uF
BC315 0.1uF
BC316
0.1uF
BC317
0.1uF
C
0.1uF
0.1uF/NC
BC327
0.1uF/NC
BC328
0.1uF
BC329
*
*
*
2 4 6 8
*1 3
5 7 2 4 6 8 1 3 5 7 2 4 6 8
R237 R238 R239 R240 R241 33 33 33 33 33 RN15 33
R233 R234 R235 R236
*1 3
5 7
MD46 MD42 DQM5 DQS5 RN18 33 MD52 MD48 MD47 MD43
2 4 6 8 1 3 5 7 2 4 6 8 1 3 5 7
*1 3
5 7
BC330 0.1uF BC331 0.1uF BC333 0.1uF
*
*
*
2 4 6 8
*
*
*
*
*1 3
5 7
DQS6 DQM6 MD53 MD49 RN21 33 MD51 MD55 MD50 MD54
*1 3
5 7
BC338
0.1uF/NC
BC339
0.1uF
BC340
0.1uF/NC
BC341
*
*
*
2 4 6 8
*
BC342
0.1uF/NC
BC343
0.1uF/NC
BC344
0.1uF/NC
BC345
*
0.1uF/NC
B
*
0.1uF
RN19 33
2 4 6 8
*
BC334 RN20 33
0.1uF
BC335
0.1uF/NC
BC336
0.1uF
BC337
*
0.1uF
BC332
0.1uF
*
B
*
*
*
Pullup resistance can reswap by layout result.
DDR_VTT RN22 33 MD57 MD61 MD56 MD60 RN23 33 MD58 MD62 DQS7 DQM7 CSAJ3 CSAJ5 CSAJ2 CSAJ4 CSAJ0 R257 CSAJ1 R259
DDR_VTT MAA14 MAA13 MAA9 MAA7 MAA8 MAA5 MAA6 MAA4 MAA3 MAA2 MAA1 MAA0 MAA10 MAA12 MAA11 RASAJ MWAJ CASAJ R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R258 R260 R261 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
2 4 6 8
*1 3
5 7
2 4 6 8
*1 3
5 7 2 4 6 8
47 47 RN24 47
*1 3
5 7
A
*
A
TECHNOLOGY COPR.
Title
DDR Termination Res
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 23 of 48
A
8
11 11 11 11 11 11 SBAJ[0..7] ST[0..2] AC-BE[0..3] AAD[0..31] ADSTBF[0..1] ADSTBS[0..1] SBAJ[0..7] ST[0..2] AC-BE[0..3]
7
6
5V_SYS
5
12V_SYS VDDQ
4
3
2
GCDET- on card GND OPEN GCDET0V 1.47V
1
AVREFCG 0.35V 0.75V APERR 0V 1.5V
AAD[0..31] ADSTBF[0..1] ADSTBS[0..1]
3D3V_SB
OK
3D3V_SYS AGP1
NOTE: This AGP slot support both AGP3.0 display card and SiS301 video bridge card.
VDDQ
3D3V_SYS
D
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 OVRCNT# +5V +5V USB+ GND INTB# CLK REQ# VCC3.3 ST0 ST2 RBF# GND RESERVEDB14 SBA0 VCC3.3 SBA2 SB_STB GND SBA4 SBA6 DBI_LO GND VCC3_AUX VCC3.3 AD31 AD29 VCC3.3 AD27 AD25 GND AD_STB1 AD23 VDDQ AD21 AD19 GND AD17 C/BE#2 VDDQ IRDY# +12V TYPEDET# GC_AGP8X_DET USBGND INTA# RST# GNT# VCC3.3 ST1 MB_AGP8X_DET PIPE# GND WBF# SBA1 VCC3.3 SBA3 SB_STB# GND SBA5 SBA7 DBI_HI GND RESERVEDA24 VCC3.3 AD30 AD28 VCC3.3 AD26 AD24 GND AD_STB1# C/BE3# VDDQ AD22 AD20 GND AD18 AD16 VDDQ FRAME# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41
GCDETJ INTJA PCIRSTJ0 AGNT ST1 DBI_HI WBF SBAJ1 SBAJ3 SBSTBS SBAJ5 SBAJ7 DBI_HI WBF 11 11 GCDETJ INTJA PCIRSTJ0 AGNT 11 25,29,30,31 25,29,30,31,40 11
D
25,29,30,31 INTJB 19 CK_66M_AGP 11 AREQ
INTJB CK_66M_AGP AREQ ST0 ST2 RBF SBAJ0 SBAJ2 SBSTBF SBAJ4 SBAJ6
11 11
RBF DBI_LOW
11
SBSTBF
SBSTBS
11 3D3V_SYS
close to AGP SLOT
5V_SYS VDDQ
C
AAD31 AAD29 AAD27 AAD25 ADSTBF1 AAD23 AAD21 AAD19 AAD17 AC-BE2 A IRDY 11 AIRDY
AAD30 AAD28 AAD26 AAD24 ADSTBS1 AC-BE3 AAD22 AAD20 AAD18 AAD16 AFRAME AFRAME 11 GCDETJ R267 4.3K B R263 10K +/-5% R0603 R264 10K +/-5% R0603 R265
R262 124 R0603 54.9 +/-1% R266 124 R0603 +/-1%
C
AVREFCG
D
Q26
G C
Q27 MMBT3904
*
BC362 10nF C0603
2N7002
E
11
ADEVSEL APERR
11
ASERR
AC-BE1 AAD14 AAD12 AAD10 AAD8 ADSTBF0 AAD7 AAD5 AAD3 AAD1 AVREFCG
B
1 2 3
B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66
DEVEL# VDDQ PERR# GND SERR# C/BE1# VDDQ AD14 AD12 GND AD10 AD8 VDDQ AD_STB0 AD7 GND AD5 AD3 VDDQ AD1 VREF_CG
AGP_SLOT
TRDY# STOP# PME# GND PAR AD15 VDDQ AD13 AD11 GND AD9 C/BE0# VDDQ AD_STB0# AD6 GND AD4 AD2 VDDQ AD0 VREF_GC
A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
ATRDY ASTOP PMEJ APAR AAD15 AAD13 AAD11 AAD9 AC-BE0 ADSTBS0 AAD6 AAD4 AAD2 AAD0
ATRDY ASTOP PMEJ APAR
11 11 26,29,30,31,40 11
S
VDDQ R268 8.2K +/-5% R0603 APERR
D
Q28
B
G S
2N7002 R269 1K +/-5% R0603
*
1 2 3
BC363 0.1uF C0603
AVREFGC
11
AGP CONNECTOR DECOUPLING
put CAP close to AGP slot each POWER PIN
close to 748
VDDQ
3D3V_SYS 12V_SYS 5V_SYS BC368 10nF/NC C0603 BC369 10nF/NC C0603 BC370 10nF C0603 BC371 10nF C0603 BC372 10nF C0603 BC373 10nF/NC C0603 BC374 10nF/NC C0603 BC375 10nF/NC C0603
A
*
BC364 10nF C0603
*
BC365 10nF C0603
*
BC366 10nF C0603
*
BC367 10nF/NC C0603
A
TECHNOLOGY COPR.
Title
*
*
*
*
*
*
*
*
*
BC376 10nF C0603
*
BC377 10nF C0603
AGP
Document Number Re v
748A01
Date: Sunday, September 05, 2004 Sheet 24 of 48
A
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1D8V_VCCSB
1
OK *
U14A PREQJ4 PREQJ3 PREQJ2 PREQJ1 PREQJ0 PGNTJ4 PGNTJ3 PGNTJ2 PGNTJ1 PGNTJ0 INTJA INTJB INTJC INTJD FRAMEJ IR D YJ TR DYJ STOPJ SERRJ PAR DEVSELJ PLOCKJ CK_33M_S964 R272 33 R273 33 R274 33 C/BEJ3 C/BEJ2 C/BEJ1 C/BEJ0 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 IDEAVDD IDEAVSS ICHRDYA IDREQA IIRQA CBLIDA IIORA# IIOWA# IDACKA# ICHRDYB IDREQB IIRQB CBLIDB IIORB# IIOWB# IDACKB# IDSAA2 IDSAA1 IDSAA0 IDECSA1# IDECSA0# W1 W2 AE15 AD14 AC15 AE16 AF15 AC14 AD15 AE22 AD21 AC22 AE23 AF22 AC21 AD22 AC16 AF16 AD16 AE17 AF17 AF24 AF23 AD23 AF25 AE24 AF14 AD13 AF13 AD12 AF12 AD11 AF11 AF10 AE10 AE11 AC11 AE12 AC12 AE13 AC13 AE14 AF21 AD20 AF20 AD19 AF19 AD18 AF18 AD17 AC17 AE18 AC18 AE19 AC19 AE20 AC20 AE21 I CHRDYA IDEREQA IDEIRQA CBLIDA IDEIORJA IDEIOWJA IDACKJA I CHRDYB IDEREQB IDEIRQB CBLIDB IDEIORJB IDEIOWJB IDACKJB IDESAA2 IDESAA1 IDESAA0 IDECSJA1 IDECSJA0 IDESAB2 IDESAB1 IDESAB0 IDECSJB1 IDECSJB0 IDEDA0 IDEDA1 IDEDA2 IDEDA3 IDEDA4 IDEDA5 IDEDA6 IDEDA7 IDEDA8 IDEDA9 IDEDA10 IDEDA11 IDEDA12 IDEDA13 IDEDA14 IDEDA15 IDEDB0 IDEDB1 IDEDB2 IDEDB3 IDEDB4 IDEDB5 IDEDB6 IDEDB7 IDEDB8 IDEDB9 IDEDB10 IDEDB11 IDEDB12 IDEDB13 IDEDB14 IDEDB15 IDESAA[0..2] 37 ICHRDYA IDEREQA IDEIRQA CBLIDA IDEIORJA IDEIOWJA IDACKJA ICHRDYB IDEREQB IDEIRQB CBLIDB IDEIORJB IDEIOWJB IDACKJB 37 37 37 37 37 37 37 37 37 37 37 37 37 37 31 30 30 29 29 31 30 30 29 29 PREQJ4 PREQJ3 PREQJ2 PREQJ1 PREQJ0 PGNTJ4 PGNTJ3 PGNTJ2 PGNTJ1 PGNTJ0 INTJA INTJB INTJC INTJD F1 F2 F3 F4 E1 H4 G1 G2 G3 G4 F5 E4 E3 E2 M1 N4 N3 P4 P3 P2 N2 N1 W3 PCIRSTJ B3 K3 M2 P1 U4 W4 V1 V2 V3 V4 U1 U2 U3 T1 T2 T3 T4 R1 R2 R3 R4 M3 M4 L1 L2 L3 L4 K1 K2 K4 J1 J2 J3 J4 H1 H2 H3 PREQ4# PREQ3# PREQ2# PREQ1# PREQ0# PGNT4# PGNT3# PGNT2# PGNT1# PGNT0# INTA# INTB# INTC# INTD# FRAME# IRDY# TRDY# STOP# SERR# PAR DEVSEL# PLOCK# BC378 10nF C0603
*
BC379 0.1uF C0603
D
D
3D3V_SYS
24,29,30,31 24,29,30,31 29,30,31 29,30,31,32
PCIRSTJ
R271 4.7K +/-5% R0603 DUMMY
29,30,31,32 FRAMEJ 29,30,31,32 IRDYJ 29,30,31,32 TRDYJ 29,30,31,32 STOPJ 29,30,31,32 SERRJ 29,30,31,32 PAR 29,30,31,32 DEVSELJ 29,30,31 PLOCKJ 19 CK_33M_S964 24,29,30,31,40 PCIRSTJ0 32 PCIRSTJ1 13,37 PCIRSTJ2
P
I
PCICLK PCIRST# C/BE3# C/BE2# C/BE1# C/BE0# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
IDSAB2 IDSAB1 IDSAB0 IDECSB1# IDECSB0#
IDECSJA[0..1] 37
C
29,30,31,32 C/BEJ[0..3]
IDESAB[0..2]
37
C I
1D8V_VCCSB
R275 150 +/-1% R0603
* *
BC380 0.1uF C0603 SZVREF BC381 0.1uF C0603
IDA0 IDA1 IDA2 IDA3 IDA4 IDA5 IDA6 IDA7 IDA8 IDA9 IDA10 IDA11 IDA12 IDA13 IDA14 IDA15 IDB0 IDB1 IDB2 IDB3 IDB4 IDB5 IDB6 IDB7 IDB8 IDB9 IDB10 IDB11 IDB12 IDB13 IDB14 IDB15
D E
C
IDECSJB[0..1] 37
IDEDA[0..15]
37
R276 49.9 +/-1% R0603
B
M U T I O L
ZCLK ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZUREQ ZDREQ ZCMP_N ZCMP_P Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS ZVREF ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZAD16 AB26 V24 W26 R25 T26 Y24 Y23 AA24 AA25 AC26 AB25 Y22 AA23 AA26 W24 W25 V22 V23 V26 U22 U25 U24 T22 U26 T23 R22 T24 R24 R26 P22 Y26
B
29,30,31,32 AD[0..31]
IDEDB[0..15] SiS964
37
19 13 13 13 13 13 13
ZCLK1 ZSTB0 ZSTBJ0 ZSTB1 ZSTBJ1 ZUREQ ZDREQ
ZCLK1
3D3V_SYS RN25 INTJB INTJA INTJC INTJD 2 4 6 8
ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZAD16
*1 3
5 7
SZCMP_N SZCMP_P SZ1XAVDD SZ1XAVSS SZ4XAVDD SZ4XAVSS SZVREF 1D8V_VCCSB 1D8V_VCCSB R278 SZ4XAVDD BC389 0.1uF C0603 BC390 10nF C0603 SZ4XAVSS R281 56 56
8.2K +/-5% 8P4R0603 ZAD[0..16] ZAD[0..16] 13
Analog Power supplies of Transzip function for 96X Chip. 1D8V_VCCSB
SZCMP_N
A
SZ1XAVDD
*
BC386 0.1uF C0603
*
BC387 10nF C0603 SZ1XAVSS
*
*
*
BC383 0.1uF C0603
*
BC384 10nF C0603 SZCMP_P Title
A
TECHNOLOGY COPR.
PCI IDE MUTIOL
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 25 of 48
A
8
7
6
5
4
3
2
1
8
7
6
5
4
U14B
3
RN60 STXEN 1 STXD0 3 STXD1 5 STXD2 7
2
1
Put closed to 964 CHIP OSC25MHO 10M OSC25MHI R1097 1 1 2 2 X8 1
*
35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35
VCCP
TXD0 TXD1
R284 CPUSLPJ
4.7K/NC 19 7 7 40 PICCLK1 PICD0 PICD1 AF26 AC25 AB24 APICCK/LDTREQ# APICD0/THERM2# APICD1/GPIOFF#
D12 STXD1 C12 STXD2 E13 STXD3 C13 RXCLK A12 RXDV A13 RXER B12 RXD0 A11 RXD1 B11 RXD2 C11 RXD3 B14 COL
TXD1 TXD2 TXD3
TXD1 TXD2 TXD3 RXCLK RXDV RXER RXD0 RXD1 RXD2 RXD3 COL CRS
50V, NPO, +/-5%
TXD2 TXD3 RXCLK RXDV
LAD[0..3] LAD0 LAD1 LAD2 LAD3 40 40 40 LFRAMEJ LDRQJ SIRQ LFRAMEJ LDRQJ SIRQ AC4 AC3 AE1 AF1 AD3 AE2 AF2 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# SIRQ
1D8V_SB MIIAVDD BC392 0.1uF C0603 MIIAVSS Analog power of MII BC393 10nF 25V, Y5V, +80%/-20% C0603
R1159
4.7K
RXER RXD0 RXD1 RXD2 RXD3
*
*
Put closed to 96X CHIP OSC32KHI OSC32KHO R285 10M
17,38 17 17,38 17,38
SDATI0 SDATI1 SDATO SYNC
SDATI0 SDATI1 SDATO SYNC AC_RESETJ BIT_CLK
E6 B4 AB3 AC1 B5 AC2
AC_SDIN0 AC_SDIN1
COL
AC_SDOUT AC_SYNC AC_RESET# AC_BIT_CLK
CRS MDC MDIO MIIAVDD
C15 CRS C9 E9 B7 A6 SMDC SMDIO MDC MDIO
C
MDC MDIO
2
D
7 7 7 7 7 7 7 7
INITJ A20MJ SMIJ INTR NMI IGNNEJ FERRJ STPCLKJ
INITJ A20MJ SMIJ INTR NMI IG NNEJ FERRJ STPCLKJ CPUSLPJ
AB23 AD26 AE25 AC24 AD25 AD24 AE26 AB22 AC23
INIT# A20M# SMI# INTR NMI IGNNE# FERR# STPCLK# CPUSLP#
OSC25MHI
D7 C7
OSC25MHI OSC25MHO TXCLK TXEN TXD0 TXEN TXD0
33 +/-5% 2 4 6 8
TXEN TXD0 TXD1 TXD2
CPU_S APIC M L P C AC97 I I
OSC25MHO TXCLK TXEN
D10 TXCLK E10 STXEN E11 STXD0
RN61 SMDIO SMDC STXD3 1 3 5 7
*
33 +/-5% MDIO 2 MDC 4 TXD3 6 8
BC717 15pF
BC718 20pF
*
XTAL-25MHz C0603
D
17 AC_RESETJ 17,38 BIT_CLK
C
X4 BC395 15pF 50V, NPO, +/-5% C0603 3 4
MIIAVDD MIIAVSS
OSC32KHI OSC32KHO 45 46 BATOK PWRGD_SB BATOK BC397 RTCVDD 0.1uF 25V, Y5V, +80%/-20% C0603
C2 C1 D4 D2
MIIAVSS OSC32KHI OSC32KHO GPIO0/SPDIF BATOK PWROK
*
1
XTAL-32.768kHz 2
20PF BC396 22pF 50V, NPO, +/-5% C0603
*
Y3 AE3 Y4 AA1 AA2 AA3 AA4 A4 C6 C5 C4 F6 E5 AB2 AB1 GPIO11 GPIO12 SMB_CLK_MAIN SMB_DATA_MAIN PREQJ5 PGNTJ5 GPIO7 R ING SDATI2 THERMJ
GPIO0 GPIO1 THERMJ GPIO3 GPIO4 PREQJ5 PGNTJ5 GPIO7 RING SDATI2 17
18 18 40 18 18 32 32 18 44 NEED NOT to place close to 96X
R T C
GPIO1/LDRQ1# GPIO2/THERM# GPIO3/EXTSMI# GPIO4/CLKRUN# GPIO5/PREQ5#
*
RN8SMDA
+/-5% 8 6 4 2
C3 D3
RTCVDD RTCVSS
3D3V_SYS
GPIO6/PGNT5# GPIO7 GPIO8/RING GPIO9/AC_SDIN2 GPIO10/AC_SDIN3
19 CK_14M_S964 38,45 SPKR
CK_14M_S964 SENTEST SPKR
AD2 D1 AD1
OSCI ENTEST SPK
LDRQJ SIRQ SENTEST
B
45 PWRBTNJ 24,29,30,31,40 PMEJ 46 PSONJ
PWRBTNJ PMEJ PSONJ
D5 A7 D8
PWRBTN# PME# PSON#
GPIO11/OSC25M/STP_PCI# GPIO12/CPUSTP# GPIO19 GPIO20
FSB0 FSB1
7,19 6,19 PMEJ R292 4.7K GPIO pins pull down NEED NOT to place close to 96X R ING R1163 4.7K DUMMY 3D3V_SYS THERMJ R293 4.7K DUMMY
SMB_CLK_MAIN 17,19,20,21,22 SMB_DATA_MAIN 17,19,20,21,22
45 S1LED_GREEN 13,45 AUXOK
S1LED_GREEN AUXOK
*
R294 3D3V_SB 41 41 41 41 KBDAT KBCLK PMDAT PMCLK R295 KBDAT KBCLK PMDAT
BC398 0.1uF 25V, Y5V, +80%/-20% C0603
B6 A3
ACPILED AUXOK NC30 NC31 NC32 GPIO13 NC33 GPIO14 NC34 GPIO15/KBDAT GPIO16/KBCLK GPIO17/PMDAT GPIO18/PMCLK NC38 D15 E14 C14 A14 D13 C10 A10 B9 A9
4.7K/NC 4.7K/NC
B2 A5 B8 A8 C8 D6
SMB_DATA_MAIN R296 SMB_CLK_MAIN R300
NC35 NC36 NC37
A
SiS963, 964 GPIO 0~7 SiS963, 964 GPIO 9,10 internal pull up internal pull down
Place near to 96X SDATI0 SDATI1 SDATI2 GPIO7 R305 R306 R307 R308 4.7K DUMMY BIT_CLK 4.7K DUMMY 4.7K DUMMY 4.7K DUMMY SiS964
*
BC399 15pF 50V, NPO, +/-5% C0603
Title
964-LPC/MII/GPIO
Document Number R ev
748A01
Date: Sunday, September 05, 2004 Sheet 26 of 48
8
7
6
5
4
3
2
*
LAD0 LAD1 LAD2 LAD3
RN26 4.7K/NC 7 5 3 1 R288 R289 R290
G P I O
4.7K DUMMY 4.7K DUMMY 0 3D3V_SB
ACPI/OTHERS K B C
B
4.7K 4.7K
A
TECHNOLOGY COPR.
A
1
8
33 33 33 33 36 36 36 36 33 33 33 33 33 33 33 33
7
UV0+ UV0UV1+ UV1UV2+ UV2UV3+ UV3UV4+ UV4UV5+ UV5UV6+ UV6UV7+ UV75V_SB R1142 UV0+ UV0UV1+ UV1UV2+ UV2UV3+ UV3UV4+ UV4UV5+ UV5UV6+ UV6UV7+ UV7-
6
G26 G25 H24 H23 C21 D21 A22 B22 C19 D19 A20 B20 C17 D17 A18 B18 C26 C24 D26 D25 D24 E24 E23 F22 E18 E20 E22 F17 F18 F19 F20 F21 G22 H22 AA6 AA7 AA8 AA9 AA10 AB6 AF3 AD4 Y2 Y1 AB5 AD5 UV0+ UV0UV1+ UV1UV2+ UV2UV3+ UV3UV4+ UV4UV5+ UV5UV6+ UV6UV7+ UV7OC0# OC1# OC2# OC3# OC4# OC5# OC6# OC7# UVDD18 UVDD18 UVDD18 UVDD18 UVDD18 U