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5 4 3 2 1
PCB:244*210mm
P4M890T-M
Customer:channel
L2:PWR
1 Cover Page L3:GND
GPIO
2 Block Diagram IC GPIO(PIN) Function Note
3 CPU P4-775(FSB) VT
GPI23(P21) -IDE2 cable detect
8237R+
D
4 CPU P4-775(PWR, GND) GPI8(AC9) -IDE1 cable detect D
5 Clock Generator, Clock Buffer Rev : 1.0 GPI18(Y4) -PCIE PME SCI
PCB SVID:1019(ECS)
6 Power (CPU Vcore) SSID:2171(Q71) Schedule GPI19(U23) -PCIE Hot Plug SCI
Schematics Lead-Free BOM
O GPO7(R2) -TBL(Top Block Lock) default=0
244*210*1.6 -2116 Schematics Layout Gerber Out M/B return
7 Power (DC to DC) OD GPO10(R25) V_DIMM volt adjust 0
15-Q71-010010 RoHS 11/28~12/30
8237R+,ALC655 A 81-605-Q71000 11/16~11/28 chipset delay 12/30 35/20/20 OD GPO11(T23) V_DIMM volt adjust 1
8 VDIMM & DDR VTT Green
RoHS O GPO5(AC7) -WP_ROM default=1
8237A,ALC883 A 81-605-Q71001 10/10
9 NB P4M890 (CPU) OD GPO29 PCIE reset
15-Q71-010020 RoHS
8237R+,ALC655 B 81-605-Q71010 2/10 2/13 2/24 30/10 GP25(22) CPU volt adjust 0
10 NB P4M890 (MEM) Purple IO
RoHS 8712KX GP26(21) CPU volt adjust 1
8237A,ALC883 B 81-605-Q71011 20/10
11 NB P4M890 (PCI-E, V-Link) Purple GP40(79) CTRL PS2 volt in S5 default=1
15-Q71-011000 RoHS
8237R+,ALC655 1.0 89-206-Q71100 4/10 6/19 100/50/10 GP23(24) CTRL over clock 1:enable
12 NB P4M890 (VGA) Purple
GP10(84) MSG LED1
13 DDR II SLOT1 1.0
C GP53(77) MSG LED2 C
14 DDR II SLOT2 GP20(27) CFG1 default=0
GP21(26) CFG2 default=0
15 DDR Terminator
16 PCI Express Slot X16, X1, CNR slot
Rev:A Initial version
17 SB VT8237R+/8237A/8237S(PCI, USB) 1. Base on P4M800PRO-M(1.0A) to modify.
18 SB VT8237R+/8237A/8237S(IDE, GPIO, AC-Link, SATA)
19 SB VT8237R+/8237A/8237S(V-Link, MII, ROM)
Rev:A->B
20 LAN PHY(VT6103L) 1.Delete 1394, add CNR slot.
2.DDR2 termination resistor:68 ohm->47 ohm.
21 Super IO(ITE8712F/KX,8718), FDD 3.Add BA0,BA1,BA2 termination resistor.
22 PCI 1, PCI 2 4.Change V_DIMM MOSFET from SO8 to TO-251.
B 5.NB:add 22UF on VCCA33HCK,VCCA33MCK. B
23 USB, PS2, IDE 6.Modify CPU thermal trip circuit.
24 COM*2, LPT, VGA 7.JP1 pull high to VCC5 on ITE 8712F/KX.
8.ALC883:modify circuit for Vista.
25 Front Panel, FAN, ATX24P 9.Add GPO29 control PCIE reset.
26 AUDIO(ALC655/ALC883),Chip 10.INT_H pull down.
11.Saving EEPROM of LAN.
27 AUDIO(ALC655/ALC883),Connector
Rev:B->1.0
28 CLOCK DIAGRAM 1.VR11
29 POWER SEQUENCE 2.Co-layout VT8237S
3.AUDIO capcitor modify.
4.VCC3 transfer to +1.5V_NB
5.CPU voltage adjustment.
6.add F_MIC2.
A A
7.Modify clock gen's enable
8.Change SIO:-PCI_RST5 to -PCI_RST3.
Elitegroup Computer Systems
Title
Cover Page
Size Document Number Rev
Custom
P4M890T-M 1.0
Date: Tuesday, June 20, 2006 Sheet 1 of 29
5 4 3 2 1
5 4 3 2 1
05A
PWM P4, Pentium-D
Richtek 9245A
+Richtek 9602 LGA775 (SMD)
Clock Gen.
VRM10.X 6 1066MHz ICS 953002DF
3,4 5
(Realtek RTM866-890)
D AGTL+ D
266MHz
VGA CON CRT
VIA NB:P4M890
24
AGTL+ P4 CPU I/F Clock Buffer Unbuffered
DDR 400/DRR2 533 ICS 9P936AF DDR II-DIMM
PCIE GFX x16 PCIE x16 5 13,14,15
INTEGRATED GRAPHICS
16 (Realtek RTM682-800) DDR2-533 Single Channel
(UniChrome Pro)
1 X16 PCIE VIDEO I/F (Non ECC)
PCIE x1 PCIE x1 1 X16 V-Link I/F WITH SB (Pin to Pin P4M900)
16 9,10,11,12 i)DDR2 667
ii)Int. DeltaChrome/DX9 support
V-LINK
X16
Revision List
C
RJ45 LAN PHY
IN C/B ITE8712
C
VT8237R +/ AC LINK ALC655/ OUT B/Sur
( ) VT6103L ALC883 ITE8716 add Dual sourcing
20 (TQFP48) 20 VT8237A 26,27 MIC S/Sur
(Pin to Pin) ITE8718 add PECI(CPU temp:digital)
USB2.0 (4+4) ITE8726 add K8 power sequence
CNR slot
SATA (2 PORTS) 16
Revision List(All pin to pin)
USB2.0*8 USB 2.0 AC97(VT8237R+)
VT8237CD First released
23 HD(VT8237A)
VT8237R LAN PHY license.
ATA 66/100/133 Serial ATA
SATA*2 VT8237R+ SATA II detect support
ACPI 2.0 18
VT8237A HD support
KB& PCI/PCI BDGE
VT8237S SATA II,HD support
MS 23 LPC I/F 17,18,19 ATA 133
IDE*2
23
B PCI BUS LPC BUS B
Impedance PCB 2116
20/7.5/7.5/7.5/20
USB_P0+/- (45/90) 20/7.5/7.5/7.5/20(VIA excel)
7.5/7.5/7.5(50/90 guide)
FLASH LAN RX+/- 24/6/9/6/24
PCI SLOT*2 ITE LPC SIO 8712F/IX,KX BIOS TX+/-
(50/100) 24/6/9/6/24(VIA excel)
22 21 8/12/8(47/91 guide)
4M 19 20/5/7/7/20
SATA (50/100) 20/5/7/7/20(VIA excel)
group mismatch 5 mil.
R.G.B NB->RES (37.5) 20/12/20/12/20/12/20
RES->CON (75) 20/5/20/5/20/5/20
1U-04( 6.3V) 1U-06(BOM 10V) Put 75 ohm on NB
0.1U-04( 16V) 0.1U-06(BOM 25V)
FLOPPY COM PCI Bus Resource
LPT
22U/25DE 5*7 mm 21 24 PCI1 AD19 INTA,BCD REQ0
100U/16DE 6.3*11 mm 2 D O
PCI2 AD20 INTB,CDA REQ1
220U/10DE 6.3*11 mm D D C 3
470U/16DE 8*11 mm
A 680U/?DE 8*8 mm A
OG I E BC ECB
1000U/10DE 8*14 mm 1 3 G S G S B E 1 2 1 2 3
G S A O I
1500U/16DE 10*25 mm
TO-263 TO-263 TO-252 SOT-223 SOT-23 SOT-23 SOT-23 T0-92 T0-92 T0-92
Elitegroup Computer Systems
3300U/25DE 10*25 mm
B55QS03 2SK3296 20N03 1086(1.5A) 2N7002 2N3904 BAT54C 78L05-D LM431 HSD882-D Title
TM3055TL-S 1085(3A) SI2303S 2N3906 BAT54S LM432 2N2222A
45N03 1117(0.8~1A) SI2301S MMBT2907A 2N2097A Block Diagram
Size Document Number Rev
Custom
P4M890T-M 1.0
Date: Tuesday, May 30, 2006 Sheet 2 of 29
5 4 3 2 1
A B C D E
5/15 CPU1A PECI:Platform Environment Control Interface. CPU1D
HA3 L5 K3 -A20M VCORE
9 HA[3:31] A#3 A20M -A20M 19
HA4 P6 R3 -FERR Y7 A20
A#4 FERR -FERR 19 GND RSVD CONROE
HA5 M5 P3 -CPUINIT Y5 AC4
HA6 A#5 INIT INTR -CPUINIT 19 GND RSVD
L4 A#6 LINT0 K1 INTR 19 Y2 GND RSVD AE4
HA7 M4 L1 NMI_SB W7 AE6
AN8
AN9
M23
M24
M25
M26
M27
M28
M29
M30
N23
N24
N25
K23
K24
K25
K26
K27
K28
K29
K30
A#7 LINT1 NMI_SB 19 GND RSVD
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
M8
-IGNNE ER87
K8
HA8
L8
J8
J9
R4 A#8 IGNNE N2 -IGNNE 19 W4 GND RSVD AH2
HA9 T5 P2 -SMI CPU1C V7 B13 COMP8 24.9-1-04
A#9 SMI HTEST13 R300 -SMI 19 GND RSVD
HA10 U6 L2 J4 V6 C9 BPM1_2
VCC_CPU182
VCC_CPU183
VCC_CPU184
VCC_CPU185
VCC_CPU186
VCC_CPU187
VCC_CPU188
VCC_CPU189
VCC_CPU190
VCC_CPU191
VCC_CPU192
VCC_CPU193
VCC_CPU194
VCC_CPU195
VCC_CPU196
VCC_CPU197
VCC_CPU198
VCC_CPU199
VCC_CPU200
VCC_CPU201
VCC_CPU202
VCC_CPU203
VCC_CPU204
VCC_CPU205
VCC_CPU206
VCC_CPU207
VCC_CPU208
VCC_CPU209
VCC_CPU210
VCC_CPU211
VCC_CPU212
VCC_CPU213
VCC_CPU214
VCC_CPU215
VCC_CPU216
VCC_CPU217
VCC_CPU218
VCC_CPU219
VCC_CPU220
VCC_CPU221
VCC_CPU222
VCC_CPU223
VCC_CPU224
VCC_CPU225
VCC_CPU226
HA11 A#10 SLP/TESTH13 -STPCLK 0-04 -SLP 9,19 GND GND RSVD VCC_PLL
T4 A#11 STPCLK M3 -STPCLK 19 J7 GND GND B5 V30 GND RSVD D1
HA12 U5 K2 B8 V3 D14
A#12 GND GND GND RSVD
9 5/15
HA13 U4 D2 K5 C10 V29 D16 C303
HA14 A#13 ADS -ADS GND GND GND RSVD .1u-16VY-04
V5 A#14 ADSTB0 R6 -HA_STB0 9 K7 GND GND C13 V28 GND RSVD D23
4 HA15 V4 AD5 L23 C16 V27 E23 C258 4
HA16 A#15 ADSTB1 -HA_STB1 9 GND GND GND RSVD 10u-10V-08
W5 A#16 BNR C2 -BNR 9 L24 GND GND C19 H28 GND RSVD E5
HA17 AB6 B2 L25 C22 AF30 E6
HA18 A#17 DBSY -DBSY 9 GND GND GND RSVD R190 1K-04
W6 A#18 DEFER G7 -DEFER 9 L26 GND GND C24 V26 GND RSVD E7
HA19 Y6 C1 L27 C4 V25 F23
HA20 A#19 DRDY -DRDY 9 GND GND GND RSVD GTLVREF4_CPU
Y4 A#20 HIT D4 -HIT 9 L28 GND GND C7 V24 GND RSVD G10
HA21 AA4 E4 L29 D12 V23 J3 R199 1K-04
HA22 A#21 HITM -HITM 9 GND GND GND RSVD
AD6 A#22 TRDY E3 -HTRDY 9 L3 GND GND D15 U7 GND RSVD N4
HA23 AA5 G8 L30 D18 HTEST12 U1 N5 R201 1K-04
HA24 A#23 BPRI -BPRI 9 GND GND GND RSVD
AB5 A#24 BR0 F3 -BREQ0 9 CONROE L6 GND GND D21 T7 GND RSVD P5
HA25 AC5 C3 L7 D24 CONROE T6
HA26 A#25 LOCK -HLOCK 9 GND GND GND 60 ohm/X
AB4 A#26 PCREQ G5 PECI 21 M1 GND GND D3 T3 GND
HA27 AF5 F2 GTLVREF3_CPU M7 D5 R7 50 ohm/ install
HA28 A#27 EDRDY GND GND GND
AF4 A#28 N3 GND GND D6 R5 GNDRSVD(VID6) AM5 VID6 6
HA29 AG6 K4 N6 D9 R30 F6
HA30 A#29 REQ0 -HREQ0 9 GND GND GND IMPSEL R297 51-1-04
AG4 A#30 REQ1 J5 -HREQ1 9 N7 GND GND E11 R29 GND
HA31 AG5 M6 P23 E14 CONROE
A#31 REQ2 -HREQ2 9 GND GND LGA-775PS-AMP
STP6 1 AH4 A#32 REQ3 K6 -HREQ3 9 P24 GND GND E17
1 AH5 J6 P25 E2 VTT_CPU
STP5 A#33 REQ4 -HREQ4 9 GND GND
AJ5 A#34 P26 GND GND E20
AJ6 B3 P27 E25 HTEST0 R185 62-04
A#35 RS0 -RS0 9 GND GND
5/15 RS1 F5 -RS1 9 P28 GND GND E26 HTEST2