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PIC16C62B/72A
Pin Diagram
SDIP, SOIC, SSOP, Windowed CERDIP
28-Pin 8-Bit CMOS Microcontrollers
Microcontroller Core Features:
· High-performance RISC CPU · Only 35 single word instructions to learn · All single cycle instructions except for program branches which are two cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) · Interrupt capability (up to 7 internal/external interrupt sources) · Eight level deep hardware stack · Direct, indirect, and relative addressing modes · Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Brown-out detection circuitry for Brown-out Reset (BOR) · Programmable code-protection · Power saving SLEEP mode · Selectable oscillator options · Low-power, high-speed CMOS EPROM technology · Fully static design · In-Circuit Serial ProgrammingTM · Wide operating voltage range: 2.5V to 5.5V · High Sink/Source Current 25/25 mA · Commercial, Industrial and Extended temperature ranges · Low-power consumption: - < 2 mA @ 5V, 4 MHz - 22.5 µA typical @ 3V, 32 kHz - < 1 µA typical standby current
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL
·1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA
Peripheral Features:
· Timer0: 8-bit timer/counter with 8-bit prescaler · Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · Capture, Compare, PWM module · Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit · 8-bit multi-channel Analog-to-Digital converter · Synchronous Serial Port (SSP) with Enhanced SPITM and I2CTM
© 1998 Microchip Technology Inc.
Preliminary
PIC16C72A
DS35008A-page 1
PIC16C62B/72A
Pin Diagrams
SDIP, SOIC, SSOP, Windowed CERDIP
MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL
·1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA
Key Features PICmicroTM Mid-Range Reference Manual (DS33023) Operating Frequency Resets (and Delays) Program Memory (14-bit words) Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM modules Serial Communications 8-bit Analog-to-Digital Module
PIC16C62B
PIC16C62B DC - 20 MHz POR, BOR (PWRT, OST) 2K 128 6 Ports A,B,C 3 1 SSP --
PIC16C72A DC - 20 MHz POR, BOR (PWRT, OST) 2K 128 7 Ports A,B,C 3 1 SSP 5 input channels
DS35008A-page 2
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
Table of Contents
1.0 Device Overview.................................................................................................................................................... 5 2.0 Memory Organization ............................................................................................................................................ 7 3.0 I/O Ports .............................................................................................................................................................. 19 4.0 Timer0 Module..................................................................................................................................................... 25 5.0 Timer1 Module..................................................................................................................................................... 27 6.0 Timer2 Module..................................................................................................................................................... 31 7.0 Capture/Compare/PWM (CCP) Module(s) .......................................................................................................... 33 8.0 Synchronous Serial Port (SSP) Module .............................................................................................................. 39 9.0 Analog-to-Digital Converter (A/D) Module ........................................................................................................... 49 10.0 Special Features of the CPU ............................................................................................................................... 55 11.0 Instruction Set Summary ..................................................................................................................................... 69 12.0 Development Support.......................................................................................................................................... 71 13.0 Electrical Characteristics ..................................................................................................................................... 75 14.0 DC and AC Characteristics Graphs and Tables .................................................................................................. 95 15.0 Packaging Information......................................................................................................................................... 97 Appendix A: Revision History..................................................................................................................................... 103 Appendix B: Conversion Considerations ................................................................................................................... 103 Appendix C: Migration from Base-line to Mid-Range Devices ................................................................................... 104 Index ........................................................................................................................................................................... 105 On-Line Support.......................................................................................................................................................... 109 Reader Response ....................................................................................................................................................... 110 PIC16C62B/72A Product Identification System .......................................................................................................... 111
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: · Fill out and mail in the reader response form in the back of this data sheet. · E-mail us at [email protected]. We appreciate your assistance in making this a better document.
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 3
PIC16C62B/72A
NOTES:
DS35008A-page 4
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
1.0 DEVICE OVERVIEW
This document contains device-specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are two devices (PIC16C62B, PIC16C72A) covered by this datasheet. The PIC16C62B does not have the A/D module implemented. Figure 1-1 is the block diagram for both devices. The pinouts are listed in Table 1-1.
FIGURE 1-1:
PIC16C62B/PIC16C72A BLOCK DIAGRAM
13 Program Counter EPROM 2K x 14 Program Memory 8 Level Stack (13-bit) RAM 128 x 8 File Registers RAM Addr(1) 9 PORTB Data Bus 8 PORTA RA0/AN0(2) RA1/AN1(2) RA2/AN2(2) RA3/AN3/VREF(2) RA4/T0CKI RA5/SS/AN4(2)
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8 W reg ALU PORTC
MUX
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
MCLR
VDD, VSS
Timer0
Timer1
Timer2
CCP1
Synchronous Serial Port
A/D(2)
Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C62B.
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 5
PIC16C62B/72A
TABLE 1-1
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C62B/PIC16C72A PINOUT DESCRIPTION
DIP Pin# 9 10 SOIC Pin# 9 10 I/O/P Type I O Buffer Type Description
MCLR/VPP
1
1
I/P
RA0/AN0(4) RA1/AN1(4) RA2/AN2(4) RA3/AN3/VREF(4) RA4/T0CKI RA5/SS/AN4(4)
2 3 4 5 6 7
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. TTL RA0 can also be analog input0 TTL TTL TTL ST TTL RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 VSS VDD Legend: I = input Note 1: 2: 3: 4:
21 22 23 24 25 26 27 28 11 12 13 14 15
21 22 23 24 25 26 27 28 11 12 13 14 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) ST ST ST ST ST
16 16 I/O ST 17 17 I/O ST 18 18 I/O ST 8, 19 8, 19 P -- Ground reference for logic and I/O pins. 20 20 P -- Positive supply for logic and I/O pins. O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. The A/D module is not available on the PIC16C62B.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input. RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode).
DS35008A-page 6
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
2.0 MEMORY ORGANIZATION
FIGURE 2-1:
There are two memory blocks in each of these PICmicros. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
2.1
Program Memory Organization
Stack Level 8 Reset Vector
The PIC16C62B/72A PICmicros have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Each device has 2K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wraparound. User Memory Space The reset vector is at 0000h and the interrupt vector is at 0004h.
0000h
Interrupt Vector
0004h 0005h
On-chip Program Memory 07FFh 0800h
1FFFh
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 7
PIC16C62B/72A
2.2 Data Memory Organization FIGURE 2-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Registers 7Fh Bank 0 Bank 1 ADRES(2) ADCON0(2) ADCON1(2) General Purpose Registers TMR1L TRM1H T1CON TRM2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON PR2 SSPADD SSPSTAT PCON PCLATH INTCON PIR1 PCLATH INTCON PIE1 INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1)
OPTION_REG
REGISTER FILE MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BFh C0h FFh
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1(1) = 00 = 01 = 10 = 11 RP0 (STATUS<6:5>)
PCL STATUS FSR TRISA TRISB TRISC
Bank0 Bank1 Bank2 (not implemented) Bank3 (not implemented)
Note 1: Maintain this bit clear to ensure upward compatibility with future products.
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some "high use" special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 2.5).
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C62B, read as '0'.
DS35008A-page 8
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1. The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.
TABLE 2-1
Addr Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (4)
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h-09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h-1Dh 1Eh 1Fh INDF(1) TMR0 PCL
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(5) RP1(5) RP0 TO PD Z DC C
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 rr01 1xxx rr0q quuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- --
STATUS(1) FSR(1) PORTA(6) PORTB(7) PORTC(7) -- PCLATH(1,2) INTCON(1) PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON -- ADRES
(3)
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read Unimplemented -- GIE -- -- PEIE ADIF(3) -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE SSPIF T0IF CCP1IF INTF TMR2IF RBIF TMR1IF
---0 0000 ---0 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000 -- --
Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --uu uuuu 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- Unimplemented A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON -- CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000 --00 0000 -- --
xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0
ADCON0(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as '0'. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 5: The IRP and RP1 bits are reserved. Always maintain these bits clear. 6: On any device reset, these pins are configured as inputs. 7: This is the value that will be in the port output latch.
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 9
PIC16C62B/72A
TABLE 2-1
Addr Name
SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (4)
Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h-89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-91h 92h 93h 94h 95h-9Eh 9Fh PR2 SSPADD SSPSTAT -- ADCON1
(3)
INDF(1) OPTION_ REG PCL(1) STATUS FSR(1) TRISA TRISB TRISC -- PCLATH(1,2) INTCON(1) PIE1 -- PCON --
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP
(5)
RP1
(5)
RP0
TO
PD
Z
DC
C
rr01 1xxx rr0q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 -- --
Indirect data memory address pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register PORTC Data Direction Register Unimplemented -- GIE -- -- PEIE ADIE(3) -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE SSPIE T0IF CCP1IE INTF TMR2IE RBIF TMR1IE
---0 0000 ---0 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000 -- --
Unimplemented -- Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF -- -- -- -- -- POR BOR
---- --qq ---- --uu -- --
1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 -- -- ---- -000
Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as '0'. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 5: The IRP and RP1 bits are reserved. Always maintain these bits clear. 6: On any device reset, these pins are configured as inputs. 7: This is the value that will be in the port output latch.
DS35008A-page 10
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
2.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: These devices do not use bits IRP and RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 2-3:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear 0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes Note: RP1 = not implemented, maintain clear bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 11
PIC16C62B/72A
2.2.2.2 OPTION_REG REGISTER Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-4:
R/W-1 RBPU bit7
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS35008A-page 12
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
FIGURE 2-5:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 PEIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt IINTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 13
PIC16C62B/72A
2.2.2.4 PIE1 REGISTER Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts.
FIGURE 2-6:
U-0
--
PIE1 REGISTER (ADDRESS 8Ch)
U-0
--
R/W-0 ADIE(1)
U-0
--
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0 TMR2IE
bit7
R/W-0 TMR1IE bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as `0' ADIE(1): A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 5-4: Unimplemented: Read as `0' bit 3:
bit 2:
bit 1:
bit 0:
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear.
DS35008A-page 14
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 2-7:
U-0
--
PIR1 REGISTER (ADDRESS 0Ch)
U-0
--
R/W-0 ADIF(1)
U-0
--
R/W-0 SSPIF
R/W-0 CCP1IF
R/W-0 TMR2IF
bit7
R/W-0 TMR1IF bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as `0' ADIF(1): A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 5-4: Unimplemented: Read as `0' bit 3:
bit 2:
bit 1:
bit 0:
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear.
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 15
PIC16C62B/72A
2.2.2.6 PCON REGISTER Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. If the BODEN configuration bit is set, BOR is '1' on Power-on Reset. If the BODEN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BODEN configuration bit is clear). BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred.
FIGURE 2-8:
U-0 -- bit7
PCON REGISTER (ADDRESS 8Eh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-q BOR bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0:
DS35008A-page 16
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
2.3 PCL and PCLATH 2.4 Program Memory Paging
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.1 STACK The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper bit of the address is provided by PCLATH<3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bit is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the return instructions (which POPs the address from the stack).
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 17
PIC16C62B/72A
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 2-2:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
EXAMPLE 2-1:
· · · ·
INDIRECT ADDRESSING
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h · Increment the value of the FSR register by one (FSR = 06) · A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
NEXT
movlw movwf clrf incf btfss goto :
CONTINUE
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-9. However, IRP is not used in the PIC16C62B/72A.
FIGURE 2-9:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
0 IRP 7 FSR register 0
RP1:RP0
6
from opcode
(2)
bank select location select 00 00h 01 80h 10 100h 11 180h
(2)
bank select location select
Data Memory(1)
not used (3) (3)
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register file map detail see Figure 2-2. 2: Maintain clear for upward compatibility with future products. 3: Not implemented.
DS35008A-page 18
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
3.0 I/O PORTS
FIGURE 3-1:
Data bus WR Port
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Q VDD
D
CK
Q
P
Data Latch
3.1
PORTA and the TRISA Register
WR TRIS
D
Q
N
I/O pin(1)
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. On the PIC16C72A device, other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
CK
Q
VSS Analog input mode (72B only) TTL input buffer D
TRIS Latch
RD TRIS Q
EN RD PORT
To A/D Converter (72A only)
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-2:
Data bus WR PORT
BLOCK DIAGRAM OF RA4/T0CKI PIN
D Q Q
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
CK
N Data Latch
D Q Q
I/O pin(1)
VSS Schmitt Trigger input buffer
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as '0'.
WR TRIS
CK
STATUS, RP0 PORTA
TRIS Latch
BSF MOVLW
STATUS, RP0 0xCF
RD TRIS
Q D EN EN
MOVWF
TRISA
RD PORT TMR0 clock input
Note 1: Note 1: I/O pin has protection diodes to VSS only.
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 19
PIC16C62B/72A
TABLE 3-1
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 Buffer TTL TTL TTL TTL ST Function Input/output or analog input(1) Input/output or analog input(1) Input/output or analog input(1) Input/output or analog input(1) or VREF(1) Input/output or external clock input for Timer0 Output is open drain type
bit5 TTL Input/output or slave select input for synchronous serial port or analog input(1) RA5/SS/AN4 Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: On PIC16C72A only.
TABLE 3-2
Address Name 05h 05h 85h 9Fh PORTA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- -- -- Bit 6 -- -- -- -- Bit 5 RA5 RA5 Bit 4 RA4 RA4 Bit 3 RA3 RA3 Bit 2 RA2 RA2 Bit 1 RA1 RA1 Bit 0 RA0 RA0 Value on POR, BOR --0x 0000 --xx xxxx --11 1111 PCFG0 ---- -000 Value on all other resets --0u 0000 --uu uuuu --11 1111 ---- -000
(for PIC16C72A only)
PORTA
(for PIC16C62B only)
TRISA ADCON1(1)
PORTA Data Direction Register -- -- -- PCFG2 PCFG1
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: On PIC16C72A only.
DS35008A-page 20
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
STATUS, RP0 PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-4:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
FIGURE 3-3:
RBPU(2)
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2)
Data bus WR Port
Data bus WR Port
WR TRIS TTL Input Buffer
CK
TTL Input Buffer
ST Buffer
WR TRIS
CK
RD TRIS Q RD TRIS Q RD Port D EN From other RB7:RB4 pins RB0/INT Schmitt Trigger Buffer RD Port RB7:RB6 in serial programming mode Set RBIF RD Port
Latch D EN Q1
Q
D RD Port EN Q3
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 21
PIC16C62B/72A
TABLE 3-3
Name RB0/INT
PORTB FUNCTIONS
Bit# bit0 Buffer TTL/ST(1) Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4
Address 06h 86h 81h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name PORTB TRISB OPTION_ REG Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on: POR, BOR xxxx xxxx 1111 1111 PSA PS2 PS1 PS0 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
PORTB Data Direction Register RBPU INTEDG T0CS T0SE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS35008A-page 22
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
3.3 PORTC and the TRISC Register FIGURE 3-5:
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin. PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT
D CK Q
0 1
Q
VDD P
Data Latch WR TRIS
D CK Q Q
I/O pin(1) N VSS
TRIS Latch Schmitt Trigger
Q D EN
RD TRIS Peripheral OE(3) RD PORT Peripheral input
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTC
; ; ; ; ; ; ; ; ; ; ; Select Bank 0 Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs
STATUS, RP0 PORTC
BSF MOVLW
STATUS, RP0 0xCF
Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.
MOVWF
TRISC
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 23
PIC16C62B/72A
TABLE 3-5
Name RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input Input/output port pin or Timer1 oscillator input Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output Input/output port pin Input/output port pin
Legend: ST = Schmitt Trigger input
TABLE 3-6
Address Name 07h 87h PORTC TRISC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR, BOR xxxx xxxx 1111 1111 Value on all other resets uuuu uuuu 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS35008A-page 24
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: · · · · · · 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h Additional information on external clock requirements is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
4.2
Prescaler
Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler T0SE 3 PS2, PS1, PS0 T0CS PSA Set interrupt flag bit T0IF on overflow PSout Sync with Internal clocks (2 cycle delay) TMR0 PSout 8
RA4/T0CKI pin
0
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 25
PIC16C62B/72A
4.2.1 SWITCHING PRESCALER ASSIGNMENT
4.3
Timer0 Interrupt
The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicro Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1
Address 01h 0Bh,8Bh 81h 85h
REGISTERS ASSOCIATED WITH TIMER0
Name TMR0 INTCON OPTION_REG TRISA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR xxxx xxxx INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 --11 1111 Value on all other resets uuuu uuuu 0000 000u 1111 1111 --11 1111
Timer0 module's register GIE PEIE T0IE T0CS
RBPU INTEDG -- --
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS35008A-page 26
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
5.0 TIMER1 MODULE
5.1 Timer1 Operation
The Timer1 module timer/counter has the following features: · 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) · Readable and writable (Both registers) · Internal or external clock select · Interrupt on overflow from FFFFh to 0000h · Reset from CCP module trigger Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Figure 5-2 is a simplified block diagram of the Timer1 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023). Timer1 can operate in one of these modes: · As a timer · As a synchronous counter · As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal "reset input". This reset can be generated by the CCP module (Section 7.0).
FIGURE 5-1:
U-0 -- bit7
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON bit0
bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 2:
bit 0:
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 27
PIC16C62B/72A
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
Set flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON on/off T1SYNC
Synchronized clock input
T1OSC RC0/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Synchronize det
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS35008A-page 28
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
5.2 Timer1 Oscillator 5.3 Timer1 Interrupt
A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
Resetting Timer1 using a CCP Trigger Output
TABLE 5-1
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq 32 kHz 100 kHz 200 kHz C1 33 pF 15 pF 15 pF C2 33 pF 15 pF 15 pF
If the CCP module is configured in compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
Osc Type LP
These values are for design guidance only.
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.
Crystals Tested: 32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
TABLE 5-2
Address Name 0Bh,8Bh 0Ch 8Ch 0Eh 0Fh 10h Legend:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR, BOR Value on all other resets
INTCON PIR1 PIE1 TMR1L TMR1H T1CON
0000 000x 0000 000u -0-- 0000 -0-- 0000 -0-- 0000 -0-- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 29
PIC16C62B/72A
NOTES:
DS35008A-page 30
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
6.0
· · · · · · ·
TIMER2 MODULE
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (Both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift
Timer2 has a control register, shown in Figure 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 6-2 is a simplified block diagram of the Timer2 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
FIGURE 6-1:
U-0 -- bit7
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6-3:
Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale · · · 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2:
bit 1-0:
FIGURE 6-2:
Sets flag bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2 output (1) Reset Prescaler 1:1, 1:4, 1:16 2
TMR2 reg Comparator
FOSC/4
Postscaler 1:1 to 1:16 4
EQ
PR2 reg
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 31
PIC16C62B/72A
6.1 Timer2 Operation 6.2 Timer2 Interrupt
Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: · a write to the TMR2 register · a write to the T2CON register · any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset.
6.3
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock.
TABLE 6-1
Address 0Bh,8Bh 0Ch 8Ch 11h 12h 92h Legend: Name INTCON PIR1 PIE1 TMR2 T2CON PR2
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR, BOR Value on all other resets
0000 000x 0000 000u -00- 0000 0000 0000 -0-- 0000 0000 0000 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
DS35008A-page 32
Preliminary
© 1998 Microchip Technology Inc.
PIC16C62B/72A
7.0 CAPTURE/COMPARE/PWM (CCP) MODULE(S)
Additional information on the CCP module is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes. Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.
TABLE 7-1
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
FIGURE 7-1:
U-0 -- bit7 U-0 --
CCP1CON REGISTER (ADDRESS 17h)
R/W-0 CCP1X R/W-0 R/W-0 CCP1Y CCP1M3 R/W-0 CCP1M2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode
© 1998 Microchip Technology Inc.
Preliminary
DS35008A-page 33
PIC16C62B/72A
7.1 Capture Mode
7.1.4 CCP PRESCALER In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: · · · · every falling edge every rising edge every 4th rising edge every 16th rising edge There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler