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For Europe model




SERVICE MANUAL Ver. 1

MODEL AVR-M330
AV SURROUND RECEIVER




For purposes of improvement, specifications and
design are subject to change without notice.



Please use this service manual with referring to ,
the operating instructions without fail.



Some illustrations using in this service manual are
slightly different from the actual set.




TOKYO, JAPAN


X0225V.01 DE/CDM 0410
AVR-M330




SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.

LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.




2
AVR-M330


BLOCK DIAGRAM




SYSTEM
LC72723M
CONNECTOR

1
2


DIGITAL
(OPTICAL) TU




1

2 STANDBY
TRANS




AC 230V
50Hz


MAIN
TRANS


TU




ANALOG




VKK -31V




F.I.PAC




SEL

MULTI-B

MULTI-A




B.P.F.

FAN

THERMAL FAN Drive
SEL

MULTI-B

MULTI-A
Protector Protector




3
AVR-M330


LEVEL DIAGRAM




B. P. F.




29dB
8




(70Hz)




7




7




4
AVR-M330


SEMICONDUCTORS/
Only major semiconductors are shown, general semiconductors etc. are omitted to list.




CS49400 (IC12)




AUDATA7, XMT958B, GPIO31
AUDATA3, XMT958A




SD_ADDR3 ,EXTA3
SD_ADDR2 ,EXTA2
SD_ADDR1 ,EXTA1
SD_ADDR0, EXTA0
SDATAN0, GPIO24
SDATAN1, GPIO25
SDATAN2, GPIO26
SDATAN3, GPIO27
AUDATA4, GPIO28




AUDATA5, GPIO29
AUDATA6, GPIO30




LRCLKN, GPIO23
SCLKN, GPIO22
HDATA3, GPIO3


HDATA4, GPIO4




HDATA5, GPIO5
HDATA6, GPIO6
HDATA7, GPIO7
AUDATA2




SD_CAS
SD_RAS
LRCLK0




LRCLK1
SCLK0




SCLK1
MCLK
VDD2




VDD1
VSS2




VSS1


NC1
NC2




NC3
NC4
105




100




90




85




75
95




80
AUDATA1 SD_ADDR10, EXTA10
AUDATA0 110 SD_BA, EXTA19
CMPCLK, FSCLKN2 70 VDDSD1




ce
HDATA2, GPIO2 VSSSD1
VSS3 SD_CS
VDD3 SD_ADDR4, EXTA4
HDATA1, GPIO1 115 SD_ADDR5, EXTA5
HDATA0, GPIO0 65 SD_ADDR6, EXTA6
CMPREQ, FLRCLKN2 SD_CLK_EN
CMPDAT, FSDATAN2 SD_ADDR7, EXTA7
FLRCLKN1 SD_ADDR8, EXTA8
WR, DS, GPIO10 120 SD_CLK_IN
RD, R/W, GPIO11 60 SD_ADDR9, EXTA9
PLLVSS SD_CLK_OUT
an FILT2 VDDSD2
FILT1 VSSSD2
PLLVDD 125 SD_DATA8, EXTA11
XTALO 55 SD_DATA9, EXTA12
CLKIN, XTALI SD_DATA10, EXTA13
CLKSEL SD_DATA11, EXTA14
CS, GPIO9 SD_DATA12, EXTA15
A0, GPIO13 130 VDDSD3
FSDATAN1 50 VSSSD3
VDD4 SD_DATA13, EXTA16
VSS4 NC5
FSCLKN1, STCCLK2 SD_DATA14, EXTA17
SCS 135 SD_DATA15, EXTA18
dv
SCDIN 45 SD_DQM1
VSS5 SD_DATA7, EXTD7
VDD5 SD_DATA6, EXTD6
A1, GPIO12 VDDSD4
SCDOUT, SCDIO 140 VSSSD4
HINBSY, GPIO8 40 SD_DATA5, EXTD5
SCCLK SD_DQM0
UHS2, CS_OUT, GPIO17 SD_DATA4, EXTD4
RESET 144 SD_DATA3, EXTD3
35
25




30
20
10




15
5
1
UHS0, GPIO18
UHS1, GPIO19
INTREQ, ABOOT
FA1, FSCDIN
GPIO20
FAO, FSCCLK
FHS2, FSCDIO, FSCDOUT
GPIO21
FDAT7
VDD6
VSS6
FHS0, FWR, FDS
FHS1, FRD, FR/W
FDAT6
FCS
FINTREQ
FDBCK
FDAT5
FDAT4
VDD7
VSS7
FDAT3
FDBDA
FDAT2
DBDA
DBCK
FDAT1
TEST
FDAT0
NV_WE, GPIO16
NV_OE, GPIO15
NV_CS, GPIO14
SD_WE
SD_DATA0, EXTD0
SD_DATA1, EXTD1
SD_DATA2, EXTD2




Block Diagram


SAI 0
Serial External Memory
SAI 1
SAI 3
Audio Interface
SAI 2 Interface
Compressed
Audio
DSP C
Internal Bus




Digital DAO 0
Interface Frame Audio
Programmable 32-Bit DSP
Shifter
Shared Memory




Digital Multistandard Interface DAO 1
Audio Audio Decoder
Interface DSP DSP GPIO and I/O
Input
RAM ROM Controller
DSP AB Buffer
RAM
PLL Clock Parallel or Serial Parallel or Serial
Debug Port
Manager Host Interface Host Interface




5
AVR-M330

ST92F124V1 (IC16)




P7.6/AIN14/WKUP12
P7.5/AIN13/WKUP11
P7.4/AIN12/WKUP3
P7.7/AIN15/7/WKUP13




P7.0/AIN8/CK_AF
P7.3/AIN11
P7.2/AIN10
P7.1/AIN9



P8.7/AIN7
P8.6/AIN6
P8.5/AIN5
P9.1/TDO

HW0SW1

OSCOUT
P9.5/A19
P9.4/A18
P9.3/A17
P9.2/A16

P9.0/RDI

RESET

OSCIN




AVDD
AVSS
VDD
VSS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

A20/P9.6 1 75 P8.4/AIN4
A21/P9.7 2 74 P8.3/AIN3
WAIT/WKUP5/P5.0 3 73 P8.2/AIN2
WKUP6/WDOUT/P5.1 4 72 P8.1/AIN1/WKUP15
SIN/WKUP2/P5.2 5 71 P8.0/AIN0/WKUP14
WDIN/SOUT/P5.3 6 70 NC
TXCLK/CLKOUT/P5.4 7 69 P6.5/WKUP10/INTCLK
RXCLK/WKUP7/P5.5 8 68 P6.4/NMI
DCD/WKUP8/P5.6 9 67 P6.3/INT3/INT5
WKUP9/RTS/P5.7 10 66 P6.2/INT2/INT4/DS2
ICAPA1/P4.0 11 65 P6.1/INT6/RW
CLOCK2/P4.1 12 64 P6.0/INT0/INT1/CLOCK2/8
OCMPA1/P4.2 13 63 P0.7/A7/D7
VSS 14 62 VDD
VDD 15 61 VSS
ICAPB1/OCMPB1/P4.3 16 60 P0.6/A6/D6
EXTCLK1/WKUP4/P4.4 17 59 P0.5/A5/D5
EXTRG/STOUT/P4.5 18 58 P0.4/A4/D4
SDA/P4.6 19 57 P0.3/A3/D3
WKUP1/SCL/P4.7 20 56 P0.2/A2/D2
ICAPB0/P3.1 21 55 P0.1/A1/D1
ICAPA0/OCMPA0/P3.2 22 54 P0.0/A0/D0
OCMPB0/P3.3 23 53 AS
EXTCLK0/SS/P3.4 24 52 DS
MISO/P3.5 25 51 P1.7/A15

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
VREG




VREG




NC
SCK/WKUP0/P3.7

RW


TOUTA0/P2.2
TOUTB0/P2.3


TOUTA1/P2.6
TOUTB1/P2.7



*VTEST
MOSI/P3.6




A10/P1.2
A11/P1.3


A12/P1.4
A13/P1.5
A14/P1.6
TINPA0/P2.0
TINPB0/P2.1


TINPA1/P2.4
TINPB1/P2.5




A8/P1.0
A9/P1.1


WKUP6
VDD




Block Diagram
FLASH
128 Kbytes Ext. MEM.
ADDRESS A[7:0]
DATA D[7:0]
Port0
E3 TM
1 Kbyte
Ext. MEM.
ADDRESS A[10:8]
MEMORY BUS




RAM Ports A[21:11]
4 Kbytes 1,9
P0[7:0]
AS
DS P1[7:3]
RW Fully P1[2:0]
256 bytes
WAIT Prog. P2[7:0]
Register File
NMI I/Os P3[7:4]
DS2 P3[3:1]
8/16 bits
RW P4[7:4]
CPU
P4[3:0]
Interrupt P5[7:0]
INT[6:0] Management P6[5:2,0]
WKUP[15:0] P6.1
ST9 CORE P7[7:0]
OSCIN P8[7:0]
OSCOUT P9[7:0]
RESET RCCU SDA
CLOCK2/8 I2C BUS SCL
INTCLK
CK_AF
STOUT ST. TIMER WATCHDOG WDOUT
REGISTER BUS




HW0SW1
ICAPA0
OCMPA0 MISO
ICAPB0 EF TIMER 0 MOSI
OCMPB0 SPI SCK
EXTCLK0 SS
AVDD
ICAPA1 AVSS
OCMPA1 AIN[15:8]
ICAPB1 EF TIMER 1 ADC
AIN[7:0]
OCMPB1 EXTRG
EXTCLK1
TXCLK
TINPA0 RXCLK
TOUTA0 SIN
MF TIMER 0
TINPB0 SCI M DCD
TOUTB0 SOUT
TINPA1 CLKOUT
TOUTA1 RTS
MF TIMER 1
TINPB1
TOUTB1 RDI
SCI A
TDO
VOLTAGE
VREG
REGULATOR



The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8 and Port9.


6
AVR-M330


AK4588VQ (IC11)




Block Diagram




7
AVR-M330

AK4588VQ Terminal Function




8
AVR-M330




9
AVR-M330




Note : Please make no digital input pins except an internal bias pins into floating.




10
AVR-M330

NJW1157 (IC73)


PIN FUNCTION











1R 6<0%2/ )81&7,21 1R 6<0%2/ )81&7,21
/287 /FK RXWSXW /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
5287 5FK RXWSXW 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
&287 &FK RXWSXW /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
/6287 /6FK RXWSXW 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
56287 56FK RXWSXW /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
/%287 /%FK RXWSXW 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
5%287 5%FK RXWSXW /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
6:287 6:FK RXWSXW 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
'&B/ /FK %DVV ILOWHU '& FXW FDSDFLWRU RXWSXW WHUPLQDO /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
'&B/ /FK %DVV ILOWHU '& FXW FDSDFLWRU LQSXW WHUPLQDO 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
),/B%/ /FK %DVV ILOWHU WHUPLQDO /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
),/B7/ /FK 7UHEOH ILOWHU WHUPLQDO 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
'&B5 5FK %DVV ILOWHU '& FXW FDSDFLWRU RXWSXW WHUPLQDO /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
'&B5 5FK %DVV ILOWHU '& FXW FDSDFLWRU LQSXW WHUPLQDO 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
),/B%5 5FK %DVV ILOWHU WHUPLQDO /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
),/B75 5FK 7UHEOH ILOWHU WHUPLQDO 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
1& 1R &RQQHFW /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
1& 1R &RQQHFW 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
9 3RZHU VXSSO\ YROWDJH LQSXW /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
9 3RZHU VXSSO\ YROWDJH LQSXW 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
5(&B$/ ³,QSXW VHOHFWRU´ /FK 5(& RXWSXW $ /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
5(&B$5 ³,QSXW VHOHFWRU´ 5FK 5(& RXWSXW $ 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
5(&B$/ ³,QSXW VHOHFWRU´ /FK 5(& RXWSXW $ /,1 ³,QSXW VHOHFWRU´ /FK LQSXW
5(&B$5 ³,QSXW VHOHFWRU´ 5FK 5(& RXWSXW $ 5,1 ³,QSXW VHOHFWRU´ 5FK LQSXW
5(&B$/ ³,QSXW VHOHFWRU´ /FK 5(& RXWSXW $ 1& 1R &RQQHFW
5(&B$5 ³,QSXW VHOHFWRU´ 5FK 5(& RXWSXW $ '*1' 'LJLWDO *URXQG
5(&B%/ ³,QSXW VHOHFWRU´ /FK 5(& RXWSXW % '$7$ &RQWURO GDWD VLJQDO LQSXW
5(&B%5 ³,QSXW VHOHFWRU´ 5FK 5(& RXWSXW % &/2&. &ORFN VLJQDO LQSXW
5(&B%/ ³,QSXW VHOHFWRU´ /FK 5(& RXWSXW % /$7&+ /DWFK VLJQDO LQSXW
5(&B%5 ³,QSXW VHOHFWRU´ 5FK 5(& RXWSXW % /$,1 0XOWLFKDQQHO /FK LQSXW $
'&&$3B/ 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU 5$,1 0XOWLFKDQQHO 5FK LQSXW $
'&&$3B5 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU &$,1 0XOWLFKDQQHO &FK LQSXW $
'&&$3B& 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU /6$,1 0XOWLFKDQQHO /6FK LQSXW $
*1' *URXQG 56$,1 0XOWLFKDQQHO 56FK LQSXW $
*1' *URXQG /%$,1 0XOWLFKDQQHO /%FK LQSXW $
'&&$3B/6 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU 5%$,1 0XOWLFKDQQHO 5%FK LQSXW $
'&&$3B56 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU 6:$,1 0XOWLFKDQQHO 6:FK LQSXW $
'&&$3B/% 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU /%,1 0XOWLFKDQQHO /FK LQSXW %
'&&$3B5% 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU 5%,1 0XOWLFKDQQHO 5FK LQSXW %
'&&$3B6: 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU &%,1 0XOWLFKDQQHO &FK LQSXW %
'&/B287 ³,QSXW VHOHFWRU´ /FK RXWSXW /6%,1 0XOWLFKDQQHO /6FK LQSXW %
'&/B,1 ³0XOWLFKDQQHO VHOHFWRU´ /FK LQSXW 56%,1 0XOWLFKDQQHO 56FK LQSXW %
'&5B287 ³,QSXW VHOHFWRU´ 5FK RXWSXW /%%,1 0XOWLFKDQQHO /%FK LQSXW %
'&5B,1 ³0XOWLFKDQQHO VHOHFWRU´ 5FK LQSXW 5%%,1 0XOWLFKDQQHO 5%FK LQSXW %
)/ ³,QSXW VHOHFWRU JDLQ FRQWURO´ /FK QRLQYHUWHG RXWSXW 6:%,1 0XOWLFKDQQHO 6:FK LQSXW %
)/ ³,QSXW VHOHFWRU JDLQ FRQWURO´ /FK LQYHUWHG RXWSXW *1' *URXQG
)5 ³,QSXW VHOHFWRU JDLQ FRQWURO´ 5FK QRLQYHUWHG RXWSXW *1' *URXQG
)5 ³,QSXW VHOHFWRU JDLQ FRQWURO´ 5FK LQYHUWHG RXWSXW 966287 ,QWHUQDO 'LJLWDO 3RZHU 6XSSO\ 2XWSXW
9''287 ,QWHUQDO 'LJLWDO 3RZHU 6XSSO\ 2XWSXW 9''287 ,QWHUQDO 'LJLWDO 3RZHU 6XSSO\ 2XWSXW
966287 ,QWHUQDO 'LJLWDO 3RZHU 6XSSO\ 2XWSXW 7&&$3 6ZLWFKLQJ QRLVH UHMHFWLRQ FDSDFLWRU




11
AVR-M330

Block Diagram




5(&%5


5(&%5
5(&$5


5(&$5


5(&$5
5(&%/
5(&$/


5(&$/


5(&$/




5(&%/
/$,1
0XOWL&KDQQHO ,QSXW $

5$,1
&$,1
/6$,1
56$,1
/%$,1 9