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IRAUDAMP5
120W x 2 Channel Class D Audio Power Amplifier Using the IRS2092S and IRF6645
By Jun Honda, Manuel Rodríguez and Jorge Cerezo
Fig 1
CAUTION: International Rectifier suggests the following guidelines for safe operation and handling of IRAUDAMP5 Demo Board; · Always wear safety glasses whenever operating Demo Board · Avoid personal contact with exposed metal surfaces when operating Demo Board · Turn off Demo Board when placing or removing measurement probes
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IRAUDAMP5 REV 3.0
Table of Contents
Page
Introduction............................................................................. Specifications........................................................................... Connection Setup...................................................................... Test Procedure........................................................................... Typical Performance................................................................... Theory of Operation................................................................... IRS2092S System Overview......................................................... Selectable Dead Time.................................................................. Protection Features..................................................................... Efficiency................................................................................ Thermal Considerations............................................................... Click and Pop Noise Control.......................................................... Startup and Shutdown Sequencing................................................... PSRR..................................................................................... Bus Pumping............................................................................. Input/Output Signal and Volume Control........................................... Self Oscillating PWM Modulator..................................................... Switches and Indicators................................................................ Frequency Lock, Synchronization Feature.......................................... Schematics............................................................................... Bill of Materials........................................................................ PCB specifications...................................................................... Assembly Drawings..................................................................... END....................................................................................... 2 3 4 5 5-9 9-10 10-11 11-12 12-17 17-18 18 18-19 19-21 21-22 22-23 23-26 27 28 29 32-36 37-40 42 43-49 49
Hardware................................................................................. 41
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Introduction
The IRAUDAMP5 reference design is a two-channel, 120W half-bridge Class D audio power amplifier. This reference design demonstrates how to use the IRS2092S Class D audio controller and gate driver IC, implement protection circuits, and design an optimum PCB layout using the IRF6645 DirectFET MOSFETs. The resulting design requires no heatsink for normal operation (one-eighth of continuous rated power). The reference design provides all the required housekeeping power supplies for ease of use. The two-channel design is scalable for power and the number of channels.
Applications
AV receivers Home theater systems Mini component stereos Powered speakers Sub-woofers Musical Instrument amplifiers Automotive after market amplifiers
Features
Output Power: Residual Noise: Distortion: Efficiency: Multiple Protection Features: 120W x 2 channels, Total Harmonic Distortion (THD+N) = 1%, 1 kHz 170µV, IHF-A weighted, AES-17 filter 0.005% THD+N @ 60W, 4 96% @ 120W, 4, single-channel driven, Class D stage Over-current protection (OCP), high side and low side Over-voltage protection (OVP), Under-voltage protection (UVP), high side and low side DC-protection (DCP), Over-temperature protection (OTP) Self-oscillating half-bridge topology with optional clock synchronization
PWM Modulator:
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Specifications
General Test Conditions (unless otherwise noted) Supply Voltage ±35V Load Impedance 8-4 Self-Oscillating Frequency 400kHz Gain Setting 26dB Electrical Data IR Devices Used Notes / Conditions No input signal, Adjustable 1Vrms input yields rated power
Typical Notes / Conditions IRS2092S Audio Controller and Gate-Driver, IRF6645 DirectFET MOSFETs Modulator Self-oscillating, second order sigma-delta modulation, analog input Power Supply Range ± 25V to ±35V Bipolar power supply Output Power CH1-2: (1% THD+N) 120W 1kHz Output Power CH1-2: (10% THD+N) 170W 1kHz Rated Load Impedance 8-4 Resistive load Standby Supply Current ±100mA No input signal Total Idle Power Consumption 7W No input signal Channel Efficiency 96% Single-channel driven, 120W, Class D stage .
Audio Performance
THD+N, 1W THD+N, 10W THD+N, 60W THD+N, 100W Dynamic Range Residual Noise, 22Hz - 20kHzAES17 Damping Factor Channel Separation Frequency Response : 20Hz-20kHz : 20Hz-35kHz
*Before
Demodulator
0.009% 0.003% 0.003% 0.008% 101dB 170µV 2000 95dB 85dB 75dB N/A
Class D Output
0.01% 0.004% 0.005% 0.010% 101dB 170µV 170 90dB 80dB 65dB ±1dB ±3dB
Notes / Conditions
1kHz, Single-channel driven A-weighted, AES-17 filter, Single-channel operation Self-oscillating 400kHz 1kHz, relative to 4 load 100Hz 1kHz 10kHz 1W, 4 - 8 Load
Thermal Performance
Idling 2ch x 15W (1/8 rated power) 2ch x 120W (Rated power) Physical Specifications Dimensions
Typical
TC =30°C TPCB=37°C TC =54°C TPCB=67°C TC =80°C TPCB=106°C 5.8"(L) x 5.2"(W)
Notes / Conditions
No signal input, TA=25°C Continuous, TA=25°C At OTP shutdown @ 150 sec, TA=25°C
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Note: Class D Specifications are typical *Before demodulator refers to audio performance measurements of the Class D output power stage only, with preamp and output filter bypassed this means performance measured before the low pass filter.
Connection Setup
35V, 5A DC supply 35V, 5A DC supply
250W, Non-inductive Resistors
4 Ohm
J3 G J7 TP1 TP2
4 Ohm
J4
CH1 Output
LED
CH2 Output
S1 J9
Protection
J6
J5
J8 S3 Volume
Normal
CH1 Input
CH2 Input
S2 R113
Audio Signal Generator
Typical Test Setup
Fig 2 Connector Description
CH1 IN CH2 IN POWER CH1 OUT CH2 OUT EXT CLK DCP OUT J6 J5 J7 J3 J4 J8 J9 Analog input for CH1 Analog input for CH2 Positive and negative supply (+B / -B) Output for CH1 Output for CH2 External clock sync DC protection relay output
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Test Procedures
1. Connect 4, 250W load to both output connectors, J3 and J4 and Audio Precision analyzer (AP). 2. Connect Audio Signal Generator to J6 and J5 for CH1 and CH2 respectively (AP). 3. Connect a dual power supply to J7, pre-adjusted to ±35V, as shown in Figure 2 above. 4. Set switch S3 to middle position (self oscillating). 5. Set volume level knob R108 fully counter-clockwise (minimum volume). 6. Turn on the power supply. Note: always apply or remove the ±35V at the same time. 7. Orange LED (Protection) should turn on almost immediately and turn off after about 3s. 8. Green LED (Normal) then turns on after orange LED is extinguished and should stay on. 9. One second after the green LED turns on; the two blue LEDS on the Daughter Board should turn on and stay on for each channel, indicating that a PWM signal is present at LO 10. With an Oscilloscope, monitor switching waveform at test points TP1 and TP2 of CH1 and CH2 on Daughter Board. 11. If necessary, adjust the self-oscillating switching frequency of AUDAMP5 to 400KHz ±5kHz using potentiometer R29P. For IRAUDAMP5, the self-oscillating switching frequency is pre-calibrated to 400KHz. To modify the AUDAMP5 frequency, change the values of potentiometers R21 and R22 for CH1 and CH2 respectively. 12. Quiescent current for the positive supply should be 70mA ±10mA at +35V. 13. Quiescent current for the negative supply should be 100mA ±10mA at 35V. 14. Push S1 switch, (Trip and Reset push-button) to restart the sequence of LEDs indicators, which should be the same as noted above in steps 6-9.
Audio Tests:
15. Apply 1 V RMS at 1KHz from the Audio Signal Generator 16. Turn control volume up (R108 clock-wise) to obtain an output reading of 100Watts for all subsequent tests as shown on the Audio Precision graphs below, where measurements are across J3 and J2 with an AES-17 Filter
Typical Performance
The tests below were performed under the following conditions: ±B supply = ±35V, load impedance = 4 resistive load, 1kHz audio signal, Self oscillator @ 400kHz and internal volume-control set to give required output with 1Vrms input signal, with AES-17 Filter, unless otherwise noted.
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THD versus Power:
10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 W 10 20 50 100 200
Blue, CH1 - 4 Ohm Red, CH2 - 4 Ohm
Figure 18. Total Harmonics Distortion + Noise (THD+N) versus power output
Fig 3
+4 +3 +2 +1 -0 -1 d B r A -2 -3 -4 -5 -6 -7 -8 -9 -10 20 50 100 200 500 1k 2k Hz 5k 10k 20k 50k 100k 200k
Frequency Response:
Red Blue CH1 - 4 Ohm, 2V Output CH1 - 8 Ohm, 2V Output
Frequency Characteristics vs. Load Impedance Fig 4
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. THD versus Frequency:
100 50 10 5 1
%
0.1 0.05 0.01
0.001 0.0005 0.0001 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Pink Blue Cyan Green
CH1, 1W Output CH1, 10W Output CH1, 50W Output CH1, 100W Output
THD+N Ratio vs. Frequency
Fig 5
.
Frequency Spectrum :
+0 -10 -20 -30 -40 d B V -50 -60 -70 -80 -90 -100 -110 10 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red Blue
CH1, 1V, 1kHz, Self Oscillator @ 400kHz CH2, 1V, 1kHz, Self Oscillator @ 400kHz
Fig 6
Frequency Spectrum
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.
Floor Noise:
+20 +0 -20 -40 d B V -60 -80 -100 -120 -140 10 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red Blue
CH1 - ACD, No signal, Self Oscillator @ 400kHz CH2 - ACD, No signal, Self Oscillator @ 400kHz
Fig 7 Residual Noise (ACD)
. Channel Separation:
+0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red Blue
CH1 CH2, 60W CH2 CH1, 60W
Fig 8 Channel Separation vs. Frequency
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. Clipping Characteristics:
Red Trace: Total Distortion + Noise Voltage Green Trace: Output Voltage
60W / 4, 1kHz, THD+N=0.008%
174W / 4, 1kHz, THD+N=10%
Measured Output and Distortion Waveforms
Fig 9
.
IRAUDAMP5 Theory of Operation
Referring to Fig 10 below, the input error amplifier of the IRS2092S forms a front-end secondorder integrator with C1, C21, C23 and R21. This integrator also receives a rectangular feedback waveform from R31, R33 and C17 into the summing node at IN- from the Class D power stage switching node (connection of DirectFET Q3 and DirectFET Q4). The quadratic oscillatory waveform of the switch node serves as a powered carrier signal from which the audio is recovered at the speaker load through a single-stage LC filter. The modulated signal is created by the fluctuations of the analog input signal at R13 that shifts the average value of this quadratic waveform through the gain relationship between R13 and R31 + R33 so that the duty cycle varies according to the instantaneous signal level of the analog input signal at R13. R33 and C17 act to immunize the rectangular waveform from possible narrow noise spikes that may be created by parasitic impedances on the power output stage. The IRS2092S input integrator then processes the signal from the summing node to create the required triangle wave amplitude at the COMP output. The triangle wave then is converted to Pulse Width Modulation, or PWM, signals that are internally level-shifted Down and Up to the negative and positive supply rails. The level shifted PWM signals are called LO for low output, and HO for high output, and have opposite polarity. A programmable amount of dead time is added between the gate signals to avoid cross conduction between the power MOSFETs. The IRS2092S drives two IRF6645 DirectFET MOSFETs in the power stage to provide the amplified PWM waveform. The amplified analog output is reconstructed by demodulating the powered PWM at the switch node, called VS. (Show as VS on the schematic)This is done by means of the LC low-pass filter (LPF) formed by L1 and C23A, which filters out the Class D switching carrier signal, leaving the audio powered output at the speaker load. A single stage output filter can be used with switching
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frequencies of 400 kHz and greater; lower switching frequencies may require additional filter components. +VCC is referenced to B and provides the supply voltage to the LO gate driver. D6 and C5 form a bootstrap supply that provides a floating voltage to the HO gate driver. The VAA and VSS input supplies are derived from +B and -B via R52 and C18, and R50 and C12, respectively. Thus, a fully functional Class D PWM amplifier plus driver circuit is realized in an SO16 package with just a few small components.
.
R31 C17 R33 R52 C18
+B
0V
C21 R21 C23
+VAA IRS2092S VB HO Modulator and Shift level Integrator
C5 R32
DirectFet
Q3 IRF6645
0V
COMP
C1
0V
INPUT
R13
INGND
LP Filter
D6 L1 Q4 IRF6645 C23A
0V
+
VS VCC LO
.
R30
.
DirectFet
C3
-VSS
C12 R50
COM
+VCC
-B
.
Simplified Block Diagram of IRAUDAMP5 Class D Amplifier
Fig 10
System overview
IRS2092S Gate Driver IC
The IRAUDAMP5 uses the IRS2092S, a high-voltage (up to 200V), high-speed power MOSFET PWM generator and gate driver with internal dead-time and protection functions specifically designed for Class D audio amplifier applications. These functions include OCP and UVP. Bidirectional current protection for both the high-side and low-side MOSFETs are internal to the IRS2092S, and the trip levels for both MOSFETs can be set independently. In this design, the dead time can be selected for optimized performance by minimizing dead time while preventing shoot-through. As a result, there is no gate-timing adjustment on the board. Selectable dead time through the DT pin voltage is an easy and reliable function which requires only two external resistors, R11 and R9 as shown on Fig11 below.
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.
+B
VAA GND IN-
CSH VB HO VS VCC LO COM DT
R13 R5
.
AUDIO_INPUT
COMP
.
Feedback
CSD VSS
R19
CH1
VREF CSLO
+VCC -B
R18
IRS2092S
.
System-level View of Class D Controller and Gate Driver IRS2092S
Fig 11
Selectable Dead-Time
The dead time of the IRS2092S is based on the voltage applied to the DT pin. (Fig 12) An internal comparator determines the programmed dead time by comparing the voltage at the DT pin with internal reference voltages. An internal resistive voltage divider based on different ratios of VCC negates the need for a precise reference voltage and sets threshold voltages for each of the four programmable settings. Shown in the table below are component values for programmable dead times between 15 and 45 ns. To avoid drift from the input bias current of the DT pin, a bias current of greater than 0.5mA is suggested for the external resistor divider circuit. Resistors with up to 5% tolerance can be used.
Selectable Dead-Time
Dead-time mode DT1 DT2 DT3 DT4 Dead time ~15ns ~25ns ~35ns ~45ns
Operational Mode
R5 3.3k 5.6k 8.2k open
R13 8.2k 4.7k 3.3k <10k
DT voltage 0.71 x Vcc 0.46 x Vcc 0.29 x Vcc 0 x Vcc
Default
Default
15nS 25nS Dead-time 35nS 45nS Shutdown
0.23xVcc 0.36xVcc 0.57xVcc 0.89xVcc Vcc
VDT
Fig 12 Dead-time Settings vs. VDT Voltage
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Over-Current Protection (OCP)
In the IRAUDAMP5, the IRS2092S gate driver accomplishes OCP internally, a feature discussed in greater detail in the "Protection" section.
Offset Null (DC Offset)
The IRAUDAMP5 is designed such that no output-offset nullification is required, thanks to closed loop operation. DC offsets are tested to be less than ±20mV.
Protection
The IRAUDAMP5 has a number of protection circuits to safeguard the system and speaker as shown in the figure 13 below, which fall into one of two categories internal faults and external faults, distinguished by the manner in which a fault condition is treated. Internal faults are only relevant to the particular channel, while external faults affect the whole board. For internal faults, only the offending channel is stopped. The channel will hiccup until the fault is cleared. For external faults, the whole board is stopped using the shutdown sequencing described earlier. In this case, the system will also hiccup until the fault is cleared, at which time it will restart according to the startup sequencing described earlier.
. CSH
R41 R43 D1
+B
BAV19 R25
+ 1.2V
VB HO
R32 10R
Q3 IRF6645
LP Filter . CSD VS CSD VCC OCSET LO
R30 10R Q4 IRF6645
.
OCREF 5.1V OCREF Green Yellow LEDs
D4 R19
R18
-B
OCSET Trip RESET
COM
UVP
OVP OTP
DCP
To next channel
Functional Block Diagram of Protection Circuit Implementation
Fig 13
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Internal Faults
OCP and OTP are considered internal faults, which will only shutdown the particular channel by pulling low the relevant CSD pin. The channel will shutdown for about one-half a second and will hiccup until the fault is cleared.
Over-Temperature Protection (OTP, Fig 14)
A separate PTC resistor is placed in close proximity to the high-side IRF6645 DirectFET MOSFET for each of the amplifier channels. If the resistor temperature rises above 100°C, the OTP is activated. The OTP protection will only shutdown the relevant channel by pulling the CSD pin low and will recover once the temperature at the PTC has dropped sufficiently. This temperature protection limit yields a PCB temperature at the MOSFET of about 100°C, which is limited by the PCB material and not by the operating range of the MOSFET.
Rp1 is thermally connected with Q3 -B R31 100K Q7 OTP1 -B R47 100K R48 1K Rp1 100C 2 2 Q3 3 3
C28 47nF
IRF6645
OTP CH1
Fig 14
Over-Current Protection (OCP)
The OCP internal to the IRS2092S shuts down the IC if an OCP is sensed in either of the output MOSFETs. For a complete description of the OCP circuitry, please refer to the IRS2092S datasheet. Here is a brief description:
Low-Side Current Sensing
Fig 15 shows the low side MOSFET as is protected from an overload condition by measuring the low side MOSFET drain-to-source voltage during the low side MOSFET on state, and will shut down the switching operation if the load current exceeds a preset trip level. The voltage setting on the OCSET pin programs the threshold for low-side over-current sensing. Thus, if the VS voltage during low-side conduction is higher than the OCSET voltage, the IRS2092S will trip and CSD goes down. It is recommended to use VREF to supply a reference voltage to a resistive divider (R19 and R18 for CH1) to generate a voltage to OCSET; this gives better variability against VCC fluctuations. For IRAUDAMP5, the low-side over-current trip level is set to 0.65V. For IRF6645 DirectFET MOSFETs with a nominal RDS-ON of 28mOhms at 25°C, this results in a ~23A maximum trip level. Since the RDS-ON is a function of temperature, the trip level is reduced to ~15A at 100°C.
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. CSH
R41 R43 D1
+B
BAV19 R25
+ 1.2V
VB HO
R32 10R
Q3 IRF6645
LP Filter . CSD VS CSD VCC OCSET LO
R30 10R Q4 IRF6645
.
OCREF 5.1V OCREF
R19
R18
-B
OCSET
COM
Simplified Functional Block Diagram of High-Side and Low-Side Current Sensing (CH1) Fig 15
High-Side Current Sensing (Fig15)
The high-side MOSFET is protected from an overload condition and will shutdown the switching operation if the load current exceeds a preset trip level. High-side over-current sensing monitors detect an overload condition by measuring the high side MOSFET's drain-to-source voltage (VDS) through the CSH and VS pins. The CSH pin detects the drain voltage with reference to the VS pin, which is the source of the high-side MOSFET. In contrast to the low-side current sensing, the threshold of CSH pin to engage OC protection is internally fixed at 1.2V. An external resistive divider R43+R25 and R41 (for Ch1) can be used to program a higher threshold. An additional external reverse blocking diode (D1 for CH1) is required to block high voltage feeding into the CSH pin during low-side conduction. By subtracting a forward voltage drop of 0.6V at D1, the minimum threshold which can be set for the high-side is 0.6V across the drain-to-source. For IRAUDAMP5, the high-side over-current trip level is set to 0.6V across the high-side MOSFET. For the IRF6645 MOSFETs with a nominal RDS-ON of 28 mOhms at 25°C, this results in a ~21A maximum trip level. Since the RDS-ON is a function of temperature, the trip level is reduced to ~14A at 100°C. For a complete description of calculating and designing the over-current trip limits, please refer to the IRS2092S datasheet. Positive and Negative Side of Short Circuit, versus switching output shut down: The plots below show the speed that the IRS2092S responds to a short circuit condition. Notice that the envelope behind the sine wave output is actually the switching frequency ripple. Bus pumping naturally affects this topology.
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Positive and Negative side of Short Circuit, versus switching output shut down:
CSD pin VS pin Load current CSD pin VS pin Load current VS pin Load current VS pin Load current CSD pin CSD pin
OCP Waveforms Showing Load Current and Switch Node Voltage (VS) Fig 16
.
Short Circuit Response:
CSD pin VS pin VS pin
CSD pin
Load current
Load current
OCP Waveforms Showing CSD Trip and Hiccup Fig 17
External Faults
OVP, UVP and DCP are considered external faults. In the event that any external fault condition is detected, the shutdown circuit will disable the output for about three seconds, during which time the orange AUDAMP5 "Protection" LED will turn on. If the fault condition has not cleared, the protection circuit will hiccup until the fault is removed. Once the fault is cleared, the green "Normal" LED will turn on. There is no manual reset option.
Over-Voltage Protection (OVP Fig 18)
OVP will shut down the amplifier if the bus voltage between GND and -B exceeds 40V. The threshold is determined by the voltage sum of the Zener diode Z105, R140, and VBE of Q109. As a result, it protects the board from hazardous bus pumping at very low audio signal frequencies by shutting down the amplifier. OVP will automatically reset after three seconds. Since the +B and B supplies are assumed to be symmetrical (bus pumping, although asymmetrical in time,
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IRAUDAMP5 REV 3.0
will pump the bus symmetrically in voltage level over a complete audio frequency cycle), it is sufficient to sense only one of the two supply voltages for OVP. It is therefore up to the user to ensure that the power supplies are symmetrical. Q109 Over-Voltage Protection (OVP)
SD
R139 D105 1N4148 OT DCP 47k OT
R140 10k Z105 39V R144 10k R149 47K
Z107 18V R145 47K
UVP
Q109 MMBT5551
Q110 MMBT5551 R141 47k
OVP
R146 47K
S1 SW-PB C119 0.1uF, 50V
-B
Trip and restart
Q110 Under-Voltage Protection (UVP) Fig 18
Under-Voltage Protection (UVP, Fig18)
UVP will shutdown the amplifier if the bus voltage between GND and -B falls below 20V. The threshold is determined by the voltage sum of the Zener diode Z107, R145 and VBE of Q110. As with OVP, UVP will automatically reset after three seconds, and only one of the two supply voltages needs to be monitored.
Speaker DC-Voltage Protection (DCP, Fig 19)
DCP is provided to protect against DC current flowing into the speakers. This abnormal condition is rare and is likely caused when the power amplifier fails and one of the high-side or low-side IRF6645 DirectFET MOSFETs remain in the ON state. DCP is activated if either of the outputs has more than ±4V DC offset (typical). Under this fault condition, it is normally required to shutdown the feeding power supplies. Since these are external to the reference design board, an isolated relay P1 is provided for further systematic evaluation of DC-voltage protection. This condition is transmitted to the power supply controller through connector J9, whose pins are shorted during a fault condition.
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+B R125 10K
Q106
MMBT5401
R126 100K Q105
MMBT5551
To DCP
DCP
R130 47K
DC protection
R131 47K
R128 6.8k
Q104
R124 10k
C116 100uF, 16V R123 1K R122 47k R121 47k
From CH1 Output
CH1 O
MMBT5401 R129 6.8k R127 6.8k -B
From CH2 Output
CH2 O
Fig 19
Efficiency
Figs 20 demonstrate that IRAUDAM5 is highly efficient, due to two main factors: a.) DirectFETs offer low RDS(ON) and very low input capacitance, and b). The PWM operates as Pulse Density Modulation.
100.0% 90.0% 80.0% 70.0% 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0 20 40 60 80 100 120 140 160 180 Output Power (W)
Efficiency vs. Output Power, 4 Single Channel Driven, ±B supply = ±35V, 1kHz Audio Signal
Power Stage Efficiency (%)
Fig20
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Thermal Considerations The daughter-board design can handle one-eighth of the continuous rated power, which is generally considered to be a normal operating condition for safety standards. Without the addition of a heatsink or forced air-cooling, the daughter board cannot handle fully rated continuous power. A thermal image of the daughter board is as shown in Fig 21 below.
Thermal Distribution
67°C 54°C 67°C 54°C
Thermal image of Daughter-Voard Two-Channel x 1/8th Rated Power (15W) in Operation, TC = 54°C at Steady State ±B supply = ±35V, 4 Load, 1kHz audio signal, Temp ambient = 25°C
Fig 21
Click and POP noise:
One of the most important aspects of any audio amplifier is the startup and shutdown procedures. Typically, transients occurring during these intervals can result in audible pop- or click-noise from the output speaker. Traditionally, these transients have been kept away from the speaker through the use of a series relay that connects the speaker to the audio amplifier only after the startup transients have passed and disconnects the speaker prior to shutting down the amplifier. Thanks to the click and pop elimination function in the IRS2092S, IRAUDAMP5 does not use any series relay to disconnect the speaker from the audible transient noise.
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Click-Noise Reduction Circuit (Solid-State Shunt)
IRS2092S controller is relatively quiet with respect to class AB, but for additional click or POP noise reduction you may add a shunt circuit that further attenuates click or pop transients during turn on sequencing. The circuit is not populated on the present demo board; for implementation details, please refer to the IRAUDAMP4 user's manual at http://www.irf.com/technicalinfo/refdesigns/audiokits.html
Startup and Shutdown Sequencing (Fig 22)
The IRAUDAMP5 sequencing is achieved through the charging and discharging of the CStart capacitor C117. Along with the charging and discharging of the CSD voltage (C10 on daughter board for CH1) of the IRS2092S, this is all that is required for complete sequencing. The startup and shutdown timing diagrams are show in Figure 22A below:
CStart Ref2
CStart Ref1
CStart Ref1
CStart Ref2
CSD= 2/3VDD CSD CStart
Time External trip Reset
CHx_O
SP MUTE
Audio MUTE Music shutdown Class D shutdown Class D startup Music startup
Click Noise Reduction Sequencing at Trip and Reset Fig 22A For startup sequencing, the control power supplies start up at different intervals depending on the ±B supplies. As the +/-B supplies reach +5 volts and -5 volts respectively, the +/-5V control supplies for the analog input start charging. Once +B reaches ~16V, VCC charges. Once B reaches -20V, the UVP is released and CSD and CStart (C117) start charging. The Class D amplifier is now operational, but the preamp output remains muted until CStart reaches Ref2. At this point, normal operation begins. The entire process takes less than three seconds.
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For Shutdown (Fig22B) sequencing is initiated once UVP is activated. As long as the supplies do not discharge too quickly, the shutdown sequence can be completed before the IRS2092S trips UVP. Once UVP is activated, CSD and CStart are discharged at different rates. In this case, threshold Ref2 is reached first and the preamp audio output is muted. It is then possible to shutdown the Class D stage (CSD reaches two-thirds VDD). This process takes less than 200ms.
+B
CStart Ref2
CStart Ref1 CSD= 2/3VDD
CSD CStart
+5V Time -5V
Vcc -B UVP@-20V CHx_O SP MUTE
Audio MUTE Class D shutdown Music shutdown
Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing Fig22B
For any external fault condition (OTP, OVP, UVP or DCP see "Protection") that does not lead to power supply shutdown, the system will trip in a similar manner as described above. Once the fault is cleared, the system will reset (similar sequence as startup).
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IRAUDAMP5 REV 3.0
Page 20 of 49
Power Supplies
The IRAUDAMP5 has all the necessary housekeeping power supplies onboard and only requires a pair of symmetric power supplies ranging from ±25V to ±35V (+B, GND, -B) for operation. The internally-generated housekeeping power supplies include a ±5V supply for analog signal processing (preamp etc.), while a +12V supply (VCC), referenced to B, is included to supply the low and high side Class D gate-driver stages. For the externally-applied power, a regulated power supply is preferable for performance measurements, but is not always necessary. The bus capacitors, C31 and C32 on the motherboard, along with high-frequency bypass-caps C14, C15; C32 and C33 on the daughter board, address the high-frequency ripple current that results from switching action. In designs involving unregulated power supplies, the designer should place a set of external bus capacitors having enough capacitance to handle the audio-ripple current. Overall regulation and output voltage ripple for the power supply design are not critical when using the IRAUDAMP5 Class D amplifier as the power supply rejection ratio (PSRR) of the IRAUDAMP5 is excellent, as shown on Figure 23 below.
Power Supply Rejection Ratio Green: IRAUDAMP5, Cyan: VAA/VSS are fed by Vbus Fig 23
Bus Pumping (Fig24)
Since the IRAUDAMP5 is a half-bridge configuration, bus pumping does occur. Under normal operation during the first half of the cycle, energy flows from one supply through the load and into the other supply, thus causing a voltage imbalance by pumping up the bus voltage of the receiving power supply. In the second half of the cycle, this condition is reversed, resulting in bus pumping of the other supply. These conditions worsen bus pumping: 1. Lower frequencies (bus-pumping duration is longer per half cycle) 2. Higher power output voltage and/or lower load impedance (more energy transfers between supplies)
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IRAUDAMP5 REV 3.0
Page 21 of 49
3. Smaller bus capacitors (the same energy will cause a larger voltage increase) The IRAUDAMP5 has protection features that will shut down the switching operation if the bus voltage becomes too high (>40V) or too low (<20V). One of the easiest countermeasures is to drive both of the channels in a stereo configuration out of phase so that one channel consumes the energy flow from the other and does not return it to the power supply. Bus voltage detection is only done on the B supply, as the effect of the bus pumping on the supplies is assumed to be symmetrical in amplitude (although opposite in phase) with the +B supply.
Bus Pumping Figure: Cyan = Positive Rail voltage (+B) Green = Speaker Output Pink = Negative Rail voltage (-B) Fig 24
Input Signal
A proper input signal is an analog signal below 20 kHz, up to ±3.5V peak, having a source impedance of less than 600 ohms. A 30-60 kHz input signal can cause LC resonance in the output LPF, resulting in an abnormally large amount of reactive current flowing through the switching stage (especially at 8 ohms or higher impedance towards open load), and causing OCP activation. The IRAUDAMP5 has an RC network (Fig25), or Zobel network (R47 and C25 [CH1]), to dampen the resonance and protect the board in such an event, but is not thermally rated to handle continuous supersonic frequencies. These supersonic input frequencies therefore should be avoided. Separate mono RCA connectors provide input to each of the two channels. Although both channels share a common ground, it is necessary to connect each channel separately to limit noise and crosstalk between channels.
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IRAUDAMP5 REV 3.0
Page 22 of 49
. LP Filter . 0V
L1 C23A
0V .
C25
R47
.
Zobel Filter and Output filter demodulator Fig 25
Output
Both outputs for the IRAUDAMP5 are single-ended and therefore have terminals labeled (+) and (-), with the (-) terminal connected to power ground. Each channel is optimized for a 4-Ohm speaker load for a maximum output power (120W), but is capable of operating with higher load impedances (at reduced power), at which point the frequency response will have a small peak at the corner frequency of the output LC low pass filter. The IRAUDAMP5 is stable with capacitive-loading; however, it should be noted that the frequency response degrades with heavy capacitive loading of more than 0.1µF.
Gain Setting / Volume Control
The IRAUDAMP5 has an internal volume control (potentiometer R108 labeled, "VOLUME", Fig 26) for gain adjustment. Gain settings for both channels are tracked and controlled by the volume control IC (U_2), setting the gain from the microcontroller IC (U_1). The maximum volume setting (clockwise rotation) corresponds to a total gain of +37.9dB (78.8V/V). The total gain is a product of the power-stage gain, which is constant (+23.2dB), and the input-stage gain that is directly-controlled by the volume adjustment. The volume range is about 100dB, with minimum volume setting to mute the system with an overall gain of less than -60dB. For best performance in testing, the internal volume control should be set to a gain of 21.9V/V, such that 1Vrms input will result in rated output power (120W into 4), allowing for a >11dB overdrive.
+5V +5V C107 4.7uF, 16V R108 CT2265-ND 8 7 6 C108 10nF, 50V 5 VSS VR0 VR1 CLK U_2 VDD CS SDATA SIMUL 1 2 CS 3 SDATAI 4 +5V 10uF, 50V SCLK R10 R7 R8 47R CS 47R SDATAI AOUTL 10R C1 VD+ DGRD SCLK 47R MUTE R11 47R VAVA+ AOUTR -5V +5V Level OUT 2 R2 R4 100R 100K R9 AGNDL Level OUT 1 4.7uF, 16V U_1 ZCEN AINL R3 100R 100K R1 C109
Audio in
J5
3310S06S
Control Volume
SDATAOAGNDR MUTE CS3310 AINR
Audio in
J6
Fig 26 Digital volume Control
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IRAUDAMP5 REV 3.0
Page 23 of 49
Bridged Output
The IRAUDAMP5 is not intended for a bridge-tied-load, or BTL configuration. However, BTL operation can be achieved by feeding out-of-phase audio input signals to the two input channels as shown in the figure 27 below. In BTL operation, minimum load impedance is 8 Ohms and rated power is 240W non-clipping. The installed clamping diodes D5 D8 are required for BTL operation, since reactive energy flowing from one output to the other during clipping can force the output voltage beyond the voltage supply rails if not clamped.
.
R31 C17 R33
+VAA
+B
C21 R21 C23
COMP
C1
IRS2092S
VB HO
0V
Q3 IRF6645
.
INPUT
+
VS
L1
CH1
10k 1%
GND
VCC LO
Integrator .
R32 C18 R34
Q4 IRF6645
D7
D5
R13
IN-
LP Filter Modulator and Shift level
+B
-B
10k 1%
COM
1
-B
. +VAA
+B
C22
C24
COMP
C2
IRS2092S
VB HO
0V
Q6 IRF6645
.
+
VS
L2
CH2
GND
VCC LO
Integrator
Q5 IRF6645
D8
D6
R14
IN-
LP Filter Modulator and Shift level
+B
-B
COM
-B
Bridged configuration Fig 27
Output Filter Design, Preamplifier and Performance
The audio performance of IRAUDAMP5 depends on a number of different factors. The section entitled, "Typical Performance" presents performance measurements based on the overall system, including the preamp and output filter. While the preamp and output filter are not part of the Class D power stage, they have a significant effect on the overall performance. Output filter Since the output filter is not included in the control loop of the IRAUDAMP5, the reference design cannot compensate for performance deterioration due to the output filter. Therefore, it is important to understand what characteristics are preferable when designing the output filter:
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IRAUDAMP5 REV 3.0
Page 24 of 49
1) The DC resistance of the inductor should be minimized to 20 mOhms or less. 2) The linearity of the output inductor and capacitor should be high with respect to load current and voltage. Preamplifier (Fig 28) The preamp allows partial gain of the input signal, and controls the volume in the IRAUDAMP5. The preamp itself will add distortion and noise to the input signal, resulting in a gain through the Class D output stage and appearing at the output. Even a few micro-volts of noise can add significantly to the output noise of the overall amplifier.
R13
C5 10uF, 50V
IN-1
Feedback
R31 R33 1K C17 150pF, 500V OC -5V
Audio in
R1 J5 U_? 1 2 3 4 5 6 7 8 100K AINL AGNDL 16 15 14 13 12 11 10 9 R4 100R R72 OPEN R3 100R R71 OPEN
3.3K R55 0.0
CH1 IN
4 5 6 J1A 1 2 3
47k 1%
ZCEN CS
+5V
SDATAI AOUTL VD+ DGRD SCLK VAVA+ AOUTR
C2 10uF, 50V R5 4.7R 4.7R R6 C3 10uF, 50V C6 10uF, 50V -5V -5V +5V
IRS2092S MODULE
J1B 7 8 9 10 11 12 VCC SD
SDATAOAGNDR MUTE CS3310 R2 100K J6 AINR
R14 3.3K
CH2 IN
IN-2
R56 0.0
VCC
Feedback
R32 47k 1% R34 1K
Audio in
Preamplifier Fig28
It is possible to evaluate the performance without the preamp and volume control, by moving resistors R13 and R14 to R71 and R72, respectively. This effectively bypasses the preamp and connects the RCA inputs directly to the Class D power stage input. Improving the selection of preamp and/or output filter components will improve the overall system performance, approaching that of the stand-alone Class D power stage. In the "Typical Performance" section, only limited data for the stand-alone Class D power stage is given. For example, Fig 20 below shows the results for THD+N vs. Output Power are provided, utilizing a range of different inductors. By changing the inductor and repeating this test, a designer can quickly evaluate a particular inductor.
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IRAUDAMP5 REV 3.0
Page 25 of 49
I IRAUDAMP5 can be used as output inductors evaluation tool
100 TTTTTTT 10
1
%
0.1
0.01
0.001
0.0001 100m 200m 500m 1 2 5 W 10 20 50 100 200
Results of THD+N vs. Output Power with Different Output Inductors Fig 29
Self-Oscillating PWM Modulator
The IRAUDAMP5 Class D audio power amplifier features a self-oscillating type PWM modulator for the lowest component count, highest performance and robust design. This topology represents an analog version of a second-order sigma-delta modulation having a Class D switching stage inside the loop. The benefit of the sigma-delta modulation, in comparison to the carrier-signal based modulation, is that all the error in the audible frequency range is shifted to the inaudible upper-frequency range by nature of its operation. Also, sigma-delta modulation allows a designer to apply a sufficient amount of correction. The self-oscillating frequency (Fig 30) is determined by the total delay time inside the control loop of the system. The delay of the logic circuits, the IRS2092S gate-driver propagation delay, the IRF6645 switching speed, the time-constant of front-end integrator (e.g.R13, R33, R31, R21, P1, C17, C21, C23 and C1 for CH1) and variations in the supply voltages are critical factors of the self-oscillating frequency. Under nominal conditions, the switching-frequency is around 400kHz with no audio input signal and a +/-35V supply.
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IRAUDAMP5 REV 3.0
Page 26 of 49
.
R31 C17 P1 R33
C21
R21 C23
+B
COMP
C1
IRS2092S
VB HO
0V
Q3 IRF6645
. INPUT
R13
INCH1 GND
LP Filter + Modulator and Shift level Integrator VS VCC LO COM
Q4 IRF6645
.
-B
Self Oscillating determined components Fig 30
Adjustments of Self-Oscillating Frequency
The PWM switching frequency in this type of self-oscillating switching scheme greatly impacts the audio performance, both in absolute frequency and frequency relative to the other channels. In absolute terms, at higher frequencies distortion due to switching-time becomes significant, while at lower frequencies, the bandwidth of the amplifier suffers. In relative terms, interference between channels is most significant if the relative frequency difference is within the audible range. Normally, when adjusting the self-oscillating frequency of the different channels, it is best to either match the frequencies accurately, or have them separated by at least 25kHz. With the installed components, it is possible to change the self-oscillating frequency from about 300kHz up to 450kHz, as shown on Fig 30
Switches and Indicators
There are four different indicators on the reference design as shown in the figure 31 below: 1. An orange LED, signifying a fault / shutdown condition when lit. 2. A green LED on the motherboard, signifying conditions are normal and no fault condition is present. 3. A blue LED on the daughter board module, signifying there are HO pulses for CH1 4. A blue LED on the daughter board module signifying there are HO pulses for CH2 There are three switches on the reference design: 1. Switch S1 is a trip and reset push-button. Pushing this button has the same effect as a fault condition. The circuit will restart about three seconds after the shutdown button is released. 2. Switch S2 is an internal clock-sync frequency selector. This feature allows the designer to modify the switching frequency in order to avoid AM radio interference. With S3 set to INT, the two settings "H" and "L" will modify the internal clock frequency by about
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IRAUDAMP5 REV 3.0
Page 27 of 49
20 kHz to 40 kHz, either higher "H" or lower "L." The actual internal frequency is set by potentiometer R113 - "INT FREQ." 3. Switch S3 is an oscillator selector. This three-position switch is selectable for internal self oscillator (middle position "SELF"), or either internal ("INT") or external ("EXT") clock synchronization.
SW-3WAY_A-B S3A I E S S2 1 2
SW R109 1K D103 1N4148 C110 1nF, 50V R110 100k R111 10K
SW_H-L C112 1200pF, 50V
100pF, 50V C111
+5V R120 100R
R112 820R Q103 C113 100pF, 50V
U_3 1A 1Y VCC 6A 6Y 5A 5Y 4A 4Y C114 10nF, 50V
MMBT5551
R113 5K POT
2A 2Y 3A 3Y
SW-3WAY_A-B S3B SW S E I
R114 100R J8 BNC A24497
R116 47R CLK CLK
GND 74HC14 +5V
R118 1k R119 1k PROTECTION NORMAL
R115 47R
EXT. CLK
MUTE
MUTE R117 47R
LED, Switches and Sync frequencies Fig 31
Switching Frequency Lock / Synchronization Feature
For single-channel operation, the use of the self-oscillating switching scheme will yield the best audio performance. The self-oscillating frequency, however, changes with the duty ratio. This varying frequency can interfere with AM radio broadcasts, where a constant-switching frequency with its harmonics shifted away from the AM carrier frequency is preferred. In addition to AM broadcasts, multiple channels can also reduce audio performance at low power, and can lead to increased residual noise. Clock frequency locking/synchronization can address these unwanted characteristics. Please note that the switching frequency lock / synchronization feature is not possible for all frequencies and duty ratios, and operates within a limited frequency and duty-ratio range around the self-oscillating frequency (Figure 32 below).
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IRAUDAMP5 REV 3.0
Page 28 of 49
600
Locking range
500
Suggested clock frequency for maximum locking range Self-oscillating frequency
Operating Frequency (kHz)
400
300
200
Self-oscillating frequency
100
0 10%
20%
30%
40%
50%
60%
70%
80%
90%
Duty Cycle
Typical Lock Frequency Range vs. PWM Duty Ratio (Self-oscillating frequency set to 400 kHz with no input)
Fig 32
The output power range, for which frequency-locking is successful, depends on what the locking frequency is with respect to the self-oscillating frequency. As illustrated in Figure 33, the locking frequency is lowered (from 450kHz to 400kHz to 350kHz and then 300kHz) as the output power range (where locking is achieved) is extended. Once locking is lost, however, the audio performance degrades, but the increase in THD seems independent from the clock frequency. Therefore, a 300 kHz clock frequency is recommended, as shown on Fig 34 It is possible to improve the THD performance by increasing the corner frequency of the high pass filter (HPF) (R17 and C15 for Ch1 Fig 33) that is used to inject the clock signal, as shown in Figure 33 below. This drop in THD, however, comes at the cost of reducing the locking range. Resistor values of up to 100 kOhms and capacitor values down to 10pF may be used.
.
+VAA
+B
C15
SYNC
R22 22k R13
COMP
IRS2092S
VB HO
0V
Q3 IRF6645
33pF
0V .
INPUT
INCH1 GND
LP Filter + Modulator and Shift level Integrator VS VCC LO
Q4 IRF6645
.
COM
-B
Switching Frequency Lock / Synchronization Feature
Fig 33
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IRAUDAMP5 REV 3.0
Page 29 of 49
In IRAUDAMP5, this switching frequency lock/synchronization feature (Fig 31 and Fig 33) is achieved with either an internal or external clock input (selectable through S3). If an internal (INT) clock is selected, an internally-generated clock signal is used, adjusted by setting potentiometer R113 "INT FREQ." If external (EXT) clock signal is selected, a 0-5V squarewave (~50% duty ratio) logic signal must be applied to BNC connector J17.
10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 W 10 20 50 100 200
Red Pink Blue Cyan
CH1, = Self Oscillator @ 400kHz CH1, = Sync Oscillator @ 400kHz CH1, = Sync Oscillator @ 450kHz CH1, = Sync Oscillator @ 350kHz
THD+N Ratio vs. Output Power for Different Switching Frequency Lock/Synchronization Conditions
Fig 34
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IRAUDAMP5 REV 3.0
Page 30 of 49
Class D, Daughter Board IRS2092S Module CH1 Schematic
-B 100K Q7 100C R31 Rp1 Rp1 is thermally connected with Q3
+35V Bus
OTP1 R40 33k -B R43 U1 D1 1 R21 P1 1K 1k 2 GND 22uF 3 INR32 4 COMP D6 5 CSD R26 4.7R VSS VREF OCSET IRS2092S 3.3K R13 8.2K 10uF DT 9 R5 COM 10 R9 10R C3 R12 4.7K DS1 LO 11 VCC VCC 10R R30 7 8 R50 open R17 1.2k 6 C12 R19 8.2k 3.3uF 12 2 2 D-FET2 IRF6645 1 3 3 R37 1R VS 13 HO 1nF,250V C30 10nF 1nF C21 10uF C23 1nF,250V C1 14 10R 1 3 3 VB 2 2 D-FET1 IRF6645 15 VAA 10k C5 R25 10K CSH 16 0.0 R41 100K 1K R47 R48 R52 open C18
OTP CH1
C28 47nF
CH1
+5V Audio Gnd 1
3.3uF
+35V Bus +B
R7
VAA
10R
C32 0.1uF,100V C17 0.1uF C14 0.1uF,100V TP1 CH1 O J2A
GND1
J1A
IN-1
OC
R46
VSS
1 2 3
4 5 6
3.01k VAA
CH1
+B
A26568-ND
SD C10
D4
R1
SD
9 10 11 12
13 14 15 16 A26570-ND
100R R3
VSS
-5V
10R
CH1 Output to LPF1 -35V Bus -B
-35V Bus
Drawing by: M.Rodriguez [email protected]
.
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IRAUDAMP5 REV 3.0
Page 31 of 49
Class D, Daughter Board IRS2092S Module CH2 Schematic
OTP1 -B 100K MMBT5401 Q2 OTP2 R39 33k -B R44 U2 1 VAA GND 22uF 3 1nF,250V 1nF 4 COMP D5 5 CSD R23 4.7R VSS VREF OCSET IRS2092S 3.3K R14 8.2K DT 9 R6 COM 10 R10 10R C4 10uF LO 11 VCC 6 R20 7 8 R49 open D7 R18 1.2k 8.2k 12 VCC 10R R28 2 2 D-FET4 IRF6645 1 3 3 R38 1R VS 13 C22 10uF C24 1nF,1250V C2 R27 INHO 14 10R 1 3 3 2 2 VB 15 10k C6 R29 10K D-FET3 IRF6645 CSH R22 P2 1K 1k SD 16 0.0 R42 D2 C33 0.1uF,100V C13 0.1uF C15 0.1uF,100V TP2 CH2 O J2B 100K 1K R33 R24 C9 47nF 100C R11 100K OTP2 R35 Rp2 Rp2 is thermally connected with Q5
OC
Q1
R34 100K
+35V Bus
R36 10K C19 -B 3.3uF C29 47nF R51 open
MMBT5551
OTP CH2
+35V Bus +B
VAA
R8
+5V Audio Gnd 2 2
10R
J1B
PWM2 VSS
7 8 9 C31 10nF,50V
10 11 12
VCC
A26568-ND IN-2
3.01k R53
CH2
-B
SD
D3
R2
SD
C11 C16 3.3uF
1 2 3 4
5 6 7 8 A26570-ND
VSS
100R R4
-5V
10R
CH2 Output to LPF2 -35V Bus -B
R45 4.7K DS2
CH2
-35V Bus
Drawing by: M.Rodriguez [email protected]
.
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IRAUDAMP5 REV 3.0
Page 32 of 49
Rp1 is thermally connected with Q3 -B 100K MMBT5401DICT-ND Q7 OTP1 R40 33k -B R43 U1 1 R21 P1 1K 2 GND 22uF 3 INCOMP D6 5 CSD R26 2 2 4.7R 10R 1 3 3 R30 7 VREF OCSET IRS2092S C3 10uF Rp2 is thermally connected with Q5 OC -B R34 100K R11 100K OTP1 OTP2 R35 100K MMBT5401 Q2 OTP2 R39 33k R44 U2 1 VAA GND INCOMP CSD VSS 7 8 R49 open D7 R18 1.2k VREF OCSET IRS2092S HO VS VCC LO COM DT 14 13 12 11 10 9 R6 3.3K R14 R10 10R C4 8.2K R45 4.7K DS2 D5 R23 4.7R 6 C16 R20 8.2k 3.3uF VCC 10R R28 VB 15 CSH R22 P2 1K 2 3 1nF,250V 1nF 4 5 C22 10uF C24 1nF,1250V C2 1k SD R53 3.01k C31 10nF,50V 16 D2 10k C6 22uF C33 0.1uF,100V 2 2 R29 10K 10R R27 D-FET3 IRF6645 1 3 3 C13 0.1uF C15 0.1uF,100V TP2 CH2 O J2B 0.0 R42 -B R33 100K R24 1K Rp2 100C DS1 3.3K R13 8.2K 10R 4.7K DT 9 R5 R9 R12 COM 8 R50 open R17 1.2k 10 R37 1R VSS LO 11 VCC 6 R19 8.2k 12 VCC D-FET2 IRF6645 VS 13 3 3 R32 4 TP1 CH1 O J2A HO 1nF,250V C30 10nF R1 1nF C21 10uF C23 1nF,250V C1 14 10R 1 2 2 C17 0.1uF C14 0.1uF,100V VB 15 R25 10K D-FET1 IRF6645 10k C5 1k VAA C32 0.1uF,100V CSH 16 0.0 R41 D1 100K 1K R47 R48 C28 47nF 100C R31 Rp1
Class D, Daughter Board IRS2092S Module Schematic
+35V Bus
R52 open C18
OTP CH1
CH1
R7 VAA 10R GND1 IN-1 R46 3.01k VAA D4 4 5 6
+35V Bus +B
+5V
3.3uF
Audio Gnd 1
J1A 1 2 3
OC
VSS
CH1
+B
A26568-ND SD 100R R3 VSS 10R C12 3.3uF
SD -5V
C10
9 10 11 12
13 14 15 16 A26570-ND
CH1 Output to LPF1 -35V Bus -B
IR_Logo
-35V Bus
Q1
+35V Bus
R36 10K C19 -B 3.3uF C29 47nF R51 open
MMBT5551
OTP CH2
C9 47nF
+35V Bus +B
R8 VAA 10R VCC
+5V
J1B 10 11 12 IN-2
VSS GND2
7 8 9
Audio Gnd 2
SD -5V 10R 100R R4 C11 D3 R2
A26568-ND
CH2
-B D-FET4 IRF6645 1 3 3 1 2 3 4 2 2 R38 1R 5 6 7 8 A26570-ND
SD
-5V
CH2 Output to LPF2 -35V Bus -B
CH2
-35V Bus
10uF
Drawing by: M.Rodriguez [email protected]
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IRAUDAMP5 REV 3.0
Page 33 of 49
.
Class D, Mother Board Control Volume and Power Supplies Schematic
C19 R39 470 C15 R17 +B L1 22uH R33 1K C17 150pF, 500V OC -5V +B 0.47uF, 400V C23 R47 10, 1W -B C25 0.1uF, 400V J7 +B CH1 O D5 D7 R49 2.2k 22k R13 3.3K 47k 1% R55 0.0 C5 10uF, 50V IN-1 R31 33pF +5V 2.2uF,16V CLK 47R 74AHC1G04 U3 R27
CH1 Feedback
CH1 IN
CH1 OUT
C27 OPEN
J3 1 2
Control Volume
C109 R1 J5 4.7uF, 16V U_? 1 ZCEN CS SDATAI AOUTL VD+ DGRD SCLK SDATAOAGNDR MUTE CS3310 R2 3.3K VCC L2 R34 1K C18 150pF, 500V R18 22k CH2 O 22uH 100K R72 OPEN IN-2 R32 47k 1% R40 470 C16 33pF +5V J6 R4 100R R14 R56 0.0 AINR 9 C6 10uF, 50V -5V 10 7 8 9 10 11 12 VCC SD C3 10uF, 50V AOUTR 11 J1B R6 VA+ 12 +5V J2B -B 4.7R 4.7R VA13 -5V 14 C2 10uF, 50V R5 AGNDL 15 J1A J2A AINL R7 2 3 C1 10uF, 50V 6 47R 7 8 R11 47R 5 4 R8 10R 47R 47R 16 +5V 100K R3 100R 4 5 6 1 2 3 R71 OPEN
+5V
Audio in
9 10 11 12 13 14 15 16
+ CH1 -
+5V
C107 4.7uF, 16V
U_2
8
VSS
VDD
1
R108
7
VR0 R9
CS
2 CS
6
VR1
SDATA
3 SDATAI
C108 10nF, 50V
5
CLK
SIMUL
4
+5V
IRS2092S_ MODULE
Trace under J7
R58 100K
C33 OPEN
2 1 3 C31 1000uF,50V R57 100K
+35V Gnd -35V
3310S06S
SCLK R10
C34 OPEN 1 2 3 4 5 6 7 8
C32 1000uF,50V
MUTE
Chassis Gnd
-B +B D6 C24 0.47uF, 400V R48 10, 1W -B C26 0.1uF, 400V D8 R50 2.2k
CH2 IN
CH2 Feedback
Audio in
C20 2.2uF,16V CLK 47R 74AHC1G04 U4 R28
CH2 OUT
C28 OPEN
J4 1 2
Drawing by: M.Rodriguez [email protected]
+ CH2 -
VCC UVP
Z103
R107
15V
4.7K
+B
Q102
R106 47K R105
MMBT5401
10R
Q101 FX941 VCC HS1
U_6 MC78M12
VCC Power Supply
Heat Sink
+B Z101 R101 4.7V 47R, 1W ZM4732ADICT
+5V Power Supply
R102 47R, 1W C101 U_4 Vin GND MC78M05 Vout
+5V Z102 -B 4.7V R103 47R, 1W ZM4732ADICT D101 MA2YD2300 10uF, 50V C102 10uF, 50V
-5V Power Supply
R104 47R, 1W U_5 IN GND MC79M05 OUT
-5V
Vin
Vout
GND
D102 MA2YD2300 C103 10uF, 50V C104 10uF, 50V
Z104 24V C105 10uF, 50V
C106 10uF, 50V
-B
.
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IRAUDAMP5 REV 3.0
Page 34 of 49
Class D, Mother Board Clock and House Keeping Schematic
+B R143 SD 10K +5V R142 68k R139 R138 4.7k 1N4148 OT DCP R144 10k Q109 MMBT5551
UVP
SW-3WAY_A-B S3A Q111 MMBT5401 D105 OT 39V Z105 47k R149 47K CStart D107 C117 1N4148 100uF, 16V R148 10k D106 1N4148 Z106 18V R147 47k R140 10k Z107 18V R145 47K
I E S
SW
S2
1 2
R109 1K SP MUTE C112 1200pF, 50V +5V
SW_H-L
D103
1N4148 R120 100R VCC 6A 6Y 5A 5Y 4A 4Y 10nF, 50V Q108 +5V R118 1k NORMAL 47k R137 R119 1k PROTECTION D104 1N4148 -5V MUTE 47R R150 47k R151 47k Q112 MMBT5551 Z109 8.2V -5V MMBT5551 +5V R133 47k Q107 1 2 3 PVT412 R132 47k P1 6 5 4 J9 2 1 R129 6.8k R127 6.8k MMBT5401 MUTE R117 R130 47K DCP R131 47K R128 6.8k Q104
DC protection
100pF, 50V C111
C110 R112 820R U_3 1A 1Y R113 2A 2Y 3A 3Y R116 47R 74HC14 R134 10k MMBT5401 CLK CLK GND C114 R135 82k R126 100K Q105 10uF, 50V Z108 8.2V Q106 R125 10K C115 R136 68k +B 5K POT -B
R110
1nF, 50V
100k
R111 10K
Q103
Q110 MMBT5551 R141 47k
OVP
R146 47K
S1 C119 SW-PB 0.1uF, 50V
MMBT5551
C113
Trip and restart
SW-3WAY_A-B
100pF, 50V
S3B
SW
S E I
R114 100R
CH1 O
R124 10k
C116 100uF, 16V R123 1K
R122 47k
CH2 O R121 47k DC_PS
EXT. CLK
+B
Drawing by: M.Rodriguez [email protected]
MMBT5551
R115 47R
J8 BNC A24497
MMBT5551
-B
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IRAUDAMP5 REV 3.0
Page 35 of 49
IRAUDAMP5 Bill of Materials
Class D, Daughter Board:
Amp5_DB_2092_Rev 3.0_BOM
Footprint
805 TAN-A TAN-B 0805 TAN-B TAN-B 0805 1206 0805 0805 SOD-323 SOD-323 SMA SMA 805 CON EISA31 CON EISA31 CON_POWER CON_POWER SOT23-BCE
SOT23-BCE Direct Fet SJ 0805 0805 0805 MMBT5401-7 IRF6645 100R 10R 3.3K 2 4 2 11 2
Designator
1nF,250V,COG 10uF, 16V, Tan 10uF, 16V, Tan 47nF,50V, X7R 10uF, 16V, Tan 3.3uF, 16V, X7R 0.1uF,100V, X7R 0.1uF,100V, X7R open 10nF,50V, X7R BAV19WS-7-F 1N4148WS-7-F MURA120T3G ES1D LTST-C171TBKT CON EISA31 CON EISA31 CON_POWER CON_POWER MMBT5551 6 2 2 3 2 4 2 3 1 2 2 2 2 1 2 1 1 1 1 1
PartType
Quantity
VENDER
DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY
IR DIGI KEY DIGI KEY DIGI KEY
C1, C2, C21,C22,C23,C24 C3, C4 C5, C6 C9, C28, C29 C10, C11 C12, C16, C18, C19 C13, C17 C14, C15, C32, C33 C20 C30, C31 D1, D2 D3, D4 D5, D6 D7 DS1, DS2 J1A J1B J2A J2B Q1
Q2, Q7
D-FET1, D-FET2, D-FET3, D-FET4
R1, R2
R3,R4,R9,R10,R15,R16,R27,R28,R30,R32,R8
R5, R6
PART NO 445-2325-1-ND 495-2236-1-ND 399-3706-1-ND PCC1836CT-ND 399-3706-1-ND 445-1432-1-ND 399-3486-1-ND PCC2239CT-ND open PCC103BNCT-ND BAV19WS-FDICT-ND 1N4148WS-FDICT-ND MURA120T3GOSCT-ND ES1DFSCT-ND 160-1645-1-ND A26568-ND A26568-ND A26570-ND A26570-ND MMBT5551FSCT-ND MMBT5401DICT-ND IRF6645 P100ACT-ND P10ACT-ND P3.3KACT-ND
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IRAUDAMP5 REV 3.0
Page 36 of 49
R7 0805 0805 0805 0805 805 0805 0805 0805 0805 0805 0805 1206 805 ST-32 3mm SQ 805 SOIC16 IR Driver 3 3.01k 1k 100C 3 open 3 0 3 33K 3 1R 3 10K 5 4.7R 2 1k 2 1.2k 1K 2 8.2K 2 4.7K 2 DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY DIGI KEY MOUSER DIGI KEY DIGI KEY IR 100K 2 DIGI KEY
1206
10R
1
DIGI KEY
R11, R31, R33, R34, R35, R47
R12, R45
R13, R14,R19,R20
R24, R48
R7,R18
R21, R22
R23, R26
R25, R29,R36,R41, R42
R37, R38
R39, R40
R43, R44
R49, R50, R51, R52,
Rp1, Rp2
P10ECT-ND P100KACT-ND P4.7KACT-ND P8.2KACT-ND P1.0KACT-ND RHM1.2KARCT-ND P1.0KACT-ND P4.7ACT-ND P10KACT-ND P1.0ACT-ND RHM33KARCT-ND RHM0.0ARCT-ND open 594-2322-675-21007 ST32ETB102TR-ND RHM3.01KCCT-ND IRS2092S
P1,P2
R46,R53
U1, U2
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IRAUDAMP5 REV 3.0
Page 37 of 49
Class D Motherboard:
IRAUDAMP5 MOTHERBOARD BILL OF MATERIAL NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Designator C1, C5, C6, C101, C102, C103, C104, C105, C106, C115 C2, C3 C7, C8, C9, C10 C11, C12, C13, C14 C15, C16 C17, C18 C19, C20 C119 C23, C24 C25, C26 C27, C28, C29, C30, C40, C41, C42, C43, C44, C45, C46, C47 R29, R30, R55, R56, R60, R61, R62, R63, R64, R65, R66, R67, R71, R72 C31, C32 C33, C34, C48, C49 C107, C109 C108, C114 C110 C111, C113 C112 C116, C117 D103, D104, D105, D106, D107 D5, D6, D7, D8 D101, D102 HS1 J1A, J1B J2A, J2B J3, J4 J5, J6 J7 J8 J9 L1, L2 NORMAL P1 PROTECTION Q101 Q102, Q104, Q106, Q111 Q103, Q105, Q107, Q108, Q109, Q110, Q112 R1, R2, R57, R58, R110, R126 R3, R4, R114 R5, R6 R7, R8, R10, R11, R27, R28, R115, R116, R117 R9, R105 R13, R14 R17, R18 R106, R121, R122, R130, R131, R132, R133, R137, R139, R141, R145, R146, R147, R149, R150, R151 R152 R55, R56 R39, R40 R21, R22, R23, R24 R120 R29P, R30P R31, R32 R33, R34 R109, R118, R119, R123 R47, R48 R49, R50 R68, R69 # 10 2 4 4 2 2 2 1 2 2 12 14 2 4 2 2 1 2 1 2 5 4 2 1 2 2 2 2 1 1 1 2 1 1 1 1 4 7 6 3 2 9 2 2 2 16 1 2 2 4 1 2 2 2 4 2 2 2 Footprint RB2/5 RB2/5 open open 805 AXIAL0.19R 1206 1206 CAP MKP CAP MKPs 805 805 RB5/12_5 AXIAL0.1R 805 805 805 805 805 rb2/5 SOD-123 SMA SOD-123 Heat_S6in1 CON EISA-31 CON_POWER MKDS5/2-9.5 Blue RCA J HEADER3 BNC_RA CON ED1567 Inductor from Panasonic Led rb2/5 DIP-6 Led rb2/5 SOT89 SOT23-BCE SOT23-BCE 805 805 1206 805 805 805 805 805 805 805 805 open 1206 open 2512 1206 805 2512 1206 AXIAL-0.3 Part Type 10uF, 50V 2.2uF, 50V Part No 565-1106-ND 565-1103-ND Vender Digikey Digikey
33pF 150pF, 500V 2.2uF, 16V 0.1uF, 50V 0.47uF, 400V 0.1uF, 400V OPEN OPEN 1000uF,50V OPEN 4.7uF, 16V 10nF, 50V 1nF, 50V 100pF, 50V 1200pF, 50V 100uF, 16V
478-1281-1-ND 338-1052-ND PCC1931CT-ND PCC104BCT-ND 495-1315-ND 495-1311-ND
Digikey Digikey Digikey Digikey Digikey Digikey
565-1114-ND PCC2323CT-ND PCC103BNCT-ND PCC102CGCT-ND PCC101CGCT-ND 478-1372-1-ND 565-1037-ND
1N4148W-7-F
MURA120T3G MA2YD2300 HEAT SINK CON EISA31 CON_POWER 277-1022
1N4148W-FDICT-ND
MURA120T3GOSCT-ND MA2YD2300LCT-ND 294-1086-ND A26453-ND A26454-ND 277-1271-ND or 651-1714971
RCJ-055
277-1272 BNC ED1567 ETQA21ZA220 or ETQA17B220 404-1106-ND PVT412 404-1109-ND FX941
CP-1422-ND
277-1272-ND or 651-1714984 A32248-ND ED1567
Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey or Mouser Digikey Digikey or Mouser Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey
P13504-ND
160-1143-ND PVT412-ND 160-1140-ND FCX491CT-ND
MMBT5401-7-F
MMBT5551 100K 100R 4.7R 47R 10R 3.3K, 1% 22k 47k OPEN 0.0 Ohms 470R 100R 47K, 1% 1K 1K 10, 1W 2.2k OPEN
MMBT5401-FDICT-ND
MMBT5551-7DICT-ND P100KACT-ND P100ACT-ND P4.7ECT-ND P47ACT-ND P10ACT-ND P3.3KZCT-ND P22KACT-ND P47KACT-ND P0.0ACT-ND P470ACT-ND P100ECT-ND PT47KAFCT-ND P1.0KECT-ND P1.0KACT-ND PT10XCT P2.2KECT-ND -
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IRAUDAMP5 REV 3.0
Page 38 of 49
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
R101, R102, R103, R104 R107, R138 R108 R111, R124, R125, R134, R140, R143, R144, R148 R112 R113 R127, R128, R129 R135 R136, R142 S1 S2 S3 U1, U2 U3, U4 U7, U8 U9, U10 U_1 U_2 U_3 U_4 U_5 U_6 Z1, Z2, Z103 Z101, Z102 Z104 Z105 Z106, Z107 Z108, Z109 Volume Knob Thermalloy TO-220 mounting kit with screw 1/2" Standoffs 4-40 4-40 Nut No. 4 Lock Washer
4 2 1 8 1 1 3 1 2 1 1 1 2 2 2 2 1 1 1 1 1 1 3 2 1 1 2 2 1 3 5 5 5
2512 805 V_Control 805 805 POTs 1206 805 805 Switch SW-EG1908-ND SW-EG1944-ND open SOT25 MINI5 SO-8 SOIC16 N8A M14A TO-220 TO-220 TO-220 SOD-123 SMA SOD-123 SOD-123 SOD-123 SOD-123 Blue Knob Kit screw, ROHS Standoff 100 per bag 100 per bag
47R, 1W 4.7K CT2265 10K 820R 5K POT 6.8k 82k 68k SW-PB SW_H-L SW-3WAY 74AHC1G04 open open CS3310 3310S06S 74HC14
PT47XCT-ND P4.7KACT-ND CT2265-ND P10KACT-ND P820ACT-ND
Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey
3362H-502LF-ND
P6.8KECT-ND P82KACT-ND P68KACT-ND P8010S-ND EG1908-ND EG1944-ND 296-1089-1-ND open open 73C8016 or 72J5420 3310-IR01 296-1194-1-ND
Newark *Tachyonix Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Newark Newark Digikey Digikey Digikey
MC78M05CTG LM79M05CT LM78M12CT
15V 4.7V 24V 39V 18V 8.2V MC21060 AAVID 4880G
MC78M05CTGOS-ND LM79M05CT-ND LM78M12CT-ND
BZT52C15-FDICT-ND 1SMA5917BT3GOSCT-ND BZT52C24-FDICT-ND BZT52C39-13-FDICT-ND BZT52C18-FDICT-ND BZT52C8V2-FDICT-ND 10M7578 82K6096 8401K-ND H724-ND H729-ND
*Tachyonix Corporation, 14 Gonaka Jimokuji Jimokuji-cho, Ama-gun Aichi, JAPAN 490-1111 http://www.tachyonix.co.jp [email protected]
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IRAUDAMP5 REV 3.0
Page 39 of 49
IRAUDAMP5 Hardware
Voltage regulator mounting: Item Description 1 2 3 4
7
Insulator Thermalfilm Shoulder Washer Flat Washer #4 No. 4-40 UNC-2B Hex Nut No. 4-40 UNC-2A X 1/2 Long Phillips Pan Head Screw Lockwasher, No.4 Heatsink PCB
5 6
8
7 8
Item Description 1 2 3 4
7
Insulator Thermalfilm Shoulder Washer Flat Washer #4 No. 4-40 UNC-2B Hex Nut No. 4-40 UNC-2A X 1/2 Long Phillips Pan Head Screw Lockwasher, No.4 Heatsink PCB
5 6
8
7 8
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IRAUDAMP5 REV 3.0
Page 40 of 49
IRAUDAMP5 PCB Specifications
Figure 34. Motherboard and Daughter-board Layer Stack
Daughter board:
Material: Layer Stack: Dimensions: Solder Mask: Plating: Silkscreen: FR4, UL 125°C 2 Layers, 1 oz. Cu each, Through-hole plated 3.125" x 1.52" x 0.062" LPI Solder mask, SMOBC on Top and Bottom Layers Open copper solder finish On Top and Bottom Layers
Motherboard:
Material: Layer Stack: Dimensions: Solder Mask: Plating: Silkscreen: FR4, UL 125°C 2 Layers, 1 oz. Cu 5.2" x 5.8" x 0.062" LPI Solder mask, SMOBC on Top and Bottom Layers Open copper solder finish On Top and Bottom Layers
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IRAUDAMP5 REV 3.0
Page 41 of 49
IRAUDAMP5 PCB layers
Class D, Daughter-board:
Figure 40. PCB Layout Top-Side Solder-Mask and Silkscreen
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IRAUDAMP5 REV 3.0
Page 42 of 49
Figure 41. PCB Layout Bottom Layer and Pads and bottom silk screen
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IRAUDAMP5 REV 3.0
Page 43 of 49
Figure 39. PCB Layout Motherboard:
Top Layer
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IRAUDAMP5 REV 3.0
Page 44 of 49
Top silk screen
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IRAUDAMP5 REV 3.0
Page 45 of 49
Bottom
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IRAUDAMP5 REV 3.0
Page 46 of 49
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IRAUDAMP5 REV 3.0
Page 47 of 49
4.0 4.0
Bottom Silkscreen
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 7/27/2007
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IRAUDAMP5 REV 3.0
Page 48 of 49