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SIS M650/645DX(2/3)
14 DDR_MD[0..63] DDR_MD[0..63] U9B DDR_MD0 DDR_MD1 DDR_MD2 DDR_MD3 DDR_MD4 DDR_MD5 DDR_MD6 DDR_MD7 DDR_DQM0 DDR_DQS0 DDR_MD8 DDR_MD9 DDR_MD10 DDR_MD11 DDR_MD12 DDR_MD13 DDR_MD14 DDR_MD15 DDR_DQM1 DDR_DQS1 DDR_MD16 DDR_MD17 DDR_MD18 DDR_MD19 DDR_MD20 DDR_MD21 DDR_MD22 DDR_MD23 DDR_DQM2 DDR_DQS2 DDR_MD24 DDR_MD25 DDR_MD26 DDR_MD27 DDR_MD28 DDR_MD29 DDR_MD30 DDR_MD31 DDR_DQM3 DDR_DQS3 DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_DQM4 DDR_DQM5 DDR_DQM6 DDR_DQM7 DDR_MD32 DDR_MD33 DDR_MD34 DDR_MD35 DDR_MD36 DDR_MD37 DDR_MD38 DDR_MD39 DDR_DQM4 DDR_DQS4 DDR_MD40 DDR_MD41 DDR_MD42 DDR_MD43 DDR_MD44 DDR_MD45 DDR_MD46 DDR_MD47 DDR_DQM5 DDR_DQS5 DDR_MD48 DDR_MD49 DDR_MD50 DDR_MD51 DDR_MD52 DDR_MD53 DDR_MD54 DDR_MD55 DDR_DQM6 DDR_DQS6 DDR_MD56 DDR_MD57 DDR_MD58 DDR_MD59 DDR_MD60 DDR_MD61 DDR_MD62 DDR_MD63 DDR_DQM7 DDR_DQS7 AJ23 AG22 AH21 AJ21 AD23 AE23 AF22 AF21 AD22 AH22 AD21 AG20 AE19 AF19 AE21 AD20 AD19 AH19 AF20 AH20 AF18 AG18 AH17 AD16 AD18 AD17 AF17 AJ17 AE17 AH18 AD14 AG14 AJ13 AE13 AJ15 AF14 AD13 AF13 AH13 AH14 AD10 AH10 AE9 AD8 AG10 AF10 AH9 AF9 AD9 AJ9 AH5 AG4 AE5 AH3 AG6 AF6 AF5 AF4 AH4 AJ3 AE4 AD6 AE2 AC5 AG2 AG1 AF3 AC6 AD4 AF2 AB6 AD3 AA6 AB3 AC4 AE1 AD2 AC1 AB4 AC2 MD0/SMD63 MD1/SMD30 MD2/SMD29 MD3/SMD59 MD4/SMD31 MD5/SMD62 MD6/SMD60 MD7/SMD28 DQM0/SMD61 DQS0/CSB0# MD8/SMD27 MD9/SMD58 MD10/SMD55 MD11/SMD23 MD12/SMD26 MD13/SMD57 MD14/SMD56 MD15/SMD24 DQM1/SMD25 DQS1/CSB1# MD16/SMD22 MD17/SMD53 MD18/SMD20 MD19SMD19 MD20/SMD54 MD21/SMD21 MD22/SMD51 MD23/SMD50 DQM2/SMD52 DQS2/CSB2# MD24/SMD18 MD25/SMD17 MD26/SDQM7 MD27/SDQM6 MD28/SMD49 MD29/SMD48 MD30/SDQM3 MD31/SDQM2 DQM3/SMD16 DQS3/CSB3# MD32/SDQM5 MD33/SDQM4 MD34/SMD47 MD35/SMD45 MD36/SDQM1 MD37/SDQM0 MD38/SMD46 MD39/SMD14 DQM4/SMD15 DQS4/CSB4# MD40/SMD13 MD41/SMD43 MD42/SMD42 MD43/SMD10 MD44/SMD44 MD45/SMD12 MD46/SMD41 MD47/SMD9 DQM5/SMD11 DQS5/CSB5# MD48/SMD40 MD49/SMD8 MD50/SMD37 MD51/SMD36 MD52/SMD39 MD53/SMD7 MD54/SMD6 MD55/SMD5 DQM6//SMD38 DQS6/CSB6# MD56/SMD35 MD57/SMD34 MD58/SMD1 MD59/SMD0 MD60/SMD4 MD61/SMD3 MD62/SMD33 MD63/SMD32 DQM7/SMD2 DQS7/CSB7# SIS650 BGA540_77_85 U9C DDR_MA[0..12] MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 SRAS# SCAS# SWE# AH11 AF12 AH12 AG12 AD12 AH15 AF15 AH16 AE15 AD15 AF11 AG8 AJ11 AG16 AF16 AH8 AJ7 AH7 DDR_MA0 DDR_MA1 DDR_MA2 DDR_MA3 DDR_MA4 DDR_MA5 DDR_MA6 DDR_MA7 DDR_MA8 DDR_MA9 DDR_MA10 DDR_BA0 DDR_BA1 DDR_MA11 DDR_MA12 DDR_RAS# DDR_CAS# DDR_WE# 13 DDR_MA[0..12] 14 15 15 15 15 15 15 15 ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZAD[0..15] ZCLK0 ZCLK0 ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZAD[0..15] ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZVREF VDDZCMP ZCMP_N ZCMP_P VSSZCMP Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS T4 R3 T5 T6 R2 R6 R1 R4 P4 N3 P5 P6 N1 N6 N2 N4 U3 V5 U4 U2 V6 W1 W2 V2 V1 V3 U6 U1 T3 T1 P1 P3 ZCLK VOSCI ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ROUT GOUT BOUT HSYNC VSYNC A12 B13 A13 F13 E13 D13 D12 B11 E12 A11 F12 E14 D14 F14 B12 C12 C13 C14 B15 A15 B14 A14 PID1 RSYNC PID2 VCOMP VRSET VVBWN DACAVDD1 DACAVSS1 DACAVDD2 DACAVSS2 DCLKAVDD DCLKAVSS ECLKAVDD ECLKAVSS HSYNC VSYNC DDCK DDDA R713 R710 R712 R711 1 1 1 1 2 2 2 2 33 33 100 100 C15 REFCLK0
A A

14 DDR_DQS[0..7]

DDR_DQS[0..7]

REFCLK0 13

NOT STUFF IN SiS645DX
CRT_RED CRT_GREEN CRT_BLUE CRT_HSYNC CRT_VSYNC CRT_DDCK CRT_DDDA PCI_INTA# CRT_RED 11,12 CRT_GREEN 11,12 CRT_BLUE 11,12 CRT_HSYNC 11,12 CRT_VSYNC 11,12 CRT_DDCK 11,12 CRT_DDDA 11,12 PCI_INTA# 9,10,15

NC IN SiS645DX
A10 TESTMODE2 F11 TESTMODE1 C11 TESTMODE0 Y3 PCIRST# W 4 PW ROK W 6 AUXOK E11 DLLEN# F10 ENTEST D11 TRAP1 E10 TRAP0

DDR_BA0 14 DDR_BA1 14

MA11 --> BANK SELECT 0 MA12 --> BANK SELECT 1 MA13 --> MEM_MA11 MA14 --> MEM_MA12

DDR_RAS# 14 DDR_CAS# 14 DDR_WE# 14

CS0# CS1# CS2# CS3# CS4# CS5#

AE7 AF7 AH6 AJ5 AF8 AD7

DDR_CS0# DDR_CS1# DDR_CS2# DDR_CS3# 1 1 TP517 TP518 1 2 3 4

14 DDR_DQM[0..7]

DDR_DQM[0..7]

DDR_CS0# 14 DDR_CS1# 14 DDR_CS2# 14 DDR_CS3# 14 8 +2.5V_DDR 7 RP8 6 470*4 5 1206 CKE0 14 CKE1 14 CKE2 14 CKE3 14 TP521 TP519 S3AUXSW# 16,24 SDRAMCLK 13 FWDSDCLKO 13

ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZVREF VDDZCMP ZCMP_N ZCMP_P VSSZCMP Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS

VGPIO0 VGPIO1 INTA# CSYNC RSYNC LSYNC VCOMP VRSET VVBWN DACAVDD1 DACAVSS1 DACAVDD2 DACAVSS2 DCLKAVDD DCLKAVSS ECLKAVDD ECLKAVSS

B

CKE0 CKE1 CKE2 CKE3 CKE4 CKE5 S3AUXSW# SDCLK FWDSDCLKO SDRCLKI

AB2 AA4 AB1 Y6 AA5 Y5 Y4 AA3 AD11 AE11 R728 1

CKE0 CKE1 CKE2 CKE3 S3AUXSW# SDRAMCLK 2 22 1 1 1

SIS650 BGA540_77_85

B

C745 10P/NA 0603

9,10,15,18,19,22,23 PCIRST# 16,24 PWROK 16 AUXOK TP16 TP515 TP15

SDAVDD SDAVSS

Y1 Y2

SDAVDD SDAVSS

PCIRST# PWROK AUXOK PID0 TRAP0 1 1 1 DLLEN# 1 1

1 R748 4.7K 0603D 2 C782 0.1U 0603 50V C770 0.1U 0603 50V 2 2

DDRAVDD DDRAVSS

AA1 AA2

DDRAVDD DDRAVSS

DDRVREFA DDRVREFB DRAM_SEL

AJ19 AH2 W3

DDRVREFA DDRVREFB DRAM_SEL

C

2

C

NOT STUFF IN SiS645DX
C755 VVBWN L532 VDDZCMP ZCMP_N ZCMP_P VSSZCMP R739 1 R751 1 2 56 2 56 2 1 2 VCOMP 1 C705 10U 1206 10V 1 +1.8VS 0603D 0.1U C733 2 0.1U 50V +1.25V_REF 1 1 L530 1 2 1 1 DACAVDD1 DACAVDD2 +1.8VS R144 0/NA 0603 R714 130 1% 0603D 2 R98 49.9 0603 1% 2 2 R755 150 0603D 1% 1 VRSET +2.5V_DDR 0603D +1.8VS 50V 1 2

C776 0.01U 0603 2

120Z/100M 2012 C779 0.1U 0603 50V JL5 1 2 JP_NET20

1

1

2

2

2

2

L41 DDRAVDD 1 2

+3VS Z1XAVDD 1

L39 2

+3VS DACAVSS2

1

1

1

JL6 1 2 JP_NET20 L32 ECLKAVDD 1 2 DACAVSS1 C203 10U 1206 10V

2

C189 0.01U 0603 2 2 DDRAVSS

120Z/100M 2012 C183 0.1U 0603 50V JL7 1 2 JP_NET20

C201 10U 1206 10V Z1XAVSS

C181 0.01U 0603 2 2

120Z/100M 2012 C187 0.1U 0603 50V JL8 1 2 JP_NET20

C113 0.01U 0603D 2 2

1

C757 0.1U 0603D 50V

120Z/100M 2012 C756 1U 0603

1

1

1

C111 0.01U 0603D DDRVREFA 2

C788 0.1U 0603D 50V ZVREF

NOT STUFF IN SiS645DX
PID0 PID1 R742 1 0 R740 1 0 R736 1 0 2 0603 2 0603 2 0603 LCD_ID0 LCD_ID1 LCD_ID2

1

C754 10U 1206 10V

2

LCD_ID0 11,12 LCD_ID1 11,12 LCD_ID2 11,12

R108 49.9 0603 1% 2

R754 150 0603D 1%

C787 0.1U 0603D 50V

PID2

1

1

1

1

1

1

+3VS

2

2

2

NB Hardwre Trap Table
+2.5V_DDR 1 +1.25V_REF C121 10U 1206 10V 1 R824 0/NA 0603 2 1 DLLEN# DRAM_SEL SDR R750 49.9 0603 1% 2 TRAP0 DDR
Enable Debug Mode Enable VGA Int function Reserved for Panel ID Reserved for Panel ID Reserved for Panel ID

C123 0.01U 0603 2 2 +3VS ECLKAVSS

D

L40 SDAVDD 1 2

+3VS Z4XAVDD 1

L38 2

120Z/100M 2012 C122 0.1U 0603 50V JL9 1 2 JP_NET20

0
Enable PLL

1
Disable PLL

Default
0 1(DDR) 0 1

Embedded pull-low (30 50K Ohm)
Yes Yes Yes

1

1

2

1

C781 0.01U 0603D 2

For 645DX

RSYNC CSYNC TRAP1

DDRVREFB 1 1 +3VS LSYNC R745 49.9 0603 1% 2

C182 0.01U 0603 2 2 SDAVSS

120Z/100M 2012 C188 0.1U 0603 50V JL10 1 2 JP_NET20

C200 10U 1206 10V Z4XAVSS

C186 0.01U 0603 2 2

120Z/100M 2012 C180 0.1U 0603 50V JL11 1 2 JP_NET20

C198 10U 1206 10V

L30 DCLKAVDD 1 2

C775 0.01U 0603D 1 2

Disable Debug Mode Disable VGA Int function Reserved for Panel ID Reserved for Panel ID Reserved for Panel ID

For M650
D

1

1

1

1

1

1

C116 0.01U 0603 2 2 DCLKAVSS

120Z/100M 2012 C115 0.1U 0603 50V JL12 1 2 JP_NET20

2

2

1

1

C119 10U 1206 10V

+3VS +3V DLLEN# DRAM_SEL TRAP0 RSYNC R118 R734 R746 R116 1 1 1 1 2 2 2 2 4.7K/NA 4.7K 4.7K/NA 4.7K

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Title

SIS M650/M645DX (2/3)
Size Date: Document Number

8640
Sheet
8

Rev 01 7 of 32

Wednesday, August 28, 2002

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