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Notebook Mitac 8640
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MODEL : 8640
Contexts
Title
COVER SHEET & SCREW HOLE System Block Diagram Power Block Diagram P4-CPU (1/2) P4-CPU (2/2) SIS M650(1/3) SIS M650(2/3) SIS M650(3/3) TV/LVDS ENCODER(SiS301LV/CH7019) nVidia MAP17/31(1/2) nVidia MAP17/31(1/2) LCD & CRT Interface Clock Generator/Buffer DDR SO-DIMM SIS962(1/3) SIS962(2/3) SIS962(3/3) IDE Interface Card Bus PHY Of LAN & MDC IEEE1394a/USB 2.0/Parallel Port Super I/O & Flash ROM MiNi-PCI & USB 2.0 Embeded Controller Invter Conn. and +1.8VS/+1.5VS/+2.5V_DDR/VDD_MEM2.5 Battery Conn. & +5VA/+1.2VS/+3VA Charger CPU Core +3V/+5V DC Jack & +12VS/+5VS/+3VS History 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Revision 02
Page
TP26 TP8 TP18 TP24 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 4 5 6 1 1 1 1 7 8 9 MTG16 ID3.0/OD7.6 12 11 10 4 5 6 7 8 9 13 12 11 10 MTG11 ID4.5/OD7.5 4 5 6 7 8 9 MTG5 ID3.0/OD7.6 12 11 10 4 5 6 7 8 9 13 12 11 10 MTG1 ID4.5/OD7.5 3 2 1 3 2 1 3 2 1 E504 TOUCHPAD_METAL9 E513 E514 E503 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 3 2 1
1
1
1
1
MTG17 ID3.0/OD7.6 12 11 10 4 5 6
MTG12 ID3.0/OD7.6 12 11 10 4 5 6
MTG8 ID3.0/OD7.6 12 11 10 4 5 6
MTG2 ID3.0/OD7.6 12 11 10
3 2 1
3 2 1
3 2 1
E507 E508 E520 E519 E518 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9
4 5 6 7 8 9
7 8 9
7 8 9
1
1
1
1
E517 E516 E512 E515 E502 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 MTG14 ID3.0/OD7.6 12 11 10 7 8 9 4 5 6 7 8 9 MTG10 ID3.0/OD7.6 12 11 10 4 5 6 7 8 9 MTG3 ID3.0/OD7.6 12 11 10 3 2 1 3 2 1 3 2 1
2
2
1
4 5 6
1
1
1
1
GND_USB
E501 E505 E510 E506 E509 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL9
1
1
1
1
GND_USB
E2 E1 TOUCHPAD_METAL9 TOUCHPAD_METAL9
LAN_GND
1
1
For NB heatshink
MTG13 ID3.2/OD8.0 MTG6 ID3.2/OD8.0 MTG4 ID3.2/OD8.0
For CPU FAN
MTG15 ID3.2/OD6.0 MTG9 ID3.2/OD6.0 MTG7 ID3.2/OD6.0
1
1
1
1
1
1
1
FD2 FIDUCIAL-MARK
FD3 FIDUCIAL-MARK
FD4 FIDUCIAL-MARK
FD1 FIDUCIAL-MARK
1
1
1
FD502 FIDUCIAL-MARK
FD504 FIDUCIAL-MARK
FD503 FIDUCIAL-MARK
FD501 FIDUCIAL-MARK
1
1
1
1
1
POWER STATES
STATE SIGNAL -SUSB -SUSC ADP BATTERY +VCC_RTC +VCC_CORE +1.8VS +1.8V +1.8VA VOTAGE +19V +12V +3.3V +1.75V +1.8V +1.8V +1.8V +2.5V +3.3V +3.3V +3.3V +5V +5V +5V +12V +12V FULL ON HIGH HIGH O O O O O O O O O O O O O O O O STR LOW HIGH O O O O X O O O X O O X O O X O STD LOW LOW O O O X X X O X X X O X X 0 X X MEC-OFF LOW LOW O O O X X X O X X X 0 X X 0 X X REMARK
IDSEL
IDSEL AD20 AD21 AD22 CHIP TI1410 MINI PCI MINI PCI
BUS MASTER
REQ/GNT -REQ0/-GNT0 -REQ2/-GNT2 -REQ3/-GNT3 CHIP TI1410 MINI PCI MINI PCI
PCIINT
PCIINT INTA# INTB# INTC# INTD# CHIP SIS 650 / MAP17 PCMCIA (TI1410) MINI PCI MINI PCI
1
+2.5V_DDR +3VS +3V
Board Stackup-up
COMP 4.33 mil 4.92 mil 8.07 mil 4.72 mil 8.07 mil 4.92 mil 4.33 mil PP 2116 GND FR4 IN-1 0.54 mil 0.54 mil 0.54 mil 0.54 mil 0.54 mil PP 7628 IN-2 FR4 POWER PP 7628 IN-3 FR4 GND PP 2116 SOLDER 1.79 mil 0.54 mil 1.79 mil
1
7 8 9
3 2 1
1
DRAW
DESIGN
CHECK
ISSUED
+3VA +5VS +5V +5VA +12VS +12V
Title
COVER SHEET & SCREW HOLD
Size Date:
A B
Document Number
8640
Sheet 1 of 32
Rev 01
Wednesday, August 28, 2002
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
A
B
8640
DT/Mobile Pentium 4
Willamette/Northwood
C.P.U.
Micro-FCPGA 478 pin
ADM 1032
Thermal Recorder
-HD[0..63]
-HA3..31]
Power Switch SSOP 16
692PBGA A[0..25] D[0..15] Control AV/RGB
Control
IC CARD Socket
TPS2211
nVIDIA MAP 17
200 Pin DDR SO-DIMM Socket*2
S-VIDEO
TV
2
SIS301LV
AGP BUS
128-pin LQFP AGP
HOST
2
DDR SO-DIMM
MINI PCI SLOT
Type III A
PCI1410A
PCMCIA CONTROLLER PQFP 144
Pannel
LVDS
SiS M650/645DX
SDRAM
DDR SDRAM PC2100 Memory Bus / 266MHz
CRT
Local
Memory
702-Balls BGA
Hyper Zip HyperZip Data Bus 266MHz 512MB/sec
AD[0..31]
Control
Control
AD[0..31]
PCI BUS
HUB[0..11] AD[0..31] Control Control
13
MuTIOL Media I/O
ND3050-LA
SMK Cardreader Connector External Microphone
8
DUAL USB
USB 2.0 MINI
IEEE1394
RJ45
LAN PHY 10/100 M
ICS1893
MII
LAN
PCI
HyperZip USB
IEEE1394
PHY
RTL8801
Internal Microphone Internal Speaker
Ultra DMA 33/66/100
SiS 962
IDE
Ultra DMA 33/66/100
Primary EIDE (HDD)
AC Link AC'97
5
Realtek ALC202
Audio Codec PQFP 48
LM 4835
Amplifier
371-Balls BGA LPC
SPDIF JACK RJ-11 JACK
Secondary EIDE (CDROM/DVD)
FWH
5 LPC
M.D.C.
(30 pin)
1
IR Module
HP-3600
PRINTER PORT
PC87393F
Super I/O TQFP 100PIN
ISA BUS
H8-3437S
Keyboard Controller PQFP 100
Cover Switch Keyboard PS/2 Power Button
1
Flash ROM
512KB PLCC 32 16MHz
Touch PAD
FAN1 For CPU FAN2 For D/D
Title
SYSTEM BLOCK DIAGRAM
Size Date:
A B
Document Number
8640
Sheet 2 of 32
Rev 01
Wednesday, August 28, 2002
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POWER BLOCK DIAGRAM OF THE 8640A(mode1.2.3)
D
+1.8VS +5V_CD 5V DC to DC Convertor FAN5234 LDO SC1565-1.2V
+1.2VS
* OPTION(NO LINK) RTC REF_1.25V +1.2VS ICH3M DDR NV17-MAP 845M NV17-MAP M-P4 845M ICH3M ICH3M 4uA 2A ? 3.5A ? 40A 800mA 470mA
D
CPU_CORE_EN SUSB# +3V +3VS Shut Down MOSFET +5V Shut Down MOSFET +12V +12VS Shut Down MOSFET CPU_CORE +5VS
+1.5VS CPU_CORE +1.8VS +1.8V_ICH
64mA
PWR_ON
VDDR_MEM2.5 +3V
DDR NV17-MAP NV17-MAP ICH3M RTL8139CL IEEE1394 PCI4410 PCMCIA CARD ICH3M CLOCK NV17-MAP SIO LCD ICH3M MODEM PCMCIA CARD IDE ALC200 USBX2 H8 AUDIO AMP CD_ROM
4A ? ? 26mA 330mA 69mA 79mA 500mA 420mA 280mA ? 50mA 1.5A 14mA ? 500mA 900mA 40mA 4A 40mA 1A 1.5A
C
3.3V&5V&12V ADAPTOR Selfdischarge SWITCH I_Limit Rsense Diode Protector D/VMAIN DC to DC Convertor MAX1632
+3VS
+3V_ICH +5V +5VS
learning
C
Discharge Battery Pack
+5VA +5V_CD
Adaptor / Battery Change Switch Vcc Core DC to DC Convertor Celeron & DT for LTC1709EG-9 Mobile for LTC3716 Diode Protector DDR DC to DC Converter LTC3707 REF DC to DC Convertor CM8500
+1.8V Regulator SI4800-1.8V
SWITCH SI4800
+1.8VS
DDR_2.5V SWITCH SI4800 REF_1.25V +5VA
B
VDD_MEM2.5V SWITCH SI4800
+1.5VS
Charge
B
Always ADINP
Regulator LP2951-5V High Low Side Choke Rsense +5VA +3VA Regulator AME8800 +5VAS SWITCH SI2301
ADINP_2
LI_OVP
DCIN SW CC
H8 D/A A/D
A
CHARGING I_LIMIT
ADINP_1
D/A
CHG_I
PWM Charge IC MAX1772
+3VS CC CV
MUST BE MEET ICH2 POWER ON SEQUENCE
CHARGE SWITCH
Li-ovp
+2.8VS Regulator AME8801CEEV
A
Title
Power Block Diagram
Size Date:
5 4 3 2
Document Number
8640
Sheet 3 of 32
1
Rev 01
Wednesday, August 28, 2002
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CPU (1/2)
D
TP12
TP13
D
1
6
HA#[3..31]
HA#[3..31] HA#3 K2 HA#4 K4 HA#5 L6 HA#6 K1 HA#7 L3 HA#8 M6 HA#9 L2 HA#10 M3 HA#11 M4 HA#12 N1 HA#13 M1 HA#14 N2 HA#15 N4 HA#16 N5 HA#17 T1 HA#18 R2 HA#19 P3 HA#20 P4 HA#21 R3 HA#22 T2 HA#23 U1 HA#24 P6 HA#25 U3 HA#26 T4 HA#27 V2 HA#28 R6 HA#29 W1 HA#30 T5 HA#31 U4 H_ADSTB#1 R5 H_ADSTB#0 L5 H_REQ#4 H3 H_REQ#3 J3 H_REQ#2 J4 H_REQ#1 K5 H_REQ#0 J1 AB1 Y1 W2 V3
U8B U8A A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 ADSTB#1 ADSTB#0 REQ#4 REQ#3 REQ#2 REQ#1 REQ#0 A#35 A#34 A#33 A#32 ADS# AP#0 AP#1 BINIT# BNR# DP#3 DP#2 DP#1 DP#0 TESTHI8 TESTHI9 TESTHI10 BR#0 BPRI# DBSY# DEFER# DRDY# HIT# HITM# IERR# INIT# LOCK# MCERR# RESET# RS#2 RS#1 RS#0 RSP# TRDY# G1 AC1 V5 AA3 G2 L25 K26 K25 J26 U6 W4 Y3 H6 D2 H5 E2 H2 F3 E3 TESTHI8 TESTHI9 TESTHI10 H_BR#0 H_BPRI# H_DBSY# H_DEFER# H_DRDY# H_HIT# H_HITM# 2 62 H_ADS# H_ADS# 6 HD#31 HD#30 HD#29 HD#28 HD#27 HD#26 HD#25 HD#24 HD#23 HD#22 HD#21 HD#20 HD#19 HD#18 HD#17 HD#16 HD#15 HD#14 HD#13 HD#12 HD#11 HD#10 HD#9 HD#8 HD#7 HD#6 HD#5 HD#4 HD#3 HD#2 HD#1 HD#0 6 CPURST# 6 DBI#[0..3] DBI#[0..3] DBI#0 DBI#1 DBI#2 DBI#3 DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3 6 DSTBN#[0..3] DSTBN#[0..3] E21 G25 P26 V21 E22 K22 R22 W22 H25 K23 J24 L22 M21 H24 G26 L21 D26 F26 E25 F24 F23 G23 E24 H22 D25 J21 D23 C26 H21 G22 B25 C24 C23 B24 D22 C21 A25 A23 B22 B21 D#31 D#30 D#29 D#28 D#27 D#26 D#25 D#24 D#23 D#22 D#21 D#20 D#19 D#18 D#17 D#16 D#15 D#14 D#13 D#12 D#11 D#10 D#9 D#8 D#7 D#6 D#5 D#4 D#3 D#2 D#1 D#0 DBI#0 DBI#1 DBI#2 DBI#3 DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3 WMT478/NWD_14 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 DSTBP#[0..3] DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3 F21 J23 P23 W23 DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3 DSTBP#[0..3] 6 24 THRMTRIP# 13 13 HCLK_CPU HCLK_CPU# TP9 TP10 H_A20M# H_FERR# H_IGNNE# H_INTR H_NMI H_SMI# H_STPCLK# HCLK_CPU HCLK_CPU# 1 1 H_A20M# H_FERR# H_IGNNE# H_INTR H_NMI H_SMI# H_STPCLK# PVID4 PVID3 PVID2 PVID1 PVID0 AF22 AF23 AC26 AD26 C6 B6 B2 D1 E5 B5 Y4 AE1 AE2 AE3 AE4 AE5 AF2 AF3 AF4 AD20 A5 AE23 AD22 A4 AE21 A22 A7 B3 C4 A2 AD3 AF25 AD2 AF24
1
6
HD#[0..63]
HD#[0..63] U8C BCLK0 BCLK1 ITP_CLK0 ITP_CLK1 A20M# FERR# IGNNE# LINT0 LINT1 SMI# STPCLK# VID4 VID3 VID2 VID1 VID0 VCC RSVD VCCVID VCCA VCCSENSE VCCIOPLL VSSA VSSSENSE RSVD RSVD RSVD THRMDA THRMDC THRMTRIP# RSVD RSVD RSVD RSVD WMT478/NWD_14 BSEL0 BSEL1 TESTHI11 COMP0 COMP1 BPM#5 BPM#4 BPM#3 BPM#2 BPM#1 BPM#0 TESTHI0 DBR# TESTHI12 GTLREF3 GTLREF2 GTLREF1 GTLREF0 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI7 TESTHI6 SKTOCC# TESTHI1 PWRGOOD PROCHOT# SLP# TCK TDI TDO TMS TRST# AD6 AD5 A6 L24 P1 AB4 AA5 Y6 AC4 AB5 AC6 AD24 AE25 AD25 AA6 F6 AA21 F20 AC23 AC24 AC20 AC21 AB22 AA20 AF26 AA2 AB23 C3 AB26 D4 C1 D5 F7 E6 BSEL0 BSEL1 CPUPERF# H_COMP0 H_COMP1 H_BPM#5 H_BPM#4 H_BPM#3 H_BPM#2 H_BPM#1 H_BPM#0 TESTHI0 DPSLP# H_GTLREF CPU_GTLREF TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI7 TESTHI6 1 TESTHI1 CPUPWRGD H_PROCHOT# SLP# ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# TP11 1 TP14 DPSLP# 16 1 BSEL0 13 TP512 CPUPERF# 16
H_BNR#
H_BNR#
6
16 16 16 16 16 16 16 28 28 28 28 28 PVID4 PVID3 PVID2 PVID1 PVID0
H_BR#0
6
H_BPRI# 6 H_DBSY# 6 H_DEFER# 6 H_DRDY# 6 H_HIT# 6 H_HITM# 6 0603 +VCC_CORE 16
+VCC_CORE VCCPVID PLL_VCCA TP506 TP503 1 VCCIO_PLL PLL_VSSA 1
AC3 R668 1 W5 G4 V6 AB25 F4 G5 F1 AB2 J6 CPURST# H_RS#2 H_RS#1 H_RS#0 H_TRDY# H_INIT# H_LOCK#
H_INIT#
H_LOCK# 6
6 6
H_ADSTB#1 H_ADSTB#0
CPUPWRGD 6 SLP# 16
C
C
CPU_THERMDA CPU_THERMDC THRMTRIP#
H_RS#[0..2]
6
H_REQ#[0..4]
H_REQ#[0..4]
H_RS#[0..2] 6 H_TRDY# 6
WMT478/NWD_14
FSB SELECTION
BSEL1 0 0 BSEL0 0 1 0 1 FUNCTION 100MHz 133MHz RESERVED RESERVED
CPU Temperature Monitor
Placement : 3" (Maximum) From CPU
+VCC_CORE
1 FOR MOBILE ONLY 1
1
1
1
1
1
1
1
1
1
+VCC_CORE
Change to 10Kohm
RP4 TESTHI4 TESTHI5 TESTHI6 TESTHI7
B
R560 200 0603 CPUPERF# H_A20M# H_IGNNE# H_INTR H_NMI H_SMI# H_STPCLK# DPSLP# SLP# H_INIT# 2 2
R549 200 0603 2
R558 200 0603 2
R586 200 0603 2
R604 200 0603 2
R548 200 0603 2
R662 200 0603 2
R94 200 0603 2
R90 200 0603 2
1 R655 200 0603
1 2 3 4 5 1K*8 RP509 1206
10 9 8 7 6
TESTHI0 TESTHI1 TESTHI2 TESTHI3
CPU_THERMDA 1 C569 2200P CPU_THERMDC 0603D 2 3 1 5 1 C550 0.1U 0603 50V 2
+/- 1 Degree C
U504 D+ DVDD GND ADM1032 SO8 SCLK SDATA ALERT THEPM 8 7 6 4 SCL_THRM SDA_THRM SCL_THRM 24 SDA_THRM 24 THERM_ADM# 24
B
TESTHI8 TESTHI9 TESTHI10
1 2 3 4 10K*4 1206
8 7 6 5
+3VS
THERM_ADM#
R94 must be pull hi at DT.Because the signal was input of TEST_HI12.
GTL Reference CKT 1.5" MAX.
+VCC_CORE 1 51.1 R645 2 1 1 1 R647 100 0603 1% 2 1 0603 1% C640 1U 0805 5% C651 220P 0603 5% H_GTLREF
PLL SUPPLY FILTER
VCCPVID +VCC_CORE
2
CPU SIGNAL TERMINATION
+VCC_CORE
PLACE CLOSE TO CPU SOCKET
+VCC_CORE
PRECISION FSB COMPENSATION RESISTORS
+VCC_CORE R59 1 51.1 R619 1% 1 51.1 1% H_BPM#5 H_BPM#4 H_BPM#3 H_BPM#2 H_BPM#1 H_BPM#0 ITP_TDI ITP_TDO ITP_TMS ITP_TCK ITP_TRST# 2 0603 2 0603 1 1 H_COMP0 H_COMP1 2 1 R576 62 0603 2 R547 62 0603 2 R557 62 0603 THRMTRIP# H_PROCHOT# VCCPVID
MOBILE
1 R700 0 0603 2 2 1
D/T
R703 0 0603
PLACE AT CPU END
1 1 1 1 1 1 1 1 1 1 1 1 1 R673 51.1 0603 1% 2 2 R679 51.1 0603 1%
R559 62 0603 1% H_FERR# CPUPWRGD H_BR#0 CPURST#
C604 220P 0603 5%
1
1
R89 51.1 0603 1% 2 2 L528 4.7UH 2012 PLL_VCCA
R611 51.1 0603 1% 2
R88 301 0603 2
R610 39 0603 1% 2 2
R585 75 0603 2
R577 150 0603 1% 2
R681 51.1 0603 1% 2
R674 51.1 0603 1% 2
R680 51.1 0603 1% 2
R667 51.1 0603 1%
PLACE THESE INSIDE SOCKET CAVITY FOR DT FOR MOBILE
2
2
2
L527 4.7UH 2012 +VCC_CORE 1 51.1
A
R648 2 1 1
PLACE AT CPU END
CPU_GTLREF 1 1 R646 100 0603 1% 2 0603 1%
7343 C696 2 1 20% 16V 33U +
2
2
C644 1U 0805 5%
C650 220P 0603 5%
C602 220P 0603 5% 7343 C693 2 1 20% 16V 33U +
PLL_VSSA
CPURST#
DT : 51 ohm MOBILE: NA
1 1
A
2
2
2
VCCIO_PLL
R603 27 0603 1% 2 2
R606 680 0603
CLOSE TO CPU SOCKET
One 220PF for each GTL REF Pin
CP1812_7243 SHAPE
Title
PENTIUM4 (1/2)
Size Date:
5 4 3 2
Document Number
8640
Sheet 4 of 32
1
Rev 01
Wednesday, August 28, 2002
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CPU (2/2)
+VCC_CORE
D D
U8D N6 N3 N24 N21 P5 P2 P25 P22 R26 R4 R1 R23 T6 T3 T24 T21 U5 U2 U25 U22 V26 G21 H26 H4 H1 H23 J5 J2 J25 J22 K6 K3 K24 K21 L26 L4 L1 L23 M5 M2 M25 M22 E11 E9 E26 E7 E4 E1 E23 E19 F18 F16 F14 F12 F10 F8 F5 F2 F25 F22 G6 G3 G24 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A8 A10 A12 A14 A16 A18 A20 B7 B9 B11 B13 B15 B17 B19 C8 C10 C12 C14 C16 C18 C20 D7 D9 D11 D13 D15 D17 D19 E8 E10 E12 E14 E16 E18 E20 F9 F11 F13 F15 F17 F19 AA8 AA10 AA12 AA14 AA16 AA18 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AC8 AC10 AC12 AC14 AC16 AC18 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE7 AE24 AE22 AE19 AD14 AD12 AD10 AD8 AD4 AD1 AD23 AD21 AE17 AE15 AE13 AE11 AE9 AE26 AB20 AC17 AC15 AC13 AC11 AC9 AC7 AC5 AC2 AC25 AC22 AC19 AD18 AD16 AA4 AA1 AA23 AA19 AB18 AB16 AB14 AB12 AB10 AB8 AB6 AB3 AB24 AB21 V4 V1 V23 W6 W3 W24 W21 Y5 Y2 Y25 Y22 AA17 AA15 AA11 AA9 AA26 AA7
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
C
C5 VSS C2 VSS C25 VSS C22 VSS C19 VSS D18 VSS D16 VSS D14 VSS D12 VSS D10 VSS D8 VSS D6 VSS D3 VSS D24 VSS D21 VSS D20 VSS E17 VSS E15 VSS E13 VSS A3 VSS A24 VSS A21 VSS A19 VSS B18 VSS B16 VSS B12 VSS B10 VSS B26 VSS B8 VSS B4 VSS B23 VSS B20 VSS C17 VSS C15 VSS C13 VSS C11 VSS C9 VSS C7 VSS AF18VSS AF16VSS AF14VSS AF12VSS AF10VSS
WMT478/NWD_14
B
AF8 VSS AF6 VSS AF1 VSS AF20VSS A17 VSS A15 VSS A13 VSS A11 VSS A9 VSS A26 VSS AA13VSS B14 VSS
B
Place these caps at CPU solder side
+VCC_CORE
Place these caps at CPU south side
1 +VCC_CORE +
+VCC_CORE
C72 10U 1206 10V
C74 10U 1206 10V
C71 10U 1206 10V
C73 10U 1206 10V
C75 10U 1206 10V
C560 10U 1206 10V
C561 10U 1206 10V
C562 10U 1206 10V
C563 10U 1206 10V
C51 150U 7343 10V
1 + 1 2 1 2 2
C567 150U 7343 10V
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
+VCC_CORE +VCC_CORE +VCC_CORE 1 1 1 1 C667 0.1U 0603 50V C597 0.1U 0603 50V
C91 10U 1206 10V
C610 10U 1206 10V
C619 10U 1206 10V
C620 10U 1206 10V
C617 10U 1206 10V
C564 10U 1206 10V
C565 10U 1206 10V
C566 10U 1206 10V
C611 10U 1206 10V
C616 10U 1206 10V
C666 0.1U 0603 50V
C581 0.1U 0603 50V
C596 0.1U 0603 50V
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
+VCC_CORE
2
2
+VCC_CORE
Place these caps at CPU north side
1 1 1 1 1 C665 0.1U 0603 50V C657 0.1U 0603 50V C658 0.1U 0603 50V 1 C659 0.1U 0603 50V +VCC_CORE C609 10U 1206 10V C90 10U 1206 10V 1 C612 10U 1206 10V C660 0.1U 0603 50V
2
2
1
1
1
1
1
2
2
2
2
C642 10U 1206 10V
C641 10U 1206 10V
C643 10U 1206 10V
C88 10U 1206 10V
C621 10U 1206 10V
2
2
2
2
2
FOR D/T CPU VID
+5VS VCCPVID +5VS 1
A
2
FOR Mobile CPU VID
+5VS 1 VCCPVID
A
R602 10 0603 2
150mA
U506 1 3 2 IN EN GND MIC5248 SOT25 PG OUT 4 5 1 C600 1U 0603 2 2
R609 10K 0603 CPU_CORE_EN CPU_CORE_EN 28
R850 100K 0603 2
U520 1 2 3 4 5 VIN FC GND PG FB
1
300mA
PGND L EN SYNC ILIM 10 9 8 7 6 1
L539 2 10UH 1608 10%
1 C903 10U 1206 10V Title 2
C608 0.1U 0603 16V 10%
C904 10U 1206 10V
C905 0.1U 0603 16V 10%
TPS62003 PSOP10_0.5MM
1
1
2
2
2
1
PENTIUM4 (2/2)
Size Date: Document Number
8640
Sheet 5 of 32
1
Rev 01
Wednesday, August 28, 2002
5
4
3
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SIS M651/645DX(1/3)
A
AGP_ST0 AGP_ST1 AGP_ST2 AGP_AD[0..31]
AGP_ST0 10 AGP_ST1 10 AGP_ST2 10 AGP_AD[0..31] 10
AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31
AGP_SBA0
CPUAVSS CPUAVDD
HPCOMP HNCOMP HNCVREF
PHYAVSS PHYAVDD
HVREF
A
AH25 AJ25
AH27 AJ27
U21 T21 P21 N21 J17
B20 B19 A19
A7 F9 B7 M6 M5 M4 L3 L6 L4 K6 L2 K3 J3 K4 J2 J6 J4 J1 H6 F4 F1 G6 E3 F5 E2 E4 E1 D3 D4 C2 F7 C3 E6 B2 D5
D6 A3 D7 C5 A5 C6 D8 C7
U9A L27 CPUAVDD 1 2 +3VS 13 HCLK_SIS650 13 HCLK_SIS650# 4 4 4 4 4 4 4 H_RS#[0..2] H_LOCK# H_DEFER# H_TRDY# CPURST# CPUPWRGD H_BPRI# H_BR#0 HCLK_SIS650 AJ26 HCLK_SIS650# AH26 H_LOCK# H_DEFER# H_TRDY# CPURST# CPUPWRGD H_BPRI# H_BR#0 H_RS#2 H_RS#1 H_RS#0 4 4 4 4 4 4 H_REQ#[0..4] H_ADS# H_HITM# H_HIT# H_DRDY# H_DBSY# H_BNR# H_ADS# H_HITM# H_HIT# H_DRDY# H_DBSY# H_BNR# H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 4 HA#[3..31] 4 H_ADSTB#1 H_ADSTB#0 H_ADSTB#1 H_ADSTB#0 HA#31 HA#30 HA#29 HA#28 HA#27 HA#26 HA#25 HA#24 HA#23 HA#22 HA#21 HA#20 HA#19 HA#18 HA#17 HA#16 HA#15 HA#14 HA#13 HA#12 HA#11 HA#10 HA#9 HA#8 HA#7 HA#6 HA#5 HA#4 HA#3 U24 U26 V26 C20 D19 T27 U25 T24 T26 U29 V28 T28 U28 W26 V24 V27 W28 W29 W24 W25 Y27 AD24 AA24 AF26 AE25 AH28 AD26 AG29 AE26 AF28 AC24 AG28 AE29 AD28 AC25 AD27 AE28 AF27 AB24 AB26 AC28 AC26 AC29 AA26 AB28 AB27 AA25 AA29 AA28 Y26 Y24 Y28 CPUCLK CPUCLK# HLOCK# DEFER# HTRDY# CPURST# CPUPWRGD BPRI# BREQ0# RS2# RS1# RS0# ADS# HITM# HIT# DRDY# DBSY# BNR# HREQ4# HREQ3# HREQ2# HREQ1# HREQ0# ADSTB1# ADSTB0# HA31# HA30# HA29# HA28# HA27# HA26# HA25# HA24# HA23# HA22# HA21# HA20# HA19# HA18# HA17# HA16# HA15# HA14# HA13# HA12# HA11# HA10# HA9# HA8# HA7# HA6# HA5# HA4# HA3#
AGP_CBE#[0..3] AC/BE3# AC/BE2# AC/BE1# AC/BE0# AREQ#/VBCAD AGNT# AFRAME# AIRDY# ATRDY# ADEVSEL# ASERR# ASTOP# APAR RBF#/VBHCLK WBF#/VGPIO2 PIPE#/VGPIO3 AGP8XDET ADBIH ADBIL SB_STB SB_STB# F6 F3 H4 K5 C9 A6 G2 G1 G3 G4 H5 H1 H3 E8 F8 D9 D10 B3 C4 B5 A4 K1 L1 C1 D1 B10 M1 B9 A9 B8 A8 M3 M2 F20 F23 K24 P24 F21 F24 L24 N25 AGP_SBSTB AGP_SBSTB# AGP_ADSTB0 AGP_ADSTB0# AGP_ADSTB1 AGP_ADSTB1# AGP_CLK AGPRCOMP AGPAVDD1 AGPAVSS1 AGPAVDD2 AGPAVSS2 AGP_VREF AGP_CBE#3 AGP_CBE#2 AGP_CBE#1 AGP_CBE#0 AGP_REQ# AGP_GNT# AGP_FRAME# AGP_IRDY# AGP_TRDY# AGP_DEVSEL# AGP_SERR# AGP_STOP# AGP_PAR AGP_RBF# AGP_WBF# AGP_PIPE# 1 1 1
AGP_CBE#[0..3] 10
ST0 ST1 ST2 AD0/VBD7 AD1/VBD6 AD2/VBD5 AD3/VBD4 AD4/VBD3 AD5/VBD2 AD6/VBD1 AD7/VBD0 AD8/VAD6 AD9VAD5 AD10/VAD4 AD11/VAD7 AD12/VAD8 AD13/VAD9 AD14/VAD10 AD15/VAD11 AD16/VADE AD17/VAVSYN AD18/VAHSYNC AD19/VBD11 AD20/VBD10 AD21/VBD8 AD22/VBD9 AD23/VAD1 AD24/VAD0 AD25/VAD2 AD26/VAD3 AD27/VBDE AD28/VBCTL0 AD29/VBCTL1 AD30/VBHSYNC AD31/VBVSYNC
C103 0.01U 0603 2 2 CPUAVSS
120Z/100M 2012 C104 0.1U 0603 50V JL36 1 2 JP_NET20
C100 10U 1206 10V 4 H_RS#[0..2]
HPCOMP HNCOMP HCOMPVREF
1
1
1
CPUAVSS CPUAVDD
PHYAVSS PHYAVDD
HVREF0 HVREF1 HVREF2 HVREF3 HVREF4
SBA7 SBA6 SBA5 SBA4 SBA3 SBA2 SBA1 SBA0
AGP_REQ# 10,15 Check AGP_GNT# 10 AGP_FRAME# 10,15 AGP_IRDY# 10,15 AGP_TRDY# 10,15 AGP_DEVSEL# 10,15 AGP_SERR# 15 AGP_STOP# 10,15,16 AGP_PAR 10,15 AGP_RBF# 10,15 AGP_WBF# 10,15 AGP_PIPE# 10,15 TP516 TP522 TP520 AGP_SBSTB 15 AGP_SBSTB# 15 AGP_ADSTB0 10,15 AGP_ADSTB0# 10,15 AGP_ADSTB1 10,15 AGP_ADSTB1# 10,15 AGP_CLK 13
AGP_GNT# pull up?
L25 PHYAVDD 1 2
+3VS
C98 0.01U 0603 2 2 PHYAVSS
120Z/100M 2012 C99 0.1U 0603 50V JL37 1 2 JP_NET20
2
C768 10U 1206 10V
4
H_REQ#[0..4]
1
1
2
1
+VCC_CORE
B
4
HA#[3..31]
SiS651/646
AD_STB0/VAGCLK AD_STB0#/VAGCLK# AD_STB1/VBGCLK AD_STB1#/VBGCLK# AGPCLK AGPRCOMP AGPAVDD1 AGPVSS1 AGPVDD2 AGPVSS2 AGPVERF AGPVSSREF DSTBN3# DSTBN2# DSTBN1# DSTBN0# DSTBP3# DSTBP2# DSTBP1# DSTBP0#
B
1
R695 75 0603D 1% 2
1 C686 0.01U 0603 2
Change net name AGPVREF to AGP_VREF AC30. 4/11/2002 by Jim
connect to MAP17 pin
Keep away from high speed signals
HVREF
L34 AGP_VREF 10 DSTBN#[0..3] DSTBN#[0..3] 4 1 1 C138 0.01U 0603 DSTBP#[0..3] 2 2 DSTBP#[0..3] 4 AGPAVSS1 AGPAVDD1 1 2
+3VS
1
R694 150 0603D 1% 2
C685 0.01U 0603 2 2
C711 0.1U 0603 50V
DSTBN#3 DSTBN#2 DSTBN#1 DSTBN#0 DSTBP#3 DSTBP#2 DSTBP#1 DSTBP#0
Place this cap under 650 solder side
+VCC_CORE
120Z/100M 2012 C137 0.1U 0603 50V JL38 1 2 JP_NET20
1
1
1 C139 10U 1206 10V +3VS 1 C154 10U 1206 10V 2 2
FOR M650 ONLY
HD63# HD62# HD61# HD60# HD59# HD58# HD57# HD56# HD55# HD54# HD53# HD52# HD51# HD50# HD49# HD48# HD47# HD46# HD45# HD44# HD43# HD42# HD41# HD40# HD39# HD38# HD37# HD36# HD35# HD34# HD33# HD32# HD31# HD30# HD29# HD28# HD27# HD26# HD25# HD24# HD23# HD22# HD21# HD20# HD19# HD18# HD17# HD16# HD15# HD14# HD13# HD12# HD11# HD10# HD9# HD8# HD7# HD6# HD5# HD4# HD3# HD2# HD1# HD0#
M650 2X AGP mode VREF set from 0.39*VDDQ to 4.41VDDQ.
1 1 R97 150 0603D 1% 2 1 C110 0.01U 0603 2 HNCVREF 1 1 1
DBI3# DBI2# DBI1# DBI0#
L35 AGPAVDD2 SIS650 BGA540_77_85 1 C146 0.01U 0603 2 AGPAVSS2 DBI#[0..3] 4 2 1 1 2
B21 F19 A21 E19 D22 D20 B22 C22 B23 A23 D21 F22 D24 D23 C24 B24 E25 E23 D25 A25 C26 B26 B27 D26 B28 E26 F28 G25 F27 F26 G24 H24 G29 J26 G26 J25 H26 G28 H28 J24 K28 J29 K27 J28 M24 L26 K26 L25 L28 M26 P26 L29 N24 N26 M27 N28 P27 N29 R24 R28 M28 P28 R26 R29
+3VS
+1.5VS
E21 A27 H27 R25
R91 75 0603D 1% 2
2
AGP_VREF 1
C
4 1
HD#[0..63]
HD#[0..63]
DBI#3 DBI#2 DBI#1 DBI#0
C105 0.01U 0603 2
R158 301 0603 1% 2
R151 200/NA 0603 1%
DBI#[0..3]
120Z/100M 2012 C145 0.1U 0603 50V JL4 1 2 JP_NET20
HD#63 HD#62 HD#61 HD#60 HD#59 HD#58 HD#57 HD#56 HD#55 HD#54 HD#53 HD#52 HD#51 HD#50 HD#49 HD#48 HD#47 HD#46 HD#45 HD#44 HD#43 HD#42 HD#41 HD#40 HD#39 HD#38 HD#37 HD#36 HD#35 HD#34 HD#33 HD#32 HD#31 HD#30 HD#29 HD#28 HD#27 HD#26 HD#25 HD#24 HD#23 HD#22 HD#21 HD#20 HD#19 HD#18 HD#17 HD#16 HD#15 HD#14 HD#13 HD#12 HD#11 HD#10 HD#9 HD#8 HD#7 HD#6 HD#5 HD#4 HD#3 HD#2 HD#1 HD#0
C
+VCC_CORE 1 20
R92 2 1% 0603D HNCOMP 2
C168 0.1U 0603 50V 2
R154 200 0603 1% AGPRCOMP
FOR M650
R157 1 60.4 1% R156 1 2 1% 0603D 2 0603D
+3VS
60 OHM 1%
R93 1 110 1% 2 0603D HPCOMP
+1.5VS
60.4
112 OHM 1%
FOR 645DX
FOR SiS651 WITH SiS301LV ONLY
FC_VBD[0..11] FA4 AGP_AD19 AGP_AD20 AGP_AD22 AGP_AD21 8 7 6 5 1 2 3 4 FC_VBD11 FC_VBD10 FC_VBD9 FC_VBD8 FC_VBD[0..11] 9 FC_VAD[0..11] FA1 AGP_AD15 AGP_AD14 AGP_AD13 AGP_AD12 8 7 6 5 130OHM/100MHZ FA2 8 7 6 5 130OHM/100MHZ FA3 8 7 6 5 130OHM/100MHZ 1206 22P*4/NA CP6 4 3 2 1 4 3 2 1 1206 22P*4/NA CP5 4 3 2 1 1206 22P*4/NA CP4 1 2 3 4 FC_VAD11 FC_VAD10 FC_VAD9 FC_VAD8 FC_VAD[0..11] 9 AGP_AD18 AGP_AD17 AGP_AD30 AGP_AD31 FC_VBD7 FC_VBD6 FC_VBD5 FC_VBD4 AGP_SBA0 1 2 3 4 FC_VAD7 FC_VAD6 FC_VAD5 FC_VAD4 AGP_AD11 AGP_AD8 AGP_AD9 AGP_AD10 R12 R17 R25 R26 1 1 1 1 2 22 2 22 2 22 2 22 2 22 2 22 VAHSYNC VAVSYNC VBHSYNC VBVSYNC VBCLK VBGCLK VAHSYNC 9 VAVSYNC 9 2 VBHSYNC 9 VBVSYNC 9 VBCLK VBGCLK 9 9 2 AGP_ADSTB0# R526 1 2 22/NA 1 VAGCLK# C524 10P/NA 0603 10%
D
AGP_ADSTB0 R525 1
2 22 1
VAGCLK C541 10P/NA 0603 10%
VAGCLK
9
AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3
130OHM/100MHZ FA5 8 1 7 2 6 3 5 4 130OHM/100MHZ FA6 8 1 7 2 6 3 5 4 5 6 7 8 5 6 7 8 5 6 7 8 130OHM/100MHZ
R136 1
VAGCLK# 9
AGP_ADSTB1 R539 1 AGP_ADSTB1# R528 1 AGP_AD16 R532 1 1 1 1 1 1 1 1
2 22/NA VBGCLK# 2 0 0603 2 0 0603 2 0 0603 2 0 0603 2 0 0603 2 0 0603 2 0/NA0603 2 0/NA0603 VADE VBDE VBCTL0 VBCTL1 VBCAD VBHCLK
VBGCLK# 9 VADE VBDE VBCTL0 VBCTL1 VBCAD VBHCLK 9 9 9 9 9 9
D
AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7
FC_VBD3 FC_VBD2 FC_VBD1 FC_VBD0
AGP_AD26 AGP_AD25 AGP_AD23 AGP_AD24
1 2 3 4 5 6 7 8 5 6 7 8 5 6 7 8
FC_VAD3 FC_VAD2 FC_VAD1 FC_VAD0
AGP_AD27 R543 AGP_AD28 R530 AGP_AD29 R541 AGP_REQ#R553
1206 22P*4/NA CP3 4 3 2 1 4 3 2 1
1206 22P*4/NA CP2 4 3 2 1
1206 22P*4/NA CP1
AGP_RBF#R564 AGP_PIPE# R554 AGP_WBF# R563
Title
SIS M650/645DX (1/3)
Size Date:
1 2 3 4 5 6 7
Document Number
8640
Sheet
8
Rev 01 6 of 32
Wednesday, August 28, 2002
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
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SIS M650/645DX(2/3)
14 DDR_MD[0..63] DDR_MD[0..63] U9B DDR_MD0 DDR_MD1 DDR_MD2 DDR_MD3 DDR_MD4 DDR_MD5 DDR_MD6 DDR_MD7 DDR_DQM0 DDR_DQS0 DDR_MD8 DDR_MD9 DDR_MD10 DDR_MD11 DDR_MD12 DDR_MD13 DDR_MD14 DDR_MD15 DDR_DQM1 DDR_DQS1 DDR_MD16 DDR_MD17 DDR_MD18 DDR_MD19 DDR_MD20 DDR_MD21 DDR_MD22 DDR_MD23 DDR_DQM2 DDR_DQS2 DDR_MD24 DDR_MD25 DDR_MD26 DDR_MD27 DDR_MD28 DDR_MD29 DDR_MD30 DDR_MD31 DDR_DQM3 DDR_DQS3 DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_DQM4 DDR_DQM5 DDR_DQM6 DDR_DQM7 DDR_MD32 DDR_MD33 DDR_MD34 DDR_MD35 DDR_MD36 DDR_MD37 DDR_MD38 DDR_MD39 DDR_DQM4 DDR_DQS4 DDR_MD40 DDR_MD41 DDR_MD42 DDR_MD43 DDR_MD44 DDR_MD45 DDR_MD46 DDR_MD47 DDR_DQM5 DDR_DQS5 DDR_MD48 DDR_MD49 DDR_MD50 DDR_MD51 DDR_MD52 DDR_MD53 DDR_MD54 DDR_MD55 DDR_DQM6 DDR_DQS6 DDR_MD56 DDR_MD57 DDR_MD58 DDR_MD59 DDR_MD60 DDR_MD61 DDR_MD62 DDR_MD63 DDR_DQM7 DDR_DQS7 AJ23 AG22 AH21 AJ21 AD23 AE23 AF22 AF21 AD22 AH22 AD21 AG20 AE19 AF19 AE21 AD20 AD19 AH19 AF20 AH20 AF18 AG18 AH17 AD16 AD18 AD17 AF17 AJ17 AE17 AH18 AD14 AG14 AJ13 AE13 AJ15 AF14 AD13 AF13 AH13 AH14 AD10 AH10 AE9 AD8 AG10 AF10 AH9 AF9 AD9 AJ9 AH5 AG4 AE5 AH3 AG6 AF6 AF5 AF4 AH4 AJ3 AE4 AD6 AE2 AC5 AG2 AG1 AF3 AC6 AD4 AF2 AB6 AD3 AA6 AB3 AC4 AE1 AD2 AC1 AB4 AC2 MD0/SMD63 MD1/SMD30 MD2/SMD29 MD3/SMD59 MD4/SMD31 MD5/SMD62 MD6/SMD60 MD7/SMD28 DQM0/SMD61 DQS0/CSB0# MD8/SMD27 MD9/SMD58 MD10/SMD55 MD11/SMD23 MD12/SMD26 MD13/SMD57 MD14/SMD56 MD15/SMD24 DQM1/SMD25 DQS1/CSB1# MD16/SMD22 MD17/SMD53 MD18/SMD20 MD19SMD19 MD20/SMD54 MD21/SMD21 MD22/SMD51 MD23/SMD50 DQM2/SMD52 DQS2/CSB2# MD24/SMD18 MD25/SMD17 MD26/SDQM7 MD27/SDQM6 MD28/SMD49 MD29/SMD48 MD30/SDQM3 MD31/SDQM2 DQM3/SMD16 DQS3/CSB3# MD32/SDQM5 MD33/SDQM4 MD34/SMD47 MD35/SMD45 MD36/SDQM1 MD37/SDQM0 MD38/SMD46 MD39/SMD14 DQM4/SMD15 DQS4/CSB4# MD40/SMD13 MD41/SMD43 MD42/SMD42 MD43/SMD10 MD44/SMD44 MD45/SMD12 MD46/SMD41 MD47/SMD9 DQM5/SMD11 DQS5/CSB5# MD48/SMD40 MD49/SMD8 MD50/SMD37 MD51/SMD36 MD52/SMD39 MD53/SMD7 MD54/SMD6 MD55/SMD5 DQM6//SMD38 DQS6/CSB6# MD56/SMD35 MD57/SMD34 MD58/SMD1 MD59/SMD0 MD60/SMD4 MD61/SMD3 MD62/SMD33 MD63/SMD32 DQM7/SMD2 DQS7/CSB7# SIS650 BGA540_77_85 U9C DDR_MA[0..12] MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 SRAS# SCAS# SWE# AH11 AF12 AH12 AG12 AD12 AH15 AF15 AH16 AE15 AD15 AF11 AG8 AJ11 AG16 AF16 AH8 AJ7 AH7 DDR_MA0 DDR_MA1 DDR_MA2 DDR_MA3 DDR_MA4 DDR_MA5 DDR_MA6 DDR_MA7 DDR_MA8 DDR_MA9 DDR_MA10 DDR_BA0 DDR_BA1 DDR_MA11 DDR_MA12 DDR_RAS# DDR_CAS# DDR_WE# 13 DDR_MA[0..12] 14 15 15 15 15 15 15 15 ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZAD[0..15] ZCLK0 ZCLK0 ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZAD[0..15] ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZVREF VDDZCMP ZCMP_N ZCMP_P VSSZCMP Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS T4 R3 T5 T6 R2 R6 R1 R4 P4 N3 P5 P6 N1 N6 N2 N4 U3 V5 U4 U2 V6 W1 W2 V2 V1 V3 U6 U1 T3 T1 P1 P3 ZCLK VOSCI ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ROUT GOUT BOUT HSYNC VSYNC A12 B13 A13 F13 E13 D13 D12 B11 E12 A11 F12 E14 D14 F14 B12 C12 C13 C14 B15 A15 B14 A14 PID1 RSYNC PID2 VCOMP VRSET VVBWN DACAVDD1 DACAVSS1 DACAVDD2 DACAVSS2 DCLKAVDD DCLKAVSS ECLKAVDD ECLKAVSS HSYNC VSYNC DDCK DDDA R713 R710 R712 R711 1 1 1 1 2 2 2 2 33 33 100 100 C15 REFCLK0
A A
14 DDR_DQS[0..7]
DDR_DQS[0..7]
REFCLK0 13
NOT STUFF IN SiS645DX
CRT_RED CRT_GREEN CRT_BLUE CRT_HSYNC CRT_VSYNC CRT_DDCK CRT_DDDA PCI_INTA# CRT_RED 11,12 CRT_GREEN 11,12 CRT_BLUE 11,12 CRT_HSYNC 11,12 CRT_VSYNC 11,12 CRT_DDCK 11,12 CRT_DDDA 11,12 PCI_INTA# 9,10,15
NC IN SiS645DX
A10 TESTMODE2 F11 TESTMODE1 C11 TESTMODE0 Y3 PCIRST# W 4 PW ROK W 6 AUXOK E11 DLLEN# F10 ENTEST D11 TRAP1 E10 TRAP0
DDR_BA0 14 DDR_BA1 14
MA11 --> BANK SELECT 0 MA12 --> BANK SELECT 1 MA13 --> MEM_MA11 MA14 --> MEM_MA12
DDR_RAS# 14 DDR_CAS# 14 DDR_WE# 14
CS0# CS1# CS2# CS3# CS4# CS5#
AE7 AF7 AH6 AJ5 AF8 AD7
DDR_CS0# DDR_CS1# DDR_CS2# DDR_CS3# 1 1 TP517 TP518 1 2 3 4
14 DDR_DQM[0..7]
DDR_DQM[0..7]
DDR_CS0# 14 DDR_CS1# 14 DDR_CS2# 14 DDR_CS3# 14 8 +2.5V_DDR 7 RP8 6 470*4 5 1206 CKE0 14 CKE1 14 CKE2 14 CKE3 14 TP521 TP519 S3AUXSW# 16,24 SDRAMCLK 13 FWDSDCLKO 13
ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZVREF VDDZCMP ZCMP_N ZCMP_P VSSZCMP Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS
VGPIO0 VGPIO1 INTA# CSYNC RSYNC LSYNC VCOMP VRSET VVBWN DACAVDD1 DACAVSS1 DACAVDD2 DACAVSS2 DCLKAVDD DCLKAVSS ECLKAVDD ECLKAVSS
B
CKE0 CKE1 CKE2 CKE3 CKE4 CKE5 S3AUXSW# SDCLK FWDSDCLKO SDRCLKI
AB2 AA4 AB1 Y6 AA5 Y5 Y4 AA3 AD11 AE11 R728 1
CKE0 CKE1 CKE2 CKE3 S3AUXSW# SDRAMCLK 2 22 1 1 1
SIS650 BGA540_77_85
B
C745 10P/NA 0603
9,10,15,18,19,22,23 PCIRST# 16,24 PWROK 16 AUXOK TP16 TP515 TP15
SDAVDD SDAVSS
Y1 Y2
SDAVDD SDAVSS
PCIRST# PWROK AUXOK PID0 TRAP0 1 1 1 DLLEN# 1 1
1 R748 4.7K 0603D 2 C782 0.1U 0603 50V C770 0.1U 0603 50V 2 2
DDRAVDD DDRAVSS
AA1 AA2
DDRAVDD DDRAVSS
DDRVREFA DDRVREFB DRAM_SEL
AJ19 AH2 W3
DDRVREFA DDRVREFB DRAM_SEL
C
2
C
NOT STUFF IN SiS645DX
C755 VVBWN L532 VDDZCMP ZCMP_N ZCMP_P VSSZCMP R739 1 R751 1 2 56 2 56 2 1 2 VCOMP 1 C705 10U 1206 10V 1 +1.8VS 0603D 0.1U C733 2 0.1U 50V +1.25V_REF 1 1 L530 1 2 1 1 DACAVDD1 DACAVDD2 +1.8VS R144 0/NA 0603 R714 130 1% 0603D 2 R98 49.9 0603 1% 2 2 R755 150 0603D 1% 1 VRSET +2.5V_DDR 0603D +1.8VS 50V 1 2
C776 0.01U 0603 2
120Z/100M 2012 C779 0.1U 0603 50V JL5 1 2 JP_NET20
1
1
2
2
2
2
L41 DDRAVDD 1 2
+3VS Z1XAVDD 1
L39 2
+3VS DACAVSS2
1
1
1
JL6 1 2 JP_NET20 L32 ECLKAVDD 1 2 DACAVSS1 C203 10U 1206 10V
2
C189 0.01U 0603 2 2 DDRAVSS
120Z/100M 2012 C183 0.1U 0603 50V JL7 1 2 JP_NET20
C201 10U 1206 10V Z1XAVSS
C181 0.01U 0603 2 2
120Z/100M 2012 C187 0.1U 0603 50V JL8 1 2 JP_NET20
C113 0.01U 0603D 2 2
1
C757 0.1U 0603D 50V
120Z/100M 2012 C756 1U 0603
1
1
1
C111 0.01U 0603D DDRVREFA 2
C788 0.1U 0603D 50V ZVREF
NOT STUFF IN SiS645DX
PID0 PID1 R742 1 0 R740 1 0 R736 1 0 2 0603 2 0603 2 0603 LCD_ID0 LCD_ID1 LCD_ID2 LCD_ID0 11,12 LCD_ID1 11,12 LCD_ID2 11,12
1
C754 10U 1206 10V
2
R108 49.9 0603 1% 2
R754 150 0603D 1%
C787 0.1U 0603D 50V
PID2
1
1
1
1
1
1
+3VS
2
2
2
NB Hardwre Trap Table
+2.5V_DDR 1 +1.25V_REF C121 10U 1206 10V 1 R824 0/NA 0603 2 1 DLLEN# DRAM_SEL SDR R750 49.9 0603 1% 2 TRAP0 DDR
Enable Debug Mode Enable VGA Int function Reserved for Panel ID Reserved for Panel ID Reserved for Panel ID
C123 0.01U 0603 2 2 +3VS ECLKAVSS
D
L40 SDAVDD 1 2
+3VS Z4XAVDD 1
L38 2
120Z/100M 2012 C122 0.1U 0603 50V JL9 1 2 JP_NET20
0
Enable PLL
1
Disable PLL
Default
0 1(DDR) 0 1
Embedded pull-low (30 50K Ohm)
Yes Yes Yes
1
1
2
1
C781 0.01U 0603D 2
For 645DX
RSYNC CSYNC TRAP1
DDRVREFB 1 1 +3VS LSYNC R745 49.9 0603 1% 2
C182 0.01U 0603 2 2 SDAVSS
120Z/100M 2012 C188 0.1U 0603 50V JL10 1 2 JP_NET20
C200 10U 1206 10V Z4XAVSS
C186 0.01U 0603 2 2
120Z/100M 2012 C180 0.1U 0603 50V JL11 1 2 JP_NET20
C198 10U 1206 10V
L30 DCLKAVDD 1 2
C775 0.01U 0603D 1 2
Disable Debug Mode Disable VGA Int function Reserved for Panel ID Reserved for Panel ID Reserved for Panel ID
For M650
D
1
1
1
1
1
1
C116 0.01U 0603 2 2 DCLKAVSS
120Z/100M 2012 C115 0.1U 0603 50V JL12 1 2 JP_NET20
2
2
1
1
C119 10U 1206 10V
+3VS +3V DLLEN# DRAM_SEL TRAP0 RSYNC R118 R734 R746 R116 1 1 1 1 2 2 2 2 4.7K/NA 4.7K 4.7K/NA 4.7K
2
Title
SIS M650/M645DX (2/3)
Size Date: Document Number
8640
Sheet
8
Rev 01 7 of 32
Wednesday, August 28, 2002
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SIS M650/645DX(3/3)
A
+VCC_CORE
+1.8VS
A
1
1
1
1
1
1
1
1
C712 0.1U 0603 50V
C713 0.1U 0603 50V
C690 0.1U 0603 50V
C702 0.1U 0603 50V
C593 0.1U 0603 50V
C738 10U 1206 10V
C720 1U 0603
C709 1U 0603
1 C762 0.1U 0603 50V 2
2
2
2
2
2
2
2
+VCC_CORE
+1.8VS
+3VS
+3V +1.8V +3V
+VCC_CORE
+1.8V
1
1
1
1
1
H21 H22 J16 J20 J21 J22 K16 K17 K18 K19 K20 K21 L20 M20 N20 P20 R20 R21 T20 U20 V20 W 20 Y20 Y21 AA20 AA21 AA22 AB21 AB22
L12 L14 L15 L16 L18 M11 M19 N11 P19 R11 T19 U11 V19 W 11 W 13 W 15 W 17
W 10 Y11 Y13 Y15 Y17
+VCC_CORE U9D A16 A17 A18 B16 B17 B18 C16 C17 C18 D15 D16 D17 D18 E15 E16 E17 E18 F15 F16 F17 F18 AB5 AD5 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE22 V10 V11 W18 Y9 Y10 Y12 Y14 Y16 Y18 Y19 AA8 AA9 AA10 AA13 AA14 AA15 AA16 AA17 AB8 AB9 AB13 AB17 E5 E7 E9 G5 J5 L5 H8 H9 J8 J9 J10 J13 K9 K11 K13 L10 N9 N10 N5 R5 U5 W5 P9 P10 R9 R10 T9 T10 T11 VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20
IVDD_0 IVDD_1 IVDD_2 IVDD_3 IVDD_4 IVDD_5 IVDD_6 IVDD_7 IVDD_8 IVDD_9 IVDD_10 IVDD_11 IVDD_12 IVDD_13 IVDD_14 IVDD_15 IVDD_16
OVDD_0 OVDD_1 OVDD_2 PVDD_0 PVDD_1 PVDD_2 PVDD_3
PVDDM_0 PVDDM_1 PVDDM_2 PVDDM_3 PVDDM_4
VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49
PVDDZ
AUX1.8 AUX3.3 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84
U10 U9 A20 A22 A24 A26 C19 C21 C23 C25 C27 E20 E22 E24 F25 H25 K25 M25 P25 T25 V25 Y25 AB25 AD25 E27 G27 J27 L27 N27 R27 U27 W27 AA27 AC27 AE27 D29 F29 H29 K29 M29 P29 T29 V29 Y29 AB29 AD29 AF29 AE24 AG25 B4 B6 C8 C10 D2 F2 H2 K2 P2 T2 V4 AD1 AF1 AC3 AE3 AG3 AG5 AG7 AG9 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AJ4 AJ6 AJ8 AJ10 AJ12 AJ14 AJ16 AJ18 AJ20 AJ22 AJ24 AG27
C694 10U 1206 10V
C106 10U 1206 10V
C716 10U 1206 10V
C683 10U 1206 10V
C714 0.1U 0603 50V
1
C746 0.1U 0603 50V
J14 J15 K15 K10 K12 K14 M10
P11
2
2
2
2
2
+VCC_CORE
1
1
1
1
C108 1U 0603
C109 1U 0603
C689 1U 0603
C688 1U 0603
1
C687 0.1U 0603 50V
2
2
2
2
+VCC_CORE
1
1
+2.5V_DDR
B
C697 0.1U 0603 50V
C717 0.1U 0603 50V
1
C580 0.1U 0603 50V
B
2
2
For M650 Used(AGP 2X)
R756 0 0805 +3VS 1 2
VDDQ
VDDM_0 VDDM_1 VDDM_2 VDDM_3 VDDM_4 VDDM_5 VDDM_6 VDDM_7 VDDM_8 VDDM_9 VDDM_10 VDDM_11 VDDM_12 VDDM_13 VDDM_14 VDDM_15 VDDM_16 VDDM_17 VDDM_18 VDDM_19 VDDM_20 VDDM_21 VDDM_22 VDDM_23 VDDM_24 VDDM_25 VDDM_26 VDDM_27 VDDM_28 VDDM_29 VDDM_30 VDDM_31 VDDM_32 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDZ_0 VDDZ_1 VDDZ_2 VDDZ_3 VDDZ_4 VDDZ_5 VDDZ_6 VDDZ_7 VDDZ_8 VDDZ_9 VDDZ_10
+2.5V_DDR
1
1
1
2
1
C143 10U 1206 10V
C766 10U 1206 10V
C724 10U 1206 10V
C767 10U 1206 10V
1
2
C715 0.1U 0603 50V
2
2
2
2
+2.5V_DDR
1
1
1
1
SiS M650/645DX
C718 0.1U 0603 50V
C731 0.1U 0603 50V
C704 0.1U 0603 50V
C699 0.1U 0603 50V
1
2
C703 0.1U 0603 50V
2
2
2
2
+2.5V_DDR
1
1
1
1
C732 1U 0603
C741 1U 0603
C749 1U 0603
C773 1U 0603
1
2
C742 0.1U 0603 50V
2
2
2
2
VDDQ
1
1
1
1
1
2
1
+1.5VS
C
1 R757 0 0805
2
C760 0.1U 0603 50V
C761 0.1U 0603 50V
C771 0.1U 0603 50V
C765 0.1U 0603 50V
C734 0.1U 0603 50V
2
2
2
2
2
2
2
C192 10U 1206 10V
C
+3VS
For 645DX Used (AGP 4X)
1
1
1
+1.8VS
C101 10U 1206 10V
C726 1U 0603
C737 0.1U 0603 50V
1
C744 0.1U 0603 50V
2
2
2
+3VS
1
L17 PVDDP_0 L19 PVDDP_1 N19 PVDDP_2 R19 PVDDP_3 U19 PVDDP_4 W 19 PVDDP_5
M12 VSS_85 M13 VSS_86 M14 VSS_87 M15 VSS_88 M16 VSS_89 M17 VSS_90 M18 VSS_91 N12 VSS_92 N13 VSS_93 N14 VSS_94 N15 VSS_95 N16 VSS_96 N17 VSS_97 N18 VSS_98 P12 VSS_99 P13 VSS_100 P14 VSS_101 P15 VSS_102 P16 VSS_103 P17 VSS_104 P18 VSS_105 R12 VSS_106 R13 VSS_107 R14 VSS_108 R15 VSS_109 R16 VSS_110 R17 VSS_111 R18 VSS_112 T12 VSS_113 T13 VSS_114 T14 VSS_115 T15 VSS_116 T16 VSS_117 T17 VSS_118 T18 VSS_119 U12 VSS_120 U13 VSS_121 U14 VSS_122 U15 VSS_123 U16 VSS_124 U17 VSS_125 U18 VSS_126 V12 VSS_127 V13 VSS_128 V14 VSS_129 V15 VSS_130 V16 VSS_131 V17 VSS_132 V18 VSS_133 B25 VSS_134 C28 VSS_135 C29 VSS_136 D27 VSS_137 D28 VSS_138 E28 VSS_139 E29 VSS_140 AF23VSS_141 AF24VSS_142 AF25VSS_143 AG24 VSS_144 AG26 VSS_145 AH23VSS_146 AH24VSS_147
C752 0.1U 0603 50V
1
C723 0.1U 0603 50V
2
SIS650 BGA540_77_85
+3V
1
1
1
1
+1.8VS
2
2
C710 0.1U 0603 50V
C763 0.1U 0603 50V
C747 0.1U 0603 50V
C727 1U 0603
2
2
2
+1.8VS
1
1
1
1
2
D
C735 0.1U 0603 50V
C748 0.1U 0603 50V
C730 0.1U 0603 50V
C707 0.1U 0603 50V
1
C708 0.1U 0603 50V
2
D
2
2
2
2
2
Title 8640 Size Document Custom Number Date:
1 2 3 4 5 6 7
Sheet
8
Rev 01 8 of 32
Wednesday, August 28, 2002
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
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1
SiS302LV/CH7019
+DVDD 13 14.318MHZ_TV R573 1 10K/NA 2 0603 R601 1 10K/NA 2 0603 R598 1 10K/NA 2 0603 R597 1 10K/NA 2 0603 R570 1 10K/NA 2 0603
D
CLOSE TO CH7017 R607 14.318MHZ_TV R572 1 357K/NA2 0603 R600 1 357K/NA2 0603 1 R599 1 357K/NA2 0603 R608 1 357K/NA2 0603 R571 1 357K/NA2 0603 AS VB_GPIO2 VB_GPIO3 VB_GPIO4 VB_GPIO5 PCIRST# R575 2 0/NA 2 0 0603 R566 1 2 2 1 0 0603 1 2 X501 2 1 C585 22P/NA 0603 5% MOD_XOUT
Spread Range Selection
FS0 SR0 Spreading Range 1 0 +/- 1.50% 1 1 +/- 2.50% 0 0 +/- 1.25% 0 1 +/- 2.00% Input Frequency Modulation Rate
10 MHz to 20 MHz 10 MHz to 20 MHz 20 MHz to 35 MHz 20 MHz to 35 MHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz
D
14.318MHZ/NA C575 22P/NA 0603 5%
R596 1 0/NA 1 2 3 4 R574 1M/NA 0603
2 0603
MOD_XOUT +DVDD
2
U505 XIN XOUT FS0 VSS P2010/NA SO8 +DAC_VDD 2 0 0603 R47 1 1 0 R50 75/NA 0603 2 2 0603 1 2 3 4 75*4 1206 RP3 8 7 6 5 VDD SR0 MODOUT SSON 8 7 6 5
FS0 and SR0 HAVE INTERNAL PULL_UP 100K Ohm
1 R605 1M/NA 0603 2
7,10,15,18,19,22,23 PCIRST#
1
R561 1 6 6 +3VS 1 VBCLK VBDE VBCLK VBDE
CLOSE TO CH7017 6 VBCTL1 R542 1 2 0 0603
L521 2 120Z/100M 2012 1 1 C576 0.1U 0603 50V C606 0.1U 0603 50V +TVPLL_VCC L518 1 2 120Z/100M 2012 1 2 JL13 +VDDV 1 1
1
TV_LUMA +TVPLL_VDD 1 1 1 1 C568 10U 1206 25V C573 0.1U 0603 2 2 C588 10U 1206 25V C579 0.1U 0603 TVPLL_GND 1 1 R612 75/NA 0603 2 R616 1 0/NA 1 2 0805 2 TP5 TV_CRMA TV_COMP
TV_LUMA 11,12 TV_CRMA 11,12 TV_COMP 11,12 U507 5 4 NC0 NC1 GND0 VIN VOUT 1 2 3 +5VS
+3VS
2
2
L13 1 2 120Z/100M 2012
2
JP_NET20
TVPLL_GND +VREF1 2 C37 0.1U/NA 0603 R30 2 10K/NA 0603 1 2 0 0603 10K CH7019 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
MOD_XOUT
C41 10U 1206 25V
C39 0.1U 0603 50V
C613 0.1U 0603 50V +DAC_VDD
2
+3VS +DAC_VDD 1 1 2 L17 1 1 C70 10U 1206 25V 2 120Z/100M 2012 JL14 1 2 JP_NET20 1 1 1 L22 2 120Z/100M 2012 JL15 2 JP_NET20 1 +3VS AME8800AEEV/NA SOT25
1 C618 2.2U/NA 0805C
2
2
1
L11 1
C
R31 2 1
DVDD1 DE1 FLD/STL1 VREF1 VDDV P-OUT RESET* GPIO[5] GPIO[4] TVPLL_VDD TVPLL_VCC XO XI / FIN TVPLL_GND BCO/VSYNC C/HSYNC DAC_GND0 DACA[3] DACB[3] DACA[2[ DACB[2] DACA[1] DACB[1] DACA[0] DACB[0] DAC_GND1
120Z/100M/NA 2012 6 6 VBVSYNC VBHSYNC
140 CH7019 U7 SIS302LV R614 150 1% PQFP128A_0.5MM 1 2 0603D
C66 0.1U 0603 50V
C65 0.1U 0603 50V
2
2
2
C
VBVSYNC VBHSYNC R16 R15 1 FC_VBD[0..11] 1 2 0/NA 0603 FC_VBD0 FC_VBD1 FC_VBD2 FC_VBD3 FC_VBD4 FC_VBD5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
DAC_GND R801 2 6.04K 2.4K CH7019 R81 1 2K TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKTXCLK+ R74 2 1 0603 1U C87 2 0603 2
2
2
6 VBCTL0 6 FC_VBD[0..11]
2 0 0603
+DVDD 6 6 VBGCLK# VBGCLK
R540 1 VBGCLK# VBGCLK
2 0 0603
+DVDD 1 1 1 C554 10U/NA 1206 25V C557 0.1U/NA 0603 2 2
R552 1 C556 0.1U/NA 0603
2 0/NA 0603
FC_VBD6 FC_VBD7 FC_VBD8 FC_VBD9 FC_VBD10 FC_VBD11 FC_VAD0 FC_VAD1 FC_VAD2 FC_VAD3 FC_VAD4 FC_VAD5
CLOSE TO CH7017 DGND +DVDD 6 6 VAGCLK# VAGCLK R533 1 VAGCLK# VAGCLK 2 0 0603
FC_VAD6 FC_VAD7 FC_VAD8 FC_VAD9 FC_VAD10 FC_VAD11 FC_VAD[0..11]
B
6 FC_VAD[0..11] 6 VAHSYNC 6 VAVSYNC +3VS L9 1
V1 H1 DGND3 D1[0] D1[1] D1[2] D1[3] D1[4] D1[5] XCLK1* DGND2 XCLK1 D1[6] D1[7] D1[8] D1[9] D1[10] D1[11] DVDD3 DVDD2 D2[0] D2[1] D2[2] D2[3] D2[4] D2[5] XCLK2* DGND1 XCLK2 D2[6] D2[7] D2[8] D2[9] D2[10] D2[11] DGND0 H2 V2
SiS301LV/ Chrontel CH7019
ISET DAC_VDD VSWING LGND5 LDC0* LDC0 LVDD5 LDC1* LDC1 LGND4 LDC2* LDC2 LVDD4 LL1C* LL1C LGND3 LDC3* LDC3 LVDD3 LVDD2 LDC4* LDC4 LGND2 LDC5* LDC5 LVDD1 LDC6* LDC6 LGND1 LDC7* LDC7 LVDD0 LL2C* LL2C LGND0 LPLL_GND LPLLCAP LPLL_VDD
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
C64 0.1U 0603 50V
C63 0.1U 0603 50V
C82 10U 1206 25V
1
TXOUT0- 11,12 TXOUT0+ 11,12 +LVDD3 TXOUT1- 11,12 TXOUT1+ 11,12 TXOUT2- 11,12 TXOUT2+ 11,12 TXCLKTXCLK+ 2 0 0603 TX2OUT0- 11,12 TX2OUT0+ 11,12 2 TX2OUT1- 11,12 TX2OUT1+ 11,12 TX2OUT2- 11,12 TX2OUT2+ 11,12 11,12 11,12 LGND
R69 +LVDD2 1
1
2 0/NA 0603 1
+LVDD0/1 L20 2 120Z/100M 2012 JL16 1 2 JP_NET20 L19 1 2 120Z/100M 2012 JL17 2 JP_NET20
B
+3VS
1
+LPLL_VDD 1 1 C56 0.1U 0603 50V C81 10U 1206 25V LGND1 +LVDD0/1 1 1 1 2
TX2OUT0TX2OUT0+ TX2OUT1TX2OUT1+ TX2OUT2TX2OUT2+
2
C55 0.1U 0603 50V
2
+3VS
TX2CLKTX2CLK+
2
2
2
TX2CLK- 11,12 TX2CLK+ 11,12
C57 0.1U 0603 50V
C58 0.1U 0603 50V
C86 10U 1206 25V
1 L15 1
LGND2 +LPLL_VDD 1 1 1 C52 100P 0603 10% C54 0.1U 0603 50V C76 10U 1206 25V
+3VS 2 1 C53 0.1U 0603 50V +5VS 2
DVDD0 DE2 FLD/STL2 AS SPD SPC HIN VIN VREF2 SDD SDC DD1 DC1 DD2 DC2 V5V HOUT VOUT HPD HPINT* GPIO[0] GPIO[1] GPIO[2] GPIO[3] ENAVDD ENABKL
+DVDD 2 1 1 1
120Z/100M 2012 JL18 1 2 JP_NET20
2
2
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
1
GPIOA GPIOB GPIOC GPIOD DD2 DC2
120Z/100M 2012 JL19 2 JP_NET20
C29 10U 1206 25V
C30 0.1U 0603 2 2
C31 0.1U 0603
14x20 LQFP
C44 1 0.1U R46 1 1 TP4
1
HPD
DGND VADE R33 AS 1 2 0 0603
100 R53 1 0603
2
6
VADE
ENABKL ENAVDD
VB_GPIO3 VB_GPIO2 R49 1 1 PCIRST# 2 0 0603
ENPBLT 11,25 ENAVDD 11,12 2
R595 4.7K/NA 0603 2
1 R592 4.7K/NA 0603 R569
2 50V 0603 2 0 0603
LPLLGND PCI_INTA# 7,10,15
2
2
PCIRST# 7,10,15,18,19,22,23
DD2
1 0/NA
+VREF2 +3VS +3VS 1 L520 2 120Z/100M 2012 1 1 R555 4.7K 0603 6 6 VBCAD VBHCLK VBCAD VBHCLK 2 2 R565 4.7K/NA 0603 1 R578 2 0 0603D_DFS 2 R42
1 2 10K/NA 0603 C42 0.1U 50V 0603 R40 1 0603 R32
C49 0.1U/NA 0603 50V
1
2 0603
R567
1
2 33/NA 0603
GPIOC
C50 0.1U/NA 0603 50V DC2 +5VS 1 1 R593 1 0/NA 2 0603 R594 1 2 33/NA 0603 GPIOD
2
2
VGA
C96 10U 1206 25V
YUV TV 0 1
SCART 1 0
Normal TV 1 1
1
2 0
2
1 1
1
A
C559 27P/NA 0603 5%
1
2 10K/NA 0603 2 0 0603
+3VS GPIOA R35 R39 GPIOB 1 1 2 10K/NA 0603 2 4.7K/NA 0603 2 4.7K/NA 0603 2 4.7K/NA 0603
2
+3VS
C43 0.1U 0603 50V
GPIOA GPIOB
0 0
C572 27P/NA 0603 5%
R36
GPIOC
+3VS
0 0 Normal PAL 525I
0 1 PAL-M 525P
1 0 PAL-N 750P
1
A
GPIOD Normal TV YUV TV
1 Normal NTSC 1080I
2
2
R589 1 R588 1
+3VS
Title SIS 302LV Size Date:
5 4 3 2
Document Number
8640 Sheet 9 of
1
Rev 01 32
Wednesday, August 28, 2002
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
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3
2
1
nVIDIA MAP17(1/2)
D
VDD_MEM2.5
Place under the GPU
6 AGP_AD[0..31] AGP_AD[0..31] U6A AGP_AD0 AD30 AGP_AD1 AE30 AGP_AD2 AD29 AGP_AD3 AE29 AGP_AD4 AD28 AGP_AD5 AG30 AGP_AD6 AF28 AGP_AD7 AG29 AGP_AD8 AH30 AGP_AD9 AC28 AGP_AD10 AH29 AGP_AD11 AE28 AGP_AD12 AJ30 AGP_AD13 AG28 AGP_AD14 AK30 AGP_AD15 AG27 AGP_AD16 AH23 AGP_AD17 AJ24 AGP_AD18 AH22 AGP_AD19 AK24 AGP_AD20 AH21 AGP_AD21 AJ22 AGP_AD22 AH20 AGP_AD23 AK22 AGP_AD24 AG21 AGP_AD25 AJ19 AGP_AD26 AG18 AGP_AD27 AK19 AGP_AD28 AG19 AGP_AD29 AJ18 AGP_AD30 AF19 AGP_AD31 AK18 6 AGP_CBE#[0..3] AGP_CBE#[0..3] AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 66M_AGP PCIRST# AH28 AJ27 AK25 AF21 AJ12 AH11 PCIAD0 PCIAD1 PCIAD2 PCIAD3 PCIAD4 PCIAD5 PCIAD6 PCIAD7 PCIAD8 PCIAD9 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCICBE#0 PCICBE#1 PCICBE#2 PCICBE#3 PCICLK PCIRST# PCIGNT# PCIREQ# VDDAGP VDDAGP VDDAGP VDDAGP VDDAGP VDDAGP VDDAGP VDDAGP VDDAGP VDDAGP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VD50CLAMP VD50CLAMP AG14 AK14 AG17 AK17 AG20 AK20 AK23 AK26 AK29 AF30 L6 P6 U6 Y6 D11 F11 AE11 D14 F14 AE14 D17 F17 AE17 D20 F20 AE20 L25 P25 U25 Y25 L27 P27 U27 Y27 D4 AG11 +1.5VS A1 A10 A11 A12 A13 A14 A15 A16 A17 A19 A2 A20 A21 A22 A23 A25 A26 A27 A28 A29 A3 A30 AA28 AA29 AA30 AA4 AA5 AB28 AB29 AB30 B1 B13 B15 B16 B18 B19 B21 B22 B24 B25 B27 B28 B3 B30 C1 C10 C13 C14 C15 C16 C17 C18 C19 C2 C22 C23 C24 C25 C26 C27 C28 C29 C3 C30 D1 D10 D12 D15 D16 D18 D19 D2 D21 D27 D29 D30 E10 E13 E15 E16 E18 E19 E21 E28 E30 F29 F30 G28 G29 G30 H28 H30 J2 J29 J30 K26 K27 K29 K30 L28 L30 M26 M27 M28 M29 M30 N26 N27 N28 N29 N30 P28 P30 R26 R27 R28 R30 T26 T27 T28 U6B NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC MAP17 BGA548_144_1MM VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBIO VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC VDDFBC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC FBDQS0 FBDQS1 FBDQS1 FBDQS4 FBDQS7 FBD33 FBD63 FBD8 FBD8 FBD1 FBAWE# FBARAS# FBACAS# FBAA0 FBAA0 FBVREF FBCLK1# FBCLK1 FBCLK0# FBCLK0 E4 G4 J4 AB4 1 AD4 AF4 D5 F5 AE5 AG5 E6 AF6 D7 AG7 D9 AG9 1 D22 AG22 1 D24 AG24 E25 AF25 D26 F26 AE26 AG26 E27 G27 J27 AB27 AD27 AF27 G6 J6 AB6 AD6 F7 AE7 F9 AE9 F22 AE22 F24 AE24 G25 J25 AB25 AD25 Y7 AB7 AD7 AF7 B8 E9 G9 AD9 AF9 K10 L10 M10 N10 P10 R10 T10 U10 V10 W10 Y10 AA10 B11 E11 T29 T30 U28 U30 V26 V27 V28 V29 V30 V3 W26 W27 W28 W29 W30 Y28 Y30 C4 R29 F28 K28 AA26 E12 E3 D13 D3 J28 AA27 D28 C11 B12 C12 B10 A24 A18 A4 B4 C20 C21 FBVREF -FBACLK1 FBACLK1 -FBACLK0 FBACLK0
D
Place under the GPU
VDDFBIO TP7 2 C525 4.7U 0805 +80-20% C515 4.7U 0805 +80-20% C542 0.1U 0603 50V Y11 AA11 AD11 AF11 AJ11 K12 L12 M12 N12 P12 R12 T12 U12 V12 W12 Y12 AA12 K13 L13 M13 N13 P13 R13 T13 U13 V13 W13 Y13 AA13 B14 E14 G14 K14 L14 M14 N14 P14 R14 T14 U14 V14 W14 Y14 AA14 AD14 AF14 AJ14 K15 L15 M15 N15 P15 R15 T15 U15 V15 W15 Y15 AA15 K16 L16 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16 B17 E17 G17 K17 L17 M17 N17 P17 R17 T17 U17 V17 W17 Y17 AA17 TP504 1 AD17 AF17 AJ17 K18 L18 M18 N18 P18 R18 T18 U18 V18 W18 Y18 1 1 1 U6C GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AA18 K19 L19 M19 N19 P19 R19 T19 U19 V19 W19 Y19 AA19 B20 E20 G20 K20 L20 M20 N20 P20 R20 T20 U20 V20 W20 Y20 AA20 AD20 AF20 AJ20 K21 L21 M21 N21 P21 R21 T21 U21 V21 W21 Y21 AA21 E22 G22 AD22 AF22 B23 AJ23 E24 G24 J24 L24 P24 U24 Y24 AB24 AD24 AF24 D25 F25 AE25 AG25 B26 E26 G26 J26 L26 P26 U26 Y26 AB26 AD26 AF26 AJ26 F27 AE27 B29 E29 H29 L29 P29 U29 Y29 AC29 AF29 AJ29 K11 L11 M11 N11 P11 R11 T11 U11 V11 W11 AH12 AH13 1 G11
1
1
1
C28 0.022U 0603 25V 10%
C529 0.022U 0603 25V 10%
C23 0.022U 0603 25V 10%
1
C552 0.022U 0603 25V 10%
2
2
2
2
2
1
1
Place on solder side under the BGA
+1.2VS 1 1 1 1 1 C589 470P 0603 10% C590 470P 0603 10% C591 470P 0603 10% C535 2200P 0603 2 2 C534 2200P 0603 2 1 C553 2200P 0603 MSPSEL3 C570 4700P 0603 2 MSPSEL2
C517 470P 0603 10%
C521 470P 0603 10%
1 C607 470P 0603 10% 1 2
2
1
1
2
2
2
TP501 2
1
1
1
1
C537 4700P 0603 2
C526 4700P 0603 2
C522 4700P 0603 2 C538 0.022U 0603 25V 10% 1 2
1 C598 4700P 0603 C546 0.022U 0603 25V 10%
TP508
C533 4700P 0603 2 2
C578 4700P 0603 2
C577 4700P 0603
1
1
2
C558 0.022U 0603 25V 10%
C571 0.022U 0603 25V 10%
C532 0.022U 0603 25V 10%
C896 10U 1206 10V
C897 10U 1206 10V
C898 10U 1206 10V
2
2
2
2
2
Place close to the BGA
+5VS 1 C605 0.1U 0603 50V
2
C518 0.022U 0603 25V 10%
C516 0.022U 0603 25V 10%
1
1
1
1
1
1
2
2
2
1
2
VDD_MEM2.5
1
2
C
C531 4.7U 0805 +80-20%
1 C547 0.1U 0603 50V
C
2
13 66M_AGP 7,9,15,18,19,22,23 PCIRST# 6 6,15 AGP_GNT# AGP_REQ#
Place on solder - north
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 AGP_CAL_PD AGP_CAL_PU AGP_DBI_LO AGP_MB_DET# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND TESTMODE E1 H1 AC1 AF1 L4 Y4 AH15 AH14 AH19 AK13 B2 E2 H2 AC2 AF2 AJ2 F4 AE4 B5 E5 G5 J5 L5 Y5 AB5 AD5 AF5 AJ5 D6 F6 AE6 AG6 E7 G7 J7 L7 P7 U7 R56 AJ3 1 10K 0603 2 1 1 1 1 TP505 TP507 TP502 TP1 +3VS 1 1 1 1 C614 4700P 0603 2 2 C603 0.022U 0603 25V 10% C67 0.022U 0603 25V 10% C68 4700P 0603 2 MSPSEL0
1
1
2
1
AGP_GNT# AG12 AGP_REQ# AK12
C543 4700P 0603 2 2
C536 4700P 0603 2
C595 4700P 0603 2 1
1 C584 4700P 0603
2
2
2
2
7,9,15 6,15 6,15 6,15 6 AGP_ST0 6 AGP_ST1 6 AGP_ST2 6,15 6,15 6,15 6,15 AGP_ADSTB1 AGP_ADSTB1# AGP_ADSTB0 AGP_ADSTB0# 1
PCI_INTA# AGP_RBF# AGP_WBF# AGP_PIPE#
PCI_INTA# AGP_RBF# AGP_WBF# AGP_PIPE# AGP_ST0 AGP_ST1 AGP_ST2
AK11 AJ13 AG15 AF18 AF12 AF13 AG13
PCIINTA# AGPRBF# AGPWBF# AGPPIPE# AGPST0 AGPST1 AGPST2 AGPADSTB1 AGPADSTB1# AGPADSTB0 AGPADSTB0# AGPSBA0 AGPSBA1 AGPSBA2 AGPSBA3 AGPSBA4 AGPSBA5 AGPSBA6 AGPSBA7 AGPSBSTB AGPSBSTB# AGPBUSY# AGPSTOP# AGPVREF MAP17 BGA548_144_1MM
AGP_ADSTB1 AK21 AGP_ADSTB1# AJ21 AGP_ADSTB0 AK28 AGP_ADSTB0# AJ28 1 R14 220K 0603 2 2 R20 220K 0603 +3VS 1 R591 10K 0603 2 AH16 AH17 AGP_BUSY# AF10 N_AGP_STOP#AG10 AGP_VREF AC30 AJ15 AF15 AK15 AG16 AK16 AF16 AJ16 AH18
VDD_MEM2.5 R45 120/NA 2 0603 1 FBACLK1 R43 100/NA 0603 R48 VDD_MEM2.5 R19 120/NA 2 0603 1 FBACLK0 R24 100/NA 0603 R27 1 R29 1 1K 0603 2 1 FBVREF R28 1K 0603 2 120/NA 2 0603 2 -FBACLK0 1 120/NA 2 0603 2 -FBACLK1
2
6,15 AGP_FRAME# 6,15 AGP_IRDY# 6,15 AGP_TRDY# 6,15 AGP_DEVSEL# 6,15,16 AGP_STOP# 6,15 AGP_PAR
AGP_FRAME# AH24 AGP_IRDY# AJ25 AGP_TRDY# AH25 AGP_DEVSEL# AK27 AGP_STOP# AH26 AGP_PAR AH27
PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# PCISTOP# PCIPAR
Place on solder - south
2
1
1
1
C599 0.022U 0603 25V 10%
C592 0.022U 0603 25V 10%
C528 0.022U 0603 25V 10%
C594 0.022U 0603 25V 10%
1
C583 0.022U 0603 25V 10%
B
1
MSPSEL1
B
6 AGP_VREF
FOR MAP17 ONLY
MAP17 4X AGP mode VREF set from 0.48*VDDQ to 0.52*VDDQ.
+3VS +1.5VS R590 10K 1 2 R1 1K 0603 1% AGP_VREF 2 R51 1 10K 2
1
TP509
1
0603 AGP_BUSY# 0603 SUS_STAT# SUS_STAT# 11 1 R529 2 10K 0603
MAP17 BGA548_144_1MM
1
R2 1K 0603 1% 2
1 C2 0.1U 0603 50V 1 10K 0603
2
R838 2 MSPSEL0 1
R839 2 10K/NA 0603 R841 2 MSPSEL1 1 10K 0603 R843 2 MSPSEL2 1 10K/NA 0603 R845 2 MSPSEL3 1 10K/NA 0603 2 PAMCFG3 PAMCFG3 11 2 PAMCFG2 PAMCFG2 11 2 PAMCFG1 PAMCFG1 11 PAMCFG0 PAMCFG0 11
A
R840 1 10K/NA 0603 R842 1 10K 0603 RAM_CFG[3:0] 0111: 2Mx32 DDR SDRAM, DQS per byte, dll-on, low drive streng th 1101: 4Mx32 DDR SDRAM, DQS per byte, dll-on, low drive streng th 1111: 4Mx32 DDR SDRAM, DQS per byte, dll-on, high drive strength DEFAULT 1 10K 0603
5 4
A
R844
Title
nVIDIA MAP17 (1/2)
Size Date:
3 2
Document Number
8640
Sheet 10 of
1
Rev 01 32
Wednesday, August 28, 2002
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
5
4
3 GPIO0:General purpose I/O GPIO1:General purpose I/O GPIO2:Provid backlight enable. GPIO3:Provid panel power enable. GPIO4:Panel power good signal to GPU. GPIO5:Provid spread spectrum support. GPIO6:Provid hardware suspend signal for mobile system.Active low. GPIO7:Dynamic core voltage power control. ( 0:VDD=1.1V, 1:VDD=1.5V)
2
1
+5VS U6E R41 9,25 ENPBLT 9,12 ENAVDD ENPBLT ENAVDD 1 2 0 0603 TP2 GPIO5 SUS_STAT# R54 A3V 1 2 0 0603 TP6 L16 1 2 120Z/100M 1608 1 C84 4.7U 0805 +80-20% GPIO0 TP3 1 C6 A6 A7 A8 GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 GPIOD6 GPIOD7 I2C2SDA I2C2SCL TXD0# TXD0 TXD1# TXD1 TXD2# TXD2 IFP0IOAVDD IFP0IOBVDD IFP0VREF IFP0RSET TXD3# TXD3 TXC0 TXC0# TXD4# TXD4 TXD5# TXD5 L21 1 1 C89 4.7U 0805 +80-20% 2 120Z/100M 1608 1 1 C85 4.7U 0805 +80-20% C78 4700P 0603 2 2 1 C60 470P 0603 10% V2 IFP0PLLGND TXD8# TXD8 M1 1 L2 R78 10K 0603 L1 IFP1IOVDD IFP1VREF IFP1RSET TXC2 TXC2# TXD9# TXD9 TXD10# TXD10 M3 N3 M4 M5 N4 N5 L3 K3 IFP0PLLVDD V1 IFP0PLLVDD TXD6# TXD6 TXD7# TXD7 TXC1 TXC1# AJ6 AK6 P4 P5 R4 R5 P3 R3 P1 P2 K2 K1 U4 U5 T3 U3 V4 V5 W4 W5 T5 T4 TX2CLK+ TX2CLKTXCLK+ TXCLKTX2OUT0TX2OUT0+ TX2OUT1TX2OUT1+ TX2OUT2TX2OUT2+ TXCLK+ TXCLK9,12 9,12
D
nVIDIA MAP17(2/2)
U6D B7 A5 B6
D
Check!
I2C2SDA I2C2SCL
R649 1 2.2K R701 1 2.2K TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+
2 0603 2 0603
R0A-->R01
10 SUS_STAT#
1 C9 B9 C5 1 F3
TXOUT0- 9,12 TXOUT0+ 9,12 TXOUT1- 9,12 TXOUT1+ 9,12 TXOUT2- 9,12 TXOUT2+ 9,12
Close to GPU
C77 4700P 0603 2 2 C59 470P 0603 10% 0.047U 0603 C83 1 1 1 1
IFP0IOAVDD IFP0IOBVDD 2 IFP0VREF R68 2 1K IFP0RSET 0603 1%
T1 U1 R2 R1
LVDS CH1
VIPPCLK VIPHCLK VIPHCTL VIPHAD0 VIPHAD1 ROMA14 ROMA15 ROMCS# BUFRST# DACVDD DACVREF DACRSET
7,12 LCD_ID2 12 LCD_ID3
LCD_ID2 LCD_ID3
C8 C7 J1 F2 AH2
VIPD0 VIPD1 VIPD2 VIPD3 VIPD4 VIPD5 VIPD6 VIPD7 I2C0SDA I2C0SCL DDCSCL/I2C1SCL DDCSDA/I2C1SDA
K4 J3 H3 K5 G2 G1 F1 G3 AJ4 AK4 AH5 AH4
LCD_ID0 LCD_ID1 ROMTYPE1 PCI_DEVID2 PCI_DEVID0 PCI_DEVID1 CRYSTAL1 AGP_FASTWR R900 2.2K 0603 1 2 1 2 R901 2.2K 0603 CRT_DDCK CRT_DDDA
LCD_ID0 7,12 LCD_ID1 7,12
+5VS
2
R0A-->R01
+2.8VS CRT_DDCK 7,12 CRT_DDDA 7,12
U2 T2
A3V A9 L10 1 2 120Z/100M 1608 1 1 1 1
IFP0IOBGND IFP0IOAGND
TX2OUT0- 9,12 TX2OUT0+ 9,12 TX2OUT1- 9,12 TX2OUT1+ 9,12 TX2OUT2- 9,12 TX2OUT2+ 9,12
Close to GPU
DACVDD DACVREF DACRSET
AK10 AK9 AJ8
LVDS CH2
Place close together
C33 4.7U 0805 +80-20%
C36 4700P 0603 2 2
C35 470P 0603 10%
C34 0.01U 0603 2 2
CRTHSYNC R587 113 0603 1% AK8 DACGND PLLVDD CRTVSYNC
1
AH10 AH9
CRT_HSYNC CRT_VSYNC
CRT_HSYNC 7,12 2 CRT_VSYNC 7,12
2
2
TX2CLK+ 9,12 TX2CLK- 9,12
DACRED
AJ9
CRT_RED
CRT_RED 7,12
L12 1 1 C48 4.7U 0805 +80-20% 2 120Z/100M 1608 1 1 C47 4.7U 0805 +80-20% C45 470P 0603 10% 1 C46 470P 0603 10% PLLVDD AK5
A3V 10 PAMCFG0 10 PAMCFG1 10 PAMCFG2 10 PAMCFG3 1
R77
C
PCI_AD SUB_VENDOR PAMCFG0 PAMCFG1 PAMCFG2 PAMCFG3 CRYSTAL0 TVMODE0 TVMODE1 AGP_4X ROMTYPE0 BUS_TYPE
AK2 AK3 AH3 AJ1 AG1 AG2 AD3 AE1 AE3 AE2 AG3 AH1
DVOD0 DVOD1 DVOD2 DVOD3 DVOD4 DVOD5 DVOD6 DVOD7 DVOD8 DVOD9 DVOD10 DVOD11
2
2
2
2
DACGREEN
AJ10
CRT_GREEN
CRT_GREEN 7,12
2
DAC2RED M2 N1 1 DACBLUE AH8 CRT_BLUE CRT_BLUE 7,12 R79 10K 0603 2 IFP1IOGND IFP1PLLVDD DAC2GREEN DAC2BLUE
Y2 AA2 W3
TV_CRMA TV_LUMA TV_COMP
TV_CRMA 9,12 TV_LUMA 9,12 TV_COMP 9,12
C
10K 1% DVOVREF 1 R72 10K 1% 2 PCI_DEVID3 2 AB1 AC3 AB3 AK1 AD2 AD1 DVOCLKIN AB2 1 XTALSSIN AH7 R617 10K 0603 2 AJ7 DVOVREF DVOVSYNC DVOHSYNC DVODE DVOCLKOUT DVOCLKOUT# DVOCLKIN
1
C62 0.047U 0603 2
R37 ENPBLT 1 10K 0603 R34 ENAVDD 1 10K 0603 R581 GPIO0 1 10K 0603 R582 GPIO5 1 10K 0603 2 2 2 2 N2 IFP1PLLGND DAC2VDD DAC2VREF DAC2RSET CRT2HSYNC CRT2VSYNC W1 DAC2GND MAP17 BGA548_144_1MM AA3 Y3
+3VS VDDDVO VDDDVO AF3 AG4 1 C601 4700P 0603 XTALSOUTBUFF AH6 AK7 XTALSOUTBUFF 2 L18 A3V 1 2 120Z/100M 1608 R84 1 C69 0.01U 0603 DAC2VDD
AA1
1
1
1
1
DAC2VREF Y1 2 DAC2RSET W2 63.4 0603 1%
C80 4.7U 0805 +80-20%
C79 4700P 0603 2 2
C61 470P 0603 10%
2
XTALSSIN XTALIN MAP17 BGA548_144_1MM XTALOUT
Keep close to the nVidia +3VS
L14 1 2 120Z/100M 2012
A3V
R38 REFOUT 1 0/NA 0603 2 1 C40 18P 0603 25V 10% 1
X1 3 2 4 1 C38 18P 0603 25V 10%
27MHZ 2
LOGIC 0
PCI_AD R57
2
LOGIC 1
+3VS 1 2 10K 0603 PCI_AD_SWAP SUB_VENDOR 0: REVERSED 1: NORMAL DEFAULT
2
B
R55
1
2 10K 0603
SUB_VENDOR
0: system BIOS 1: adapter BIOS DEFAULT
Check!
B
+3VS 1
R579 2 1 10 0603 C545 4.7U 0805 +80-20% 1 C586 0.1U 0603 50V LSB R613 1 2 10K 0603 CRYSTAL0 CRYSTAL1 R63 1 2 10K 0603 CRYSTAL[1:0] [VIPD6:DVOD6] 00: 13.5MHz 01: 14.318 MHz 10: 27 MHz 11: unknown 00: SECAM 01: NTSC 10: PAL 11: VGA 0: enabled 1: disabled 0: enabled 1: disabled 2
2
Modulation seletion mode
MSB
DEFAULT
Spread 1.25% 2.50% 5.00% 10.0% STOP Fout 0 Enable
S2
(GPIO0)
S3
(GPIO5) I2C2SCL 1
0 0 1 1
0 1 0 1
I2C2SDA 1 0/NA 0603
R534 0/NA 2
R531 1 1 C548 0.001U 0603 20%
2
1K 0603 1
LSB MSB C527 0.01U 0603
R630 R632
1 1
2 10K/NA 0603 2 10K 0603
TVMODE0 TVMODE1
R631 R633
1 1
2 10K 0603 2 10K/NA 0603
TVMODE[1:0]
DEFAULT
U503 R538 2 2 4 5 10 R537 0 0603 1 SUS_STAT# GPIO0 GPIO5 6 9 14 11 17 16 1 2 D_C STOP SSON S0 S1 S2 S3 R0 R1 OSCin OSCout
0603 AVDD DVDD LF FOUT REFout 3 12 7 22 15 20 R580 1 2
AGP4x R629 1 2 10K 0603 AGP_4X
DEFAULT
2 22/NA 2
0603 XTALSSIN 0603 REFOUT LSB
2
R70
1
2 10K 0603
AGP_FASTWR R82
1
2 10K/NA 0603
AGP_FW
DEFAULT
1 Disable R0 R1 S0 S1 Fout X
A
R568 1
R65 R66 R584
1 1 1 1
2 10K 0603 2 10K/NA 0603 2 10K/NA 0603 2 10K 0603
PCI_DEVID0 PCI_DEVID1 PCI_DEVID2 PCI_DEVID3
R64 R67 R583 R627
1 1 1 1
2 10K/NA 0603 PCI_DEVID[3:0] 2 10K 2 10K 0603 0603
A
Place these resistors close to U1 OVDD OVSS AVSS DVSS 1 19 18 8 13 2
0110: NV17-MAP DEFAULT
X 1
0 0
0
Power down mode
0
1 1x Fin
SM530 TSSOP20 XTALSOUTBUFF 1 C555 18P/NA 25V 0603D 10% 1 X502 3 2 4
C587 0.1U 0603 50V
MSB
R628
2 10K/NA 0603
Power down mode : SO S1 S2 S3 Fout 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 Factory Test Hi-z 0 1
BUS_TYPE
R61
1
2 10K
0603
BUS_TYPE
0: PCI 1: AGP
DEFAULT
ALT CLK GEN W245-30 CAN I2C CONTROL
1 C551 18P/NA 25V 10% 0603D LSB R636 R62 MSB 1 1 2 10K 2 10K 0603 0603 ROMTYPE0 ROMTYPE1 R637 R83 1 1 2 10K/NA 0603 2 10K/NA 0603 ROMTYPE[1:0] 00: parallel DEFAULT 01: serial AT25F 10: serial SST45V 11: serial future Title 2
27MHZ/NA 2
nVIDIA MAP17 (2/2)
Size Date:
5 4 3 2
Document Number
8640
Sheet 11 of 32
1
Rev 01
Wednesday, August 28, 2002
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
5
4
3
+3VS 1 2 2 1 2 D504 D1 GND_TV BAV99/NA 3 BAV99/NA 3 1 D2 GND_TV BAV99/NA 3 L7 120Z/100M 1608 1 2 C17 33P 1 0603 50V 2
2
1
LCD & CRT INTERFACE
GND_TV
S-VIDEO
R0A-->R01
+5VA J3 1 2 3 4 5 6 7 GND1 GND2 GND3 MINI-DIN/7P C10828-107XX 1 2 3 4 5 6 7 GND1 GND2 GND3
TV_COMP
TV_COMP 9,11
1
2
74VHC164
D
U511 24 LED_DATA LED_DATA 1 2 A B QA QB QC QD QE QF QG QH VCC 3 4 5 6 10 11 12 13 14 1 C664 0.1U 0603 50V R902 R903 R904 R905 R906 R907 R908 R909 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 0603 0603 0603 0603 0603 0603 0603 0603 SCROLL# NUM# CAP# MPM_LED# AC_POWER# BATT_POWER# BATT_R# BATT_G# SCROLL# 24 NUM# 24 CAP# 24 MPM_LED# 24 AC_POWER# 25 BATT_R# 25 BATT_G# 25
C513 33P 0603 50V L510 120Z/100M 1608 1 2 1 L8 C15 C5 270P 0603 10% 1 2 120Z/100M 1608 33P 0603 50V 1 2 1 1 C519 100P 0603 10% C22 100P 0603 10% 1 C20 100P 0603 10% 4 3 2 1
D
TV_CRMA TV_LUMA TV_CRMA 9,11 TV_LUMA 9,11 RP505 75*4 1206
24 LED_CLK 24 H8_RESET#
LED_CLK H8_RESET#
8 9 7
CLK CLR GND
1
1
74VHC164 TSSOP14
C503 270P 0603 10%
C4 270P 0603 10%
1
2
2
2
2
2
L501 2 JP_BEAD_DFS GND 5 6 7 8 GND
2
GND_TV
LCD 14" 330mA,15"800mA Check!
Need to check the current capa city of signal wire ??
LCDVCC J11 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND1 GND2 MA/20PX2/ST ACES 87216-4000 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 LCDVCC L1 120Z/100M 2012 1 2 F1 mircoSMDC110 2 1 3 2 1 S 1 2 G C18 10U 1206 10V C24 0.1U 50V 0603 Q3 NDS9410 SO8 +3VS 8 7 6 5 1 C21 0.1U 0603 50V 1 C25 10U_NA 1206 10V 2
Close to LCD Connector
TXCLK+ TXCLKTX2OUT1+ TX2OUT1TXOUT0+ TXOUT0TXOUT1+ TXOUT11 2 3 4 8 7 6 5 +3VS TXCLK+ TXCLK9,11 9,11 1 1 C1 1000P 0603 C3 0.1U 0603 50V 1 C16 1000P 0603 2 2
2
LCD CONNECTOR
9,11 9,11
TX2CLK+ TX2CLK-
TX2CLK+ TX2CLKTX2OUT0+ TX2OUT0TX2OUT2+ TX2OUT2TXOUT2+ TXOUT2-
CLOSE TO NDS 9410
D
1 3 R18 Q4 R1 2
2 470K 0603
C
7,11 7,11 7,11 11 LCD_ID0 LCD_ID1 LCD_ID2 LCD_ID3
9,11 TX2OUT2+ 9,11 TX2OUT29,11 TXOUT2+ 9,11 TXOUT2LCD_ID0 LCD_ID1 LCD_ID2 4 3 2 1
TXOUT0+ 9,11 TXOUT0- 9,11 TXOUT1+ 9,11 TXOUT1- 9,11 RP1 1K*4 1206
2
9,11 TX2OUT0+ 9,11 TX2OUT0-
TX2OUT1+ 9,11 TX2OUT1- 9,11
+12VS
2
2
1
4
C
DTC144TKA 1 ENAVDD
ENAVDD 9,11
RP2 10K*4 1206
5 6 7 8
Layout Note:
Display
QDI 14.1" XGA TFT: QD141X1LH03-MP01/03 AU 14.1" XGA TFT: B141XN04-2 (UB141X03) CMO 14.1" XGA TFT: N141X6 Sumsung 15 XGA TFT: LT150X3-124 Sumsung 15 SXGA+ TFT: LTN150P1-L04 HannStar 15 XGA TFT: HSD151PX11-B AU 15" XGA TFT: (TBD) AU 15" SXGA+ TFT: B150PN01 LCD_ID3 LCD_ID2 LCD_ID1 LCD_ID0
S/W/W/S=12/6/6/12 mils as short as possible 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1
+5VS
0 1
1 U1 +3V BATT_LED# R719 10K 0603 2 3
B
0
+5VS 2 3 1 7 6 5 16 ACPILED ACPILED
1
8
BATT_LED# 25
B
R1 Q501 DTC144TKA 1
1 0
+3VS +5VS 2 PACDN006/NA SSOP8 D502 3 16 F501 mircoSMDC110 4
2
1
1 1
R3 2.2K 0603 7,11 CRT_RED CRT_RED CRT_GREEN CRT_BLUE 2 2
R4 2.2K 0603
Close to VGA Connector
1 1 1 2 L502120Z/100M 2 L503120Z/100M 2 L504120Z/100M 1608 1608 1608
DDC2B 1Amp (40mil-60mil)
A
2 EC11FS2 D503 1 BAV99_NA
BATT_POWER#
K
GND_CRT15 DDC2B
W/S=16/12/12/12/16 mils
7,11 CRT_GREEN 7,11 CRT_BLUE
External VGA Connector
17
7,11 CRT_DDDA
CRT_DDDA
S D S
Q1 D 2N7002
4 3 2 1
5 6 7 8 FA501 120OHM/100MHZ
1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 +3V
J6 VGA SUYIN 7535S-15G2T-05
7,11 CRT_HSYNC
CRT_HSYNC 4 3 2 1 CP508 22P*4/NA 1206 4 3 2 1
G
4 3 2 1
4 3 2 1
1 CP501 22P*4 1206 C501 10U 1206 10V 1
Close to VGA Connector
RP501 75*4 1206 CP502 22P*4 1206
G
2
7,11 CRT_VSYNC
CRT_VSYNC Q2 D 5 6 7 8
A
2
1
JL502 SHORT-SMT3 JL501 1 2 SHORT-SMT3
5 6 7 8
2N7002
5 6 7 8
5 6 7 8
7,11 CRT_DDCK
CRT_DDCK
S D S
R501 10K 0603 2 R502 1 1K 0603 2 CRT_IN# CRT_IN# 16 GND_CRT15 1 C502 100P 0603 10%
A
GND_CRT15 GND_CRT15
GND_CRT15
GND_CRT15
GND_CRT15
2
Title
LXD / VGA INTERFACE
GND_CRT15 Size Date: Document Number
8640
Sheet 12 of 32
Rev 01
Wednesday, August 28, 2002
5
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PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
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8
CLOCK GEN/BUFFER
+3VS +3VS U510 +3VS
A
L523 1 1 2 1 120Z/100M 1608 2 VDDREF C632 0.1U 0603 50V 16 STP_PCI# 16,28 CPU_STP# L525 1 2 1 120Z/100M 1608 2 VDDZ C655 0.1U 0603 50V STP_PCI# CPU_STP# K 1 R657 10K 0603 2 D506 A RLS4148 K D505 A RLS4148 2 R675 10K 0603
VDDREF VDDZ VDDPCI VDDA48 VDDAGP VDDCPU VDDSD
1 11 13 19 28 29 42 48 12 45 5 8 18 24 25 32 41 46
VDDREF VDDZ VDDPCI0 VDDPCI1 VDDA48 VDDAGP VDDCPU VDDSD *PCI_STOP# CPU_STOP#* GNDREF GNDZ GNDPCI0 GNDPCI1 GND48 GNDAGP GNDCPU GNDSD
A
CPUCLKT_0 CPUCLKC_0 CPUCLKT_1 CPUCLKC_1 SDRAM AGPCLK0 AGPCLK1 ZCLK0 ZCLK1 **FS3/PCICLK_F0 **FS4/PCICLK_F1 PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5
40 39 44 43 47 31 30 9 10 14 15 16 17 20 21 22 23 2 3 4 27 26 35 34 FS3 FS4
R664 R671 R654 R658 R651 R686 R692 R661 R660 R678 R21 R689
1 1 1 1 1 1 1 1 1 1 1 1
2 33 2 33 2 33 2 33 2 22 2 22 2 22 2 22 2 22 2 33 2 33 2 33
HCLK_CPU HCLK_CPU# HCLK_SIS650 HCLK_SIS650# SDRAMCLK AGP_CLK 66M_AGP ZCLK0 ZCLK1 CLK_SBPCI CLK_LPC33 PCICLK_CARD
HCLK_CPU 4 HCLK_CPU# 4 HCLK_SIS650 6 HCLK_SIS650# 6 SDRAMCLK 7 AGP_CLK 6 66M_AGP 10
FSB 400/533 SELECT (DDR DEFAULT 266)
+3VS 1 +3VS 1 +3VS 1 R87 10K 0603 R76 10K 0603 1 R73 10K 0603 2 2 FS0 FS1 3 Q6 2 R1 1 DTC144TKA 1 R86 10K 0603 4 BSEL0 BSEL0 1 2 2 FS3 R85 10K 0603 2 FS2 FS4 R669 4.7K/NA
+3VS
R195 475 0603 2 2
ZCLK0 ZCLK1
7 15
+3VS L26 1 VDDAGP C681 0.1U 0603 50V
+VCC_CORE
+3VS
+3VS
CLK_SBPCI 15 CLK_LPC33 22 PCICLK_CARD 19
1 R107 10K 0603 VTT_PWRGD 2 33 38 PD#*/VTT_PWRGD IREF 1
1
2 120Z/100M 1608 2
1
R100 10K 0603 R96 10K 0603 2
R696 FS0 FS1 FS2 R643 R644 R684 R620 R704 R699 R652 R683 R685
1 1 1 1 1 1 1 1 1 1
2 33 2 2 2 2 2 2 2 33 33 33/NA 33 22 2