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5

4

3

2

1

+VCCP +3V
D

6

CPU_BSEL0

R535

R_0402

0 +-5%

R534 1.2K +-1% NS R594 R_0402 8.2K +-5%

VCC3_CLK BSEL0 C366 C313 C363 C315

FB22 600 OHM/1.5A C345 10uF/6.3V C_0805

FB23 600 OHM/1.5A

R532 8 MCH_BSEL0

1K +-1% R533 1.2K +-1% R_0603 NS +VCCP R354 2 +-5% R_0603

0.047UF/16V 0.047UF/16V C_0402 C_0402

0.1UF/10V 0.1UF/10V C_0402 C_0402

R473 2 +-5% R_0603

C365 0.047UF/16V C_0402

C414 10uF/6.3V C_0805

+V3.3S_CLKVDD1 R496 1.2K +-1% NS R595 R_0402 0 +-5% R463 1K +-1% 8 MCH_BSEL1 R482 1.2K +-1% R_0603 NS C413 U19 VDD_A_CR C310 33PF/50V C_0603 C314 C324 R337 1 +-5% R_0603 C350 C513

Y4

0.1UF/10V 0.047UF/16V C_0402 C_0402 C312 0.047UF/16V C_0402

VDD_PCI1

6

CPU_BSEL1

14.31818MHZ C311 33PF/50V C_0603

VDD_SRC0 VDD_SRC1 VDD_SRC2 VDD_CPU VDD_A VSS_A XTAL_IN XTAL_OUT FSA/USB_48 FSB/TEST_MODE

VDD_PCI0

R500

R_0402

0 +-5%

BSEL1

21 28 34 42 37 38

VDD_48 VDD_REF PCI_STOP# CPU_STOP# CPU1 CPU1# CPU0 CPU0#

11 48 55 54
VDD_REF_CR

0.047UF/16V 10uF/6.3V C_0402 C_0805

C

XTAL_IN +VCCP XTAL_OUT BSEL0 R352 1.2K +-1% R_0603 NS 6 CPU_BSEL2 R363 8 MCH_BSEL2 R345 R_0402 0 +-5% R362 1.2K +-1% R_0603 NS +3V R353 NS R498 10K +-5% 24 PCLK_LAN R346 R380 R379 R326 R325 BSEL1 R593 8.2K +-5% BSEL2 R_0402 1K +-1% 31 PCLK_591 R378 33 +-5% BSEL2 17 CLK48_USB R381 33 +-5%

50 49 12 16 53 5 4 3

CPU_2_ITP/SRC_7 CPU2_ITP/SRC7# SRC6/CLKREQA# SRC6#/CLKREQB# SRC5 SRC5# SRC4 SRC4# SRC3 SRC3# SRC2 SRC2# SRC1 SRC1#

REF1/FSC/TEST_SEL PCI5 PCI4 PCI3

33 +-5% 33 +-5% 33 +-5%

+3V

10K +-5% R_0603

26 PCLK_OZ711 16 PCLK_ICH7

14,16

SMB_CLK_ICH7

0 +-5% CGCLK_SMB

14,16 SMB_DATA_ICH7

0 +-5% CGDAT_SMB IREF

For SLG8LP453.

B

w

w w

p la .

s p to
PCI2

56 9 8

PCI2/REQ_SEL

PCIF1/DREF_SEL PCIF0/ITP_EN SCLOCK SDATA IREF

PCIF0

46 47 39 13 29 45 2 6 51

DREF_SSCLK DREF_SSCLK# DOT96 DOT96#

VSS_48 VSS_SRC VSS_CPU VSS_PCI0 VSS_PCI1 VSS_REF

m e h c
41 40 44 43
CPU1 CPU#1 CPU0 CPU#0 ITP ITP#

36 35 33 32

31 30 26 27 24 25 22 23 19 20

PCIE5 PCIE#5 PCIE4 PCIE#4 PCIE3 PCIE#3 PCIE2 PCIE#2 PCIE1 PCIE1#

RN4 0X2 1 2 3 4 RN3 0X2 R_SMT4_0402 1 2 3 4 R_SMT4_0402 RN5 0X2 1 2 NS 3 4 R_SMT4_0402 R338 10K +-5% NS R364 10K +-5% PCIE5 1 NS PCIE#5 3 PCIE#4 1 PCIE4 3 PCIE#3 1 PCIE3 3 PCIE#2 1 PCIE2 3 PCIE1# 1 PCIE1 3

STP_PCI# STP_CPU#

CLK_MCH_BCLK 8 CLK_MCH_BCLK# 8 CLK_CPU_BCLK 6 CLK_CPU_BCLK# 6 6 6

CLK_ITP CLK_ITP#

a
17 17 8 8 8 8 36 17

7

1

10uF/6.3V C_0805

ic t
20 20 CLK_PCIE_MCH# 8 CLK_PCIE_MCH 8 CLK_PCIE_ICH# 17 CLK_PCIE_ICH 17

For SLG8LP453 buildin Pulldown res.

.c s
CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK# DREFSSCLK DREFSSCLK# DREFCLK DREFCLK# CLK_PCIE_ICH# CLK_PCIE_ICH CLK_PCIE_SATA# CLK_PCIE_SATA CLK_PCIE_MCH

m o
54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1% 54.9 +-1%

D

1

1 1

NS R_0402 R316 NS R_0402 R317 NS R_0402 R318 NS R_0402 R319 NS R_0402 R497 NS R_0402 R530 NS R_0402 R389 NS R_0402 R465 NS R_0402 R505 NS R_0402 R495 NS R_0402 R456 NS R_0402 R531

1

C

17 18

3 1 3 1

RN15 0X2 DREFSSCLK 4 R_SMT4_0402 2 DREFSSCLK# RN14 0X2 R_SMT4_0402 4DREFCLK 2DREFCLK#

RN19 0X2 2 4 R_SMT4_0402 RN30 0X2 2 4 R_SMT4_0402 RN18 0X2 2 4 0X2 RN17 R_SMT4_0402 2 CLK_PCIE_SATA# 4 CLK_PCIE_SATA RN16 0X2 R_SMT4_0402 2 4 R_SMT4_0402 DREFSSCLK DREFSSCLK# DREFCLK DREFCLK#

PCIECLK_3G PCIECLK_3G#

PCIECLK_WLAN# 20 PCIECLK_WLAN 20 NS R_0402 R501 NS R_0402 CLK_PCIE_MCH# R502

CLK_PCIE_SATA# 15 CLK_PCIE_SATA 15

change from 49.9 to 54.9

Note:Pls confirm need BIOS modify? Place termination close to source IC

14 15

VTT_PWRGD#/PD REF

10 52

CKGEN_EN# R334 12.1 +-1%

CKGEN_EN#

B

CLK14_ICH7

SLG8LP453B/SLG84420

Check the CLK14_ICH6 clock SI after bring up!! If need changed to 33R

SLG8LP453 buildin dumping and terminal res.

5

4

3

2

1

8

H_A#[31:3] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

U3A

D

CONTROL

8 8

H_ADSTB#0 H_REQ#[4:0]

J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 K3 H2 K2 J3 L5 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 A6 A5 C4 D5 C6 B4 A3 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 B25

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] RSVD[11]

ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK#

H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 D21 A24 A25 C7
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST#

8 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BREQ#0 H_IERR# H_INIT# H_LOCK# H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# 8 8 8 R65 +VCCP +3V R597 R312 1K +-5% NS TP_PROCHOT# THERMDA_CPU THERMDC_CPU PM_THRMTRIP# 8,15 TP76 TP_PROCHOT# 36 68 +-5% TDI 54.9 +-1% R_0603 15 8 H_CPURST# H_RS#[2:0] 8 8 8 8 8 8 56 +-5% 8 8 8 8 8 8 8 R76

H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[63:0] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

U3B

H_D#[63:0]

+VCCP

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#

+VCCP

E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3]

AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE6

8

H_A#[31:3]

C

THERM

8 15 15 15 15 15 15 15

H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#

PROCHOT# THERMDA THERMDC

THERMTRIP#

8 H_DSTBN#1 8 H_DSTBP#1 8 H_DINV#1 +VCCP C63 100PF/50V C_0402 R200 1K +-1% R_0603

H CLK

BCLK[0] BCLK[1] RSVD[12]

A22 A21 T22 D2 F6 D3 C1 AF1 D22 C23 C24

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20]

Yonah ULV FCBGA

B

+VCCP

R491 R357 54.9 +-1% NS TDI TMS TRST# TCK TDO 4 4 8 CLK_ITP# CLK_ITP H_CPURST# TCK H_CPURST# PREQ# PRDY# BPM3# BPM2# BPM1#
A

R490 54.9 +-1% R_0603

R596

54.9 +-1% R_0603

54.9 +-1% R_0603

R367 22.6 +-1% NS

BPM0# 16,17 PM_SYSRST#

R392 54.9 +-1%

5

w

R366 54.9 +-1%

w w
R492 22.6 +-1% NS +VCCP C595 0.1UF/10V NS CRB 54.9R

p la .
CON71

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

s p to
4 4 4 ACLKPH DCLKPH R311 R288 +3V 51 +-5% 1K +-5% NS 100 +-5% R487 C589 0.1UF/10V Q13 3 1 MMBT3904 2
3

RESERVED

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

m e h c
GTLREF0 R31 2K +-1% R_0603 ACLKPH

a
31,33

XDP/ITP SIGNALS

ic t
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 COMP0 COMP1 COMP2 COMP3 R34 R69 R86 R56 THERMDA_DDR THERMDC_DDR T59 *PAD

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#[63:0]

.c s
8 8 8 8 8 8 8 8 27.4 +-1% 54.9 +-1% 27.4 +-1% 54.9 +-1% 15,36 15 8 15 8 36

m o
H_DINV#[3:0] H_DSTBP#[3:0] H_DSTBN#[3:0] 8 8 8 Zo=27.4ohm, make than 0.5". Zo=55ohm, make than 0.5".

D

DATA GRP 3

DATA GRP 2

ADDR GROUP ADDR GROUP 0

DATA GRP 0

ADDR GROUP ADDR GROUP 1

DATA GRP 1

C

H_DSTBN#3 H_DSTBP#3 H_DINV#3 R_0603 R_0603 R_0603 R_0603

AD26 C26 D25 B22 B23 C21

MISC

Layout note: Comp0,2 connect with trace length shorter Comp1,3 connect with trace length shorter

DCLKPH

BSEL[0] BSEL[1] BSEL[2]

DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# PSI#

Yonah ULV FCBGA

R486

0 +-5%

R_0603

HWPG

NS +5V_FAN

C392 U15

C_0603

0.1UF/25V

R358 R320

20K +-1% NS 10K +-1%

GMT_VCC_W20

1 2 3 FAN_FG1 4 5 6 7 8 9 10

FAN1 RESET# THERM_SET FG1 DGND1 VCC DXP1 SGND1 DXP2 SGND2
GMT-G792SFX 20P_QSOP_150

DXP3 SGND3 THERM# CLK ALERT# SDA DGND2 SCL NC DVCC

11 12 13 14 15 16 17 18 19 20

B

3 ICH_SUSCLK TEMP_ALERT# MBDATA MBCLK ICH_SUSCLK 17 TEMP_ALERT# 31 MBDATA 31,37 MBCLK +5V 31,37 C590 2200PF/50V C_0603 1 2 Q33 MMBT3904

THERMDA_CPU C_0603 C588 2200PF/50V

THERMDC_CPU THERMDA_VGA THERMDC_VGA

For VGA ambient TEMP
C586 10uF/6.3V C582 1000PF/50V

C591 2200PF/50V C_0603

For systeam ambient TEMP

NOTE: 1.hardware shutdown for sensor2. THERM_SET=[(Tset-72) x 0.02+0.34] x VCC THERM_SET pin voltage from 0.35VCC to 0.95 VCC and trigger point set from 72C to 102C,2C a step. 2.software shutdown for sensor1,sensor3.

T8 CON7 *PAD +5V_FAN FAN_FG1 C75 4.7UF/10V C_0805 0 +-5% R_0603 C76 0.1UF/10V NS R85 +5V

1 2 3
1ST_FAN

MLX-CON28-U NS R104 10K +-5% R_0603 +5V_FAN

4

2

5

4

3

2

1

U3D VCORE_CPU VCORE_CPU

U3C

D

TP78 TP77

C

A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 AD6 AF5 AE5 AF4 AE3 AF2 AE2
AF7

+VCCP

C46 0.1UF/10V

C201 0.1UF/10V

C248 0.1UF/10V

C256 0.1UF/10V

C284 0.1UF/10V

C291 0.1UF/10V

+VCCP

C260 0.1UF/10V

C240 0.1UF/10V

C249 0.1UF/10V 0.1UF/10V

C263 0.1UF/10V

C281 0.1UF/10V

C289 0.1UF/10V

+

CT3 220UF/2.5V TAJ_E

+VCCP

+VCCP C233 10uF/6.3V C203 0.01UF/16V C_0402

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

36 36 36 36 36 36 36

VCORE_CPU

R314 100 +-1% R_0603

VCCSENSE VSSSENSE

36 36

AE7

Yonah ULV FCBGA
B

VCORE_CPU

A

5

w

w w
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

p la .
C199 C199 C202 C211 C242 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
4

R70 100 +-1% R_0603

s p to
Layout note: Route VCCSENSE and VSSSENSE traces at 27.4 OHM with 50 mil spacing ,place PU and PD within 1 inch of CPU
C247 C253 C261 C269 C280 C285 C290 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
3

Layout note: Place c233 c203 near pin B26

m e h c
C293 C293 C300 C67 C67 C198 C200 C204 C241 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

a

ic t

A2 A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3

VSS[999] VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162]

.c s

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24

m o

D

C

B

Yonah ULV FCBGA

C299 C299 22UF/6.3V 22UF/6.3V

C250 22UF/6.3V

C254 22UF/6.3V

C264 22UF/6.3V

C270 22UF/6.3V

C282 22UF/6.3V

C288

C292 C292

C294

C585 C585

C53

C243

C251

C255

22UF/6.3V

22UF/6.3V

22UF/6.3V

22UF/6.3V

2

5

4

3

2

1

6

H_D#[63:0]

U5A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 24.9 +-1%

D

C

+VCCP

R393 54.9 +-1% R_0603R390

F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 E1 E2 E4

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING H_CLKIN H_CLKIN#

TP80 TP81 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# 6 6 6 6 6 6 6 6 6 6 6 6 TP82 TP84 TP83

HOST

H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF_0 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF_1 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_HIT# H_HITM# H_LOCK#

E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13 J7 W8 U3 AB10 K4 T7 Y5 AC4 K3 T6 AA5 AC5 D3 D4 B3

H_VREF

H_VREF H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_DINV#[3:0]

14 H_DSTBN#[3:0] 6

MEM_TS# 17,36 DPRSLPVR 6,15 PM_THRMTRIP# 17,31 PWROK 16,17,20 PLT_RST# R400

R397 R405

PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN#

CLK

TP85 TP86 +3V TP88 TP89 TP53 TP79 R399 10K +-5% R_0402 17 PM_BMBUSY#

H_DSTBP#[3:0]

6

NS R_0402

16 MCH_ICH_SYNC# TP93 H_HIT# H_HITM# H_LOCK#

H_XRCOMP H_XSCOMP H_XSWING

DMI

+VCCP

R382 R387

24.9 +-1% H_YRCOMP Y1 54.9 +-1% H_YSCOMP U1 H_YSWING W1

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_SLPCPU# H_TRDY#

D8 G8 B8 F8 A8 B4 E6 D6 E3 E7

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP#

4 CLK_MCH_BCLK 4 CLK_MCH_BCLK#

AG2 AG1

B

CALISTOGA_1p0

+VCCP +VCCP

R394 221 +-1% R_0603
A

R395 221 +-1% R_0603 H_XSWING

R386 100 +-1% R_0603

C398 0.1UF/10V

Layout Note:10mil width

5

w

R383 100 +-1% R_0603

Layout Note:10mil width

w w
H_YSWING C438 0.1UF/10V

MCH_CFG11

MCH_CFG12

MCH_CFG13

MCH_CFG5

MCH_CFG6

H_VREF

C425 0.1UF/10V

R385 200 +-1% R_0603

R417 R409 R410 R413 R_0402 R_0402 R_0402 R_0402 2.2K +-5% 2.2K +-5% 2.2K +-5% 2.2K +-5% NS NS NS NS

MCH_CFG9

R414 R415 R_0402 R_0402 2.2K +-5% 2.2K +-5% NS NS

R416 R_0402 2.2K +-5% NS

Layout Note:close to GMCH less than 100 mils

4

3

2

MCH_CFG16

p la .
+VCCP

s p to
6 6 6 R407 H_REQ#[4:0] 6 40.2 +-1% R_0402 NS R408 H_RS#[2:0] 6 40.2 +-1% R_0402 NS H_CPUSLP# H_TRDY# 6 6 M_VREF C479 C480 0.1UF/10V

SM_OCDCOMP_0

SM_OCDCOMP_1

m e h c
G28 F25 H26 G6 0 +-5% AH33 100 +-1% AH34 H28 H27 K28 H32
0 +-5% TP87

MCH_CFG3 MCH_CFG4 MCH_CFG5 MCH_CFG6 MCH_CFG7 MCH_CFG8 MCH_CFG9 MCH_CFG10 MCH_CFG11 MCH_CFG12 MCH_CFG13 MCH_CFG14 MCH_CFG15 MCH_CFG16 MCH_CFG17 MCH_CFG18 MCH_CFG19 MCH_CFG20

MUXING

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31

H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_A#[31:3]

6

U5B

TP39 TP43

T32 R32 F3 F7 AG11 AF11 H7 J19 K30 J29 A41 A35 A34 D28 D27 K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26

RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3 SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21

4 MCH_BSEL0 4 MCH_BSEL1 4 MCH_BSEL2

SM_OCDCOMP_0 SM_OCDCOMP_1 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

a
DDR CFG PM
MISC

G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN

ic t
AL20 AF10 BA13 BA12 AY20 AU21 SM_RCOMP# SM_RCOMP SM_VREF_0 SM_VREF_1 AV9 AT9 AK1 AK41 AF33 AG33 A27 A26 C40 D41 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 AE37 AF41 AG37 AH41 AC37 AE41 AF37 AG41

SM_OCDCOMP_0 SM_OCDCOMP_1

M_RCOMPN M_RCOMPP R398

.c s
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4 M_CKE0 M_CKE1 M_CKE2 M_CKE3 14 14 14 14 M_CS#0 M_CS#1 M_CS#2 M_CS#3 14 14 14 14 M_ODT0 M_ODT1 M_ODT2 M_ODT3 14 14 14 14 80.6 +-1% R_0603 M_VREF DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4

14 14 14 14

14 14 14 14

m o
VDIMM R406 80.6 +-1% R_0603 17 17 17

RSVD

D

CLK_PCIE_MCH# 4 CLK_PCIE_MCH 4 DREFCLK# 4 DREFCLK 4 DREFSSCLK# 4 DREFSSCLK 4 DMI_RXN[3:0]

C

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC# CLK_REQ# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18

DMI_RXP[3:0]

D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3

DMI_TXN[3:0]

CALISTOGA_1p0

NC

DMI_TXP[3:0]

17

B

LEVEL CFG5 CFG6 CFG9 CFG11 CFG12 CFG13 CFG16 DMI x2

0 DMI x4 (default) Calistoga

1

Moby Dick Reverse Lanes Calistoga Reserved Reserved Dynamic ODT Disabled

2.2UF/16V

Normal Operation (default) Moby Dick Reserved Reserved Dynamic ODT Enabled (default)

placed close to VREF pins of DDR2 SO-DIMM

CFG[17:3] INTERNAL PULLUP CFG[20:18] INTERNAL PULLDOWN

R396 100 +-1% R_0603

5

4

3

2

1

D

M_B_DQ[63:0] M_A_DQ[63:0] U5D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 14 U5E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

14

C

B

AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
CALISTOGA_1p0

SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

AU12 AV14 BA20 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# M_A_DM[7:0]

14 14 14 14 14

M_A_DQS[7:0] 14

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#

M_A_DQS#[7:0] 14

M_A_A[13:0]

14

AW14 AK23 TP_MA_RCVENIN# AK24 TP_MA_RCVENOUT# AY14

M_A_RAS# M_A_WE#

A

5

w

w w

p la .
4

s p to
1 1
14 1 1 14 TP1 TP47
3

m e h c
DDR SYSTEM
CALISTOGA_1p0

AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

AT24 AV23 AY28 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

DDR

SYSTEM

a
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 AU23 AK16 AK18 AR27

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

MEMORY

MEMORY

ic t

.c s
M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS# M_B_DM[7:0] 14 14 14 14 14 M_B_DQS[7:0] 14 M_B_DQS#[7:0] 14 M_B_A[13:0] 14

m o

D

A

B

C

SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#

TP_MB_RCVENIN# TP_MB_RCVENOUT#

M_B_RAS# M_B_WE#

1 1

14 1 1 14

TP2 TP49

B

2

5

4

3

2

1

+VCCP U5G +VCCP U5F

D

C

B

A

AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16

5

w

VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110

VCC

CALISTOGA_1p0

w w

VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107

AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1

C484 0.1UF/25V C_0603

C600 0.1UF/25V C_0603

C601 0.1UF/25V C_0603

C635 0.47uF/16V C_0603

C636 0.47uF/16V C_0603

C496 0.1UF/25V C_0603

C593 0.1UF/25V C_0603

C483 0.1UF/25V C_0603

C637 0.47uF/16V C_0603

C638 0.47uF/16V C_0603

p la .
C633 0.47uF/16V C_0603 C634
4

s p to
VDIMM C598 C495 10uF/6.3V
3

m e h c
+VCCP + CT23 220UF/2.5V TAJ_E

AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18

VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72

VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12

AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17

a

NCTF

VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57

ic t
AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15

.c s
+1.5V

m o

D

C

B

CALISTOGA_1p0

C587 C602 0.22UF/16V C_0603 C604 0.22UF/16V C_0603 C599 0.22UF/16V C_0603 C597 1UF/10V C_0603 C603 10uF/6.3V C_0805 10uF/6.3V C_0805

10uF/6.3V

0.47uF/16V C_0603

2

5

4

3

2

1

+2.5V +2.5V C453 C440 C86 10uF/6.3V C88 0.1UF/10V C_0402 U5H +1.5V L9 INDCT,91NH, 20%, 1.5A,L_3225 20% + CT12 220UF/2.5V TAJ_E +1.5V +1.5V_PCIE VCCSTNC +VCCP

4.7UF/10V 0.1UF/10V

H22 C30 B30 A30

VCCSYNC VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS VCCA_MPLL VCCA_TVBG VSSA_TVBG VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76

C455 10uF/6.3V

C462 10uF/6.3V +2.5V C446 C387 0.1UF/10V 10uF/6.3V

D

1

L11 2 1uH,500mA,20%,L_3225 20% C389 10uF/6.3V

C90 0.1UF/10V C_0402

D57 +VCCP +2.5V

R453

FB37 1K +-1% 1 C472 22nF/25V C_0402 C386 0.1UF/10V C_0402 +1.5V_DPLLA +1.5V_DPLLB +1.5V_HPLL +2.5V_CRTDAC

AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41 F21 E21 G21 B26 C39 AF1 A38 B39

2

1
RB751V-40

R_0603 BLM18PG600SN

+2.5V VCCA_LVDS C449 C437 +1.5V D64 R454 +3V

0.01UF/16V 0.1UF/10V C_0402 C_0402 +1.5V 1 BLM18PG121SN R_0603 C463 22UF/6.3V 0.1UF/10V
C

+1.5V_MPLL FB38 1 +3.3V_ATVBG BLM18PG121SN R_0603

AF2 H20 G20

2

1
RB751V-40 1K +-1%

FB42 +1.5V_HPLL C388 +1.5V

FB43 1 BLM18PG121SN R_0603 C434

C444 +1.5V_MPLL 10uF/6.3V

C447 0.1UF/10V

+1.5V

C458 22UF/6.3V 0.1UF/10V

+1.5V +3V

+1.5V

C460

1

L6 2 1uH,500mA,20%,L_3225 C456 20% CT20 + 220UF/2.5V 220UF/2.5V 0.1UF/10V

+1.5V_DPLLA

22nF/25V C_0402

FB26 1 +1.5V_DPLLB

1

L10 2 1uH,500mA,20%,L_3225 20% CT21 C457 + 220UF/2.5V 220UF/2.5V 0.1UF/10V

R_0603 BLM18PG121SN

B

+1.5V

+3.3V_ATVBG

+3.3V_TVDACA

C394 10uF/6.3V C_0805

C452 0.1UF/10V C_0402

C469 22nF/25V C_0402

C461

0.1UF/10V C_0402

A

5

w

w w
C477 C474 22nF/25V C_0402

0.1UF/10V C_0402

p la .
+3.3V_TVDACB C433 C432 22nF/25V C_0402 0.1UF/10V C_0402
4

s p to
C482 0.1UF/10V C_0402 C397 10uF/6.3V C_0805 C443 C441 22nF/25V C_0402 0.1UF/10V C_0402 +1.5V C424 0.1UF/10V C_0402 +3.3V_TVDACC C451 22nF/25V C_0402 C448 0.1UF/10V C_0402
3

m e h c
+3.3V_TVDACA +3.3V_TVDACB +3.3V_TVDACC

E19 F19 C20 D20 E20 F20

VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2

AH1 AH2

a

POWER

ic t

A28 B28 C28 D21 A23 B23 B25

VCCD_TVDAC VCC_HV0 VCC_HV1 VCC_HV2

C439

+1.5V_TVDAC

H19

VCCD_QTVDAC VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40

0.1UF/10V C_0402

AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12

AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1

.c s

m o

D

C

C639 0.47uF/16V C_0603

B

C640 0.47uF/16V C_0603 +VCCP

C641 0.47uF/16V C_0603

C376 4.7UF/10V C_0805

C436

C423

+

2.2UF/16V 0.22UF/16V C_0603 C_0603

CT11 220UF/2.5V TAJ_E

C646 0.22UF/16V C_0603

CALISTOGA_1p0

2

5

4

3

2

1

+3V +3V NS R436
D

NS R430 10K +-5% 10K +-5%

+1.5V_PCIE

R445

R433 10K +-5% 10K +-5%

U5C

R423 24.9 +-1% R_0603

22 BLPWM-ADJ 22 VGA_BLON 22 22 EDIDCLK EDIDDATA 22 DISP_ON

R421

1.5K +-1%

L_IBG

D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 A33 A32 E27 E26 C37 B35 A37

L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LA_CLK# LA_CLK LB_CLK# LB_CLK

EXP_A_COMPI EXP_A_COMPO EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15 EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15 EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15 EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15

D40 D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38

PEG_COMP

22 TXLCLKOUT22 TXLCLKOUT+

TXUCLKOUTTXUCLKOUT+

22 22 22

TXLOUT0TXLOUT1TXLOUT2-

LA_DATA#_0 LA_DATA#_1 LA_DATA#_2

22 22 22
C

TXLOUT0+ TXLOUT1+ TXLOUT2+ TXUOUT0TXUOUT1TXUOUT2-

B37 B34 A36 G30 D30 F29

LA_DATA_0 LA_DATA_1 LA_DATA_2 LB_DATA#_0 LB_DATA#_1 LB_DATA#_2

Check all the chanelB!!!
TXUOUT0+ TXUOUT1+ TXUOUT2+

PCI-EXPRESS

F30 D29 F28

LB_DATA_0 LB_DATA_1 LB_DATA_2

+1.5V R443 R418 R424 R437 R448 R451 R419 0 +-5% 0 +-5% 0 +-5% 0 +-5% 0 +-5% 0 +-5% 0 +-5% INTTV_COMP INTTV_LUMA INTTV_CHROMA TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

A16 C18 A19 J20 B16 B18 B19

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

21 21 21
B

CRT_B CRT_G CRT_R

E23 D23 C22 B22 A21 B21 C26 C25 G23 J22 H23

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

21 DDCCLK 21 DDCDAT 21 CRTHS_VGA 21 CRTVS_VGA

R427 R440

39 +-5% 39 +-5%

INTCRTHS_VGA INTCRTVS_VGA

A

5

w

w w

p la .
CRT_IREF R450 255 +-1% R_0603
4

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC

CALISTOGA_1p0

s p to
TV VGA
R446 R431 R447 150 +-1% 150 +-1% 150 +-1% CRT_R CRT_G CRT_B
3

F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40

m e h c

a

GRAPHICS

ic t

.c s

m o

D

LVDS

C

B

2

5

4

3

2

1

U5I

D

C

B

AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34

VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96

VSS

VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23

U5J

CALISTOGA_1p0

A

5

w

w w

p la .
4

s p to
3

AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11

m e h c
CALISTOGA_1p0

VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272

VSS

VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1

a

ic t

.c s

m o
D C

B

2

5

4

3

2

1

9

M_A_A[13:0]

CON8 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_DQ[63:0]

9 9 M_B_A[13:0] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

CON9

D

9

M_A_BS#2

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF GND0 GND1 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15

R123 R124

9 M_A_BS#0 9 M_A_BS#1 8 M_CS#0 8 M_CS#1 8 M_CLK_DDR0 8 M_CLK_DDR#0 8 M_CLK_DDR1 8 M_CLK_DDR#1 8 M_CKE0 8 M_CKE1 9 M_A_CAS# 9 M_A_RAS# 9 M_A_WE# 10K +-5% 10K +-5% 4,16 SMB_CLK_ICH7 4,16 SMB_DATA_ICH7 8 8 9 M_ODT0 M_ODT1 M_A_DM[7:0]

SA0_DIM1 SA1_DIM1

C

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 VDIMM

10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 112 111 117 96 95 118 81 82 87 103 88 104 199 83 120 50 69 163

9

M_A_DQS[7:0]

9 M_A_DQS#[7:0]

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

9

M_B_BS#2

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 112 111 117 96 95 118 81 82 87 103 88 104 199 83 120 50 69 163 1 201 202 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

+3V

9 M_B_BS#0 9 M_B_BS#1 8 M_CS#2 8 M_CS#3 8 M_CLK_DDR4 8 M_CLK_DDR#4 8 M_CLK_DDR3 8 M_CLK_DDR#3 8 M_CKE2 8 M_CKE3 9 M_B_CAS# 9 M_B_RAS# 9 M_B_WE# 10K +-5% SA0_DIM2 R121 R118 10K +-5% SA1_DIM2 14,16 SMB_CLK_ICH7 14,16 SMB_DATA_ICH7 8 M_ODT2 8 M_ODT3 M_B_DM[7:0]

9

9

M_B_DQS[7:0]

9 M_B_DQS#[7:0]

+3V

C361 0.1UF/10V C_0402
B

C357 2.2UF/16V C_0603

8

MEM_TS#

M_VREF C176 0.1UF/10V C_0402

M_VREF C370 2.2UF/16V

1 201 202 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8

A

Layout Note:place these near dimm0

C403

C368

C349

C327

2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V C_0603 C_0402 C_0603 C_0402 C_0603 C_0402 C_0603 C_0402 C_0603 C_0402

5

w
C369

w w
Fox-DDRII-STD C330 C381 C351

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

p la .
VDIMM C336 + CT16 220UF/2.5V TAJ_E
4

s p to
+3V C378 8 C335
3

m e h c
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DDRII SDRAM SO-DIMM (200P)

DDRII SDRAM SO-DIMM (200P)

a
18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

ic t

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQ[63:0]

9 T20

VTT_MEM RN20

0.1UF/10V 0.1UF/10V

C391 C359

.c s
0.1UF/10V 0.1UF/10V C161 C160 0.1UF/10V 0.1UF/10V C159 C334 0.1UF/10V 0.1UF/10V C341 C371 0.1UF/10V 0.1UF/10V C354 C396 0.1UF/10V 0.1UF/10V C158 C343 0.1UF/10V 0.1UF/10V C353 C348 0.1UF/10V 0.1UF/10V C384 C162 0.1UF/10V 0.1UF/10V C377 C352 0.1UF/10V C393 0.1UF/10V 0.1UF/10V C406 C329

RN21

RN22

RN23

m o
1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7
56 X4 +-5% 2 M_B_A11 4 M_B_A8 6 M_B_A7 8 M_B_A6 56 X4 +-5% 2 4 6 8 56 X4 +-5% 2 4 6 8 56 X4 +-5% 2 4 6 8 56 X4 +-5% 2 4 6 8 56 X4 +-5% 2 4 6 8 M_ODT2 M_B_WE# M_CS#3 M_B_A13 M_ODT0 M_A_A13 M_A_CAS# M_CS#1 M_B_A0 M_B_A1 M_B_A10 M_B_BS#0 M_A_RAS# M_CS#0 M_A_WE# M_A_BS#0 M_B_BS#1 M_B_RAS# M_CS#2 M_B_CAS#

D

RN24

RN25

RN26

1 3 5 7
RN27

56 X4 +-5% 2 4 6 8

C

M_B_BS#2 M_B_A9 M_B_A12 M_CKE3

1 3 5 7
RN41

56 X4 +-5% 2 M_A_BS#2 4 M_CKE1 6 M_A_A12 8 M_A_A9 56 X4 +-5% 2 M_B_A3 4 M_B_A5 6 M_B_A4 8 M_B_A2 R_0402 M_CKE2 56 +-5% M_CKE0 R_0402 56 +-5% 56 X4 +-5% M_A_A3 2 4 M_A_A0 6 M_A_A10 8 M_A_BS#1 56 X4 +-5% 2 M_A_A8 4 M_A_A6 6 M_A_A11 8 M_A_A4 56 X4 +-5% 2 M_A_A7 4 M_A_A1 6 M_A_A5 8 M_A_A2 M_ODT3 56 +-5% R_0402 M_ODT1 56 +-5% R_0402

1 3 5 7
R122 R116 RN43

VDIMM

C328 2.2UF/16V C_0603

0.1UF/10V C_0402

VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF GND0 GND1 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
Fox-DDRII-REV

MEM_TS#

M_VREF C362 0.1UF/10V C_0402 C346 2.2UF/16V

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

1 3 5 7
RN40

0.1UF/10V 0.1UF/10V

C367 C401 RN42

1 3 5 7 1 3 5 7
R114 R117

B

0.1UF/10V 0.1UF/10V

C175 C326

0.1UF/10V

C344

Layout Note:place these near dimm1
VDIMM

C358

C356

C402

C385

C390

C404

C342

C321

C355

C379

2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V 2.2UF/16V 0.1UF/10V C_0603 C_0402 C_0603 C_0402 C_0603 C_0402 C_0603 C_0402 C_0603 C_0402

2

5

4

3

2

1

Consider VCCRTC sources

VCCRTC
D

+3VALW D23

2

2

1 RB751V-40
C511 1UF/10V C_0603

C560 C559 18PF/50V Y6 18PF/50V 32.768KHZ C_0402 C_0402 Cap values depend on Xtal

4

1

R466 R127 BAT +3VALW R_0603 BT2 CON13 JBAT1 CR2032WC VCCRTC R162 R_0402 330K +-5% R132 1M +-5% R_0603 R131 1M +-5% NS C510 0.1UF/10V C_0402 1K +-5% 2 R_0603 D26

1 RB751V-40
R134 20K +-1% 10M +-5% R_0603

U10A RTC_X1 RTC_X2 RTC_RST# SM_INTRUDER#

AB1 AB2 AA3 Y5 W4 W1 Y1 Y2 W3 V3 U3

RTXC1 RTCX2

RTC LPC

RTCRST# INTRUDER# INTVRMEN EE_CS EE_SHCLK EE_DOUT EE_DIN LAN_CLK

LAD0 LAD1 LAD2 LAD3 LDRQ0# LDRQ1#/GPIO23 LFRAME# A20GATE A20M#

AA6 AB5 AC4 Y6 AC3 AA5 AB3 AE22 AH28
LDRQ0# LDRQ1#

LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3

31 31 31 31

LFRAME#/FWH4 GATEA20 H_A20M#

31

C

LAN CPU

LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2

U5 V4 T5 U7 V6 V7
ACZ_SYNC_R ACZ_RST#_R

TP1/DPRSTP# TP2/DPSLP# FERR#

GPIO49/CPUPWRGD IGNNE# INIT3_3V# INIT# INTR RCIN# NMI SMI#

R5 T2 T3 T1 T4

AC-97/AZALIA

+3V

R591 10K +-5% R_0402 NS 23 19 19 19 19 SATA_LED#

20 AZ_BITCLK_MDC 28 AZ_BITCLK_AUD 20 AZ_SYNC_MDC 28 AZ_SYNC_AUD 28 AZ_RST_AUD# 20 AZ_RST_MDC# 28 AZ_SDIN0 20 AZ_SDIN1 28 AZ_SDOUT_MDC 20 AZ_SDOUT_AUD

R151 R138 R141 R137 R145 R139

39 +-5% 39 +-5% 39 +-5% 39 +-5% 39 +-5% 39 +-5%

U1 R6

ACZ_BIT_CLK ACZ_SYNC ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2

R150 R142

39 +-5% 39 +-5%

SATA_RX-0 SATA_RX+0 SATA_TX-0 SATA_TX+0

SATA_RX-0C244 SATA_RX+0 SATA_TX-0 SATA_TX+0

0.01UF/16V C512

0.01UF/16V C237

0.01UF/16V C252

0.01UF/16V

B

SATA

4 CLK_PCIE_SATA# 4 CLK_PCIE_SATA R144

R144 placed within 500 mils of ICH7

A

5

w

w w

p la .
24.9 +-1% R_0603 TP90 TP91 TP92 TP94 16 IDE_IRQ
4

SATA_RBIAS_PN

s p to
ACZ_SDO_R

ACZ_SDOUT SATALED#

AF18 AF3 AE3 AG2 AH2 AF7 AE7 AG6 AH6 AF1 AE1

THERMTRIP# DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DA0 DA1 DA2 DCS1# DCS3#

SATA_RX-0-C SATA_RX+0-C SATA_TX-0-C SATA_TX+0-C

SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP

m e h c
CPUSLP# AG27 AF24 AH25
H_DPRSTP# H_DPSLP# 6,36 6

16,31 6

AG26

AG24

H_PWRGD H_IGNNE# T32 H_INIT# H_INTR RCIN#

a
6 6 6 6 16,31 6 6 6 R143

ic t
LDRQ0# LDRQ1# 24.9 +-1%

R489 10K +-5% R_0402 R339 10K +-5% R_0402

.c s
+3V R147 56 +-5% H_FERR# 6 R158 56 +-5% C239 100PF/50V C_0402

m o

D

3 2 1

3

+VCCP

C

AG22 AG21 AF22 AF25

+VCCP

AG23 AH24 AF23 AH22 AF26

H_NMI H_SMI#

STPCLK#

H_STPCLK#

PM_THRMTRIP#_R TP95 TP96 TP97 TP98 TP99 TP100 TP101 TP102 TP107 TP108 TP109 TP110 TP103 TP104 TP105 TP106

PM_THRMTRIP# 6,8

SATA_CLKN SATA_CLKP

AH10 AG10 AF15 AH15 AF16 AH16 AG16 AE15

SATARBIASN SATARBIASP DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ

AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15 AH17 AE17 AF17 AE16 AD16

SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDA0 SDA1 SDA2

Layout note: R143 needs to placed within 2" of ICH7, R158 must be placed within 2" of R143 w/o stub.
TP111 TP112 TP113 TP115 TP114

B

SDIOR# SDIOW# SDDACK# SIORDY SDDREQ

IDE

SDCS0# SDCS1#

ICH7M REV 1.02 EDS

+3V

R493 4.7K +-5% R_0402

SIORDY

3

2

5

4

3

2

1

ICH7 PULL UP
24,26 AD[0:31] U10B AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 RN45

+3V

D

E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6 A3 B4 C5 B5 AE5 AD5 AG4 AH4 AD9

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD# RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]

PCI

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4#/GPIO22 GNT4#/GPIO48 GPIO1/REQ5# GPIO17/GNT5# C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#

D7 E7 C16 REQ1# D16 C17 D17 REQ3# E13 F13 REQ4# A13 A14 C8 D8 B15 C12 D12 C15 A7 E10 B18 A12 C9 E11 LOCK# B10 F15 F14 F16 C26 A9 B19 G8 F7 F8 G7 AE9 AG8 AH8 F21 AH20
PIRQE# PIRQF# PIRQG# PIRQH#

REQ0# GNT0# REQ2# GNT2#

24 24 26 26

17,24,26,31 CLKRUN# 24,26 TRDY# 24,26 DEVSEL#

REQ3#

1 3 5 7

RN46 LOCK# R474 1K +-5% NS NS 26 24,26 24,26 R164 33 +-5% PCIRST# 24,26,31 24 26 REQ2# FRAME# STOP# REQ1# 1K +-5% 24,26 24,26 24 SERR# PERR# REQ0#

HDD_DTCT# C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR DEVSEL# PERR# SERR# STOP# TRDY# FRAME#

19 24,26 24,26 24,26 24,26 24,26 24,26 24,26 24,26 24,26 24,26 24,26 24,26

R166

1 3 5 7

RN47

PIRQA# PIRQB#

PLT_RST# PCLK_ICH7 ICH_PME#

8,17,20 4 24,26

+3V +3VSUS

Interrupt I/F

24 26

PIRQA# PIRQB#

PIRQC# PIRQD#

C

MISC
RSVD[6] RSVD[7] RSVD[8] RSVD[9] MCH_SYNC#

17

SMB_CLK

MCH_ICH_SYNC# R189 10K +-5% +3V

8

ICH7M REV 1.02 EDS

B

GNT5#

GNT4#

LPC

H

H

PCI
A

H

L

SPI

L

5

w

H

w w

p la .
4

s p to
17 SMB_DATA 17 PM_THRM# 17,26,31 SERIRQ RCIN# R190 15,31 15,31 GATEA20 SCI# 17,31 R504
3

m e h c
R611 R186 2.2K +-5% R_0402 3 4.7K +-5% R_0402

1

SMB_CLK_ICH7

4,14

2

Q79 RHU002N06 +5V

a
RI# SMB_ALERT# SMLINK0 SMLINK1 BATLOW#

15 IDE_IRQ 24,26 IRDY#

ic t
REQ4# PIRQF# PIRQH# PIRQD# PIRQC#

1 3 5 7

R194 R188 R187

RN48

1 3 5 7

RN49

.c s
2 R_SMT8 4 6 8 8.2K X4 +-5% 2 4 R_SMT8 6 8 8.2K X4 +-5%
8.2K +-5% 8.2K +-5% 8.2K +-5% R_0402 R_0402 R_0402

2 R_SMT8 4 6 8 8.2K X4 +-5%

m o

D

2 4 6 R_SMT8 8 8.2K X4 +-5%

PIRQG# PIRQE#

1 3 5 7

2 4 6 8
8.2K X4 +-5%
C

R_SMT8

HDD_DTCT#

R195

8.2K +-5% R_0402

+3VSUS

+3V

+3VSUS

R612

R193 2.2K +-5% R_0402 3

4.7K +-5% R_0402

17,20 PCIE_WAKE#

R178

R_0603

10K +-5%

1

SMB_DATA_ICH7 4,14 17,31 SWI# 17,31 KBSMI#

R204 R217

R_0402 R_0402

8.2K +-5% NS 8.2K +-5%

2

Q80

RHU002N06

+5V

24,26

ICH_PME#

R_0603 R168 NS

10K +-5%

+3VSUS +3V 17 10K +-5% 8.2K +-5% 10K +-5% R_0603 10K +-5% 8.2K +-5% 17 R169 R191 R183 R167 R165 R203 10K +-5% 10K +-5% 10K +-5% 10K +-5% 10K +-5% R_0603 R_0603 R_0603 R_0603 R_0603
B

R171

17 SMB_LINK_ALERT# 17 17 17,31

R477 R192

R_0402

8.2K +-5% R_0603

R_0402

6,17 PM_SYSRST#

R170

10K +-5%

PIRQA# : BCM5705 PIRQB# : OZ711EZ1TN

REQ0 REQ1 REQ2 REQ3

: : : :

BCM4401 NU OZ711EZ1TN NU

2

5

4

3

2

1

+3V

R461 10K +-5%

R732 10K +-5% R457 100K +-5% R_0603 R455 100K +-5% R_0603 NS

U10C
D

16 SMB_CLK 16 SMB_DATA 16 SMB_LINK_ALERT# 16 SMLINK0 16 SMLINK1 16 28 RI# PCSPK TP40 1

C22 B22 A26 B25 A25 A28 A19 A27 A22 AB18 B23 AC20 AF21 A21 B21 E23

SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 RI# SPKR SUS_STAT# SYS_RST# GPIO0/BM_BUSY# GPIO11/SMBALERT#

SMB

GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP GPIO37/SATA3GP CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# PWROK

SATA GPIO

AF19 AH18 AH19 AE19 AC1 B2 C20 B24 D23 F22 AA4 AC22 C21 C23 C19 Y4 E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20 R588 1 1 1 1 1 1 1 1 1 1 1 1 1 1 100 +-5% TP120 TP119 R733 TP118 TP117 TP116

PLANARID0 PLANARID1 R469 CLK14_ICH7 CLK48_USB ICH_SUSCLK SUSB# SUSC# TP73 1 4 4 6 31 31 10K +-5% NS R479 10K +-5%

1 6,16 PM_SYSRST# 8 16 4 4 PM_BMBUSY# SMB_ALERT# STP_PCI# STP_CPU#

1

GPIO18/STPPCI# GPIO20/STPCPU# GPIO26 GPIO27 GPIO28 GPIO32/CLKRUN# GPIO33/AZ_DOCK_EN# GPIO34/AZ_DOCK_RST# WAKE# SERIRQ THRM# VRMPWRGD GPIO6 GPIO7 GPIO8 ICH7M REV 1.02 EDS

GPIO16/DPRSLPVR TP0/BATLOW# PWRBTN# LAN_RST# RSMRST# GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 GPIO38 GPIO39

R582 BATLOW# DNBSWON# 16,31 31 R404 100K +-5%

100 +-5%

DPRSLPVR

8,36

R590 100K +-5% R_0603

R411 RSMRST# 31 R730

16,24,26,31 CLKRUN# 30 BT_PWRON# TP46 16,20 PCIE_WAKE# 16,26,31 SERIRQ 16 PM_THRM# 36 IMVP_PWG SWI# SCI# KBSMI# 1 1

AG18 AC19 U2 F20 AH21 AF20 AD22 AC21 AC18 E21

0 +-5%

CRT_SENSE#

21

R589 10K +-5% NS

R731 100K +-5%

C

16,31 16,31 16,31

FPBACK# TP75 TP74 +3V

22

GPIO

PLANARID2 PLANARID3

+3VALW R391 C592 8 7 6 5 0.1UF/10V C_0402 R488 10K +-5% C594 0.1UF/10V C_0402 +3VALW

R458 100K +-5% R_0603

R412 100K +-5% R_0603 NS

U34 10K +-5% SPI_CS# SPI_MISO SPI_CLK SPI_MOSI R344 R351 R356 R359 51 +-5% 51 +-5% 51 +-5% 51 +-5% 1 2 3 4 CE# SO WP# GND VDD HOLD# SCK SI

R459 10K +-5% NS

R475 10K +-5%

SST25VF016B-1 NS

PLACE LESS THAN 2 INCH FROM THE ICH IF USING SHARED ARCHITECTURE.
U10D 20 20 20 20
B

Direct Media Interface

PCIE_RXN0 PCIE_RXP0 PCIE_TXN0 PCIE_TXP0 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1

C516 C_0402

0.1UF/10V C700 C_0402 0.1UF/10V C705 C_0402

PCIE_TXN0_C PCIE_TXP0_C 0.1UF/10V

F26 F25 E28 E27 H26 H25 G28 G27 K26 K25 J28 J27

PERn1 PERp1 PETn1 PETp1 PERn2 PERp2 PETn2 PETp2 PERn3 PERp3 PETn3 PETp3 PERn4 PERp4 PETn4 PETp4 PERn5 PERp5 PETn5 PETp5 PERn6 PERp6 PETn6 PETp6

20 20 20 20

C704 C_0402

PCIE_TXN1_C PCIE_TXP1_C 0.1UF/10V

+3VSUS

SPI_CLK SPI_CS# SPI_MOSI SPI_MISO 19 19 +3VSUS
A

USB_OC#0 USB_OC#1

RP1 10 5 1 2 3 4 6 7 8 9 10K X8 +-5% USB_OC#2 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#1 USB_OC#4 USB_OC#3 USB_OC#0

5

w

w w
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3
4

R480 10K +-5% R_0402

R476 10K +-5% R_0402

R478 10K +-5% R_0402

p la .
PCI-Express
M26 M25 L28 L27 P26 P25 N28 N27 T25 T24 R28 R27 R2 P6 P1 P5 P2 SPI_MOSI SPI_MISO

s p to
NOTE: RX--TX TX--RX
DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP V26 Y26 AB26 AD25 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_TXN[3:0] V25 Y25 AB25 AD24 DMI_TXP[3:0] U28 DMI_RXN0 W28 DMI_RXN1 AA28 DMI_RXN2 AC28 DMI_RXN3 DMI_RXN[3:0] U27 DMI_RXP0 W27 DMI_RXP1 AA27 DMI_RXP2 AC27 DMI_RXP3 DMI_RXP[3:0] DMI_CLKN DMI_CLKP AE28 AE27 CLK_PCIE_ICH# 4 CLK_PCIE_ICH 4 DMI_ZCOMP DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBRBIAS# USBRBIAS C25 D25 F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3 D2 D1 USB_RBIAS_PN DMI_IRCOMP_R SYSUSBP0SYSUSBP0+ SYSUSBP1SYSUSBP1+ SYSUSBP2SYSUSBP2+ SYSUSBP3SYSUSBP3+ SYSUSBP4SYSUSBP4+ SYSUSBP5SYSUSBP5+ 19 19 19 19 19 19 20 20 30 30 20 20 R460
3

m e h c
PLANAR ID 1 LEVEL 3 2 1 R458 R412 R455 R479 0 R459 R475
8 8 8 8 +1.5V R464 24.9 +-1% R_0603

a
0 +-5%

PLT_RST#

0 +-5% RSMRST# NS

ic t
PWROK 8,31 8,16,20

.c s

m o
D C

SYS GPIO Power MGT

Clocks

0

R457

R469

B

Place within 500 mils of ICH

SPI

SPI_CLK SPI_CS# SPI_ARB

USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7

D3 C4 D5 D4 E5 C3 A2 B3

OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31

USB

22.6 +-1%

ICH7M REV 1.02 EDS

Place within 500 mils of ICH

2

5

4

3

2

1

+5V

+3V 2

R483 10 +-5% 1

D65 RB751V-40 VCC5REF C523 0.1UF/10V C_0402 G10 AD17 U10F V5REF[1] V5REF[2] V5REF_Sus Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53] Vcc3_3[1] VccDMIPLL Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9] VccSATAPLL Vcc3_3[2] Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] VCC PAUX Vcc1_05[20] CORE VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4] Vcc3_3/VccHDA VccSus3_3/VccSusHDA V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3] Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11] Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21] VccRTC L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 V5 V1 W2 W7 U6 R7 AE23 AE26 AH26 AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19 A5 B13 B16 B7 C10 D15 F9 G11 G12 G16 C519 0.1UF/10V C_0402 +VCCP C550 1UF/10V C_0603 C528 0.1UF/10V C_0402 C555 0.1UF/10V C_0402 + CT24 220UF/2.5V TAJ_E

C518 1UF/10V C_0603

D

+5VSUS

+3VSUS F6 2

R485 10 +-5% 1

D61 RB751V-40 V5REF_SUS

C533 1UF/10V C_0603 FB39 BLM21PG220SN1

C556 0.1UF/10V C_0402

+1.5V

1

R_0805 C539 22uF/6.3V C_0805 C525 0.1UF/10V C_0402 C536 0.1UF/10V C_0402 C541 0.1UF/10V C_0402

C701 0.1UF/10V C_0402

C553 0.1UF/10V C_0402

C702 0.1UF/10V C_0402

C703 0.1UF/10V C_0402

C

1 +-5% +1.5V R481 R_0603 GPLL_R_L 1 L12 2 1uH,700mA,20% 20% C542 0.01UF/16V C_0402

C544 10uF/6.3V C_0805

+3V

C642 0.1UF/10V C_0402

AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23 B27 AG28

+3V C543 0.1UF/10V C_0402 +3V C540 0.1UF/10V C_0402 +3VSUS

0.1UF/10V

VccSus3_3[1] VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]

+1.5V +1.5V FB41 1 600 OHM/1.5A C522 C549 10uF/6.3V C534 0.1UF/10V 0.1UF/10V C_0402

R_0805

AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5 AD2 +3V AH11

B

+1.5V C538 1UF/10V C_0603

+3VSUS C552 0.1UF/10V C_0402 +1.5V

TP37 TP38

A

5

w

w w
C529 0.1UF/10V C_0402

p la .
AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9 E3 Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18] ATX VccSus3_3[19] VccUSBPLL C1 AA2 Y7 USB CORE ICH7M REV 1.02 EDS
4

VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[1