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PAMS Technical Documentation RAE2 Series PDA Phone
Chapter 2 Transceiver BS8 Baseband Block
Original 02/99
Copyright E 1999 Nokia Mobile Phones. All rights reserved.
RAE2 Baseband
PAMS Technical Documentation
AMENDMENT RECORD SHEET
Amendment Date Number Inserted By Comments Original
11/98
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PAMS Technical Documentation
RAE2 Baseband
CONTENTS Baseband Page No
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Connections from Baseband section of BS8 module Connectors to other modules of the product . . . . . . . . . . . . . . Bottom Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board to Board Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Coax cable connector . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . Microphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Baseband interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . Battery removal during charging . . . . . . . . . . . . . . . . . . . . . . PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . MAD core regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switched mode supply VSIM . . . . . . . . . . . . . . . . . . . . . . . . Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power up with power switch (PWRKEYx) . . . . . . . . . . . Power up with a charger . . . . . . . . . . . . . . . . . . . . . . . . . . Service Request State (SRS) . . . . . . . . . . . . . . . . . . . . . . Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 2 5 2 8 2 8 2 8 2 8 2 9 2 9 2 9 2 9 2 11 2 12 2 13 2 14 2 17 2 17 2 17 2 18 2 21 2 21 2 22 2 23 2 23 2 24 2 25 2 25 2 25 2 26 2 27 2 28 2 28 2 28 2 29 2 30 2 31 2 32 2 32 2 32 2 33
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Audio control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDA Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMT Alert Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . External audio connections . . . . . . . . . . . . . . . . . . . . . . . . . . Analog audio accessory detection . . . . . . . . . . . . . . . . . . . . Headset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Headset switch detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal audio connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 4wire PCM serial interface . . . . . . . . . . . . . . . . . . . . . . . . . Digital control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAD2 memory configuration . . . . . . . . . . . . . . . . . . . . . . MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAE2 Flashing connections . . . . . . . . . . . . . . . . . . . . . . Flashing methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flashing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COBBAGJ ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 33 2 34 2 34 2 34 2 36 2 36 2 36 2 37 2 37 2 38 2 38 2 40 2 41 2 41 2 41 2 42 2 42 2 43 2 43 2 43 2 44 2 45 2 45
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RAE2 Baseband
Introduction
This document contains the specification to the Baseband section of the BS8 module. The BS8 module carries out almost all CMT functions of RAE2. BS8 can be divided into two functional sections; BaseBand (BB) and RF. Some of CMT baseband circuits are implemented to both BS1 and BS2 modules. The Baseband module BS8 comprises four ASICs (CHAPS, CCONT, COBBAGJ and MAD2) that perform the baseband functions of the module.
BS1
BS8
AFC VCOPWR VCTCXO 13MHz PA SUPPLY
Synthesizer control RF SUPPLIES TX/RX TXC RXC TXPa LNA
RF earphone BB
VREF
HF MIC
COBBA
CCONT
VCOBBA 32kHz VBB VSIM
SIMCONN
MMC IF SCOTTY
MMC CONN
VBATT
8k
BATT.CONN
CMTPDA IF
MAD + Memories MAD
Flash 512k Sram 256k Eeprom VCHARG LIM
BATTERY
CHAPS
CMT UI
CMTUI IF
MBUS
BS2
Ext. audio IF BOTTOM CONNECTOR
Charger IF
Figure 1. BS8 BaseBand block in RAE2 product
Technical Summary
The BS8 module is implemented on a single double side 8layer printed circuit board. The main part of the baseband area is located on the bottom side of the PCB and only some components (bottom connector, battery connector and some filter components) are placed on the upper side (RF side). Component height space on the baseband is 2.0mm.
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The baseband is running from a 2.8V power rail, which is supplied by the power controlling ASIC. In the CCONT ASIC there are 6 individually controlled regulator outputs for RFsection and two outputs for the baseband. In addition there is one +5V power supply output (V5V) for flash programming voltage and for other purposes where a higher voltage is needed. The CCONT contains also a SIM interface, which supports both 3V and 5V SIMcards.
BaseBand Side
RF Side
Figure 2. BS8 Module
The interface between the baseband and the RF section is handled by the specific ASIC COBBA. The COBBA provides: A/D and D/A conversion of the inphase and quadrature receive and transmit signal paths A/D and D/A conversions of received and transmitted audio signals to and from the UI section. The COBBA supplies the analog TXC and AFC signals to the RF section according to the MAD DSP digital control and converts the analog AGC into digital signal for the DSP. The data transmission between the COBBA and the MAD is implemented using a parallel connection for high speed signalling and a serial connection for PCM coded audio signals. Digital speech processing is handled by the MAD asic. The COBBA is a dual voltage circuit, the digital parts are running from the baseband supply VBB and the analog parts are running from the analog supply VCOBBA.
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RAE2 Baseband
The COBBA supports three microphone inputs and two earphone outputs. The inputs can be taken from an internal microphone, a headset microphone or from an external microphone signal source. The output for the internal earphone is a dual ended type output capable of driving a dynamic type speaker. Input and output signal source selection and gain control are performed inside the COBBA according to control messages from the MAD. Call alerts, keypad tones, DTMF, and other audio tones are generated and encoded by the MAD and transmitted to the COBBA for decoding. EMC shielding (figure below) is implemented on the BB side using a metallized plastic Bcover and conductive gasket between the Bcover and the PCB. On the RF side the engine is shielded with a conductive frame which makes a contact to a ground ring of the CMT board and a ground plane of the PDA board. There is a conductive gasket between the frame and the PCB for ensuring proper shielding. In addition he RF area has three metal cans for RF shielding. Heat generated by the circuitry is conducted out mainly via the PCB ground planes. Conductive frame +gasket Metallized Bcover BS8 module Metal gasket
4 srews for fastening Bcover to frame
Metal cans
Microphone Bottom connector
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Technical Specifications
Maximum Ratings
Parameter Battery voltage, idle mode Charger input voltage Operating temperature range Storage temperature range Rating 0.3 ... 4.1V without charger 5.0 ... 16V 25C to +70 C 40C to +85 C
DC Characteristics
Supply voltages
Line Symbol Supply battery voltage Battery powerup voltage (HW) Battery cut off voltage (HW) Regulated baseband supply voltage Regulated baseband supply current Regulated VCORE supply voltage Regulated VCORE supply current COBBA analog supply voltage COBBA analog supply current Regulated 5V supply voltage Regulated 5V supply current Regulated 5V SIM supply voltage Regulated 5V SIM supply current Regulated 3V SIM supply voltage Regulated 3V SIM supply current Voltage reference 2.7 5 4.8 0 4.8 3 2.8 1 1.4775 2.8 20 5.0 1 5.0 10 3.0 6 1.5 Minimum 3.0 2.9 2.7 2.7 3 Typical / Nominal 3.6 3.0 2.8 2.8 50 1.3 2.65 50 2.85 100 5.2 30 5.2 30 3.2 30 1.5225 Maximum 4.1 3.1 2.9 2.85 125 V V V V mA V (changeable) mA V mA V mA V mA V mA V Unit / Notes
Note: The RF voltages are described later
AC Characteristics
Table 1. AC Specifications
Line symbol 32kHz RFIClk PCMClk SIMClk Minimum Typical / Nominal 32768 13 8 3.25 Maximum Hz, Sleep clock MHz, System clock kHz, PCM clock MHz, SIM Clock Unit / Notes
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RAE2 Baseband
Connectors
External Connections from Baseband section of BS8 module
This section describes the external electrical connections and interface levels on the baseband section of the BS8 module. The electrical interface specifications are collected into tables that cover a connector or a defined interface each.
Connectors to other modules of the product
Bottom Connector
The bottom connector has spring type of connections. In BS8 module there are contact pads for the spring connections.
X170
9 4 5 6 7 8 1 3 2
Figure 3. Bottom connector pads in BS8 module
The electrical specifications in the next table show the bottom connector signals and levels on the baseband. The system connector is used to connect the transceiver to accessories. The table gives the idle voltage produced by the acceptable chargers at the DC connector input. The absolute maximum input voltage is 30 V due to the transient suppressor that is protecting the charger input.
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Table 2. Baseband signals of the bottom connector (X170)
Pin 1 2 Name L_GND VIN Min 0 7.25 3.25 320 7.1 3.25 720 3 CHRG_ CTRL 0 2.0 32 1 4 SGND 47 10 380 5 XEAR 47 10 16 4.7 10 1.0 22 10 16 2.8 HEAR 28 626 1500 626 300 99 7.6 3.6 370 8.4 3.6 800 Typ Max 0 7.95 16.9 3.95 420 9.3 3.95 850 0.5 2.85 Unit V V V V mA V V mA V V Hz % µF µF k Vpp mV k V mV Supply ground Unloaded ACP7 Charger (5kohms load) Peak charger output voltage (5kohms load) Loaded charger output voltage (10ohms load) Supply current Unloaded ACP9 Charger Loaded charger output voltage (10ohms load) Supply current Charger control PWM low Charger control PWM high PWM frequency for a ACP9 PWM duty cycle Output AC impedance (ref. GND) Series output capacitance Resistance to phone ground Output AC impedance (ref. GND) Series output capacitance Load AC impedance to SGND (Headset) Load AC impedance to SGND (Accessory) Maximum output level (no load) Output signal level Load DC resistance to SGND (Accessory) Load DC resistance to SGND (Headset) DC voltage (47k pullup to VBB) Earphone signal (HF HFCM) Connected to COBBA HF output 6 XMIC 2.0 2.2 1 1.47 2.5 100 58 HMIC 0 3.2 1.55 2.85 600 490 29.3 k Vpp V V µA mV mV Input AC impedance Maximum signal level Mute (output DC level) Unmute (output DC level) Bias current Maximum signal level Microphone signal Connected to COBBA MIC3P input 7 MBUS 0 2.1 12,1 5 13 14 GND RF_OUT RF_IN 0 5 5 (TX levels) (TX levels) logic low logic high 0.5 2.85 0 33 33 V dBm dBm V Serial bidirectional control bus. Baud rate 9600 Bit/s Phone has a 4k7 pullup resistor RF ground RF signal from RF switch to internal antenna RF signal from PA to RF switch. Notes
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RAE2 Baseband
The bottom connector has mounting holes for a fastening to a shielding frame located between the PDA and CMT modules. The bottom connector has spring type connections to the CMT and the PDA module. The bottom connector includes the following parts: DC connector for external plugin charger and a desktop charger System connector for accessories. Connector for external RF signal. This connector is equipped with throwoverswitch. This is needed to change the RF signal path between external and internal antenna depending whether the ext antenna cable is connected or not.
PDA SIDE
PDA connections GND TX RX DTR External RF with switch
MBUS XMIC
XEAR SGND DCjack CHRG_CTRL VIN GND
CMT SIDE
Guiding and locking holes
Figure 4. Bottom Connector
Battery Connector
The electrical specifications for the battery connector are listed in the next table. The BSI contact of the battery connector is also used to detect when the battery is removed suddenly. This information is needed for driving the SIM card safely down before supply voltage is lost. The BSI contact in the battery connector has 0.5mm shorter working length than the supply power contacts to give enough time for the SIM shut down.
GND
X160
BSI
BTEMP VBATT
Figure 5.
Battery Connector
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Table 3. Battery Connector Electrical Specifications (X160)
Pin 1
Name VBATT
Min 3.0
Typ 3.6
Max 4.1
Unit V
Notes Battery voltage
2
BSI
0
2.85
V
Battery size indication CMT has 180kohm pull up resistor. SIM Card removal detection (Threshold is 2.4V@VBB=2.8V)
17.1 21.8 31.35 5
18 22 33
18.9 22.2 34.65
kohm kohm kohm ms
Field Test Battery (4.1V) BBS5 Service battery (No cells) BLN3 Liion battery (4.1V) The minimum time from BSI contact disengaged its battery contact to VBATT/GND disengaged its battery contacts when battery is removed. Battery temperature indication CMT has a 100k (+5%) pullup resistor, Battery package has a NTC pulldown resistor: 47k+5%@+25C , B=4050+3% Local mode initialization (in production) Battery ground
3
BTEMP
0
1.4
V
0 4 GND 0
1 0
kohm V
SIM card Connector
The SIM card connector is located on the baseband side of the BS8 module. The contacts of the SIM card connector are protected against electric discharge with ESD protection components.
SIMRST
X150
Figure 6. SIM Card Connector
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SIMDATA
VSIM
GND
SIMCLK
VSIM
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RAE2 Baseband
Table 4. SIM Connector Electrical Specifications (X150)
Pin 4 3, 5 Name GND VSIM Parameter GND 5V SIM Card 3V SIM Card 6 DATA 5V Vin/Vout 3V Vin/Vout Min 0 4.8 2.8 4.0 0 2.8 0 2 SIMRST 5V SIM Card 3V SIM Card 4.0 2.8 5.0 3.0 "1" "0" "1" "0" "1" "1" Typ Max 0 5.2 3.2 VSIM 0.5 VSIM 0.5 VSIM VSIM V SIM reset V SIM data Trise/Tfall max 1us Unit V V Notes Ground Supply voltage
1
SIMCLK
Frequency Trise/Tfall
3.25 25
MHz ns
SIM clock
VSIM supply voltages are specified to meet type approval requirements regardless the tolerances in components.
Memory Card Connector
The Memory card connector locates on BS8 module. Memory card is a changeable Flash or ROM memory with variable memory size. The PDA CPU can access with Memory card via synchronous serial interface. Memory card signals are routed from BS1 module to BS8 module through board to board connector.
X191
MMC_DATA MMC_GND MMC_CLK MMC_VSYS MMC_GND MMC_CMD NC
Figure 7.
Memory Card Connector
The signals of the MMC connector are specified in the board to board connector table.
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Board to Board Connector
All interfaces (except RF antenna signal) from the BS8 module to the X190 other RAE2 modules are routed over a 50pins board to board conpin 50 pin 26 nector. The interfaces can be divided into several groups; CMTUI, CMTHF audio, CMTPDA, MMC Figure 8. BoBo Connector PDA and supply lines for the BS1 and the BS2 modules. The CMT keyboard with keyboard illumination parts and the CMT display module with display illumination parts are implemented on a separate UI module (BS2), which contains also the PDA user interface and an antenna matching circuit. The baseband signals to the UI are routed over an board to board connector to the BS1 module and from the BS1 module through the hinge flex to the BS2 module. The Handsfree speaker and earpiece are included in the audio holder. Because the audio holder and the HF amplifier are located on the PDA module, several signals through the board to board connector are needed for carrying audios from the CMT to the PDA. There are data signals for data transmission between the CMT and the PDA modules. Some I/O signals are needed for carrying logic state information between modules. Signal definition and the most important specifications of signals are listed in the next table.
Table 5. Board to Board Connector (X190)
Pin 1,2, 34 3,4, 5 I/O Name VBATT Function Battery Positive Min 3.0 1.5 Typ 3.6 Max 4.1 1000 Unit VDC mA Description / Note Unregulated Battery Voltage Current to BS1 and BS2 module (max=peak current) pin 1 pin 25
6 7 8
O
XEAR GND
Audio Output for Handsfree Global Ground Battery Position Information 0.23 0.28 0.39 0.26 0.30 0.43
500
mVpp Reference for other signals
O
BATTDET
0.28 0.33 0.48 0.5 2.85
VDC VDC VDC VDC VDC
Field Test battery (only R&D use) Service battery (BBS5) BLN3 battery Low, HF amplifier disabled High, HF amplifier enabled
9
O
HFENA
Internal Handsfree Amplifier Control
0 2.1
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Table 5. Board to Board Connector (X190)
Pin 10 11 12 13 I I/O O O Name EARP EARN GND PWRONx Function Earpiece Positive Earpiece Negative Global Ground PDA start CMT to Service Request State (SRS) 0 2.3 14 I 32kHz Sleep clock to CMT 0 2.3 2.8 2.8 Min 50 Typ
(continued)
Max 223 Unit mVpp Description / Note Differential voltage between EARP and EARN nodes
0.45 2.85 0.45 2.85 12 32768
VDC VDC VDC VDC mA Hz
Active state, min. 64ms Inactive state Pulse low level Pulse high level Maximum current from PDA Pulse frequency Duty cycle (CMT requirements) Jitter (CMT requirements)
20
50
80 1
% %
15 16 O
GND VBB
Global Ground CMT regulated system voltage 2.7 2.8 2.85 1 VDC mA Regulated CMT baseband voltage Maximum current Low, active state VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC High, inactive state Low, backlight off High, backlight on Low High Low High Low High Low High
17
I
PWRKEYx
CMT Power On/Off Switch
0 2.7
0.5 2.85 0.5 2.8 2.85 0.2 2.8 2.85 0.2 2.8 2.85 0.2 2.8 2.85 0.2 2.8 2.85
18
O
CMT_BL_ON
CMT UI Backlight On
0 2.1
19
I
ROW3
CMT Keys Row 3
0 2.5
20
I
ROW2
CMT Keys Row 2
0 2.5
21
I
ROW1
CMT Keys Row 1
0 2.5
22
I
ROW0
CMT Keys Row 0
0 2.5
23 24 O
GND COL4
Global Ground CMT Keys Column 4 0 2.1 0.5 2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5 2.85 VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Low High Low High Low High Low High Low High
25
O
COL3
CMT Keys Column 3
0 2.1
26
O
COL2
CMT Keys Column 2
0 2.1
27
O
COL1
CMT Keys Column 1
0 2.1
28
O
COL0
CMT Keys Column 0
0 2.1
29
GND
Global Ground
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Table 5. Board to Board Connector (X190)
Pin 30 I/O O Name LCDCD Function CMT LCD Command / Data S l t Select CMT LCD Reset Min 0 2.1 0 2.1 32 O LCDCSx CMT LCD Chip Select 0 2.1 33 34 O GND GENSCLK Global Ground CMT LCD and CCONT Serial Clock Cl k 0 2.1 Typ
(continued)
Max 0.5 2.85 0.5 2.85 0.5 2.85 Unit VDC VDC VDC VDC VDC VDC Description / Note Low, Command High, Data Low, Reset active High, Reset inactive Low, active High, inactive
31
O
LCDRSTx
0.5 2.85 3.250
VDC VDC MHz
Low HIgh Pulse frequency in active state (LCD communication) Low High Maximum pulse frequency
35
O
GENSDIO
CMT LCD and CCONT Serial Data D t
0 2.1 1.625
0.5 2.85
VDC VDC MHz
36 37 I
GND FBUS_RXD
Global Ground Fast Serial Data to CMT 0 2.3 220 0.45 2.85 VDC VDC kW 0.5 2.85 47 VDC VDC kW Low High Pulldown resistor in CMT Low High Pullup resistor in CMT
38
0
FBUS_TXD
Fast Serial Data to PDA
0 2.1
39 40 I/O
GND MBUS
Global Ground Bidirectional Serial Bus 0 2.1 0 2.3 2.8 47 0.5 2.85 0.45 2.85 VDC VDC VDC VDC kW 2.85 VDC VDC 2.85 VDC kohm Low, to the PDA Low, to the PDA Low, from the PDA High, from the PDA Pullup resistor in CMT Max current 1mA Low, Lid closed High, Lid open Pullup resistor in PDA
41 42
I I
VSYS LIDSWITCH
PDA regulated system voltage Lid State Information
2.75
2.8 0
2.75
2.8 10
43
THIS SIGNAL IS NOT IN USE! GND Global Ground
44
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Table 5. Board to Board Connector (X190)
Pin 45 I/O I/O Name MMC_CMD Function Memory Card Command / Address / Response, Bidirectional Min 0 2.3 Typ 0 2.8
(continued)
Max 0.45 2.85 Unit VDC VDC Description / Note Low, Data to the card High, Data to the card, pulled up with 10kohm resistor to MMC_VSYS in CMT module Low, Data from the card High, Data from the card, pulled up with 10kohm resistor to MMC_VSYS in CMT module Frequency
0.34 2.1
VDC VDC
259.3 46 47 I I/O MMC_VSYS MMC_DATA Memory Card Power Supply Memory Card Bidirectional Data 2.75 0 2.3 0 2.8 2.85 0.45 2.85
kHz VDC VDC VDC
Low, Data to the card High, Data to the card, pulled up with 10kohm resistor to MMC_VSYS in CMT module Low, Data from the card High, Data from the card, pulled up with 10kohm resistor to MMC_VSYS in CMT module Frequency
0 2.1
0
0.34
VDC VDC
8.294 48 49 I GND MMC_CLK Global Ground Memory Card Clock 0 2.3 0.2592 50 GND Global Ground 0 2.8 0.45 2.85 8.294
MHz
VDC VDC MHz
Low High Frequency
RF Coax cable connector
A small SMD coax cable connector is situated on the baseband side of the BS8 module. It comprises the RF output for the internal antenna.
Internal Signals and Connections
This section describes the internal electrical connections and interface levels on the baseband part of the BS8 module. The electrical interface specifications are collected into tables that cover a connector or a defined interface each.
Microphone
The internal microphone is connected to the PCB with spring contacts. The microphone input level is specified in the table below. The micro-
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phone requires a bias voltage to operate. The bias voltage is generated from the VCOBBA supply with a transistor which is driven by the MAD general I/O signal (MCUGenOut5).
Table 6. Microphone signals (B250)
Pin 6 Name MICP Min Typ 3.2 Max 20 Unit mVpp Notes Differential voltage between MICP and MICN
RF Baseband interface
The interface signals between the BB and the RF section are shown in next the table as a logical interface. On PCB level the baseband supplies voltages from the CCONT to the separate rfsubblocks. The maximum values specified for the digital signals in the table are the absolute maximum values from the RF interface point of view.
Table 7. AC and DC Characteristics of RF/BB signals
Signal name VBATT From To Battery RF MAD CCONT Parameter Voltage Current Logic high "1" Logic low "0" Logic high "1" Logic low "0" Logic high "1" Logic low "0" Logic high "1" Logic low "0" Voltage Current Source resistance PDATA0 MAD CRFU1A MAD SUMMA MAD SUMMA Logic high "1" Logic low "0" Logic high "1" Logic low "0" Logic high "1" Logic low "0" Data rate frequency SCLK MAD SUMMA Logic high "1" Logic low "0" Data rate frequency 2.1 0 3.25 2.1 0 2.1 0 2.1 0 3.25 2.85 0.8 10 2.85 0.5 2.85 0.5 2.85 0.5 2.1 0 2.1 0 2.1 0 2.1 0 1.478 1.5 Minimum 3.0 Typical 3.6 Maximum 5.0/6.0 3500 2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5 1.523 100 V mA V V V V V V V V V uA ohm V V V V V V MHz V V MHz Synthesizer clock Synthesizer data Nominal gain in LNA Reduced gain in LNA PLL enable Unit Function Supply voltage for RF (PA on/PA off) VR1, VR6 in CCONT ON VR1, VR6 in CCONT OFF VR3, VR4 in CCONT ON VR3,VR4 in CCONT OFF VR2, VR5 in CCONT ON VR2, VR5 in CCONT OFF VR7 in CCONT ON VR7 in CCONT OFF Reference voltage for SUMMA and CRFU1a
VXOENA
SYNPWR
MAD CCONT MAD CCONT MAD CCONT CCONT SUMMA
RXPWR
TXPWR
VREF
SENA
SDATA
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Table 7. AC and DC Characteristics of RF/BB signals (continued)
Signal name AFC From To COBBA VCTCXO Parameter Voltage Resolution Load resistance (dynamic) Load resistance (static) Noise voltage Settling time RFC VCTCXO MAD Frequency Signal amplitude Load resistance Load capacitance RXIP/RXIN SUMMA COBBA Output level Source impedance Load resistance Load capacitance TXIP/TXIN COBBA SUMMA Differential voltage swing DC level Differential offset voltage (corrected) Diff. offset voltage temp. dependence Source impedance Load resistance Load capacitance DNL INL Group delay missmatch TXQP/TXQN COBBA SUMMA Differential voltage swing DC level Differential offset voltage (corrected) Diff. offset voltage temp. dependence Source impedance Load resistance Load capacitance Resolution DNL INL Group delay mismatch 8 +/ 0.9 +/1 100 40 10 0.75 x 1.022 0.784 0.75 x 1.1 0.8 40 10 +/ 0.9 +/1 100 0.75 x 1.18 0.816 +/ 2.0 +/ 1.0 200 0.75 x 1.022 0.784 0.75 x 1.1 0.8 1 4 0.75 x 1.18 0.816 +/ 2.0 +/ 1.0 200 0.5 10 5 7 50 10 1344 600 13 1.0 2.0 Minimum 0.046 11 10 1 500 0.5 Typical Maximum 2.254 V bits kohm Mohm uVrms ms MHz Vpp kohm pF mVpp ohm Mohm pF Vpp V mV mV ohm kohm pF LSB LSB ns Vpp V mV mV ohm kohm pF bits LSB LSB ns Differential quadrature phase TX baseband signal for the RF modulator Differential inphase TX baseband signal for the RF modulator Differential RX 13 MHz signal to baseband High stability clock signal for the logic circ its circuits 10...10000Hz Unit Function Automatic frequency control signal for VC(TC)XO
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Table 7. AC and DC Characteristics of RF/BB signals (continued)
Signal name TXP From To MAD SUMMA COBBA SUMMA Parameter Logic high "1" Logic low "0" Voltage Min Voltage Max Vout temperature dependence Source impedance active state Source impedance power down state Input resistance Input capacitance Settling time Noise level Resolution DNL INL Timing inaccuracy RXC COBBA SUMMA Voltage Min Voltage Max Vout temperature dependence Source impedance active state Source impedance power down state Input resistance Input capacitance Settling time Noise level Resolution DNL INL 10 +/0.9 +/ 4 1 10 10 500 grounded Mohm pF us uVrms bits LSB LSB 0...200 kHz 0.12 2.27 10 +/0.9 +/ 4 1 0.18 2.33 10 200 10 10 10 500 high Z kohm pF us uVrms bits LSB LSB us V V LSB ohm Receiver gain control 0...200 kHz Minimum 2.1 0 0.12 2.27 Typical Maximum 2.85 0.5 0.18 2.33 10 200 V V V V LSB ohm Unit Function Transmitter power control enable Transmitter power control
TXC
NOTE: Logic controls in low state when RF in power off.
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Functional Descriptions
Power Management
RF SUPPLIES
VREF SYNPWR VSYN VRX VCP VTX PA SUPPLY VCO 13MHz CLK
RF BASEBAND HFamp HF COBBA
VREF VCOBBA
CCONT
VSIM
SIMCONN
VBB
SCOTTY
MAD MAD + MEMORIES
PWRKEYx PURX
BATT.CONN
PHASER
VCORE
VBATT
CMT UI
CHAPS
Liion Battery 3.6V
BS1
BS8
LIM AGND GND
BS2
BOTTOM CONNECTOR CHARGER IF
VIN
Figure 9. CMT power distribution
In normal operation the baseband is powered from the phone Liion battery. The battery consists of two LithiumIon cell connected in parallel. An external charger is used for recharging the battery and supplying power to the phone. The charger is a "performance travel charger" (Nokia ACP9) that can deliver supply current up to 850 mA . It is also possible to use a standard travel charger (Nokia ACP7). The ACP7 delivers only 400 mA which is too little for charging the battery during a call. The baseband contains components that control power distribution to the CMT parts excluding those that use continuous battery supply. The battery feeds power directly to three CMT parts of the system: CCONT, power amplifier, and CMT UI. The figure above is the block diagram of the power distribution.
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The charging control ASIC called CHAPS provides protection against overvoltages, charger failures and pirate chargers etc. that would otherwise cause damage to the phone.
Battery identification
Battery types are identified by a pulldown resistor inside the battery pack. The MCU can identify the battery by reading the BSI line DCvoltage level with a CCONT A/D converter. Also the PDA needs to know whether the battery is connected or not. The BSI line inside transceiver has a 180k pullup to PDA system voltage, VSYS. CMOS switch (D100) is added between VSYS powered and VBB powered circuits for preventing leakage current.
BATTERY BLN3
VBATT BTEMP
To PDA VSYS
VSYS
BS8
180k BSI 10k
D100
VCC
BSI
EN
CCONT
33k 27p GND VBB 2n2 100k
SIMCardDetX
MAD
Figure 10.
BSI connections
The battery identification line is used also for battery removal detection on the CMT side. The BSI line is connected to a SIMCardDetX line of MAD2 (D200). SIMCardDetX is a threshold detector with a nominal input switching level 0.85xVcc for a rising edge and 0.55xVcc for a falling edge. The battery removal detection is used as a trigger to power down the SIM card before the power is lost. The working length of the BSI contact in the battery connector is made 0.5 mm shorter than the supply voltage contacts so that there is a delay between battery removal detection and supply power off.
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Vcc 0.850.05 Vcc 0.550.05 Vcc
SIMCARDDETX GND
Figure 11. SIMCardDetX detection levels
SIGOUT
Battery charging
The electrical specifications define the idle voltages generated by the acceptable chargers at the DC connector input. The absolute maximum input voltage is 30V due to the transient suppressor that is protecting the charger input. At the phone end there is no difference between a plugin charger or a desktop charger. The DCjack pins and bottom connector charging pads are connected together inside the phone. Charging block diagram is below.
MAD To PA 33R/ 100MHz 0R22
BLN3
Liion 1030mAh
LIM VOUT
BS8
33R/100MHz VCH GND 47k 27p 1u 1.5A VIN
CHAPS
RSENSE PWM
CHARGER (ACP7) ACP9 LCH9
30V
VBAT
ICHAR PWM_OUT VCHAR
22k
CHRG_ CTRL NOT IN ACP7
CCONT
CCONTINT GND
5.5V MAD 1n
4k7 33R/ 100MHz L_GND
Figure 12.
Charging block diagram
Startup charging
When a charger is connected, the CHAPS is supplying a startup current minimum of 130mA to the phone. The startup current provides initial
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charging to a phone with an empty battery. The startup circuit charges the battery until the battery voltage level 3.0V (+/ 0.1V) is reached. Then the CCONT releases the PURX reset signal and the program execution starts. The charging mode is changed from startup charging to PWM charging that is controlled by the MCU software. If the battery voltage reaches 3.55V (3.75V maximum) before the program has taken control over the charging, the startup current is switched off. The startup current is switched on again when the battery voltage has sunk to 100mV (nominal).
Table 8. Startup characteristics
Parameter Symbol Min Typ Max Unit
VOUT Start up mode cutoff limit VOUT Start up mode hysteresis NOTE: Cout = 4.7 uF Startup regulator output current VOUT = 0V ... Vstart
Vstart Vstarthys Istart
3.45 80 130
3.55 100 165
3.75 200 200
V mV mA
Battery overvoltage protection
Output overvoltage protection is used to protect the phone from damage. The power switch is immediately turned OFF if the voltage in VOUT rises above VLIM1.
Table 9. VLIM characteristics
Parameter Symbol LIM input Min Typ Max Unit
Output voltage cutoff limit
VLIM1
LOW
4.4
4.6
4.8
V
When the switch in output overvoltage situation has once turned OFF, it stays OFF until the the battery voltage falls below VLIM1 and PWM = LOW is detected. The switch can be turned on again by setting PWM = HIGH.
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VCH
VCH
VOUT
VLIM1
t
t ON SWITCH PWM (32Hz) Figure 13. Output overvoltage protection( in principle; not in timescale) OFF ON
Battery removal during charging
Output overvoltage protection is also needed in case the main battery is removed when charger connected or charger is connected before the battery is connected to the phone. If the battery is removed during charging, the SIMCardDetX signal goes active and the SIMCard is driven down.
PWM control
The ACP9 is controlled with PWM at a frequency of 32Hz. When the PWM rate is 32Hz CHAPS keeps the power switch continuously in the ON state.
SWITCH
ON
PWM (32Hz)
Figure 14. Switch control with 32 Hz frequency (in this case 50% duty cycle)
Battery temperature
The battery temperature is measured with a NTC inside the battery pack (see table 12). The BTEMP line in the transceiver has a 100k pullup to
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the VREF. The MCU calculates the battery temperature by reading the BTEMP line DCvoltage level with a CCONT A/Dconverter.
BVOLT
VREF
BATTERY
BSI BTEMP
RT NTC 100k 10k
CMT
BTEMP
CCONT
27p
10n
BGND
MAD
Figure 15. Standard battery BTEMP connection
Based on 47kW ± 5 % NTC with B = 4090 ±1.5 %. Without any alignment, with that and 1 % pullup resistor, ± 2.5 _C accuracy is achieved between 20 and +60 _C (± 3.5 _C @ 40 ... +85 _C).
Table 10. Battery temperature vs. AD readings and NTC resistance
T [_C] 40 35 30 25 20 15 10 5 0 AD 963 942 915 882 842 795 743 685 623 R [kW] 1589 1151 842.8 622.6 464.1 349.0 264.6 202.3 155.8 T [_C] 5 10 15 20 25 30 35 40 45 AD 560 497 436 379 327 280 238 202 171 R [kW] 120.9 94.53 74.40 58.95 47.00 37.71 30.43 24.70 20.15 T [_C] 50 55 60 65 70 75 80 85 90 AD 145 122 103 88 74 63 54 46 39 R [kW] 16.53 13.63 11.30 9.404 7.865 6.607 5.573 4.721 4.015
NOTE: NTC R values and corresponding AD values are calculated values. Because of tolerances real values may differ from the calculated values.
Supply voltage regulators
The heart of the CMT power distribution is the CCONT. It includes all the voltage regulators and feeds power to the whole system. The baseband digital parts are powered from the VBB regulator which provides 2.8V baseband supply. The baseband regulator is active always when the phone is powered on. The VBB baseband regulator feeds the MAD and memories, the COBBA digital parts and the LCD driver in the UI section. There is a separate regulator for the SIM card. The regulator is selectable
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between 3V and 5V and controlled by the SIMPwr line from MAD to CCONT. The COBBA analog parts are powered from a dedicated 2.8V supply VCOBBA. The CCONT supplies also 5V for RF and for flash VPP.
Table 11. Regulator activity in different operating modes
Operating mode Power off Power on Reset Sleep Off On On On Vref RF REG Off On/Off Off VR1 On Off VCOBBA Off On On Off Off On On On VBB Off On Off On VSIM SIMIF Pull down On/Off Pull down On/Off
NOTE: The COBBA regulator is off in SLEEP mode. Its output pin may be fed from VBB in SLEEP mode by setting bit RFReg(5) to '1' (default). CCONT includes also five additional 2.8V regulators providing power to the RF section. These regulators are controlled either by the direct control signals from the MAD or by the RF regulator control register in the CCONT which the MAD updates. Below are the listed the MAD control lines and the regulators they are controlling. TxPwr controls VTX regulator (VR5) RxPwr controls VRX regulator (VR2) SynthPwr controls VSYN_1 and VSYN_2 regulators (VR4 and VR3) VCXOPwr controls VXO regulator (VR1) The CCONT generates also a 1.5 V reference voltage VREF to the COBBA, SUMMA and CRFU. The VREF voltage is also used as a reference to some of the CCONT A/D converters. In addition to the above mentioned signals, the MAD includes also a TXP control signal to the SUMMA power control block and to the power amplifier. The transmitter power control TXC is led from the COBBA to theSUMMA. NOTE 1: Characteristics above are NOT valid if Vbat < 3.0V. NOTE 2: Line regulation is 20dB for f<100kHz when battery voltage is lower than 3.1V.
MAD core regulator
This block includes a linear voltage regulator with programmable output voltage, which supplies the MAD core. The output voltage can be changed from typical 1.30 V to 2.65 V in 225mV steps. The default output voltage is 1.975V. Control is possible via control register CVReg; the details are available in the digital specification of CCONT ASIC. If the regulator is not used, the control must be set to '0', and the output left floating.
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The lower core voltage is used only with MAD c07 technology in near future. There are two jumper resistors (R151 and R152, see the BS8 schematics) in baseband for selecting between normal or lower MAD core voltage.
Switched mode supply VSIM
There is a switched mode supply for SIMinterface. SIM voltage is selected via serial IO. The 5V SMR can be switched on independently of the SIM voltage selection, but can't be switched off when the VSIM voltage value is set to 5V. In the next figure the principle of the SMR / VSIMfunctions is shown.
CCONT V5V_4 VBAT V5V_3
External
V5V_2 VSIM 5V5 V5V 5V 5/3V
Figure 16.
Principle of the SMR power functions
Power up
The baseband is powered up by: 1. 2. 3. Pressing the power key Connecting a charger to the phone. PDA can power BB to SRS by pulling PWRONx line to low state.
Power up with power switch (PWRKEYx) When the power on switch is pressed, the PWRKEYx signal goes low and pulls the CCONT PWRONx pin to low. The CCONT then switches on the CCONT digital section and the VCXO as was the case with the charger
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driven power up. If the PWRONX is low when the 62 ms delay expires, the PURX is released and the SLEEPX control goes to MAD. If the PWRONX is not low when 62 ms expires, the PURX will not be released, and CCONT will go to power off ( digital section will send power off signal to analog parts).
SLEEPX
PURX
PWRONX VR1,VR6 VBB (2.8V) Vchar
1 2
3
1:Power switch pressed ==> Digital voltages on in CCONT (VBB) 2: CCONT digital reset released. VCXO turned on 3: 62 ms delay to see if power switch is still pressed. Figure 17. Power up with switch
Power up with a charger When the charger is connected, the CCONT switches on the CCONT digital voltage as soon as the battery voltage exceeds 3.0V. The reset for the CCONT's digital parts is released when the operating voltage is stabilized (50 us from switching on the voltages). The operating voltage for the VCXO is also switched on. The counter in the CCONT digital section keeps the MAD in reset for 62 ms (PURX) to make sure that the clock provided by VCXO is stable. After this delay the MAD reset is released, and the VCXO control (SLEEPX) is given to the MAD. The CMT start to so called acting deadstate which means that only the charging software is running and e.g. the RF is powered off. The next diagram describes the power on procedure with charger (the picture assumes empty battery, but the situation would be the same with full battery):
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SLEEPX
PURX
VXO Vbat VR6 VR1 VBB (2.8V) Vchar Vref 1 2 3
1: Battery voltage over 3.0==>Digital voltages to CCONT (VBB) 2: CCONT digital reset released. VCXO turned on 3: 62ms delay before PURX released Figure 18. Power up with charger
Service Request State (SRS) If CMT is powered off, the PDA has a possibility to startup the CMT to SERVICE REQUEST (SRS) state by using PWRONx line. The PDA can do it by pulling the PWRONx line to the low ("0") state. The difference between the SRS and acting dead is that the SRS is invisible to the user. Also during the SRS the RF parts are always powered off. The SRS is needed when the PDA is going to communicate with the CMT (e.g. asking some SIM information or battery voltage information) when the CMT is powered off.
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PDA
CMT
PWRKEYx
1k ROW0
MAD SCOTTY
inactive: "HighZ" active: "0" VBAT 200k / 2k pwroff / pwron
PWRONx
10k
PWRONX
CCONT
0
1
2
3 ROW0 PWRONx
(CCONT pin 29)
CMT is powered by PWRKEYx:
VBB 0s 0 62ms 1 2 3 ROW0 PWRONx
(CCONT pin 29)
t
CMT is powered by PWRONx:
VBB 0s 62ms 0: CCONT PWRONx input goes to "0". CCONT start power on se quency and releases BB regulator (VBB 2.8V). 1: When PWRONx has been "0" at least 62ms, CCONT gives system control to MAD. MAD start execute MCU SW. 2: MCU SW read the state of the ROW0 signal. If it is "1" MCU SW go to SRS If it is "0" MCU SW continues to active state. 3: Power on/off key or PWRONx are released. Figure 19. SRS versus normal powerup.
t
Active Mode
In the active mode the phone is in normal operation, scanning for channels, listening to a base station, transmitting and processing information. All the CCONT regulators are operating. There are several substates in the active mode depending on if the phone is in burst reception, burst transmission, if DSP is working etc..
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Sleep Mode
In the sleep mode all the regulators except the baseband VBB and the SIM card VSIM regulators are off. Sleep mode is activated by the MAD after MCU and DSP clocks have been switched off. The voltage regulators for the RF section are switched off and the VCXO power control, VCXOPwr is set low. In this state only the 32 kHz sleep clock oscillator in CCONT is running. The flash memory power down input is connected to the ExtSysResetX signal, and the flash is deep powered down during the sleep mode. The sleep mode is exited either by the expiration of a sleep clock counter in the MAD or by some external interrupt, generated by a charger connection, key press, headset connection etc. The MAD starts the wake up sequence and sets the VCXOPwr and ExtSysResetX control high. After VCXO settling time other regulators and clocks are enabled for active mode. If the battery pack is disconnected during the sleep mode, the CCONT pulls the SIM interface lines low as there is no time to wake up the MCU.
Charging
Charging can be performed in any operating mode. The battery type is indicated by a resistor inside the battery pack. The resistor value corresponds to a specific battery capacity which is defined in the RAE2 to 1030mAh. The battery voltage, temperature, size and current are measured by the CCONT controlled by the charging software running in the MAD. The power management circuitry controls the charging current delivered from the charger to the battery. Charging is controlled with a PWM input signal, generated by the CCONT. The PWM pulse width is controlled by the MAD and sent to the CCONT through a serial data bus. The battery voltage rise is limited by turning the CHAPS switch off when the battery voltage has reached 4.1V (LiIon). Charging current is monitored by measuring the voltage drop across a 220mohm resistor.
Power Off
The baseband is powered down by: 1. 2. 3. Pressing the power key, that is monitored by the MAD, which starts the power down procedure. If the battery voltage is dropped below the operation limit, either by not charging it or by removing the battery. Letting the CCONT watchdog expire, which switches off all CCONT regulators and the phone is powered down.
The power down is controlled by the MAD. When the power key has been pressed long enough or the battery voltage is dropped below the
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limit, the MCU initiates a power down procedure and disconnects the SIM power. Then the MCU outputs a system reset signal and resets the DSP. If there is no charger connected, the MCU writes a short delay to CCONT watchdog and resets itself. After the set delay the CCONT watchdog expires, which activates the PURX and all regulators are switched off and the phone is powered down by the CCONT. If a charger is connected when the power key is pressed the phone enters into the acting dead mode.
Watchdog
The Watchdog block inside the CCONT contains a watchdog counter and some additional logic which are used for controlling the power on and power off procedures of CCONT. Watchdog output is disabled when WDDisX pin is tied low. The WD-counter runs during that time, though. Watchdog counter is reset internally to 32s at power up. Normally it is reset by the MAD writing a control word to the WDReg.
Audio control
The audio control and processing is controlled by the COBBAGJ ASIC, which contains the audio and rf codecs, and the MAD2, which contains the MCU, ASIC and DSP blocks handling and processing the audio signals. The RAE2 audio block diagram is presented in the figure next page.
VCOBBA Premult. Preamp Multipl. Bias+ EMC
SCOTTY
PWM
MIC
MIC2 MIC1 MIC3
COBBA
LP Pre A D
HFCM Amp AuxOut
Multipl. LP
Serial IF
Earphone
FET Switch
HF Ear
A
D
PCM BUS
Micbias HFena
MAD
MCU
DSP
encoding decoding VAD echo cancel equalization
HFspeaker
amp Emc + Acc. Interface HookDet HeadDet
SGND
BS1
BS8
XMIC
XEAR
EAD
CCONT
BOTTOM CONNECTOR
Figure 20. RAE2 audio block diagram
The baseband supports three microphone inputs and two earphone outputs. The inputs can be taken from an internal microphone, a headset mi-
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crophone or from an external microphone signal source. The microphone signals from different sources are connected to separate inputs at the COBBAGJ. Inputs for the microphone signals are differential type. The MIC3 input is used for a headset microphone that can be connected directly to the system connector. The internal microphone is connected to the MIC2 input and an external preamplified microphone (handset/ handsfree) signal is connected to the MIC1 input. In the COBBA there are also three audio signal outputs of which dual ended EAR lines are used for internal earpiece and HF line for accessory audio output. The third audio output AUXOUT is used only for bias supply to the headset microphone. When the lid is open the downlink audios can be routed to the internal HF amplifier. This amplifier and the HF speaker are located on the PDA module. The MAD is able to enable the HF amplifier with an HFenasignal. The internal microphone acts as a handsfree microphone during a HF call. The microphone signal level is amplified more during an HF call than a normal call.
PDA Tones
The PDA keyclicks and warning tones are played via the earphone. There is an external paraller FET switch circuit with earphone located on the PDA module. The PWM output of the PDA processor is connected to this circuit and thus the PDA is able to play tones via the earphone.
CMT Alert Signal Generation
A HF speaker is used for giving alert tones and/or melodies as a signal of an incoming call. The alert signals are routed to the XEAR line by the DSP. Keypress and user function response beeps are generated with the earphone.
External audio connections
The external audio connections are presented in the next figure. A headset can be connected directly to the system connector. The headset microphone bias is supplied from the COBBA AUXOUT output and fed to the microphone through the XMIC line. The 330ohm resistor from the SGND line to the AGND provides a return path for the bias current.
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Baseband
47k 22k HookDet
2.8 V
MAD
22k HeadDet 1u 100n
CCONT
EAD 2.8 V
47k 2k2 AUXOUT 1m 10m HF 22p 10m HFCM 22p 330R 450ohm/ 100M XMIC 47R 450ohm/ 100M SGND 47R 450ohm/ 100M XEAR
COBBA
33n MIC1N MIC1P 33n 33n MIC3N MIC3P 33n
22p
Figure 21. Combined headset and system connector audio signals (Headset can be connected to system connector)
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Analog audio accessory detection
The XEAR signal line comprises a 47 kW pullup in the transceiver and 10 kW pulldown to SGND in the accessory. The XEAR is pulled down when an accessory is connected, and pulled up when disconnected. The XEAR is connected to the HookDet line (in MAD), an interrupt is given due to both connection and disconnection. There is filtering between XEAR and HookDet to prevent audio signal giving unwanted interrupts. External accessory notices tha poweredup phone by detecting voltage in XMIC line. The table below is a truth table for detection signals.
Table 12. Truth table for HookDet and HeadDet
Accessory connected No accessory connected Headset HDC8 with a button switch pressed Headset HDC8 with a button switch released Handsfree (HFU2) HookDet High Low High High HeadDet High Low Low *) High Notes Pullups in the transceiver XEAR and XMIC loaded (dc) XEAR unloaded (dc) Detected via MBUS
*) HeadDet (MAD) cannot be used during a call, because of the 1.5V bias from AUX OUT (COBBA)
Headset detection
The external headset device is connected to the system connector, from which the signals are routed to the COBBA headset microphone inputs and earphone outputs. In the XMIC line there is a (47 + 2.2) kW pullup in the transceiver. The microphone is a low resistance pulldown compared to the transceiver pullup. When there is no call going, the AUXOUT is in high impedance state and the XMIC is pulled up. When the headset is connected, the XMIC is pulled down. The XMIC is connected to the HeadDet line (in MAD), an interrupt is given due to both connection and disconnection. There is filtering between the XMIC and the HeadDet to prevent audio signal giving unwanted interrupts (when an accessory is connected).
Headset switch detection
The XEAR line comprises a 47 kW pullup in the transceiver. The earphone is a low resistance pulldown compared with the transceiver pull up. When a remote control switch is open, there is a capacitor in series with the earphone, so the XEAR (and HookDet) is pulled up by the phone. When the switch is closed, the XEAR (and HookDet) is pulled down via the earphone. So both press and release of the button gives an interrupt. During a call there is a bias voltage (1.5 V) in the AUXOUT, and the HeadDet cannot be used. The headset interrupts should to be disabled during a call and the EAD line (AD converter in CCONT) should be polled to see if the headset is disconnected.
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RAE2 Baseband
Internal audio connections
The speech coding functions are performed by the DSP in the MAD2 and the coded speech blocks are transferred to the COBBAGJ for digital to analog conversion, down link direction. In the up link direction the PCM coded speech blocks are read from the COBBAGJ by the DSP. There are two separate interfaces between the MAD2 and COBBAGJ: a parallel bus and a serial bus. The parallel bus features 12 data bits, 4 address bits, read and write strobes and a data available strobe. The parallel interface is used to transfer all the COBBAGJ control information (both the RFI part and the audio part) and the transmit and receive samples. The serial interface between MAD2 and COBBAGJ includes transmit and receive data, clock and frame synchronization signals. It is used to transfer the PCM samples. The frame synchronization frequency is 8 kHz which indicates the rate of the PCM samples and the clock frequency is 1 MHz. The COBBA generates both clocks.
4wire PCM serial interface
The interface consists of the following signals: a PCM codec master clock (PCMDClk), a frame synchronization signal to DSP (PCMSClk), a codec transmit data line (PCMTX) and a codec receive data line (PCMRX). The COBBAGJ generates the PCMDClk clock, which is supplied to DSP SIO. The COBBAGJ also generates the PCMSClk signal to DSP by dividing the PCMDClk. The PCMDClk frequency is 1.000 MHz and is generated by dividing the RFIClk 13 MHz by 13. The COBBAGJ further divides the PCMDClk by 125 to get a PCMSClk signal, 8.0 kHz.
PCMDClk PCMSClk PCMTxData PCMRxData sign extended 15 14 13 sign extended MSB 12 MSB LSB 0 LSB
11
10
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Digital control
All the baseband functions are controlled by the MAD2 ASIC, which consists of a MCU, a system ASIC and a DSP. In addition to the internal RAM/ROM memory, the MAD2 has an external RAM memory and external FLASH and EEPROM type of memories.
MAD2
MAD2 comprises the following building blocks: ARM RISC processor with both 16bit instruction set (THUMB mode) and 32bit instruction set (ARM mode) TI Lead DSP core with peripherals: API (Arm Port Interface memory) for MCUDSP communication, DSP code download, MCU interrupt handling vectors (in DSP RAM) and DSP booting Serial port (connection to PCM) Timer DSP memory (80 kW RAM in PD version of MAD2) BUSC (BusController for controlling accesses from ARM to API, System Logic and MCU external memories, both 8 and 16bit memories) System Logic CTSI (Clock, Timing, Sleep and Interrupt control) MCUIF (Interface to ARM via BUSC). Contains MCU BootROM DSPIF (Interface to DSP) MFI (Interface to COBBA AD/DA Converters) CODER (Block encoding/decoding and A51&A52 ciphering) AccIF(Accessory Interface) SCU (Synthesizer Control Unit for controlling 2 separate synthesizer) UIF (Keyboard interface, serial control interface for COBBA PCM Codec, LCD Driver and CCONT) SIMI (SimCard interface with enhanced features) PUP (Parallel IO, USART and PWM control unit for vibra and buzzer) The MAD2 operates from a 13 MHz system clock, which is generated from the 13MHz VCXO frequency. The MAD2 supplies a 6,5MHz or a
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13MHz internal clock for the MCU and system logic blocks and a 13MHz clock for the DSP, where it is multiplied to 45.5MHz DSP clock. The system clock can be stopped for a system sleep mode by disabling the VCXO supply power from the CCONT regulator output. The CCONT provides a 32kHz sleep clock for internal use and to the MAD2, which is used for the sleep mode timing. The sleep clock is active when there is a battery voltage available i.e. always when the battery is connected.
MAD2
MCU SYSTEMLOGIC UIF ARM CORE BUSC M C
ICE JTAG CRUSHER
PUP
U I
SIMIF
TESTIF
F
CTSI
DSP
JTAG
DSP PERIPHERALS
API
D S P
MFI
CODER
DSP RAM
LEAD CORE
I F ACCIF
SCU
Figure 22. MAD2 ARCHITECTURE
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MAD2 memory configuration MAD2 contains 12 kb RAM memory, 68 kb ROM memory. Memory is divided as follows Data: Program: Program/Data: 10 kb DARAM 16 kb DROM 48 kb PROM 4 kb PDROM 2 kb API RAM
PROGRAM
0000h RESERVED (OVLY=1) NOT USED (OVLY=0) 0080h ONCHIP RAM (OVLY=1) NOT USED (OVLY=0) NOT USED (OVLY=0) API RAM (OVLY=1) 1000h ONCHIP RAM (OVLY=1) NOT USED (OVLY=0) 1000h 0000h 0060h 0080h
DATA
MEMORY MAPPED REGISTERS SCRATCHPAD RAM ONCHIP RAM 0800h ONCHIP API RAM
12 kW RAM
0800h
ONCHIP RAM
3000h
B
3000h
A
5000h 5800h
NOT USED ONCHIP PROGRAM ROM
(MPNMC=0)
48 kW PROM
B000h ONCHIP DATA ROM
(DROM=1)
C
16 kW DROM
NOT USED (DROM=0) F000h
4 kW PDROM
F000h
FFFFh
FFFFh
BOUNDARIES
A B C INTERNAL DARAM TO EXTERNAL BOUNDARY EXTERNAL BOUNDARY TO INTERNAL PROM EXTERNAL BOUNDARY TO INTERNAL PDROM Figure 23. MAD2 12/68 DSP MEMORY MAP NOTE! MPNMC IS TIED TO 0
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MCU Memory Map The MAD2 supports a maximum of 4GB internal and 4MB external address space. The external memories use address lines MCUAd0 to MCUAd21 and 8bit/16bit databus. The BUSC bus controller supports 8 and 16bit access for byte, double byte, word and double word data. Access wait states (0, 1 or 2) and used databus width can be selected separately for each memory block.
Table 13. MCU Memory map
Memory block boot ROM (*) API RAM System logic API ctl reg. Bus Controller The same as 07FFFF ext. RAM (*) ext. ROM1 ext. ROM2 (*) ext. EEPROM reserved The same as 0FF FFFF RAMSelX ROM1SelX ROM2SelX EEPROMSelX Chip select internal internal internal internal Internal Start address 0000 0000 0001 0000 0002 0000 0003 0000 0004 0000 0008 0000 0010 0000 0020 0000 0060 0000 00A0 0000 00E0 0000 0100 0000 Stop address 0000 FFFF 0001 FFFF 0002 FFFF 0003 FFFF 0007 FFFF 000F FFFF 001F FFFF 005F FFFF 009F FFFF 00DF FFFF 00FF FFFF FFFF FFFF Size 64k 64k 64k 64k 256k 512 k 1M 4M 4M 4M 4M 4G 16 M Size 64k 64k 64k 64k 256k 512 k 1M 4M 4M 4M 4M 4G 16 M
(*) After reset and when BootROMDis and ROM2Boot are low. MCU can boot from different memory locations, depending on hardware (GenSDIO0) and software settings.
Table 14. MCU boot memory selection
Start address 0000 0000 Stop address 0000 FFFF BootROMDis=0 ROM2Boot=0 boot ROM BootROMDis=1 ROM2Boot=0 External RAM BootROMDis=0 ROM2Boot=1 ext. ROM2 BootROMDis=1 ROM2Boot=1 External RAM
Memories
The BusController (BUSC) section in the MAD decodes the chip select signals for the external memory devices and the system logic. The BUSC controls the internal and external bus drivers and multiplexers connected to the MCU data bus. The MCU address space is divided into access areas with separate chip select signals. The BUSC supports a programmable number of wait states for each memory range. The minimum access time for all external memories is specified to 120ns. Program Memory The MCU program code resides in the program memory. The program memory size is 8Mbits (512kx16bit) and package is uBGA48.
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The flash memory has a power down pin that is kept low during the power up phase of the flash to ensure that the device is powered up in the correct state, read only. The power down pin is utilized in the system sleep mode by connecting the ExtSysResetX to the flash power down pin to minimize the flash power consumption during the sleep. SRAM Memory The work memory is a static ram of size 2Mbits (256kx8bit) in a shrink TSOP32 package. The work memory is supplied from the common baseband VBB voltage and the memory contents are lost when the baseband voltage is switched off. All retainable data is stored into the EEPROM (or flash) when the phone is powered down. EEPROM Memory An EEPROM is used for a nonvolatile data memory to store the tuning parameters and phone setup information. The short code memory for storing user defined information is also implemented in the EEPROM. The EEPROM size is 8kbytes and the default package is SO8. The memory is accessed through a serial bus including also write protection signal for protecting EEPROM content against any malfunctions.
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Flash Programming
RAE2 Flashing connections the RAE2 has two entities which can be programmed: PDA and CMT. There are four different interfaces from outside to the RAE2 which can be used to transmit software code to the RAE2. These interfaces are the following: JTAG MMC FBUS/MBUS (PDA flashing only) (PDA flashing only) (PDA and/or CMT flashing)
PDA_MBUS
IR MMC
PDA ReLink
FBUS_RX FBUS_TX
CMT
FBUS_RX
FBUS_TX
5 MBUS DB_MBUS Service battery BC_MBUS JTAG
Bottom connector
Figure 24. SPOCK's flashing connections
Flashing methods During external CMT programming only the FBUS and MBUS is used for transmitting software data. The data transmission is done in DCT3 way. This means that the data is transmitted through the FBUS synchronously. The clock signal is transmitted on the MBUS line. Since the FBUS does not go directly to the CMT (as in DCT3 phone) the PDA has to be driven to ReLink mode before the external CMT programming. In order to boot the PDA to Relink mode Testmode connection has to established. This is done inside the Service battery. The relink causes changes to the DCT3 type powerup procedure during programming. This is because if the RAE2's VBAT is turned off and on, the PDA will lose the Relink mode. In order to prevent this the CMT is started by using IBI pulse.
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In the DCT3 type the CMT programming bootstrap code is used for starting SW downloading. The bootstrap code resides in the small internal ROM of the MAD. The bootstrap code is a small part of the download code and is used only for downloading more code into the RAM. Data on CMT Flash is divided on two parts: CMT SW code PPM The idea is that first the CMT SW code is programmed and after that the PPM is programmed in same method. This allows the change of language without changing the software code. Flashing procedure The phone is connected to the flash loading adapter FLA7 so that supply voltage for the phone and data transmission lines can be supplied from/to the FLA7. When the FLA7 triggers an IBI pulse to the phone, the program execution starts from the BOOT ROM and the MCU investigates in the early startup sequence if the flash prommer is connected. This is done by checking the status of the MBUSline. Normally this line is high but when the flash prommer is connected the line is forced low by the prommer. The flash prommer serial data receive line is in receive mode waiting for an acknowledgement from the phone. The data transmit line from the baseband to the prommer is initially high. When the baseband has recognized the flash prommer, the TXline is pulled low. This acknowledgement is used to start to toggle MBUS (FCLK) line three times in order that MAD2 gets initialized. This must be happened within 15 ms after TX line is pulled low. After that the data transfer of the first two bytes from the flash prommer to the baseband on the RXline must be done within 1 ms. When the MAD2 has received the secondary boot byte count information, it forces TX line high. Now, the secondary boot code must be sent to the phone within 10 ms per 16 bit word (If these timeout values are exceeded, the MCU (MAD2) starts normal code execution from flash). After this, the timing between the phone and the flash prommer is handled with dummy bytes. A 5V programming voltage is supplied inside the transceiver from the battery voltage with a switch mode regulator (5V/30mA) of the CCONT.
Table 15. Flash programming timing characteristic
Characteristics Time from boot indication to MAD2 initialization sequence Time from MAD2 initialization sequence to byte lenght information Time from byte length information to end of secondary boot code loading. Min Typ Max 15 1 10 per16 bit word Unit ms ms ms
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Security The phone flash program and IMEI code are software protected using an external security device that is connected between the phone and a PC. The security devi