Text preview for : 03rf.pdf part of Nokia 9110 Nokia 9110 Service Manual



Back to : Nokia 9110 Service Manual | Home

PAMS Technical Documentation RAE­2 Series transceiver

Chapter 3 ­Transceiver BS8 ­ BS8_RF Block

Original 02/99

Copyright E 1999 Nokia Mobile Phones. All rights reserved.

RAE­2 BS8_RF

PAMS Technical Documentation

AMENDMENT RECORD SHEET
Amendment Number Date Inserted By Comments Original

02/99

Page 3 ­ 2

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

CONTENTS ­ RF Page No
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power distribution diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal and extreme voltages . . . . . . . . . . . . . . . . . . . . . . . . . . RF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AFC function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF block requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duplex filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNA in CRFU_1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX interstage filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1st mixer in CRFU_1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1st IF­filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC­stage and 2nd mixer in SUMMA . . . . . . . . . . . . . . 2nd IF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer in SUMMA for 2nd IF . . . . . . . . . . . . . . . . . . . . . . . Transmitter blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IQ­modulator and TX­AGC in SUMMA . . . . . . . . . . . . . 116 MHz LC TX IF­filter . . . . . . . . . . . . . . . . . . . . . . . . . . Upconversion mixer and in CRFU_1a . . . . . . . . . . . . . . TX interstage filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power amplifier MMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . Directional coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power control section in SUMMA . . . . . . . . . . . . . . . . . . Synthesizers blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCTCXO, reference oscillator . . . . . . . . . . . . . . . . . . . . . VHF PLL in SUMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHF VCO and low pass filter . . . . . . . . . . . . . . . . . . . . . . 3­5 3­5 3­5 3­6 3­6 3­7 3­8 3­8 3­8 3 ­ 10 3 ­ 10 3 ­ 10 3 ­ 12 3 ­ 13 3 ­ 14 3 ­ 16 3 ­ 17 3 ­ 18 3 ­ 18 3 ­ 18 3 ­ 18 3 ­ 19 3 ­ 19 3 ­ 20 3 ­ 20 3 ­ 21 3 ­ 21 3 ­ 21 3 ­ 21 3 ­ 22 3 ­ 23 3 ­ 23 3 ­ 24 3 ­ 25 3 ­ 25 3 ­ 26 3 ­ 27 3 ­ 27 3 ­ 28 3 ­ 28

Original 02/99

Page 3 ­ 3

RAE­2 BS8_RF

PAMS Technical Documentation

UHF PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UHF VCO module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UHF local signal input in CRFU_1a . . . . . . . . . . . . . . . . . . . RF/BB/DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Data Interface and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Power Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUMMA and Synthesizer Control . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizer clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GSM Division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUMMA and Synthesizer Control . . . . . . . . . . . . . . . . . . . . . . . List of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 ­ 29 3 ­ 30 3 ­ 31 3 ­ 31 3 ­ 31 3 ­ 32 3 ­ 34 3 ­ 35 3 ­ 35 3 ­ 35 3 ­ 35 3 ­ 36 3 ­ 36 3 ­ 36 3 ­ 35 3 ­ 36

Page 3 ­ 4

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Introduction
This document defines the RF­module of the RAE­2 GSM­"engine". This section contains electrical specifications, functional descriptions, block diagrams etc.

Technical summary
The RF in the RAE­2 GSM is based on the architecture used in DCT 3. The RAE­2 RF Engine (figure below) is a single side design, on the A­side, with all components located under the PDA unit. Shielding comprises three shielding cans with removable lids. The maximum building height for the RF Engine is 2 mm.

ANT Match CRFU RX SAW 71MHz SAW Match

116MHz

TX SAW DUPLEX

232MHz VCO

SUMMA

13MHz CER

Loop Filter

Loop Filter

PA Detect

13MHz VCTCXO

UHF VCO

stripline ustripline

RF Characteristics
Table 1. Main RF characteristics Item Receive frequency range Transmit frequency range Duplex spacing Channel spacing 935 ... 960 MHz 890 ... 915 MHz 45 MHz 200 kHz Values

Original 02/99

Page 3 ­ 5

RAE­2 BS8_RF

PAMS Technical Documentation

Table 1. Main RF characteristics Item Number of RF channels Power class Number of power levels 124 4 15

(continued) Values

Note 1 : Standard of primary GSM 900 Band, P ­ GSM 890 ­ 915 MHz : Mobile transmit, Downlink 935 ­ 960 MHz : Mobile receive, Uplink

Transmitter Characteristics
Item Type Intermediate frequency ( phase modulated ) LO frequency range Output power Power control range Maximum phase error ( RMS/peak ) 116 MHz 1006 ... 1031 MHz 2 W peak ( 33 dBm ) min. 5 ... 33 dBm max 5 deg./20 deg. peak Values Upconversion, nonlinear, FDMA/TDMA

Output power
Parameter Max. output power Max. output power tolerance (power level 5) Output power tolerance / power levels 6...15 Output power tolerance / power levels 16...19 Output power control step size 0.5 2.0 Min. Typ. 33.0 +/­ 2.0 +/­ 2.5 +/­ 3.0 +/­ 4.0 +/­ 5.0 +/­ 6.0 3.5 Max. Unit / Notes dBm dB, normal cond. dB, extreme cond. dB, normal cond. dB, extreme cond. dB, normal cond. dB, extreme cond. dB

Note 1 : Output power refers to the measure of power when averaged over the useful part of the burst. Power levels are measured at the antenna connector. Note 2 : Interval between power steps shall be 2 +/­1.5 dB

Page 3 ­ 6

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Receiver characteristics
Item Type IF frequencies LO frequencies Typical 1 dB bandwidth Sensitivity Total typical receiver voltage gain ( from antenna to RX ADC ) Receiver output level ( RF level ­95 dBm ) Values Linear, FDMA/TDMA 1st 71 MHz, 2nd 13 MHz 1st LO 1006 ... 1031 MHz, 2nd LO 58 MHz +/­ 90 kHz min. ­ 102 dBm , S/N >8 dB 73 dB 50 mVpp ( typical balanced signal level of 13 MHz IF in RF BB interface = input level to RX ADCs ) ­17 ... +40 dB 57 dB ­15 dB ­102 ... ­10 dBm ­110 ... ­48 dBm +/­ 0.8 dB +/­ 1.0 dB

Typical AGC range (dynamic range ­93dB) Accurate AGC control range Typical AGC step in LNA Usable input dynamic range RSSI dynamic range AGC relative accuracy on channel ( accurate range ) Compensated gain variation in receiving band

Original 02/99

Page 3 ­ 7

RAE­2 BS8_RF

PAMS Technical Documentation

DC characteristics
Regulators
Transceiver has got a multi function power management IC, which contains among other functions, also 7 pcs of 2.8 V regulators. All regulators can be controlled individually with 2.8 V logic directly or through control register. In GSM direct controls are used to get fast switching, because regulators are used to enable RF­functions. Use of the regulators can be seen in the power distribution diagram. CCONT also provides 1.5 V reference voltage for SUMMA and CRFU1a ( and for DACs and ADCs in COBBA too ). All control signals are coming from MAD and they are 2.8 V logic signals..

Page 3 ­ 8

Original 02/99

Power distribution diagram

Technical Documentation

PAMS

Original 02/99 C­CONT VR 1 VR 2
2.3 mA

3.6 V

BATTERY
1.6 A

VBATT

PA

TXP VXOENA SYNPWR RXPWR TXPWR

VR 3

VR 4

VR 5

VR 6

VR 7

VREF

V5V

18 mA

84 mA

0.1 mA

VCTCXO BUFFER VXO
51 mA

PLLs VSYN_2
19.5 mA

CRFU, SUMMA VTX VCOs BUFFERS VSYN_1 COBBA ANAL.

CRFU, SUMMA VRX

SUMMA CRFU VREF_1 VREF_2 1 mA CHARGE PUMPs VCP BS8_RF RAE­2

Page 3 ­ 9

RAE­2 BS8_RF

PAMS Technical Documentation

Functional descriptions
RF block diagram
The RF block comprises a conventional dual conversion receiver and the transmitter features an up­conversion mixer for the final TX­frequency. The architecture contains three ICs. Most of the functions are horizontally and vertically integrated. UHF functions except power amplifier and VCO are integrated into CRFU_1a, which is a BiCMOS­circuit suitable for LNA­ and mixer­function. Most of the functions are in SUMMA, which also is a BiCMOS­circuit. SUMMA is a IF­circuit including IQ­modulator and PLLs for VHF­ and UHF­synthesizers. Power amplifier is also an ASIC, it is a so called MMIC ( monolithic microwave integrated circuit ). It has got three amplifier stages including input and interstage matchings. Output matching network is external. Also TX gain control is integrated into this chip. See block diagram next page

Page 3 ­ 10

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

SUMMA

TQFP­48

ext.ant.conn.

Figure 1.

two way switch

antenna

Original 02/99

Page 3 ­ 11

Power amplifier

RAE­2 BS8_RF

PAMS Technical Documentation

Frequency synthesizers
Both VCOs are locked with PLLs into stable frequency source, which is a VCTCXO­module ( voltage controlled temperature compensated crystal oscillator ). The VCTCXO is running at 13 MHz. Temperature effect is controlled with AFC ( automatic frequency control ) voltage, the VCTCXO is locked into the frequency of the base station. AFC is generated by baseband with a 11 bit conventional DAC in COBBA. The UHF PLL is located in the SUMMA. There is 64/65 (P/P+1) prescaler, N­ and A­divider, reference divider, phase detector and charge pump for the external loop filter. The UHF local signal is generated by a VCO­module ( VCO = voltage controlled oscillator ) and sample of frequency of VCO is fed to prescaler. The prescaler is a dual modulus divider. The output of the prescaler is fed to the N­ and A­dividers, which produce the input to phase detector. The phase detector compares this signal to reference signal, which is divided with reference divider from VCTCXO output. Output of the phase detector is connected into charge pump, which charges or discharges integrator capacitor in the loop filter depending on the phase of the measured frequency compared to reference frequency. The loop filter filters out the pulses and generates the DC to control the frequency of UHF­VCO. The loop filter defines step response of the PLL ( settling time ) and effects to stability of the loop, that's why integrator capacitor has got a resistor for phase compensation. The other filter components are for sideband rejection. Dividers are controlled via serial bus. SDATA is for data, SCLK is serial clock for the bus and SENA1 is a latch enable, which stores new data into dividers. The UHF­synthesizer is the channel synthesizer, so the channel spacing is 200 kHz. 200 kHz is the reference frequency for the phase detector.

Page 3 ­ 12

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

R
f ref f_out / M

freq. reference AFC­controlled VCTCXO LP PHASE DET. CHG. PUMP Kd M = A(P+1) + (N­A)P= NP+A Kvco f_out VCO

M

VHF PLL is also located into SUMMA. It comprises a 16/17 ( P/P+1 ) dual modulus prescaler, N­ and A­dividers, reference divider, phase detector and charge pump for the loop filter. The VHF local signal is generated with a discrete VCO­circuit. The VHF PLL works in the same way as UHF­PLL. The VHF­PLL is locked on fixed frequency, so higher reference frequency is used to decrease phase noise.

Receiver
Receiver is a dual conversion linear receiver. The received RF­signal from the antenna is fed via the duplex filter to LNA ( low noise amplifier ) in CRFU_1a. Active parts (RF­transistor and biasing and AGC­step circuitry) are integrated into this chip. Input and output matching networks are external. Gain selection is carried out with PDATA0 control. Gain step in LNA is activated when the RF­level in the antenna is about ­45 dBm. After the LNA amplified signal ( with low noise level ) is fed to bandpass filter, which is a SAW­filter ( SAW, surface acoustic wave ). This bandpass filtered signal is then mixed down to 71 MHz, which is the first intermediate frequency. The 1st mixer is located into CRFU_1a ASIC. This integrated mixer is a double balanced Gilbert cell. All active parts and biasing are integrated and matching components are external. Because this is an axtive mixer it also amplifies IF­frequency. Also local signal buffering is integrated and upper side injection is used. First local signal is generated by the UHF­synthesizer. The first IF­signal is then bandpass filtered with a selective SAW­filter. From the mixer output to the IF­circuit input the signal path is balanced. The IF­filter provides selectivity for channels greater than +/­200 kHz. Also it attenuates image frequency of the second mixer and intermodulat-

Original 02/99

Page 3 ­ 13

RAE­2 BS8_RF

PAMS Technical Documentation

ing signals. Selectivity is required in this place, because of needed linearity and adjacent channel interferers will be on too high signal level for the stages following. The next stage in the receiver chain is AGC­amplifier. It is integrated into SUMMA­ASIC. The AGC has got analog gain control. The control voltage for the AGC is generated with DA­converter in COBBA in baseband. AGC­stage provides accurate gain control range ( min. 57 dB ) for the receiver. After the AGC there is the second mixer, which generates the second intermediate frequency, 13 MHz. The local signal is generated in SUMMA by dividing VHF­synthesizer output ( 232 MHz ) by four, so the 2nd LO­ frequency is 58 MHz. The 2nd IF­filter is a ceramic bandpass filter at 13 MHz. It attenuates adjacent channels, except for +/­ 200 kHz there is not much attenuation. Those +/­ 200 kHz interferers are filtered digitally by the baseband. So the RX DACs are so good, that there is enough dynamic range for the faded 200 kHz interferer. Also the whole RX has to be able to handle signal levels in a linear way After the 13 MHz filter there is a buffer for the IF­signal, which also converts and amplifies single ended signal from filter to balanced signal for the buffer and AD­converters in COBBA. Buffer in SUMMA has got voltage gain of 36dB and buffer gain setting in COBBA is 0 dB. It is possible to set gainstep ( 9.5 dB ) into COBBA via control bus, if needed..

Transmitter
The transmitter chain consists of IQ­modulator, upconversion mixer, power amplifier and there is a power control loop. I­ and Q­signals are generated by baseband in COBBA­ASIC. After post filtering ( RC­network ) they are fed into IQ­modulator in SUMMA. It generates modulated TX IF­frequency, which is VHF­synthesizer output divided by two, that is 116 MHz. The TX­amplifier in SUMMA has two selectable gain levels. Output is set to maximum via control register of SUMMA. After SUMMA there is a bandpass LC­filter for noise and harmonic filtering before the signal is fed for upconversion into final TX­frequency in CRFU_1a. Upconversion mixer in CRFU_1a is a so called image reject mixer. It attenuates the unwanted sideband in the upconverter output. The mixer itself is a double balanced Gilbert cell. The phase shifters required for image rejection are also integrated. The local signal needed in upconversion is generated by the UHF­synthesizer, but buffers for the mixer are integrated into CRFU_1a. The output of the upconverter is buffered and matching network makes a single ended 50 ohm impedance. The next stage is a TX interstage filter, which attenuates the unwanted signals from the upconverter, mainly LO­leakage and image frequency

Page 3 ­ 14

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

from the upconverter. Also it attenuates the wideband noise. This bandpass filter is a SAW­filter. The final amplification is carried out by the third IC, the power amplifier which is a MMIC. It features a 50 ohm input, output requires an external matching network. The MMIC comprises three amplifier stages and interstage matchings. Also included is a gain control, which is controlled with a power control loop. The PA features over 35 dB power gain and it is able to produce 2.5 W into output with 0 dBm input level. The gain control range is over 35 dB to get desired power levels and power ramping up and down. The harmonics generated by the nonlinear PA ( class AB ) are filtered out with the matching network and lowpass/bandstop filtering in the duplexer. Bandstop is required because of wideband noise located on RX­band. Power control circuitry consists of a power detector in the PA output and an error amplifier in SUMMA. There is a directional coupler connected between the PA­output and the duplex filter. It takes a sample from the forward going power with certain ratio. This signal is rectified in a schottky­diode and it produces a DC­signal signal after filtering. This peak­detector is linear on absolute scale, except it saturates on very low and high power levels ­ it produces a S­shape curve. This detected voltage is compared in the error­amplifier in SUMMA to TXC­voltage, which is generated by DA­converter in COBBA. Because also gain control characteristics in PA are linear in absolute scale, control loop defines a voltage loop, when closed. The closed loop tracks the TXC­voltage quite linearly. The TXC has got a raised cosine form ( cos4 ­ function ), which reduces switching transients, when pulsing power up and down. Because dynamic range of the detector is not wide enough to control the power ( actually RF output voltage ) over the whole range, there is a control named TXP to work under detected levels. Burst is enabled and set to rise with the TXP until the output level is high enough, that feedback loop works. The loop controls the output via the control pin in the PA MMIC to the desired output level and burst has got the waveform of TXC­ramps. Because feedback loops could be unstable, this loop is compensated with a dominating pole. This pole decreases gain on higher frequencies to get phase margins high enough.

Original 02/99

Page 3 ­ 15

RAE­2 BS8_RF

PAMS Technical Documentation

DIR.COUPLER

PA

RF_OUT
K cp
R1 DETECTOR

RF_IN

K PA

K

det
R2

K = ­R1/R2
ERROR AMPLIFIER R C DOMINATING POLE

Figure 2.

Power control feedback loop

TXC

AGC strategy
The AGC­amplifier is used to maintain output level of the receiver almost constant. AGC has to be set before each received burst, this is called pre­monitoring. The receiver is switched on before the burst begins, the DSP measures received signal level and adjusts RXC, which controls RX AGC­ amplifier or it switches off the LNA with PDATA0 control line. This pre­ monitoring is done in three phases and this sets the settling times for RX AGC. Pre­monitoring is required because of linear receiver, received signal must be in full swing, no clipping is allowed and because DSP doesn't know, what is the level going to be in next burst. There is at least 60 dB accurate gain control ( continuous, analog ) and one digital step in LNA. It is typically about 30...35 dB. RSSI must be measured on range ­48...­110 dBm. After ­48 dBm level MS reports to base station the same reading. Because of RSSI­requirements, gain step in LNA is used roughly on ­45 dBm RF­level and up to ­10 dBm input RF­level accurate AGC is used to set RX output level. LNA is ON ( PDATA0 = "0" ) below ­47 dBm. from ­47 dBm down to ­95 dBm This accurate AGC in SUMMA is used to adjust the gain to desired value. RSSI­function is in DSP, but it works out received signal level by measuring RX IQ­level after all selectivity filtering ( meaning IF­filters, ±converter and FIR­filter in DSP). So 50 dB accurate AGC dynamic range is

Page 3 ­ 16

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

required. Remaining 10 dB is for gain variations in RX­chain ( for calibration ) Below ­95 dBm RF­levels, output level of the receiver drops dB by dB. At ­95 dBm level output of the receiver gives 50 mVpp. This is the target value for DSP. Below this it drops down to ca. 9 mVpp @ ­110 dBm RF­ level. This strategy is chosen because we have to roll off the AGC in PLUSSA early enough, that it won't saturate in selectivity tests. Also we can't start too early, then we will sacrifice the signal to noise ratio and it would require more accurate AGC dynamic range. 50 mVpp target level is set, because RX­DAC will saturate at 1.4 Vpp. This over 28 dB headroom is required to have margin for +/­ 200 kHz faded adjacent channel ( ca. 19 dB ) and extra 9 dB for pre­monitoring. Production calibration is done with two RF­levels, LNA gain step is not calibrated. The gain changes in the receiver are taken off from the dynamic range of accurate AGC. Variable gain stage in SUMMA is designed in a way, that it is capable of compensating itself, there is good enough margin in AGC.

AFC function
AFC is used to lock the transceivers clock to the frequency of the base station. AFC­voltage is generated in the COBBA with a 11 bit AD­converter. There is a RC­filter in AFC control line to reduce the noise from the converter. Settling time requirement for the RC­network comes from signalling, how often PSW ( pure sine wave ) slots occur. They are repeated after 10 frames , meaning that there is PSW in every 46 ms. AFC tracks the base station frequency continuously, so the transceiver has got a stable frequency, because changes in the VCTCXO­output don't occur so fast ( temperature ). Settling time requirement comes also from the start up­time allowed. When transceiver is in sleep mode and "wakes" up to receive mode , there is only about 5 ms for the AFC­voltage to settle. When the first burst comes in system clock has to be settled into +/­ 0.1 ppm frequency accuracy. Settling time requirement comes also from the start up­time allowed. When transceiver is in sleep mode and "wakes" up to receive mode , there is only about 5 ms for the AFC­voltage to settle. When the first burst comes in system clock has to be settled into +/­ 0.1 ppm frequency accuracy. The VCTCXO­module requires also 5 ms to settle into final frequency. Amplitude rises into full swing in 1 ... 3 ms, but frequency settling time is longer so this oscillator must be powered up early enough.

Original 02/99

Page 3 ­ 17

RAE­2 BS8_RF

PAMS Technical Documentation

RF block requirements
Duplex filter
Parameter Center frequency, ftx,frx BW ( bandwidth ) at passband Maximum insertion loss at BW Ripple at BW, peak to peak Terminating impedance Maximum VSWR Minimum attenuations Transmit section ftx : 902.5 +/­ 12.5 1.6 ( at +25 deg. C ) 1.9 ( at ­20...+85 deg. C ) 1.1 50 2.2 Freq.range 925...935 935...960 1780...1830 2670...2745 Att. 3 15 28 35 Receive section frx : 947.5 +/­ 12.5 3.2 ( at +25 deg. C ) 3.7 ( at ­20...+85deg. C ) 1.5 50 1.8 Freq.range 3...200 200...500 500...890 890...915 980...1000 1000...1050 1400...1500 Permissible input power 4.0 AVG (12.5% duty cyclr) Att. 30 16 25 26 21 23 35 MHz/dB MHz/dB MHz/dB MHz/dB MHz/dB MHz/dB MHz/dB W unit MHz MHz dB dB ohms

Part no: NMP code 4512075

Receiver blocks
LNA in CRFU_1a
Parameter Frequency band Supply voltage Current consumption Insertion gain Noise figure Input 1 dB compression point Reverse isolation Input VSWR ­19 15 2 17.5 18.5 1.7 2.7 Min. Typ. 935 ­ 960 2.8 2.855 8 19.5 2.2 Max. Unit/Notes MHz V mA dB dB,PDATA0=H dBm, PDATA0=H dB

Page 3 ­ 18

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Parameter Output VSWR Gain reduction Step accuracy Noise figure, when PDATA=0

Min. 30 ­2

Typ.

Max. 2 35 +2

Unit/Notes dB,room temp. dB,over temp.range dB

20

RX interstage filter
Parameter Passband Insertion loss Ripple in passband Attenuation DC...890 MHz Attenuation 890...915 MHz Attenuation 980...1030 MHz Attenuation 1025...3000 MHz Terminating impedance VSWR Maximum drive level 45 25 25 35 UNBALANCED­BALANCED 50/50 2.0 +15 dBm Min. Typ. 935 ­ 960 3.3 1.3 Max. Unit MHz dB dB dB dB dB dB ohm

Part no: NMP code 4511049 1st mixer in CRFU_1a
Parameter Supply voltage Current consumption RX frequency range LO frequency range IF frequency Insertion gain NF, SSB IIP3 1 dB input compression point IF/2 spurious level LO power level in RF­port Input VSWR Output resistance (balanced) Output capacitance (balanced) 10 k 1.2 0 ­10 ­30 ­25 2 ohm pF 9 935 1006 71 12 11.5 Min. 2.7 Typ./ Nom. 2.8 9 960 1031 Max. 2.85 Unit/Notes V mA MHz MHz MHz dB dB dBm dBm dBm, * dBm

Original 02/99

Page 3 ­ 19

RAE­2 BS8_RF

PAMS Technical Documentation

1st IF­filter
Parameter Operating temperature range Center frequency , fo Maximum ins. loss at 1dBBW Group delay ripple at +/­90 kHz BW Bandwidths relative to 71 MHz 1 dB bandwidth 3 dB bandwidth 5 dB bandwidth 22 dB bandwidth 30 dB bandwidth 40 dB bandwidth Spurious rejection, fo +/­ 26 MHz Terminating impedance ( balanced ) resistance input resistance output capacitance ( parallel ) input capacitance ( parallel) output +/­ 70 +/­120 +/­ 230 +/­ 350 +/­ 550 +/­ 700 65 1.1 1.2 15.6 10.6 dB, * kohm kohm pF pF min. ­20 71 11 1.3 typ. max. +75 unit deg.C MHz dB us pp kHz

*

Matching network included. NMP part no. 4510137

AGC­stage and 2nd mixer in SUMMA
Parameter Supply voltage Current consumption Input frequency range 2nd IF frequency range Total noise figure, SSB, max. gain Total noise figure, SSB, min. gain Max. voltage gain Min. voltage gain Control voltage for min. gain Control voltage for max. gain Output 1 dB compression point @ max. gain Input 1 dB compresion point @ min. gain IF input impedance (balanced) 2nd mixer output impedance ( single output ) 800 80 2.4/tbd 3.8/2 5.6/tbd 100 0.5 1.4 40 ­20 45 0.4 Min. 2.7 Typ. 2.8 27 Max. 2.85 32 120 17 15 65 Unit/Notes V mA MHz MHz dB, dB, dB dB V V mVpp mVpp kohm/pF ohm

Page 3 ­ 20

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

2nd IF Filter
Parameter Center frequency, fo 1 dB bandwidth, 1dBBW ( relative to 13 MHz ) Insertion loss Amplitude ripple at 1dBBW Group delay ripple at 1 dB BW, peak to peak Attenuations, relative to 13 MHz fo +/­ 400 kHz fo +/­ 600 kHz fo +/­ 800 kHz Terminating impedance +/­ 90 6.0 1.0 1.5 min. typ. 13 max. unit MHz kHz dB dB us dB 25 35 45 313 330 347 ohm

NMP part no. 4510009 Buffer in SUMMA for 2nd IF
Parameter Input frequency range Voltage gain ( single ended input and balanced output ) 1 dB output compression point ( Rload=10 kohm balanced ) Input impedance Output impedance, balanced Min. 0.4 34 36 1.4 Typ. Max. 17 38 Unit MHz dB Vpp

3.3/4 600

kohm/pF ohm

Original 02/99

Page 3 ­ 21

RAE­2 BS8_RF

PAMS Technical Documentation

Transmitter blocks

IQ­modulator and TX­AGC in SUMMA

Parameter Supply voltage Current consumption Modulator Inputs (I/Q) Input bias current (balanced) Input common mode voltage Input level (balanced) Input frequency range Input resistance (balanced) Input capacitance (balanced) IQ­input phase balance total, temperature included IQ­input phase balance temperature effect IQ­input amplitude balance total, temperature included IQ­input amplitude balance temperature effect Modulator Output Output frequency ­4 ­2 0 tbd

Min. 2.7

Typ. 2.8 28

Max. 2.85 tbd. Maximum 100 nA V 1.2 300 2 4 2 0.5 0.2 Vpp kHz kohms pF deg. deg. dB dB

Unit V mA Unit / Notes

Minimum

Typical / Nominal 0.8

­0.5 ­0.2 Minimum 85 ­3 Typical / Nominal

Maximum 400 MHz dBm

Unit / Notes

Output power, high (bal­5 anced, into 100 ohm) NOTE: Requires input level of 1.1 Vpp (difrential) Output power, low (balanced, into 100 ohm ) NOTE: Requires input level of 1.1 Vpp (diff.) Noise level in output Total gain control range Gain step 35 ­10

­8

dBm

­145 5

dBm/Hz avg. dB dB

Page 3 ­ 22

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Modulator Output Absolute gain accuracy Any gain step up/down settling time Output 3rd Order Intermodulation products, when both wanted signals are at the level of ­12 dBm at the output

Minimum ­2

Typical / Nominal

Maximum +2 10 ­35 dB usec dB

Unit / Notes

116 MHz LC TX IF­filter
Parameter Center frequency Insertion loss @ 116 MHz Relative attenuation @ +/­ 10 MHz offset Relative attenuation @ +/­ 20 MHz offset Relative attenuation @ 232 MHz Relative attenuation @ 348 MHz Relative attenuation @ 464­1000 MHz Input impedance, balanced Output impedance, balanced 5 8 15 20 25 100 200 Min. Typ. 116 3.7 Max. Unit MHz dB dB dB dB dB dB ohm ohm

Upconversion mixer and in CRFU_1a
Parameter Supply voltage Supply current Input frequency Input level Output frequency range Output level NF,SSB LO­signal level in output Unwanted sideband level fLO+/­2xIF spurious level 7x116 MHz spurious level 890 +3 +5 20 ­29 ­15 ­40 ­40 116 ­5 ­8 915 Min. 2.7 Typ. 2.8 Max. 2.85 50 Unit V mA MHz dBm MHz dBm dB dBc dBc dBc dBc

Original 02/99

Page 3 ­ 23

RAE­2 BS8_RF

PAMS Technical Documentation

Parameter 8x116 MHz spurious level Input impedance (balanced) Output VSWR, ( with matching network and output balun)

Min.

Typ. 600//2

Max. ­55 2

Unit dBc ohm//pF

TX interstage filter
Parameter Passband Insertion loss Ripple in passband Attenuation DC...813 MHz Attenuation 925...935 MHz Attenuation 935...960 MHz Attenuation 1006...1031 MHz Attenuation 1122...1147 MHz Attenuation 1780...1830 MHz Attenuation 2670...2745 MHz Terminating impedance VSWR Maximum drive level 35 7 15 40 45 10 10 50 2.5 +15 dBm Min. Typ. 890 ­ 915 3.8 1.5 Max. Unit MHz dB dB dB dB dB dB dB dB dB ohm

NMP part no. 4511015 Power amplifier MMIC
Parameter Operating freq. range Supply voltage Auxiliary supply current Input power Output power Gain control range ( overall dynamic range) Gain control slope S ( sensitivity at the linear range ) Vcc Ireg Pin Pout Pout=35.0 dBm, Vcc=3.5 V, Vpc=2.2 V, Pin= 0 dBm, Vcc=3.0 V, Vpc=2.2 V, Tamb=+85 deg.C Vpc= 0.5 ... 2.2 V 0 34.2 45 2 Auxiliary supply voltage Vreg Symbol Test condition Min 880 3.0 2.7 3.5 2.8 Typ Max 915 5.0 2.9 tdb. 5 V V mA dBm dBm dB Unit MHz

Vpc1 @10 Vpeak output volt. 20 Vpc2 @0.5 Vpeak output volt. S=((10­0.5)/(Vpc1­Vpc2)) V/V, Pin = 0...+5dBm

tbd.

40

V/V

Page 3 ­ 24

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Parameter Isolation Carrier switching time

Symbol

Test condition Vcc=3.5 V, Vpc=0.2 V, Pin=0 dBm

Min

Typ

Max ­40 1

Unit dB us

tr, tf

Vcc=3.5 V, Pin=0 dBm Vpc is a pulse from 0.2 to 2.2 V. Rise time up to ­0.5 dB from the final power. Fall time vice versa. Pin= 0 dBm , Pout= +34.3 dBm, Vcc=3.5 V, Tamb = + 25 deg. C Pin= 0...+5 dBm , Pout= +34.8 dBm, Vcc=3.5 V Pin= 0...+5 dBm , Pout= +34.0 dBm, Vcc=3.5 V Pin= 0...+5 dBm , Pout= +6.0 ... +32.0 dBm, Vcc=3.5 V Vpc adjusted for desired power levels Vcc=3.5 V, Vpc=0 V, Vreg=0 V, no RF­drive Pinwant= 0 dBm @ 915 MHz 5 Pinint = ­50 dBm @ 905 MHz Poutwant= +34.8 dBm Vcc=3.5 V, Poutint @905 MHz Poutimd @925 MHz IMD=Poutint ­ Poutimd, Tamb = + 25 deg. C Pin= ­2.0 ... +5.0 dBm, Pout= +6.0 ... +34.0 dBm Vpc adjusted for desired output power levels Vcc=3.0 V Vcc=3.5 V , RBW=30kHz Pout = +34.8 dBm, Freq. band: 925...960 MHz Pin= 0 dBm+/­3dBm, Vcc=3.0...5.0 V, Vpc=0 ... 2.2 V Load VSWR 12:1, all phases Pin= 0 dBm, Vcc=5.0 V, Pout=Pmax Load VSWR 20:1, all phases 50

Total efficiency



%

Control current Harmonics Input VSWR

Ipc

+/­ 3 ­35

mA peak dBc

VSWRi1 VSWRi2

2:1 4:1

Leakage current Intermodulation distorsion

Ileak IMD

10

uA dB

AM­PM conversion

Kp

3

deg/dB

Receive band noise power Stability

Pn

­80

dBm

All spurious outputs more than 65 dB below desired signal

Load mismatch stress

No module damage

Original 02/99

Page 3 ­ 25

RAE­2 BS8_RF

PAMS Technical Documentation

Directional coupler
Parameter Frequency range Insertion loss Coupling factor Directivity Impedance level of the main line VSWR on main line Impedance level of the coupled line 50 13 50 1.6 ohm 15 14 Min. 890 Typ. Max. 915 0.5 Unit/Notes MHz dB dB dB ohm

NMP part no. 4551001 Power detector
Parameter Supply voltage Supply current Frequency range Dynamic range Linear range, * Bias current for detector diode Input power range, ** Output voltage Variation of the detected voltage over temperature range Load resistance 10 ­8 0.1 890 45 35 40 20 2.2 0.7 Min. 2.7 Typ. 2.8 Max. 2.85 2.0 915 Unit/Notes V mA MHz dB dB uA dBm V mV/_C kohm

* **

RF input voltage versus detected output voltage Directional coupler coupling factor 14 dB

Power control section in SUMMA, closed loop characteristics
Parameter Supply voltage Supply current TXP input voltage, LOW TXP input voltage, HIGH Detector input voltage TXC input voltage 2.4 0.1 0.1 2.2 2.2 Min. 2.7 Typ. 2.8 tbd. 0.5 Max. 2.85 Unit/Notes V mA V V V V

Page 3 ­ 26

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Parameter TXC and TXP input resistance TXC and TXP input capacitance Output voltage (POP & POG) POP­ and POG­output impedance POP and POG ­output current driving capability Switch on resistance (bet­ ween INL& POP or POG) Voltage of POP/POG when inactive (max. 3.5mA sink) Offset of OP1 and OP2 op.amp. Temperature coefficient of the offset voltage Bandwidth ( OP1 & OP2 ), unity gain Open loop gain Closed loop gain Closed loop ­3 dB bandwidth Phase margin Gain margin

Min. 50

Typ.

Max.

Unit/Notes kohm

4 0.5 50 +/­ 4 tbd. 0.1 ­40 30 6 20 15 70 45 60 30 40 2.2

pF V ohm mA ohm V mV uV/deg.C MHz dB dB kHz degrees dB

Synthesizers blocks
VCTCXO, reference oscillator
Parameter Supply voltage, Vcc Current consumption, Icc Operating temperature range Nominal frequency Output voltage swing ( swing of 13 MHz component, selective measurement from the spectrum ) Load, resistance capacitance Frequency tolerance @+25 deg. C Frequency tolerance after reflow ( @ +25 deg. C ) ­ 1.0 ­ 2.0 800 ­20 13 Min. 2.70 Typ. 2.80 Max 2.85 1.5 +75 Unit/.Notes V mA deg. C MHz mVpp

2 10 + 1.0 + 2.0

kohm pF ppm ppm

Original 02/99

Page 3 ­ 27

RAE­2 BS8_RF

PAMS Technical Documentation

Parameter Frequency stability vs. temperature ( ref. @+25 , ­20....+75 deg. C ) Frequency stablity vs. supply voltage ( 2.8 V +/­ 100 mV ) Frequency stability vs. load change ( 2 kohm//10 pF +/­ 10 % ) Aging Nominal control voltage, Vc Voltage control range Voltage control characteristics ( see note 1. ) Vc input resistance Frequency adjustment

Min. ­ 5.0 ­ 0.1 ­ 0.3 ­ 1.0

Typ.

Max + 5.0 + 0.1 + 0.3 + 1.0

Unit/.Notes ppm ppm ppm ppm/year V V ppm/V when 0.3 V
1.15 0.0 +/­ 12 1 +/­ 3.0 ­5 5 5 ­130 2.3 +/­ 24

Harmonics ( with 2 kohm//10 pF ) Start up time output level within 90% output frequency limits +/­0.05ppm from the final value Phase noise @ 1 kHz offset

dBc ms

dBc/Hz

VHF PLL in SUMMA The same VHF VCO and also the same frequency is used so the VHF PLL is common.
Table 2. VHF­synthesizer, specification Parameter Start up settling time Phase error Sidebands +/­ 1 MHz +/­ 2 MHz +/­ 3 MHz > +/­ 3.0 MHz Min. Typ. Max. 3.0 1 ­70 ­80 ­80 ­90 Table 3. VHF PLL block in SUMMA, specification Parameter Input frequency range Input signal level Input resistance Input capacitance Supply current Reference input frequency 3.5 30 Min. 150 80 tbd. tbd. Typ. Max. 500 800 Unit/notes MHz mVpp kohm pF mA MHz Unit/Notes ms deg./rms dBc

Page 3 ­ 28

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Table 3. VHF PLL block in SUMMA, specification (continued) Parameter Phase comparison frequency Charge pump output current 1 current 2 Sink to source current matching error of the charge pump Charge pump current error Charge pump min. output voltage Charge pump max. output voltage Charge pump leakage current Phase detector phase noise level 0.5 * Vcp­0.5 5 ­163 0.5 2.0 +/­ 5 +/­ 10 Min. Typ. Max. 1 Unit/notes MHz mA % % V V nA dBc/Hz

*Vcp = 5V VHF VCO and low pass filter
Parameter Supply voltage range Current consumption Control voltage Operation frequency Output level Harmonics Phase noise, fo +/­ 600 kHz fo +/­ 1600 kHz fo +/­ 3000 kHz Control voltage sensitivity Pushing figure Frequency stability Spurious content 8.0 ­13 0.5 232 ­10 ­30 ­120 ­130 ­140 14.0 +/­ 2 +/­ 3 ­70 Min. 2.7 Typ. 2.8 4 Max. 2.85 7 4.0 Unit/Notes V mA V MHz dBm ( output after the lowpass filter ) dBc, ( filtered ) dBc

MHz/V MHz/V MHz ( over temperature range ­10...+75 C deg.) dBc

Original 02/99

Page 3 ­ 29

RAE­2 BS8_RF

PAMS Technical Documentation

UHF PLL
Table 4. UHF­synthesizer, Parameter Start up settling time Settling time +/­ 25 MHz Phase error Sidebands +/­ 200 kHz +/­ 400 kHz +/­ 600...+/­1400 kHz +/­1.4... +/­ 3.0 MHz > +/­ 3.0 MHz 500 Min. Typ. Max. 3.0 800 3.7 ­40 ­60 ­66 ­76 ­86 Table 5. UHF PLL block in SUMMA Parameter Input frequency range Input signal level (f<1.5 GHz) Input resistance Input capacitance Supply current Reference input frequency Reference input level Reference input impedance Phase comparison frequency Charge pump output current 1 current 2 Sink to source current matching error of the charge pump Charge pump current error Charge pump current temperature variation Charge pump leakage current Phase detector phase noise level 0.5 2.0 +/­ 5 +/­ 10 tbd. 5 ­163 100 tbd. 1 MHz mA % % % nA dBc/Hz 8 30 Min. 650 200 tbd. tbd. Typ. Max. 1700 Unit/notes MHz mVpp kohm pF mA MHz mVpp Unit/Notes ms us, ( into +/­ 20 Hz from final frequency ) deg./rms dBc

UHF VCO module
Parameter Supply voltage, Vcc Supply current, Icc Control voltage, Vc Vcc = 2.8 V, Vc= 2.25 V Vcc = 2.8 V Conditions Rating 2.8 +/­ 0.1 < 10 0.8... 3.7 Unit/ Notes V mA V

Page 3 ­ 30

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Parameter Oscillation frequency

Conditions Vcc = 2.8 V Vc = 0.8 V Vc = 3.7 V f = 1018.5 MHz Vcc = 2.8 V f=1006...1031 MHz Vcc=2.7 V f=1006...1031 MHz f=1006...1031 MHz Vcc=2.8 V f=1006...1031 MHz VSWR=2, any phase Vcc=2.8 +/­ 0.1 V Ta=­20 ... +75 deg. C Vcc=2.8 V, Vc=0...6 V Vc= 0 V

Rating

Unit/ Notes MHz MHz V MHz/V

< 1006 > 1031 2.25 +/­ 0.25 14 +/­ 2

Tuning voltage in center frequency Tuning voltage sensitivity in operating frequency range on each spot freq. Output power level

­6.0 min.

dBm

Output impedance and VSWR Phase noise, fo +/­ 25 kHz fo +/­ 600 kHz fo +/­ 1600 kHz fo +/­ 3000 kHz Pulling figure Pushing figure Frequency stability over temperature range Harmonics Spurious Input capacitance in Vc­pin

50 ohms,VSWR <2 ­100 ­120 ­130 ­140 +/­ 1.0 +/­ 2.0 +/­ 3.0 ­10 max. ­70 max. 100 max. dBc/Hz max.

MHz max. MHz/V max. MHz max. dBc dBc pF

UHF local signal input in CRFU_1a
Parameter Input frequency range Input level Input resistance Input capacitance Min. 990 200 100 1.5 Typ. Max. 1040 700 Unit/Notes MHz mVpp ohm pF

Original 02/99

Page 3 ­ 31

RAE­2 BS8_RF

PAMS Technical Documentation

RF/BB/DSP Interface
The following three sections describe the hardware and timing interface between RF and the BB/DSP section of the RAE­2. Interface Signal Characteristics The interface signals between the BB and the RF section are shown in the next table as a logical interface. On physical board level baseband supplies voltages from CCONT to separate RF sub­blocks. The maximum values specified for the digital signals in the table are the absolute maximum values from the RF interface point of view.
Table 6. AC and DC Characteristics of RF/BB signals
Signal name VBATT VXOENA From - To Battery RF y MAD CCONT Function Supply voltage for RF y g (PA on/PA off) VR1, VR6 in CCONT ON VR1, VR6 in CCONT OFF SYNPWR MAD CCONT VR3, VR4 in CCONT ON VR3,VR4 in CCONT OFF RXPWR MAD CCONT VR2, VR5 in CCONT ON VR2, VR5 in CCONT OFF TXPWR MAD CCONT VR7 in CCONT ON VR7 in CCONT OFF VREF CCONT SUMMA Reference voltage for SUMMA and CRFU1a Nominal gain in LNA Reduced gain in LNA SENA SDATA SCLK AFC MAD SUMMA MAD SUMMA MAD SUMMA COBBA VCTCXO PLL enable Synthesizer data S th i d t Synthesizer clock S th i l k Automatic frequency control signal f VC(TC)XO A t ti f t l i l for 10 10000Hz 10...10000Hz RFC RXIP/RXIN TXIP/TXIN VCTCXO MAD SUMMA COBBA COBBA SUMMA High t bilit l k i Hi h stability clock signal for the logic circuits l f th l i i it Differential RX 13 MHz signal to baseband Diff ti l MH i lt b b d Differential in hase TX baseband signal f th Diff ti l in­phase i h b b d i l for the RF modulator Differential quadrature phase TX baseband signal q g for the RF modulator Transmitter power control enable

PDATA0

MAD CRFU1A

TXQP/TXQN TXP

COBBA SUMMA MAD SUMMA

Page 3 ­ 32

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Table 6. AC and DC Characteristics of RF/BB signals (continued)
Signal name TXC From - To COBBA SUMMA Function Transmitter power control T itt ower t l 0...200 kHz RXC COBBA SUMMA Receiver gain control 0...200 kHz

TXC and AGC signals originate from the same DAC, controlled in COBBA

Data Interface and Timing
The SUMMA is programmed via the serial bus SENA, SDATA and SCLK. The data of the SDATA is clocked by rising edge of SCLK. The data is fed MSB first and address bits before data bits. The data for the Programmable dual modulus counter is fed first and the Swallow counter last. SENA is kept low while clocking the data. (Figure below) During programming, the charge pump attached to programmed divider is switched to high impedance state. Also all counters connected to the PLL that is programmed, are kept on reset while the SENA is low.
Table 7. Logic levels Parameters High Low Min 2 0.8 Typ Max Units Volt Volt

6.9 ms ( 1.5 x 4.6 ms ( frame ) 100 us min. RXPWR 10 us 10 us 10 us 10 us 8 us

SYNPWR

2us min

SENA SDATA/ SCLK #bits

MODE 23

VHF R 23

VHF N/A 23

UHF R 23

UHF N/A 23

Original 02/99

Page 3 ­ 33

RAE­2 BS8_RF

PAMS Technical Documentation

MON

RX

MON

RX

MON

RX

MON

RX 0.5­2 sec.

20 ms 6.9 ms

4.6 ms

VCXOEN SYNPWR RXPWR AGC SENA SDATA/ SCLK

150 us

150 us

Figure 3.

Synthesizer timing / IDLE, one monitoring/frame, frame can start also from RX­burst

time slots

RX 0 1 2

TX 3 4 5

MON 6 7

RX 0

SYNPWR RXPWR TXPWR TXP SENA SDATA/ SCLK
ONLY UHF­ PLL N AND A REGISTERS CLOCKED

RX

TX
50 us max.

MON
50 us max.

RX
50 us max.

Figure 4. UHF­synthesizer timing/clocking on traffic channel

Page 3 ­ 34

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Transmit Power Timing

542.8 us

Pout

8.3...56.7 us

TXC

TXP
0...56.7 us 0...58 us

TXPWR
150 us 50 us

Figure 5. Transmitter timing diagram for normal bursts

Original 02/99

Page 3 ­ 35

RAE­2 BS8_RF

PAMS Technical Documentation

SUMMA and Synthesizer Control
Registers The following table shows the programmable registers in SUMMA which are used for programmable counters and mode selection.
Table 8. Registers addressing A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 HEX addr. 0 1 2 3 4 Bits 18 15 12 18 12 Register Control register VHF VDIV (VDIV2) VHF RDIV (RDIV2) UHF VDIV UHF RDIV

PLL Control Word Format Serial data format is shown below. Amount of bits needed for each address can be seen from Table 2. When less bits are sent, dummy bits must be inserted between the address and the real data.
MSB A2 A1 A0 ... ... S9 S8 S7 S6 S5 S4 S3 S2 LSB S1

Control Register
Bit no S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 Sign. LSB BS8 Def. 0 0 1 0 0 0 0 0 0 1 0 Name VHFOFF NF MODE1 MODE2 TEST VHFCPCS UHFCPCS VPDMOD ADDBIAS G1 NF Purpose 1=VHF synth power down No Function Mode selection LSB Mode selection MSB Test Mode selection VHF charge pump current Set = 0 (0.5 mA) 1(2.0 mA) UHF charge pump current Set 0 (0.5 mA) 1(2.0mA) Logic high keeps counters reset Extra bias for UHF prescaler TX AGC step No Function

Page 3 ­ 36

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

Bit no S12 S13 S14 S15 S16 S17 S18 S19

Sign.

BS8 Def. 0 0 1 0 0 0 1

Name NF NF fast PD_lin UHFOFF RX_SEL OA_sel TX_AGC_LATCH

Purpose No Function No Function Add current to chargepump UHF Phase detector mode 1=UHF synthesizer power down digital RX on Selects pwrctrl opamp TXP driven agc gain latching

MSB

1

NOTE:

NDIV2 divides reference frequency by programmable figure of 2­2047. Divide ratio less than 2 is prohibited.

Synthesizer clocking
GSM Division ratios The values of ch range from 1 to 124 UHF synthesizer reference divider ratio N counter division ratio A counter division ratio VHF synthesizer reference divider ratio N counter division ratio A counter division ratio Clocking scheme During power up ( first clocking ) SUMMA synthesizers should be enabled in the following order : 1. Mode setting (GSM) 2. reference divider for VHF PLL 3. N and A dividers for VHF PLL 4. reference divider for UHF PLL 5. N and A dividers for UHF PLL When transceiver is on allocated channel, then only (N and A dividers) UHF PLL is controlled, because it is the channel synthesizer. Mode settings and VHF PLL division ratios are fixed. R=65 N=INT((ch + 5030)/64) A=MOD((ch + 5030)/64) R=13 N=14 A=8

Original 02/99

Page 3 ­ 37

RAE­2 BS8_RF

PAMS Technical Documentation

List of abbreviations
ADC AFC AGC AM ASIC AVG BB BT BW CCONT CLK COBBA CRFU1A CW DAC DC DCS DCT DSP E­GSM ESD ESR ETSI FDMA FIR GMSK GND GSM HT IC IF IIP3 Analog to Digital Converter Automatic Frequency Control Automatic Gain Control Amplitude Modulation Application Specific Integrated Circuit Average Baseband Bandwidth x symbol time (GMSK filter parameter) Bandwidth DCT3 power management ASIC Clock DCT3 RF/BB and audio interface ASIC DCT3 dualband RF ASIC Continuous Wave Digital to Analog Converter Direct Current Digital Cellular System Digital Core Technology Digital Signal Processing or Digital Signal Processor Extended GSM (wider TX/RX bands) Electrostatic Discharge Effective Series Resistance European Telecommunications Standard Institute Frequency Division Multiple Access Finite Impulse Response Gaussian Minimum Shift Keying Ground Global System for Mobile communications Hilly Terrain (GSM standard fading profile) Integrated Circuit Intermediate Frequency 3rd order intermodulation Input Intercept Point

BiCMOS Bipolar and Complementary Metal Oxide Semiconductor process

Page 3 ­ 38

Original 02/99

PAMS Technical Documentation

RAE­2 BS8_RF

IMD LNA LO MAD MMIC MON MS NF OIP3 PA PCB PLL PM RA RBW RF RMS RSSI RX RXLEV SAW SACCH SPR SSB SUMMA TCH TDMA TU TX UHF VCO VCTCXO VHF VSWR

Intermodulation Distortion Low Noise Amplifier Local Oscillator DCT3 DSP/MCU/system logic ASIC (MCU­ASIC­DSP) Monolithic Microwave Integrated Circuit Monitoring slot Mobile Station Noise Figure 3rd order Output Intercept Point Power Amplifier Printed Circuit Board Phase Locked Loop Phase Modulation Rural Area (GSM standard fading profile) Resolution Bandwidth Radio Frequency Root Mean Square Received Signal Strength Indicator Receiver RX Level Surface Acoustic Wave Slow Associated Control Channel Standard Product Requirements (NMP's internal standard) Single Sideband DCT3 dualband IF ASIC Traffic Channel Time Division Multiple Access Typical Urban (GSM standard fading profile) Transmitter Ultra High Frequency (300 MHz ... 3 GHz) Voltage Controlled Oscillator Voltage Controlled Temperature Compensated Crystal Oscillator Very High Frequency (30 MHz ... 300 MHz) Voltage Standing Wave Ratio

Original 02/99

Page 3 ­ 39

RAE­2 BS8_RF

PAMS Technical Documentation

This page intentionally left blank.

Page 3 ­ 40

Original 02/99