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PAMS Technical Documentation RAE­2 Series PDA

Chapter 5 BS1 PDA Module

Section 02/99

Copyright E 1999. Nokia Mobile Phones. All Rights Reserved.

RAE­2 BS1

PAMS Technical Documentation

AMENDMENT RECORD SHEET
Amendment Date Number Inserted By OJuntune Comments Original

02/99

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CONTENTS ­ PDA module BS1 Page No
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signals and Connections . . . . . . . . . . . . . . . . . . . . . . UI flex connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board to board connector signals . . . . . . . . . . . . . . . . . . . . . System connector pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio connector pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Backup battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear regulator V28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear regulator V28_1,_2,_3 . . . . . . . . . . . . . . . . . . . . . . Switchmode regulator V17 . . . . . . . . . . . . . . . . . . . . . . . . Backup battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset and power management . . . . . . . . . . . . . . . . . . . . PDA CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IR­Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handsfree loudspeaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5­4 5­4 5­5 5­6 5­7 5­8 5­8 5­9 5 ­ 12 5 ­ 16 5 ­ 17 5 ­ 17 5 ­ 18 5 ­ 20 5 ­ 20 5 ­ 21 5 ­ 21 5 ­ 21 5 ­ 21 5 ­ 21 5 ­ 22 5 ­ 22 5 ­ 24 5 ­ 25 5 ­ 25 5 ­ 25 5 ­ 26 5 ­ 26 5 ­ 26 5 ­ 26 5 ­ 28 5 ­ 30

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Introduction
The function of the BS1 PDA module in RAE­2 Communicator device is to run all applications that utilize the PDA LCD display of the device. The GEOS operating system is applied on a 486 based PDA module platform. This processing platform utilizes the communicator­type user interface which is accessible when the RAE­2 is opened.

Technical Summary
The BS1 PDA module consists of a printed circuit board with a CPU, two kinds of memories, a Power unit, HF amplifier circuitry, and an IR­transceiver. The PDA module is assembled on a single 8­layer printed circuit board. All components are assembled on one single side. The other side is reserved for keyboard keypads. Serial ports, DMA­ and LCD controller for timers are integrated in the CPU. The operating system is GEOS supplied by Geoworks. The BS1 module includes three non­volatile Flash memories which are used for two kind of purposes. XIP (executed in place) memory is used for program file storage and RFD (resident flash disk) memory is writeable for user data. One DRAM Memory is used for the code execution and for the volatile storage of the internal run­time system data. Both memory types (DRAM and Flash) have their own address­ and data bus, routed directly from the CPU.
Table 1. Used memory blocks Memory type Flash (XIP) Flash (RFD) DRAM 4M 2M 2M Amount (Bytes)

The BS1 PWRU block regulates the PDA module power and controls the power-up and -down. After a battery has been connected, the PWRU gives the CPU system voltage and releases the reset as fast as possible after which the CPU SW has full power management control. The PWRU also generates and controls the voltages that the PDA LCD uses. The PDA has a rechargeable back­up battery which the PWRU block charges when the main battery is connected. The VBACK voltage is normally always available for real time clock. Power is fed from the battery through the CMT module to the PDA PWRU. The PWRU has a filter in battery line to reduce interference from the CMT module. The PWRU provides

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A/D converter readings of the battery voltage and temperature via a parallel interface to the CPU. Many PWRU items can be controlled by register writing or directly via pin. The system voltage is always present until battery voltage drops below 3.0V.

Electronics
The following sections of circuitry are included on the BS1:
Function

PWRU Power supply unit PDA CPU IR transceiver DRAM memory Flash memory HF Amplifier QWERTY Keyboard pads

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Interconnection Diagram

PDALCD
GND

BS2

Softkeys

CMT Keypad

CMT LCD

CMTLCD(5:0)

Flex connector FLASH 1Mx16
control (6:0) VBACK

X800 FLASH 1Mx16
C(3:0), R(1:0) C(7:0), R(9:0)

LCD PWR IF(6:0) VSYS D6:0 SA1:0 Charging LCD(10:0)

FLASH 1Mx16

BS1

PWRU
VBATT V28_3 VPDA

MA(11:0) D(15:0)

PWRKEY C4:0,R3:0

io(3:0)

QWERTY Keyboard Audio
Earpiece HF
HF_IF(1:0), EAR(1:0)

Backupbattery

Am486 CPU
X32kHz out MMC(3:0) SD(15:0) SA(21:0) JTAG(4:0) sio(1:0) X32kHz in

io(1:0)

RS_IF(2:0)

IR transceiver

DRAM 1Mx16

Test­ pads

FBUS_RXD FBUS_TXD FBUS_TXD2 MBUS

io(5:0)

FBUS_TXD FBUS_RXD

MBUS

io(3:0)

x32

System connector X810

GND

BoBo Connector

X830

VBATT

GND

Memory Card

BS8
CMT BS 1 PDA block in RAE­2 product

Figure 1.

NOTE: All modules have same ground.

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DC Characteristics
Table 2. Supply Pin / Conn. 1,2,3,4,5/ X830 1,2,3,4,5/ 1 2 3 4 5/ X830 E307 Line Symbol VBATT

Voltages and Power Consumption
Nominal 3.6 Maximum 4.1 900 Unit VDC mA VDC mA mA VDC mA VDC VDC mA VDC Notes Battery voltage, SW limit Current Backup battery voltage Charge current Quiescent current in suspend mode System voltage Current LCD Biasing voltage, NOTE1 LCD Biasing voltage, at +20C Current LCD intermediate voltage1 (12/13xV17_OUT ). NOTE1 at +20C Current LCD intermediate voltage2 (11/13xV17_OUT ). NOTE1 at +20C Current LCD intermediate voltage3 (2/13xV17_OUT). Max range at +20C Current LCD intermediate voltage4 (1/13xV17_OUT). NOTE1 at +20C Current

Minimum 3.0

VBACK

2.4 0.4

3.0 0.5 0.25

3.15 0.7 0.4 2.85 450 21.6 20.6 5 19.9

E312

VSYS

2.75 0.050

2.8 300 19.4 19.8 2

E300

V17_OUT

17.1 19.0

7/X800

V17_i1

15.8

17.9

17.5

18.3

19.0 4

VDC mA VDC

8/X800

V17_i2

14.4

16.4

18.3

16.1

16.8

17.4 4

VDC mA VDC

9/X800

V17_i3

2.6

3.0

3.3

2.9

3.0

3.2 4

VDC mA VDC

10/X800

V17_i4

1.3

1.5

1.7

1.4

1.5

1.6 4

VDC mA

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Table 2. Supply Pin / Conn. 3/X800 Line Symbol V28_1

Voltages and Power Consumption (continued)
Minimum 2.70 Nominal 2.80 1 Maximum 2.85 4 2.85 4 2.85 100 2.85 Unit VDC mA VDC mA VDC mA VDC mA Notes LCD Logic voltage Current IrDA Logic voltage Current MMC supply voltage Current Base Band operating voltage Current

21/N450

V28_2

2.70

2.8 2

46/X830

V28_3

2.75 0.01

2.8 50 2.8

16/X830

VBB

2.75

NOTE : Complete temperature range

AC Characteristics
Minimum External XTAL Nominal 32.768 20 CPU clock Memory bus clock Memory Controller clock MMC clock during data MMC clock during identification 0.2592 259.2 33.18 33.18 66.3552 8.294 Maximum kHz ppm, accuracy MHz, Rise time 1­2ns MHz, Rise time 2­3ns MHz, Rise time 1­2ns Mhz, Rise time 2­3ns, NOTE1 kHz, Rise time 2­3ns Unit / Notes

NOTE: Frequency is a multiple of 259.2kHz

External Signals and Connections
This section describes the external electrical connection and interface levels on BS1 module. The electrical interface specifications are collected into tables that cover each connector and defined interface. Table 3. List of Connectors and testpoints
Connector Name UI flex connector Board to Board connector System connector pads Code X800 X830 X810 CMT PDA interface Notes CMT/PDA LCD­ and Keyboard signals

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Table 3. List of Connectors and testpoints
Connector Name Audio connector pads Backup battery holder Testpads Frame connector pads Testpoints Code E880, E881, E850, E851 X451 E300­E315 X840 J310, J400­J404, J430, J434, J435, J440 ­ J456, J497 ­ J499, J801, J803, J804, J808, J854, J880, J881

(continued) Notes

HF­speaker connection and earpiece connection

Testpads "under" battery pack Include manufacturing testpads. Is removed before assembly Testpoints around the BS1 PCB.

UI flex connector
The Interface between the BS2 and BS1 modules comprises a 51­pin flex connector. The connector includes supply voltage for the BS2 module, and required information signals. Signals from the BS8 module are also carried via the flex connector. Table 4. UI flex Connector X800
Pin 1 2 I I/O Name GND LCD_TEMP Function Global Ground PDA LCD Temperature 0.2 0.9 2.5 VDC Voltage range throught the whole temperature range. At +25_C Min Nom Max Unit Description / Note

0.2 3 4 O O V28_1 LCD_ON PDA LCD Logic voltage PDA LCD enable 2.70 2.30

0.9 2.80 2.8 0

0.91 2.85 2.85 0.4 20.6

VDC VDC VDC VDC VDC

High Low Range at +20C. Whole range can be seen from table2

5

O

V17_OUT

PDA LCD Biasing voltage

19.0

19.8

6 7 8 9 10 11 O O O O

GND V17_i1 V17_i2 V17_i3 V17_i4 GND

Global Ground PDA LCD Intermediate bias voltage lt 17.5 16.1 2.9 1.4 Global Ground 18.3 16.8 3.0 1.5 19.0 17.4 3.2 1.6 VDC VDC VDC VDC Range at +20C. Whole Wh l range can be seen from table2

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Table 4. UI flex Connector X800
Pin 12 I/O O Name FRM Function PDA LCD Frame pulse Min 2.30

(continued)
Nom 2.80 0 72 Max 2.85 0.45 100 Unit VDC VDC Hz % Duty cycle High Low Description / Note High Low

13

O

M

PDA LCD AC Modulation

2.30

2.80 0 2.5

2.85 0.45 3.4

VDC VDC kHz

14 15 O

GND LC

Global Ground PDA LCD Line pulse 2.30 2.80 0 32 2.85 0.45 44.5 VDC VDC kHz High Low

16 17 O

GND SCK

Global Ground PDA LCD bus clock 2.30 2.80 0 2.3 2.85 0.45 3.2 VDC VDC MHz High Low

18 19 O

GND LCDD0

Global Ground PDA LCD Data signal 2.30 2.80 0 2.85 0.45 2.85 0.45 VDC VDC VDC VDC High Low High Low

20

O

LCDD1

PDA LCD Data signal

2.30

2.80 0

21 22 O

GND LCDD2

Global Ground PDA LCD Data signal 2.30 2.80 0 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5 VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC High Low High Low High, backlight enabled Low High, backlight enabled Low High Low High Low High Low High Low High Low High Low

23

O

LCDD3

PDA LCD Data signal

2.30

2.80 0

24

O

PDA_BL_ON

PDA LCD Backlight enabled

2.30

2.80 0

25

O

CMT_BL_ON

CMT Backlight enabled

2.1

2.80 0

26

I

ROW3

CMT Keys Row3, Lid closed, Base b d powered B band d CMT Keys Row2, Lid closed, B d Base b d powered band CMT Keys Row1, Lid closed, Base b d powered B band d CMT Keys Row0, Lid closed, Base b d powered B band d CMT Keys Col4

2.1

2.80 0

27

I

ROW2

2.1

2.80 0

28

I

ROW1

2.1

2.80 0

29

I

ROW0

2.1

2.80 0

30

O

COL4

2.1

2.80 0

31

O

COL3

CMT Keys Col3

2.1

2.80 0

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Table 4. UI flex Connector X800
Pin 32 I/O O Name COL2 Function CMT Keys Col2 Min 2.1

(continued)
Nom 2.80 0 Max 2.85 0.5 2.85 0.5 2.8 0.5 2.85 0.8 2.85 0.8 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.5 2.85 0.5 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Description / Note High Low High Low High Low High Low High Low High Low High Low High Low High Low High, data Low, command High Low, chip selected

33

O

COL1

CMT Keys Col1

2.1

2.80 0

34

O

COL0

CMT Keys Col0

2.1

2.80 0

35

I

APP_ROW1

PDA Application row1

2.0

2.80 0

36

I

APP_ROW0

PDA Application row0

2.0

2.80 0

37

O

APP_COL3

PDA Application col3

2.3

2.80 0

38

O

APP_COL2

PDA Application col2

2.3

2.80 0

39

O

APP_COL1

PDA Application col1

2.3

2.80 0

40

O

APP_COL0

PDA Application col0

2.3

2.80 0

41

O

LCDCD

CMT LCD driver command/ data l ti d t selection CMT LCD driver chip select

2.1

2.80 0

42

O

LCDSCx

2.1

2.80 0

43 44 O

GND GENSCLK

Global Ground CMT LCD driver bus clock 2.1 2.80 0 2.85 0.5 4.0 VDC VDC MHz High Low

45 46 O

GND GENSDIO

Global Ground CMT LCD driver serial data 2.1 2.80 0 2.85 0.5 4.0 VDC VDC MHz High Low

47 48 O

GND LCDRST

Global Ground CMT LCD Reset 2.1 2.80 0 2.85 0.5 2.85 2.85 0.45 4.1 VDC VDC VDC VDC VDC V mA 65 20 mA mA PDA and CMT backlights off PDA LCD backlight ON PDA LCD backlight OFF Inactive state L(Pulse)=Power on/off, min 64ms High Low

49 50 I

VBB PWRKEY CMT Power switch

2.7 2.1

2.8 2.80 0

51

VPDA

Filtered battery voltage from PDA

3.0

3.6 0

40 10

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Board to board connector signals
All interfaces from the BS8 module to the BS1 module are fed over a 50­pin board-to-board connector. The function of the Interface is to transfer the battery voltage from the BS8 module, and transfer data between the BS8, BS2, and BS1 modules. The signal definition and the most significant specifications of signals are collected in the next table. Table 5. Board to board connector X830
Pin 1 2 3 4 5 6 7 8 I I XEAR GND BATTDET Audio Output for Handsfree and Car Kit Use Global Ground Battery Position Information 2.0 0 9 I HFENA Internal Handsfree Amplifier Control 2.1 2.80 0 2.80 0 10 11 12 13 O EARP EARN GND PWRONx Earpiece Positive Earpiece Negative Global Ground PDA start baseband to service R i Request St t (SRS) t State 2.30 2.8 0 2.30 2.8 0 2.85 0.45 2.85 0.45 12 32768 20 50 80 1 15 16 GND VBB Global Ground CMT System Power 2.7 2.8 2.85 1 17 O PWRKEYx CMT Power Switch 2.0 2.80 0 2.85 0.45 VDC mA VDC VDC Regulated CMT baseband voltage Maximum current Inactive state L(Pulse)=Power on/off, min. 64ms VDC VDC VDC VDC mA Hz % % High Low, powering up the CMT high low Maximum current for PDA Pulse frequency Duty cycle Jitter 50 2.85 0.8 2.85 0.5 223 VDC VDC VDC VDC mVpp High, HF amplifier enabled Low, HF amplifier disabled Differential signal 500 mVpp Reference for other signals I/O Name VBATT Function Battery Positive Min 3.0 0.3 Nom 3.6 Max 4.1 1000 Unit V mA Description / Note Unregulated Battery Voltage Current from BS8 module d l

14

O

32kHz

Sleep clock for the CMT

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Table 5. Board to board connector X830
Pin 18 I/O I Name CMT_BL_ON Function CMT UI Light On Min 2.1 Nom 2.8 0 19 O ROW3 CMT Keys Row 3 2.5 2.8 0 20 O ROW2 CMT Keys Row 2 2.5 2.8 0 21 O ROW1 CMT Keys Row 1 2.5 2.8 0 22 O ROW0 CMT Keys Row 0 2.5 2.8 0 23 24 I GND COL4 Global Ground CMT Keys Column 4 2.1 2.80 0 25 I COL3 CMT Keys Column 3 2.1 2.80 0 26 I COL2 CMT Keys Column 2 2.1 2.80 0 27 I COL1 CMT Keys Column 1 2.1 2.80 0 28 I COL0 CMT Keys Column 0 2.1 2.80 0 29 30 I GND LCDCD Global Ground CMT LCD Command / Data S l t Select CMT LCD Reset 2.1 2.80 0 2.1 2.80 0 32 I LCDCSx CMT LCD Chip Select 2.1 2.80 0 33 34 I GND GENSCLK Global Ground CMT LCD and CCONT Serial Clock Cl k 2.1 2.80 0 3.250 35 I GENSDIO CMT LCD and CCONT Serial Data D t 2.1 2.80 0 1.625 36 37 O GND FBUS_RXD Global Ground Fast Serial Data to CMT 2.30 2.80 0 38 I FBUS_TXD Fast Serial Data to PDA 2.1 2.80 0

(continued)
Max 2.85 0.5 2.85 0.2 2.85 0.2 2.85 0.2 2.85 0.2 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Description / Note High, backlight enabled Low High Low High Low High Low High Low

2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5 2.85 0.5

VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC

High Low High Low High Low High Low High Low

2.85 0.5 2.85 0.5 2.85 0.5

VDC VDC VDC VDC VDC VDC

High, data Low, command High Low, LCD reset High Low, chip selected

31

I

LCDRSTx

2.85 0.5

VDC VDC MHz

High Low Pulse frequency in active state High Low Maximum pulse frequency

2.85 0.5

VDC VDC MHz

2.85 0.45 2.85 0.5

VDC VDC VDC VDC

High Low High Low

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Table 5. Board to board connector X830
Pin 39 40 I/O I/O Name GND MBUS Function Global Ground Bidirectional Serial Bus 2.30 2.80 0 2.1 2.80 0 41 VSYS PDA System voltage 2.75 2.80 Min Nom

(continued)
Max Unit Description / Note

2.85 0.45 2.85 0.5 2.85 2

VDC VDC VDC VDC VDC mA VDC VDC kohm.

High, to the CMT Low, to the CMT High, from the CMT Low, from the CMT

42

O

LIDSWITCH

Lid State Information

2.75

2.80 0 10

2.85

High, Cover open Low, Cover closed Pull­up resistor High, Cover open Low, Cover closed

43

I

MMC_SWITCH

MMC Cover State Information

2.75

2.80 0

2.85

VDC VDC

44 45 I/O

GND MMC_CMD

Global ground MMC Command / Address / Response, Bidirectional 2.30 2.80 2.85 VDC Data to the card High, Pulled up with 10kohm resistor to MMC_VSYS in CMT Module Data to the Card Low data from the card High, Pulled up with 10kohm resistor to MMC_VSYS in CMT Module Data from the card Low frequency

0 2.1 2.80

0.45 2.85

VDC VDC

0.34 259.3 46 MMC_VSYS MMC Power Supply 2.75 0.01 47 I/O MMC_DATA MMC Bidirectional Data 2.30 2.80 2.85 100 2.85

VDC kHz VDC mA VDC

Current Data to the Card High, Pulled up with 10kohm resistor to MMC_VSYS in CMT Module Data to the card Low Data from the Card High, Pulled up with 10kohm resistor to MMC_VSYS in CMT Module Data from the card Low frequency

0 2.1 2.80

0.45 2.85

VDC VDC

0 8.294 48 GND Global ground

0.34

VDC MHz

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Table 5. Board to board connector X830
Pin 49 I/O O Name MMC_CLK Function MMC Clock Min 2.30 Nom 2.80 0 0.2592 50 GND Global Ground

(continued)
Max 2.85 0.45 8.294 Unit VDC VDC MHz Description / Note High Low Frequency

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System connector pads
The RAE­2 System connector is a multipurpose connector, which is shared with the BS8 module. In this section are described only the signals that are connected to the BS1 module. These signals are needed for PC­connectivity. The connector comprises spring type contacts to the BS1 and BS8 module. The PCB comprises pads on which the springs are pressed.

Table 6. System Connector pads X810
Pin 8 Line Symbol DCT_TX Parameter PDA CPU Receive data PDA CPU Transmit data PDA CPU Data set ready read Global ground Minimum 2.0 0 2.30 0 2.0 0 2.80 2.80 Nominal 2.80 Maximum 2.85 0.8 2.85 0.45 2.85 0.8 Unit VDC VDC VDC VDC VDC VDC Unit / Notes

9

DCE_RX

10

DCE_DTR

11

GND

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Audio connector pads
The audio connector has two contact types. The earpiece contacts are of spring type, and the contacts for the handsfree speaker are elastomeric contacts. Table 7. Audio connector pads
Pin E850 E851 E880 Line Symbol EARP EARN PHFEARN Parameter Earpiece positive node Earpiece negative node Handsfree speaker negative node 6.0 Vpp VBATT=4.4V. Differential voltage between PHFEARN and PHFEARP nodes VBATT=3.6V. Differential voltage between PHFEARN and PHFEARP nodes VBATT=4.4V. Differential voltage between PHFEARN and PHFEARP nodes VBATT=3.6VBATT=4.4V. Differential voltage between PHFEARN and PHFEARP nodes. Minimum 50 Nominal Maximum 223 Unit mVpp Unit / Notes Differential voltage between EARP and EARN nodes

4.4

Vpp

E881

PHFEARP

Handsfree speaker positive node

6.0

Vpp

4.4

Vpp

Backup battery

Figure 2.

Backup battery insertion direction

NOTE: Positive node is against PCB, it can be identified by 2mm diameter contact plate Table 8. Backup battery holder X450
Pin Name VBACK GND Function Backup battery voltage Global ground Min 2.4 Nom 3.0 Max 3.1 Unit VDC Description / Note

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Internal Signals and Connections
Table 9. IR­transceiver (N300) signals
Pin 3 Line Symbol TXD Parameter Transmit data from CPU Minimum 2.30V Nominal 2.80V 0V 4 RXD Receive data to CPU 2.0V 2.8V 0 Maximum 2.85V 0.45V 2.85V 0.8V Unit / Notes

Table 10. Signals between PDA CPU and Flash memories
Name SA(21:1) Function System address Min 2.30 Nom 2.80 0 SD(15:0) System data from CPU 2.30 2.8 0 System data from memory 2.40 2.8 0 ROMCS(2:0) Chip selects for Flash memoi ries Flash write signal 2.30 2.80 0 2.30 2.80 0 ROMRDx Flash read signal 2.30 2.80 0 GPIO_CS1 Write protect for RFD memory 2.30 2.80 0 GPIO_CS7 RFD Flash ready 2.0 2.80 0 Max 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.8 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Description / Note High Low High Low High Low High Low High Low, write enabled High Low, read enabled High Low, powered down High, ready Low, busy

FLSHWRx

Table 11. Signals between PDA CPU and DRAM Memory
Name MA(11:0) Function Memory address Min 2.30 Nom 2.80 0 SD(15:0) Memory data from CPU 2.30 0 Memory data from memory 2.0 0 RAS0 Row access strobe 2.30 2.8 0 2.8 0 2.80 0 CAS(1:0) Column access strobe 2.30 2.80 0 MWEx Memory write enable 2.30 2.80 0 Max 2.85 0.4 2.85 0.4 2.85 0.6 2.85 0.4 2.85 0.4 2.85 0.4 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Description / Note High Low High Low High Low High Low High Low High Low, write enabled

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Table 12. Signals between PDA CPU and PWRU
Name SA(2:0) Function System address Min 2.30 Nom 2.80 0 SD(6:0) System data 2.40 2.8 0 CS3x Chip select for Phaser 2.30 2.80 0 IOWx Phaser write signal 2.30 2.80 0 IORx Phaser read signal 2.30 2.80 0 RESETx Reset for CPU, and for Flash memories. i Back­up battery voltage LCD bias voltage enable 2.30 2.80 0 2.40 2.30 3.0 2.80 0 V28_1EN LCD logic voltage enable 2.30 2.80 0 Max 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.4 2.85 0.4 3.1 2.85 0.4 2.85 0.4 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Description / Note High Low High Low High Low High Low, write enabled High Low, read enabled High Low High High Low High Low

VBACK V17_EN

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Functional Description
Power Unit

BS2
V28_1 VPDA VBB V17

TESTPADS VSYS VPDA V28 IOW IOR ADD(2:0) DATA (6:0) CS3x V28_EN V17_EN VBATT PWRGOOD Charging RESETx NMI PMI PMI Write protect NMI VSYS VPP

BS1
DRAM
FRAME CONNECTOR

V28_3

Interm.voltages 1­4

V28_1

MMC

VSYS VSYS

IrDA

V28_2 VPDA

PWRU HF­ power amp.
VPDA PWRGOOD

Am486 CPU

RESETx

XIP VPP XIP Flashes

RESETx VBACK

RFD RFD Flash

Backupbattery Lid Switch

VBATT

VSYS

VBB

MMC_SWITCH

Figure 3. PDA Power distribution diagram

Battery voltage is supplied from the BS8 module through a board to board connector. In the BS1 module the battery voltage is filtered and then supplied to the Phaser, IR­transceiver circuit, BS2 module, and PHF­speaker circuitry. The phaser generates internally the system voltage V28, switched voltages V28_1 ,V28_2, V28_3, the LCD bias voltage V17, the LCD intermediate voltages V17_ix, x=1­4 and the backup battery charging voltage VBACK. When the battery voltage level is adequate, the PWRU switches V28 on and after a certain time releases the reset­signal for the CPU. The CPU

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BATTDET

BS8

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controls the LCD, MMC, and IR­transceiver logic voltages by writing command to the PWRU register. Optionally the CPU can control the LCD logic- and biasing voltage directly by means of I/O signals. The backup battery supplies power to the CPU's real time clock. The PWRU charges the backup battery when the main battery is connected. The CPU puts the Flash memories to power down mode when they are not used. The BS8 signal BATTDET is a warning signal that the battery will be removed soon, when power down procedure is started. VBB is the supply voltage for the CMT display, located in the BS2 module, and the VBB provides information for the BS1 CPU whether the CMT powered or not and it enables the keyboard buffer. The MMC_SWITCH indicates that the MMC card will be removed, when the CPU controls the Phaser to turn the V28_3 off. Input filter The Battery voltage is fed from the BS8 module and then filtered by using a LC­lowpass filter, after filtering the voltage is named VPDA. The VPDA is then fed to the PWRU, the IR­transceiver, the PHF­speaker circuitry, and to the BS2 module. Linear regulator V28 System voltage V28 is generated by a linear regulator. V28 stays on all the time when the battery voltage is higher than cutoff limit. Linear regulator V28_1,_2,_3 These regulators are controlled by the CPU. The CPU can enable these regulators by writing a command to the PWRU's register. V28_1 is the switched V28 and is used for the LCD logic. V28_2 is the switched V28 and is used for the IRDA logic. V28_3 is the MMC voltage. Switchmode regulator V17 The LCD bias voltage V17 is generated by a step­up DC­DC converter. The control scheme is the current limited pulse width modulation (PWM). The switching transistor is internal. The regulator output, too, is separated from the battery line by an integrated switch transistor between the regulator output and load. Backup battery The Real time clock is kept running by a backup battery only when the main battery is not connected. At the nominal RTC load used , the 12mAh capacity of the backup battery provides about 40 days of RTC operation when the main battery is not connected. The backup battery is

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rechargeable. It is charged by the Phaser VBACK regulator using 0.5mA current when the main battery is connected. Reset and power management The Phaser is connected to the I/O space of the H3 by using a 7 bit wide data bus and a 3 bit wide address bus. The BS2 PDAPWRU on the PDA board supplies two different voltage levels to the system; 2.85V is used as the main operating voltage for all circuits and about 19V that is needed for the LCD bias (V17). The LCD bias voltage is used to adjust the contrast ratio of the LCD screen. The LCD bias voltage is controlled by the Phaser ASIC. The V17 and V28_1 ON/OFF are switched by the Phaser, but optionally also the CPU can control these signals directly with HW means, independently of the SW controlled register settings. The phaser provides also the POWERGOOD signal for the CPU. The system reset circuit is part of the power supply. When the battery voltage is higher than 3.4V a PWRGOOD is generated for the CPU. The reset circuit also asserts the reset signal whenever the Vcc supply voltage declines below the threshold, keeping it asserted for at least 50ms after Vcc has risen above the reset threshold. The reset circuit is designed to ignore fast transients (t < 64µs) in Vcc. There is an undervoltage lockout (UVLO) block inside the Phaser. Below the threshold limit the comparator shuts down all Phaser functionality to prevent the battery from overdischarge. Otherwise the VSYS regulator current drains the battery when left unused for long period. After the UVLO there is only reference block in the Phaser drawing current from the battery. The UVLO has a little hysteresis and is cancelled when the battery voltage has risen to 2.7V. However, reset to the CPU is given only when battery voltage rises to 3.45V. This in order to avoid unsuccessful power­ups. When the lockout voltage level is reached, the battery voltage rises because the load is removed.

PDA CPU
The PDA CPU is a SC450­33CC in a 256 pin plastic ball grid array package. The core features a 32­bit architecture with internal 8k write­back cache. The clock rate is 33MHz, which can be slowed down to1MHz. The default clock rate on reset is 8.29MHz. The bus clock rate is 33MHz. A 32kHz clock signal for the BS8 module is provided by the CPU PLL circuit. The clock signal is started when ever the system voltage is applied to the CPU. The CORE starts when the reset signal is provided and then it begins to execute the program code from the Flash memory. The external pull­up resistor controls the start­up procedure (Boot code Chip select, and data bus width).

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The memory controllers are integrated to the chip. A ROM controller is used for Flash interface and a DRAM controller supports extended data out (EDO) page mode DRAMs. Both memory types (DRAM and Flash) have their own address and data bus routed directly to the CPU. The power unit is controlled via an I/O-mapped 7-bit wide data- and 3-bit wide address bus, which is shared with Flash data- and address bus. The CPU block diagram is the figure below.

Addr Am486SLE Core Data Memory management unit SA bus

DMA controller 8237

Addr Address decoder

Reset

Power management unit

Data steering Graphics controller

Data bus

LCD

Loop filters x32kHz 32kHz xtal

Clock generation MMC bus controller MMC bus

Real time clock Memory controller

DRAM control ROM control

JTAG port

Boundary scan

AT port logic

Keyboard cntrl matrix/XT

Columns Rows

Timer 8254

UART 16550 UART 16550

FBUS Serial port

Interrupt controller 8259 GPIO's

Elan SC450­33CC

IrDA infrared controller

R­tranceiver

For serial interface two UART circuits are used. UART2 is a serial interface reserved for data transfer between the BS1 and BS8 modules. UART2 is disabled or enabled according to the CMT voltage. UART1 is used for RS­232 interface with external level changer. The UARTs can be connected together to establish Re­Link connection, where received data is directly linked to the UART's transmit data pin. That way the BS8 module can be programmed by using an external RS-interface. Autobauding detection circuitry is included in the UART1 block.

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The LCD­controller supports a 4-bit data and 16-grey shades. The display control signals are routed from the CPU. The bigger (640x200) LCD is located in the lid. The interconnection between the CPU and the LCD comprises a flex through the hinge. Data and control signals are provided by the CPU. The required voltages are supplied by the PWRU. The PDA CPU supports a synchronous serial interface that is compatible with the Multimedia Card Bus (MMC) Protocol. The MMC is changeable Flash or ROM memory card with variable memory size. The MMC connector is located on the BS8 Module. MMC signals are routed to the BS8 module through a Board to board connector. The interface consists of three pins: one clock(output), one command/response (bidirectional), and one data pin (bidirectional). The controller is capable up to 8Mbits/second transfer rate. The keyboard controller includes a matrix keyboard which is used for PDA keyboard and for PDA lid keys. The PC/AT standard core includes a 8254 programmable interval timer, two 8259 programmable interrupt controllers, and a real time clock. The CPU's general purpose input/outputs (GPIO) are controlled by the CPU's registers.

I/O Signals
In the Table 13 below are listed BS1 module I/O signals which are mapped to general purpose pins of the CPU.
Table 13. Spock CPU Controllable I/O Signals Scotty Pin
GPIO_CS1 GPIO_CS2 GPIO_CS5 GPIO_CS6 GPIO_CS7

Signal Name
RFD_WPx XIP_STS TESTMODEx PWRONx Flash_RDY

Low
Write operation Memory busy Testmode activated Powering the CMT up Flash performing an internal operation MMC cover closed

High
Write not possible Memory ready Reset, Suspend, Operation Reset, Suspend Flash ready for new command Reset, MMC cover open

Note
Input, CS(1:0) Flash memory status Input. Activate the power on procedure for the CMT Input. Open drain output, processor's internal pull­up is used. (Only for the RFD) Input. MMC cover status indication Output during BS8 Flashing from BS1 module, Input otherwise.

GPIO_CS8 GPIO_CS9 GPIO_CS11 GPIO_CS12 GPIO_CS13 GPIO16 GPIO18 BL1

MMC_Switch MBUS Phaser_CSx VBB

Chip Selected CMT off

Chip not selected Reset, CMT on

Output. Input.

LCDBL_EN BZR_EN BATTDET

Reset, Suspend, BL disabled Reset, Suspend Battery connected Cover closed

Backlight activated Operation Battery removed

Backlight EL driver controller. Enables the PA. Indicates when the battery is going to be removed. Pin has build in 15ms debounce STI. Indicates when the coved is open or closed

SUS/RES

LIDSWITCH

Cover open

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Table 13. Spock CPU Controllable I/O Signals (continued)
LVDD LVEE LVDD LVEE Reset, Suspend Reset, Suspend PDA LCD Logic voltage activated PDA LCD bias voltage activated Routed to the Phaser Routed to the Phaser

Memories
The memory units of the module are connected to the CPU via a 16­bit wide data bus. Both memory types (DRAM and Flash) have an own data­ and address bus.
MD [15:0] MA [11:0] control [3:0] control [7:0]

DRAM

BS1 CPU

RFD Flash

XIP Flash 1

XIP Flash 0

SD [15:0] SA [21:0]

DRAM memory
The 1Mx16bit DRAM is connected to the CPU with a dedicated 16­bit wide data- and 12-bit wide address bus. The DRAM type used is the extended data out (EDO) DRAM with 60ns access time, and self­refresh capability. DRAM is packaged in a 5.55mmX9.10mm, 40­ball uBGA package. When the DRAM is driven by the CPU, no wait states is needed.

Flash memory
Three 1Mx16bit Flash memory devices are used for non­volatile memory. The Flash type features a 120ns access time. The Flash is packaged in 8mmX11mm 64­ball CSP package. When the Flash is read by the CPU, 4 wait states are needed to ensure proper timing.

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External Serial Interface
The UART1 External serial interface is used for PC­connectivity. The RS­ connection is provided by a 3­signal interface (RXD,TXD, and DTR) which is routed to the system connector. Maximum data rate is 230.4kbps. The re­link feature connects the UART1 and the UART2 (FBUS) internally together. This provides the signal routing from the system connector to the CMT. The Autobaud detection circuitry can detect bit rates from 300 bps tp 115.2kbps. The autobaud state machine starts when enabled by the CPU. The bit rate measurement begins on the first negative edge of the CPU_RXD line. After detecting the start bit width, and therefore the bit rate, the remainder of the incoming data stream is sampled at this rate. This UART is shared with the IrDA circuitry and thus only one of them can be used at a time.

IR­Transceiver
The IR­transceiver controller is shared with the UART1. Infrared data transfer is started with 9600bps and then the data rate is increased to 115.2kbps if the connected device supports higher speed. The protocol is the standard one of the Infrared Data Association. The CPU hardware implementation includes bit stuffing (when transmitting), CRC calculation, removing bit stuffing, and removing beginning of frame (when receiving) .

Handsfree loudspeaker
The Handsfree speaker power amplifier circuitry is located on the BS1 module. The HF­speaker is used to produce the PDA key­click sounds, error beeps, and tunes. When the lid is opened, the loudspeaker is used as an handsfree speaker, producing key­click sound when a PDA QWERTY key is pressed, and producing tunes. The HF­speaker power amplifier can be controlled by the PDA CPU, or CMT.

Keyboard
The keyboard interface comprises 10x8 matrix lines. The QWERTY keyboard pads are located on the other side of the BS1 module board. 4x2 (2Row/4Column) matrix is routed to the lid. Four columns are multiplexed with CMT keyboard columns. Multiplexing is done by using buffer located on the BS1 module. This buffer is controlled by Baseband voltage (VBB). When the lid is closed these four columns are switched to inputs and they are not read by the CPU.

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Table 14. Key Reference Numbers vs. Senses and Drives. Column Col0 Row0 Row1 Row2 Row3 S730 S731 S300 S306 Col1 S732 S733 S318 S307 Col2 S734 S735 S347 S308 Col3 S736 S325 S324 S327 Col4 S331 S330 S335 S328 Col5 S337 S336 S311 S310 S341 S303 S309 Col6 Col7 S343 S342 S305 S323, S329, S334 S317 S302 S346

Row4 Row5 Row6 Row7 Row8 Row9

S312 S301 S352 S357 S362

S313 S319 S353 S358 S363

S314 S320 S354 S359 S364

S332 S321 S338 S344 S326

S333 S322 S339 S345 S351

S316 S348 S356 S361 S365

S315 S349 S355 S360 S350 S304, S340

NOTE1: Shift pads has dedicated Sense line (ROW9), These shift pads are connected parallel NOTE2: Grey shaded switches are located in BS2 module.

Figure 4.

BS1 PDA keyboard

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Test pads
Test pads are located under the battery pack. They include JTAG port which is used for After Sales Flashing purposes. The different voltages can be measured from these testpads. Serial data transfer test pads are used for data transfer between the BS1 and BS8 modules.

Figure 5.

Test pad layout

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Table 15. Test pads
Pin E300 I/O Name V17_OUT Function PDA LCD Biasing voltage Min 13.8 Nom 19.4 0 E301 I BNDSCN_TMS Boundary scan Test mode select 2.0 2.80 0 E302 I BNDSCN_TCK Boundary scan test clock 2.0 2.80 0 E303 I BNDSCN_TDI Boundary scan data in 2.0 2.80 0 E304 O BNDSCN_TDO Boundary scan data out 2.30 2.80 0 E305 I BNDSCN_EN Boundary scan enabled 2.0 2.80 0 E306 I Flash VPP Flashing voltage for XIP Flashes. 2.75 2.80 2.85 0.8 2.85 0.8 2.85 0.8 2.85 0.45 2.85 0.8 2.85 Max 22.2 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Description / Note High Low High, test mode selected Low High Low High Low High Low High, boundary scan enabled Low Connected to VBATT inside the Service battery. High High Low High Low High, to the CMT Low, to the CMT High, from the CMT Low, from the CMT

E307 E308 O

VBACK FBUS_RXD

Backup battery voltage PDA CPU Tx­pin

2.40 2.30

3.0 2.80 0

3.10 2.85 0.45 2.85 0.8 2.85 0.45 2.85 0.5 2.85

VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC

E309/ E310 E311

I

FBUS_TXD1,2

PDA CPU Rx­pin

2.0

2.80 0

I/O

MBUS

Bidirectional Serial Bus

2.30

2.80 0

2.1

2.80 0

E312 E313 E314 I

VSYS GND FLSHWRx

System voltage Global Ground Write signal for Flash memories i

2.75

2.80

2.30

2.80 0

2.85 0.45 2.85 0.8

VDC VDC VDC VDC

High Low, write enabled High Low, testmode enabled

E315

I

TESTMODEx

testmode activation

2.0

2.80 0

NOTE : Testpad E308 ... E310 is reserved for R&D use.

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Testpoints
Testpoints are located around the PDA PCB. They include clock, control, data signals and voltages which is used for R&D, fault finding and testing purposes.

Figure 6. Testpoints layout

Table 16. Testpoints
Point J310 I/O Name LID_SWITCH_IF Function Lid switch state Min 2.75 Nom 2.8 0 J400 33MHz CPU core clock 2.3 2.80 0 J401 O X32_CLK CMT sleep clock 2.3 2.80 0 J402 I VBB CMT baseband voltage 2.7 2.80 2.85 0.45 2.85 0.45 2.85 1.0 Max 2.85 Unit VDC VDC VDC VDC VDC VDC VDC mA Description / Note High, lid open Low, lid closed High Low High Low High Maximum current

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Table 16. Testpoints
Point J403 I/O I/O Name MBUS Function Bidirectional Serial Bus

(continued)
Min 2.30 Nom 2.80 0 2.1 2.80 0 Max 2.85 0.45 2.85 0.5 2.85 0.45 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.8 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.45 2.85 0.4 VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Description / Note High, to the CMT Low, to the CMT High, from the CMT Low, from the CMT High Low When PLLs are locked High, Sini vawe Low High Low High Low, chip selected High Low, chip selected High Low, write enabled High Low, write enabled High Low, read enabled High Low, write protected High Low High Low High Low High Low High Low High Low

J404

O

PWR_ONx

2.0

2.80 0

J430 J434 I

LF_INT X32IN

Intermidiate PLL loop filter

1.2 1.35 0

J435

O

X32OUT

1.0 ­0.3

J440

ROMCS2

RFD flash chip select

2.3

2.80 0

J441

ROMCS0

XIP1 flash chip select

2.3

2.80 0

J442

FLASHWRx

XIP and RFD flashes write enable f bl from CPU

2.3

2.80 0

I

XIP and RFD flashes write enable from frame connector bl f f t or testpads ROMRDx RFD flash read enable

2.0

2.80 0

J443

2.3

2.80 0

J444

WP

RFD flash write protect

2.3

2.80 0

J445

ROMCS1

XIP2 flash chip select

2.3

2.80 0

J446

RASx

DRAM row address strobe

2.3

2.80 0

J447

MWEx

DRAM write enable

2.3

2.80 0

J448

CASL1x

DRAM upper column address select l t DRAM lower column address select l t RFD flash status

2.3

2.80 0

J449

CASL0x

2.3

2.80 0

J450

FLASH_CTRL2

2.4

2.80 0

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Table 16. Testpoints
Point J451 I/O Name STS1 Function XIP1 flash status

(continued)
Min 2.4 Nom 2.80 0 Max 2.85 0.4 2.85 0.4 2.85 0.45 2.85 0.4 2.85 0.45 2.85 0.45 2.85 0.45 1.285 2.80 0 2.85 0.4 2.85 0.5 2.85 0.5 2.85 0.6 2.85 0.5 2.85 2.85 0.6 2.85 0.45 2.0 Unit VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Vpp High Low, chip selected High Low High Low High, data Low, command High Low, chip selected High High Low High, HF amplified enabled Low, HF amplified disabled Description / Note High Low High Low High, data to memory Low, data to memory High, data to CPU Low, data to CPU High Low High Low High Low

J452

STS2

XIP2 flash status

2.4

2.80 0

J453

SD1

System data bus line 1

2.3

2.80 0

2.4

2.8 0

J454

SA4

System address bus line 4

2.3

2.80 0

J455

D0

Memory data bus line 0

2.3

2.80 0

J456

MA3

Memory address bus line 3

2.3

2.80 0

J497 J498

VCOMP1 CS3x Phaser chip select

1.24 2.3

J499

RESETx

Reset from Phaser to CPU and flash memories d fl h i CMT LCD and CCONT serial data d t CMT LCD command / data select l t CMT LCD chip select

2.5

2.80 0

J801

O

GENSDIO

2.0

2.80 0

J803

I/O

LCDCD

2.0

2.80 0

J804

I/O

LCDCSx

2.1

2.80 0

J808 J854

O

SCK BZR_IF

PDA LCD data clock Buzzer signal

2.3 2.0

2.80 2.80 0

J880

HFENA

Handsfree earpiece enable

2.3

2.80 0

J881

O

XEAR

Audio output for handsfree use

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