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PAMS Technical Documentation NSM2 Series Transceivers
System Module
Issue 1 12/1999
E Nokia Mobile Phones Ltd.
NSM2 System Module
PAMS Technical Documentation
CONTENTS
Transceiver NSM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External and Internal Signals and Connections . . . . . . . . . DC (charger) connector . . . . . . . . . . . . . . . . . . . . . . . . . . . Service connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM card connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTC backup battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Overvoltage Protection . . . . . . . . . . . . . . . . . . . . Battery Removal During Charging . . . . . . . . . . . . . . . . . . PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . Switched Mode Supply VSIM . . . . . . . . . . . . . . . . . . . . . . Power Up and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . Power up with a charger . . . . . . . . . . . . . . . . . . . . . . . . . . Power Up With The Power Switch (PWRONX) . . . . . . . Power Up by RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Up by IBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acting Dead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 7 8 8 8 9 10 10 10 10 11 11 12 12 13 13 15 16 16 17 18 19 19 19 20 21 21 21 22 22 22 22 23 23 24 24
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PAMS Technical Documentation Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAD2 WD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAD memory configuration . . . . . . . . . . . . . . . . . . . . . . . Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . Work Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Memory Requirements . . . . . . . . . . . . . . . . . . . . . . MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COBBA GJP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTC backup battery charging . . . . . . . . . . . . . . . . . . . . . . RF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Frequency Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . RF Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AFC function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCcompensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Parts list of RM7 (EDMS Issue 15.1) Code: 0201236 . . . . . . . .
NSM2 System Module 25 25 33 33 33 33 33 33 33 34 36 36 36 37 37 37 38 38 38 39 40 41 42 43 44 44 45 45 45 46
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NSM2 System Module
PAMS Technical Documentation
Schematic Diagrams: RM7 (at the back of the binder) Connection between RF and BB modules (Version 0391 Ed. 2) layout 0392 A1 Baseband Block Interconnections (Version 0391 Edition 2) for layout 0392 A2 Circuit Diagram of Power Supply (Version 0391 Edition 2) for layout 0392 Circuit Diagram of CPU Block (Version 0391 Edition 2) for layout 0392 Circuit Diagram of RF Block (Version 0392 Edition 4) for layout 0392 Circuit Diagram of Audio and RFI (Version 0391 Edition 2) for layout 0392 Circuit Diagram of IR Module (Version 0391 Edition 2) for layout 0392 Circuit Diagram of UIF (Version 0391 Edition 2) for layout version 0392 Layout Diagram of RM7 Top (Version 0392) . . . . . . . . . . . . . . Layout Diagram of RM7 Bottom (Version 0392) . . . . . . . . . . . Testpoints of RM7 Top (Version 0392) . . . . . . . . . . . . . . . . . . . . Testpoints of RM7 Bottom (Version 0392) . . . . . . . . . . . . . . . . A3 A4 A5 A6 A7 A8 A9 A9 A10 A10
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NSM2 System Module
PAMS Technical Documentation
Transceiver NSM2
Introduction
The NSM2 is a dual band transceiver unit designed for the GSM900 (including EGSM) and GSM1800 networks. It is both GSM900 phase 2 power class 4 transceiver (2W) and GSM1800 power class 1 (1W) transceiver. The transceiver consists of System/RF module (RM7), Display module (UX7) and assembly parts. The transceiver has a full graphic display and the user interface is based on a Jack style UI with two soft keys. A back mounted antenna is used, there is no connection to an external antenna. The transceiver has a low leakage tolerant earpiece and an omnidirectional microphone located to a slide, providing an excellent audio quality. The transceiver supports a full rate, an enhanced full rate and a half rate speech decoding. An integrated IR link provides a connection between two NSM2 transceivers or a transceiver and a PC (internal data), or a transceiver and a printer. The small SIM ( Subscriber Identity Module ) card is located below the back cover of the phone.
Operation Modes
There are five different operation modes: power off mode idle mode active mode charge mode local mode In the power off mode only the circuits needed for power up are supplied. In the idle mode circuits are powered down and only sleep clock is running. In the active mode all the circuits are supplied with power although some parts might be in the idle state part of the time. The charge mode is effective in parallel with all previous modes. The charge mode itself consists of two different states, i.e. the fast charge and the maintenance mode. The local mode is used for alignment and testing.
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NSM2 System Module
Interconnection Diagram
Keyboard module
LCD module
14 6 SIM Radio Module 2 Antenna 2 RM7
9 4 Battery
2+2 Charger
3
2
4
Slide (mic.)
IR Link
Earpiece
HF/HS
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NSM2 System Module
PAMS Technical Documentation
System Module
Baseband Module
The baseband architecture supports a power saving function called "sleep mode". This sleep mode shuts off the VCTCXO, which is used as system clock source for both RF and baseband. During the sleep mode the system runs from a 32 kHz crystal. The phone is waken up by a timer running from this 32 kHz clock supply. The sleeping time is determined by some network parameters. The sleep mode is entered when both the MCU and the DSP are in standby mode and the normal VCTCXO clock has been switched off. The battery charging is controlled by a PWM signal from the CCONT. The PWM duty cycle is determined by a charging software and is fed to the CHAPS charging switch. Standard chargers (two wires) provide coarse supply power, which is switched by the CHAPS for suitable charging voltage and current. Advanced chargers (three wires) are equipped with a control input. Three wire chargers are treated like two wire ones.
Block Diagram
TX/RX SIGNALS RF SUPPLIES PA SUPPLY 13MHz SYSTEM CLOCK CLK
COBBA SUPPLY
COBBA
CCONT
SIM
BB SUPPLY UI
32kHz CLK SLEEP CLOCK
MAD + IR MEMORIES
VBAT
BATTERY CHAPS
BASEBAND
EXT. AUDIO
HSconnector
Charger connector
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PAMS Technical Documentation
NSM2 System Module
Technical Summary
The baseband module consists four ASICs; CHAPS, CCONT, COBBA GJP and MAD2WD1, which take care of the baseband functions of the engine. The baseband is running from a 2.8V power rail, which is supplied by a power controlling ASIC CCONT. In the CCONT there are 6 individually controlled regulator outputs for RFsection and two outputs for the baseband. In addition there is one +5V power supply output (V5V). The CCONT contains also a SIM interface, which supports both 3V and 5V SIMcards. A real time clock function is integrated into the CCONT, which utilizes the same 32kHz clock supply as the sleep clock. A backup power supply is provided for the RTC, which keeps the real time clock running when the main battery is removed. The backup power supply is a rechargable battery. The backup time with the battery is ten minutes minimum. The interface between the baseband and the RF section is mainly handled by a COBBA ASIC. COBBA provides A/D and D/A conversion of the inphase and quadrature receive and transmit signal paths and also A/D and D/A conversions of received and transmitted audio signals to and from the user interface. The COBBA supplies the analog TXC and AFC signals to RF section according to the MAD DSP digital control. Data transmission between the COBBA and the MAD is implemented using serial bus for high speed signalling and for PCM coded audio signals. Digital speech processing is handled by the MAD ASIC. COBBA is a dual voltage circuit, the digital parts are running from the baseband supply VBB and the analog parts are running from the analog supply VCOBBA. The baseband supports both internal and external microphone inputs and speaker outputs. Input and output signal source selection and gain control is done by the COBBA according to control messages from the MAD. Keypad tones, DTMF, and other audio tones are generated and encoded by the MAD and transmitted to the COBBA for decoding. A buzzer and an external vibra alert control signals are generated by the MAD with separate PWM outputs. EMC shieding is implemented using a metallized plastic frame. On the other side the engine is shielded with PCB grounding. Heat generated by the circuitry will be conducted out via the PCB ground planes.
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NSM2 System Module
PAMS Technical Documentation
External and Internal Signals and Connections
This section describes the external electrical connection and interface levels on the baseband. The electrical interface specifications are collected into tables that covers a connector or a defined interface. DC (charger) connector DC (charger) connector is physically integrated in the same component with the accessory interface connector. DC connector has both jack and contact pads for desk stand. Service connector
Name MBUS Parameter Serial clock from the Prommer Serial data from the Prommer Data acknowledge to the Prommer GND Min 0 2.0 0 2.0 0 2.0 0 Typ logic low logic low logic low logic high logic low logic high Max 0.8 2.85 0.8 2.85 0.5 2.85 0 V V V Unit V Remark Prommer detection and Serial Clock for synchronous communication Receive Data from Prommer to Baseband Transmit Data from Baseband to Prommer Ground
FBUS_RX
FBUS_TX
GND
The service connector is used as a flash programming interface for updating (i.e. reprogramming) the flash program memory and an electrical access for services to the engine. When the flash prommer is connected to the phone supply power is provided through the battery contacts and the phone is powered up with a pulse given to the BTEMP line. Battery connector The BSI contact on the battery connector is used to detect when the battery is to be removed to be able to shut down the operations of the SIM card before the power is lost if the battery is removed with power on. The BSI contact disconnects earlier than the supply power contacts to give enough time for the SIM and LCD shut down.
Name VBATT BSI Min 3.0 0 Typ 3.9 Max 4.2 2.85 Unit V V Notes Battery voltage Battery size indication Phone has 100kohm pull up resistor. SIM Card removal detection (Treshold is 2.4V@VBB=2.8V) 67 68 22 69 kohm kohm Battery indication resistor (BLB2) Battery indication resistor (service battery)
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PAMS Technical Documentation
Name BTEMP Min 0 Typ Max 1.4 Unit V Notes
NSM2 System Module
Battery temperature indication Phone has a 100k (+5%) pullup resistor, Battery package has a NTC pulldown resistor: 47k+5%@+25C , B=4050+3% Phone power up by battery (input) Power up pulse width Battery power up by phone (output) Power up pulse width Local mode initialization (in production) Battery ground
2.1 5 1.9 90 0 BGND 0 100 10
3 20 2.85 200 1 0
V ms V ms kohm V
SIM card connector The SIM card connector is located on the engine board beside the battery pack.
Pin 4 3, 5 6 Name GND VSIM DATA Parameter GND 5V SIM Card 3V SIM Card 5V Vin/Vout 3V Vin/Vout 2 SIMRST 5V SIM Card 3V SIM Card 1 SIMCLK Frequency Trise/Tfall Min 0 4.8 2.8 4.0 0 2.8 0 4.0 2.8 5.0 3.0 "1" "0" "1" "0" "1" "1" 3.25 25 Typ Max 0 5.2 3.2 VSIM 0.5 VSIM 0.5 VSIM VSIM MHz ns SIM clock V SIM reset V SIM data Trise/Tfall max 1us Unit V V Notes Ground Supply voltage
RTC backup battery The RTC block in CCONT needs a power backup to keep the clock running when the phone battery is disconnected. The backup power is supplied from a rechargable polyacene battery that can keep the clock running ten minutes minimum. The backup battery is charged from the main battery through CHAPS.
Signal VBACK Parameter Backup battery charging from CHAPS Backup battery charging from CHAPS VBACK Backup battery supply to CCONT Backup battery supply to CCONT Min 3.02 100 2 80 Typ 3.15 200 Max 3.28 500 3.28 V uA V uA Vout@VBAT0.2V Unit Notes
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NSM2 System Module
PAMS Technical Documentation
Power Distribution
In normal operation the baseband is powered from the phone`s battery. The battery consists of one LithiumIon cell. An external charger can be used for recharging the battery and supplying power to the phone. The baseband contains parts that control power distribution to whole phone excluding those parts that use continuous battery supply. The battery feeds power directly to the CCONT and UI (buzzer and display and keyboard lights). The power management circuit CHAPS provides protection against overvoltages, charger failures and pirate chargers etc. that would otherwise cause damage to the phone.
PA SUPPLY RF SUPPLIES
VCOBBA COBBA CCONT PWRONX PWM CNTVR UI VBAT VBB VBB PURX
VSIM SIM
VBB
RTC BACKUP
MAD + MEMORIES LIM CHAPS
VBAT
BATTERY
BASEBAND
VIN CHARGER CONNECTOR
Battery charging The electrical specifications give the idle voltages produced by the acceptable chargers at the DC connector input. The absolute maximum input voltage is 30V due to the transient suppressor that is protecting the charger input. At phone end there is no difference between a plugin charger or a desktop charger. The DCjack pins and bottom connector charging pads are connected together inside the phone.
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PAMS Technical Documentation
MAD
NSM2 System Module
LIM VOUT 0R22
TRANSCEIVER
2A VCH GND 100k 1u VIN
CHARGER
CHAPS
RSENSE PWM
30V
VBAT MAD CCONTINT
ICHAR PWM_OUT VCHAR
22k
CCONT
GND
1n 10k L_GND
Startup Charging When a charger is connected, the CHAPS is supplying a startup current minimum of 130mA to the phone. The startup current provides initial charging to a phone with an empty battery. Startup circuit charges the battery until the battery voltage level is reaches 3.0V (+/ 0.1V) and the CCONT releases the PURX reset signal and program execution starts. Charging mode is changed from startup charging to PWM charging that is controlled by the MCU software. If the battery voltage reaches 3.55V (3.75V maximum) before the program has taken control over the charging, the startup current is switched off. The startup current is switched on again when the battery voltage is sunken 100mV (nominal).
Parameter VOUT Start up mode cutoff limit VOUT Start up mode hysteresis NOTE: Cout = 4.7 uF Startup regulator output current VOUT = 0V ... Vstart Symbol Vstart Vstarthys Istart Min 3.45 80 130 Typ 3.55 100 165 Max 3.75 200 200 Unit V mV mA
Battery Overvoltage Protection Output overvoltage protection is used to protect phone from damage. This function is also used to define the protection cutoff voltage for different battery types (Li or Ni). The power switch is immediately turned OFF if the voltage in VOUT rises above the selected limit VLIM1 or VLIM2.
Parameter Output voltage cutoff limit (during transmission or Li battery) Symbol VLIM LIM input LOW Min 4.4 Typ 4.6 Max 4.8 Unit V
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NSM2 System Module
PAMS Technical Documentation
The voltage limit (VLIM1 or VLIM2) is selected by logic LOW or logic HIGH on the CHAPS (N101) VLIM input pin. In NSM2 VLIM is fixed low in HW. When the switch in output overvoltage situation has once turned OFF, it stays OFF until the the battery voltage falls below VLIM and PWM = LOW is detected. The switch can be turned on again by setting PWM = HIGH.
VCH
VCH
t VOUT
VLIM
t SWITCH
ON
OFF
ON
PWM (1 Hz)
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PAMS Technical Documentation Battery Removal During Charging
NSM2 System Module
Output overvoltage protection is also needed in case the main battery is removed when charger connected or charger is connected before the battery is connected to the phone. With a charger connected, if VOUT exceeds VLIM, CHAPS turns switch OFF until the charger input has sunken below Vpor (nominal 3.0V, maximum 3.4V). MCU software will stop the charging (turn off PWM) when it detects that battery has been removed. The CHAPS remains in protection state as long as PWM stays HIGH after the output overvoltage situation has occured.
VCH Vpor (Standard Charger)
VLIM Droop depends on load & C in phone Istart off due to VCH
VOUT
t PWM "1" "0" t SWITCH ON OFF 1 2 3 4 5 6 7 t
1. Battery removed, (standard) charger connected, VOUT rises (follows charger voltage) 2. VOUT exceeds limit VLIM(X), switch is turned immediately OFF 3. VOUT falls (because no battery) , also VCH Vpor and VOUT < VLIM(X) > switch turned on again (also PWM is still HIGH) and VOUT again exceeds VLIM(X). 4. Software sets PWM = LOW > CHAPS does not enter PWM mode 5. PWM low > Startup mode, startup current flows until Vstart limit reached 6. VOUT exceeds limit Vstart, Istart is turned off 7. VCH falls below Vpor
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NSM2 System Module PWM
PAMS Technical Documentation
When a charger is used, the power switch is turned ON and OFF by the PWM input. PWM rate is 1Hz. When PWM is HIGH, the switch is ON and the output current Iout = charger current CHAPS supply current. When PWM is LOW, the switch is OFF and the output current Iout = 0. To prevent the switching transients inducing noise in audio circuitry of the phone soft switching is used. Battery Identification Different battery types are identified by a pulldown resistor inside the battery pack. The BSI line inside transceiver has a 100k pullup to VBB. The MCU can identify the battery by reading the BSI line DCvoltage level with a CCONT (N100) A/Dconverter.
Name BSI Min 0 Typ Max 2.8 Unit V Notes Battery size indication 100k pullup resistor to VBB in phone SIM Card removal detection (Treshold is 2.4V@VBB=2.8V) 67 68 22 69 kohm kohm Indication of a BLB2 battery (650 mAh LiIon) Indication resistor for a service battery
VBATT
BATTERY
BTEMP
2.8V
TRANSCEIVER
100k
BSI
Rs
10k
BSI
10n
CCONT
BGND
SIMCardDetX
MAD
The battery identification line is used also for battery removal detection. The BSI line is connected to a SIMCardDetX line of MAD2. SIMCardDetX is a threshold detector with a nominal input switching level 0.85xVcc for a rising edge and 0.55xVcc for a falling edge. The battery removal detection is used as a trigger to power down the SIM card before the power is lost. The BSI contact in the battery contact disconnects before the other contacts so that there is a delay between battery removal detection and supply power off.
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NSM2 System Module
Vcc 0.850.05 Vcc 0.550.05 Vcc
SIMCARDDETX GND SIGOUT
Battery Temperature The battery temperature is measured with a NTC inside the battery pack. The BTEMP line inside transceiver has a 100k pullup to VREF. The MCU can calculate the battery temperature by reading the BTEMP line DC voltage level with a CCONT (N100) A/Dconverter.
Pin 3 Name BTEMP Min 0 Typ Max 1.4 Unit V Notes Battery temperature indication 100k pullup resistor to VREF in phone Battery package has NTC pull down resistor: 47k +/5%@+25C , B=4050+/3% Phone power up by battery (input) Power up pulse width Battery power up by phone (output) Power up pulse width 100k pullup resistor tolerance
2.1 5 1.9 90 5 100 10
3 20 2.8 200 5
V ms V ms %
VBATT
BATTERY
BSI
TRANSCEIVER
VREF
100k
BTEMP
R NTC T
10k
BTEMP BGND
CCONT
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NSM2 System Module Supply Voltage Regulators
PAMS Technical Documentation
The heart of the power distrubution is the CCONT. It includes all the voltage regulators and feeds the power to the whole system. The baseband digital parts are powered from the VBB regulator which provides 2.8V baseband supply. The baseband regulator is active always when the phone is powered on. The VBB baseband regulator feeds MAD and memories, COBBA digital parts and the LCD driver in the UI section. There is a separate regulator for a SIM card. The regulator is selectable between 3V and 5V and controlled by the SIMPwr line from MAD to CCONT. The COBBA analog parts are powered from a dedicated 2.8V supply VCOBBA. The CCONT supplies also 5V for RF and for flash VPP. The CCONT contains a real time clock function, which is powered from a RTC backup when the main battery is disconnected. The RTC backup is rechargable polyacene battery. The battery is charged from the main battery voltage by the CHAPS when the main battery voltage is over 3.2V.
Operating mode
Power off Power on Reset Sleep
Vref Off On On On
RF REG
VCOBBA
VBB
VSIM
SIMIF
Off On/Off Off VR1 On Off
Off On On Off
Off On On On
Off On Off On
Pull down On/Off Pull down On/Off
NOTE:
COBBA regulator is off in SLEEP mode. Its output pin may be fed from VBB in SLEEP mode by setting bit RFReg(5) to '1' (default). CCONT includes also five additional 2.8V regulators providing power to the RF section. These regulators can be controlled either by the direct control signals from MAD or by the RF regulator control register in CCONT which MAD can update. Below are the listed the MAD control lines and the regulators they are controlling. TxPwr controls VTX regulator (VR5) RxPwr controls VRX regulator (VR2) SynthPwr controls all the rf regulators except VR1 VCXOPwr controls VXO regulator (VR1) In additon to the above mentioned signals MAD includes also TXP control signal which goes to HAGAR power control block. The transmitter power control TXC is led from COBBA to HAGAR.
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PAMS Technical Documentation Switched Mode Supply VSIM
NSM2 System Module
There is a switched mode supply for SIMinterface. SIM voltage is selected via serial IO. The 5V SMR can be switched on independently of the SIM voltage selection, but can't be switched off when VSIM voltage value is set to 5V. NOTE: VSIM and V5V can give together a total of 30mA. In the next figure the principle of the SMR / VSIMfunctions is shown. CCONT V5V_4 VBAT V5V_3 External
V5V_2 VSIM 5V reg V5V 5V 5/3V
Power Up and Power Down
The baseband is powered up by: 1. Pressing the power key, that generates a PWRONX interrupt signal from the power key to the CCONT, which starts the power up procedure. 2. Connecting a charger to the phone. The CCONT recognizes the charger from the VCHAR voltage and starts the power up procedure. 3. A RTC interrupt. If the real time clock is set to alarm and the phone is switched off, the RTC generates an interrupt signal, when the alarm is gone off. The RTC interrupt signal is connected to the PWRONX line to give a power on signal to the CCONT just like the power key. 4. A battery interrupt. Intelligent battery packs have a possibility to power up the phone. When the battery gives a short (10ms) voltage pulse through the BTEMP pin, the CCONT wakes up and starts the power on procedure. Power up with a charger When the charger is connected CCONT will switch on the CCONT digital voltage as soon as the battery voltage exceeds 3.0V. The reset for E Nokia Mobile Phones Ltd.
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CCONT's digital parts is released when the operating voltage is stabilized ( 50 us from switching on the voltages). Operating voltage for VCXO is also switched on. The counter in CCONT digital section will keep MAD in reset for 62 ms (PURX) to make sure that the clock provided by VCXO is stable. After this delay MAD reset is relased, and VCXO control (SLEEPX) is given to MAD. The next diagram explains the power on procedure with charger ( the picture assumes empty battery, but the situation would be the same with full battery):
SLEEPX
PURX
CCPURX Vbat VR6 VR1 VBB (2.8V) Vchar Vref 1 2 3
1: Battery voltage over 3.0==>Digital voltages to CCONT (VBB) 2: CCONT digital reset released. VCXO turned on 3: 62ms delay before PURX released
When the phone is powered up with an empty battery pack using the standard charger, the charger may not supply enough current for standard powerup procedure and the powerup must be delayed. Power Up With The Power Switch (PWRONX) When the power on switch is pressed the PWRONX signal will go low. CCONT will switch on the CCONT digital section and VCXO as was the case with the charger driven power up. If PWRONX is low when the 64 ms delay expires, PURX is released and SLEEPX control goes to MAD. If PWRONX is not low when 64 ms expires, PURX will not be released, and CCONT will go to power off ( digital section will send power off signal to analog parts)
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SLEEPX
PURX
CCPURX PWRONX VR1,VR6 VBB (2.8V) Vchar
1 2
3
1:Power switch pressed ==> Digital voltages on in CCONT (VBB) 2: CCONT digital reset released. VCXO turned on 3: 62 ms delay to see if power switch is still pressed.
Power Up by RTC RTC (internal in CCONT) can power the phone up by changing RTCPwr to logical 1. Power Up by IBI IBI can power CCONT up by giving a short pulse (10ms) through the BTEMP line. After powerup BTEMP will act as any other input channel for ADC. When the PURX reset is released, the MAD releases the system reset ExtSysResetX and the internal MCUResetX signals and starts the boot program execution from MAD bootrom if MAD GenSDIO pin is pulled low or from external memory if GenSDIO pin is pulled high. In normal operation the program execution continues from the flash program memory. If the MBUS line is pulled low during the power up the bootrom starts a flash programming sequence and waits for the prommer response through FBUS_RX line. Power Down The baseband is powered down by: 1. 2. 3. Pressing the power key, that is monitored by the MAD, which starts the power down procedure. If the battery voltage is dropped below the operation limit, either by not charging it or by removing the battery. Letting the CCONT watchdog expire, which switches off all CCONT regulators and the phone is powered down. E Nokia Mobile Phones Ltd.
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PAMS Technical Documentation Setting the real time clock to power off the phone by a timer. The RTC generates an interrupt signal, when the alarm is gone off. The RTC interrupt signal is connected to the PWRONX line to give a power off signal to the CCONT just like the power key.
The power down is controlled by the MAD. When the power key has been pressed long enough or the battery voltage is dropped below the limit the MCU initiates a power down procedure and disconnects the SIM power. Then the MCU outputs a system reset signal and resets the DSP. If there is no charger connected the MCU writes a short delay to CCONT watchdog and resets itself. After the set delay the CCONT watchdog expires, which activates the PURX and all regulators are switched off and the phone is powered down by the CCONT. If a charger is connected when the power key is pressed the phone enters into the acting dead mode.
Modes of Operation
Acting Dead If the phone is off when the charger is connected, the phone is powered on but enters a state called "acting dead". To the user the phone acts as if it was switched off. A battery charging alert is given and/or a battery charging indication on the display is shown to acknowledge the user that the battery is being charged. Active Mode In the active mode the phone is in normal operation, scanning for channels, listening to a base station, transmitting and processing information. All the CCONT regulators are operating. There are several substates in the active mode depending on if the phone is in burst reception, burst transmission, if DSP is working etc. Sleep Mode In the sleep mode all the regulators except the baseband VBB and the SIM card VSIM regulators are off. Sleep mode is activated by the MAD after MCU and DSP clocks have been switched off. The voltage regulators for the RF section are switched off and the VCXO power control, VCXOPwr is set low. In this state only the 32 kHz sleep clock oscillator in CCONT is running. The flash memory power down input is connected to the ExtSysResetX signal, and the flash is deep powered down during the sleep mode. The sleep mode is exited either by the expiration of a sleep clock counter in the MAD or by some external interrupt, generated by a charger connection, key press, headset connection etc. The MAD starts the wake up sequence and sets the VCXOPwr and ExtSysResetX control high. After VCXO settling time other regulators and clocks are enabled for active mode.
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If the battery pack is disconnect during the sleep mode, the CCONT pulls the SIM interface lines low as there is no time to wake up the MCU. Charging Charging can be performed in any operating mode.The battery type/size is indicated by a resistor inside the battery pack. The resistor value corresponds to a specific battery capacity. This capacity value is related to the battery technology as different capacity values are achieved by using different battery technology. The battery voltage, temperature, size and current are measured by the CCONT controlled by the charging software running in the MAD. The power management circuitry controls the charging current delivered from the charger to the battery. Charging is controlled with a PWM input signal, generated by the CCONT. The PWM pulse width is controlled by the MAD and sent to the CCONT through a serial data bus. The battery voltage rise is limited by turning the CHAPS switch off when the battery voltage has reached 4.2 V. Charging current is monitored by measuring the voltage drop across a 220 mohm resistor. Watchdog The Watchdog block inside CCONT contains a watchdog counter and some additional logic which are used for controlling the power on and power off procedures of CCONT. Watchdog output is disabled when WDDisX pin is tied low. The WD-counter runs during that time, though. Watchdog counter is reset internally to 32 s at power up. Normally it is reset by MAD writing a control word to the WDReg.
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Audio control
PCM serial interface The interface consists of following signals: a PCM codec master clock (PCMDClk), a frame synchronization signal to DSP (PCMSClk), a codec transmit data line (PCMTX) and a codec receive data line (PCMRX). The COBBAGJP generates the PCMDClk clock, which is supplied to DSP SIO. The COBBAGJP also generates the PCMSClk signal to DSP by dividing the PCMDClk. The PCMDClk frequency is 1.000 MHz and is generated by dividing the RFIClk 13 MHz by 13. The COBBAGJP further divides the PCMDClk by 125 to get a PCMSClk signal, 8.0 kHz.
PCMDClk PCMSClk PCMTxData PCMRxData
sign extended 15 14 13 sign extended
MSB 12 MSB
11
10
LSB 0 LSB
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Digital Control
The baseband functions are controlled by the MAD asic, which consists of a MCU, a system ASIC and a DSP. MAD2 WD1 MAD2 WD1 contains following building blocks: ARM RISC processor with both 16bit instruction set (THUMB mode) and 32bit instruction set (ARM mode) TI Lead DSP core with peripherials: API (Arm Port Interface memory) for MCUDSP communication, DSP code download, MCU interrupt handling vectors (in DSP RAM) and DSP booting. Serial port (connection to PCM) Timer DSP memory BUSC (BusController for controlling accesses from ARM to API, System Logic and MCU external memories, both 8 and 16bit memories) System Logic CTSI (Clock, Timing, Sleep and Interrupt control) MCUIF (Interface to ARM via BUSC). Contains MCU BootROM DSPIF (Interface to DSP) MFI (Interface to COBBA AD/DA Converters) CODER (Block encoding/decoding and A51&A52 ciphering) AccIF(Accessory Interface) SCU (Synthesizer Control Unit for controlling 2 separate synthesizer) UIF (Keyboard interface, serial control interface for COBBA PCM Codec, LCD Driver and CCONT) SIMI (SimCard interface with enhanched features) PUP (Parallel IO, USART and PWM control unit for vibra and buzzer) Flexpool The MAD2 operates from a 13 MHz system clock, which is generated from the 13Mhz VCXO frequency. The MAD2 supplies a 6,5 MHz or a 13 MHz internal clock for the MCU and system logic blocks and a 13 MHz clock for the DSP, where it is multiplied to 45.5 MHz DSP clock. The system clock can be stopped for a system sleep mode by disabling the VCXO supply power from the CCONT regulator output. The CCONT provides a 32 kHz sleep clock for internal use and to the MAD2, which is E Nokia Mobile Phones Ltd.
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used for the sleep mode timing. The sleep clock is active when there is a battery voltage available i.e. always when the battery is connected.
Ball Name Pin Type O Connected to/from Drive req. mA 2 Reset State 0 Note Explanation
A1
MCUGemIO 0
MCU General purpose output port Lead Ground programmable pullup PR0201 programmable pullup PR0201 pullup PR0201 programmable pullup PR0201 programmable pullup PR0201 programmable pullup PR0201 external pullup/down I/O line for keyboard column 4 I/O line for keyboard column 3 General purpose I/O port Ground I/O line for keyboard column 2 I/O line for keyboard column 1 I/O line for keyboard column 0 serial LCD driver chip select, parallel LCD driver enable Lead Power NC
C2 D2
LEADGND
Col4 I/O UIF 2 Input
D3
Col3
I/O
UIF
2
Input
H11 E4 D4
MCUGenIO1 GND Col2
I/O
2
Input, pullup Input
I/O
UIF
2
C4
Col1
I/O
UIF
2
Input
C3
Col0
I/O
UIF
2
Input
D1
LCDCSX
I/O
UIF
2
Input
E1 F12 E3
LEADVCC LoByteSelX
Row5LCDCD I/O UIF 2 Input, pullup pullup PR0201
Keyboard row5 data I/O , serial LCD driver command/data indicator, parallel LCD driver read/ write select Power I/O line for keyboard row 4, parallel LCD driver register selection control I/O line for keyboard row 3, parallel LCD driver data
N4 E2
VCC_CORE Row4 I/O UIF 2 Input, pullup
Core VCC in 3325c10 pullup PR0201
F4
Row3
I/O
UIF
2
Input, pullup
pullup PR0201
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Ball Name Pin Type I/O Connected to/from UIF Drive req. mA 2 Reset State Input, pullup Note
NSM2 System Module
Explanation
F3
Row2
pullup PR0201
I/O line for keyboard row 2, parallel LCD driver data I/O line for keyboard row 1, parallel LCD driver data I/O line for keyboard row 0, parallel LCD driver data JTAG data out Ground
F2
Row1
I/O
UIF
2
Input, pullup
pullup PR0201
F1
Row0
I/O
UIF
2
Input, pullup
pullup PR0201
L11 L5 N12
JTDO GND JTRst
O
2
Tri state Input, pulldown Input Input, pullup Input, pullup pulldown PD0201 pulldown PD0201 pullup PR0201 pullup PR0201 IO VCC in 3325c10
I
JTAG reset
M12 N13 M13 G13 L12 L13 H4 L1 N3 K4 N2 N1 M4 M3 M2 M1
JTClk JTDI JTMS VCC_IO CoEmu0 CoEmu1
I I I
JTAG Clock JTAG data in JTAG mode select Power DSP/MCU emulation port 0 DSP/MCU emulation port 1 Lead Ground ARM Ground
I/O I/O
2 2
Input, pullup Input, pullup
pullup PR0201 pullup PR0201
LEADGND ARMGND
MCUAd0 O MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY 2 0
MCU address bus ARM Power MCU address bus MCU address bus MCU address bus MCU address bus MCU address bus MCU address bus
ARMVCC
MCUAd1 MCUAd2 MCUAd3 MCUAd4 MCUAd5 MCUAd6 O O O O O O 2 2 2 2 2 2 0 0 0 0 0 0
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Ball Name Pin Type Connected to/from Drive req. mA
PAMS Technical Documentation
Reset State Note Explanation
H1 L4 L3 L2 K5 J4 K3 K2 K1 J3 J2 J1 M10 H3 H2 G4 G3 G2 K6 K9 L6 M6 N6 L7
VCC_IO MCUAd7 MCUAd8 MCUAd9 MCUAd10 GND MCUAd11 MCUAd12 MCUAd13 MCUAd14 MCUAd15 MCUAd16 VCC_CORE MCUAd17 MCUAd18 MCUAd19 MCUAd20 VCONT ExtMCUDa0 GND ExtMCUDa1 ExtMCUDa2 ExtMCUDa3 ExtMCUDa4 I/O I/O I/O I/O MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY 2 2 2 2 Output Output Output Output O O O O O I/O MCU MEMORY 2 Input MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY 2 2 2 2 0 0 0 0 O O O O O O MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY 2 2 2 2 2 2 0 0 0 0 0 0 O O O O MCU MEMORY MCU MEMORY MCU MEMORY MCU MEMORY 2 2 2 2 0 0 0 0
IO VCC in 3325c10
Power MCU address bus MCU address bus MCU address bus MCU address bus Ground MCU address bus MCU address bus MCU address bus MCU address bus MCU address bus MCU address bus
Core VCC in 3325c10
Power MCU address bus MCU address bus MCU address bus MCU address bus
MCU data bus Ground MCU data bus MCU data bus MCU data bus MCU data bus
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Ball Name Pin Type I/O I/O I/O I/O I/O I/O I/O Connected to/from MCU MEMORY MCU MEMORY MCU MEMORY Drive req. mA 2 2 2 2 2 2 2 Reset State Output Output Output Input Input Input Input MCU Data in 16bit mode MCU Data in 16bit mode MCU Data in 16bit mode MCU Data in 16bit mode Note
NSM2 System Module
Explanation
M7 N7 N8 M8 L8 K8 N9 E10 M9 L9 N10 L10 M5 G11 N5 N11 M11 J11 A1 D8 K10 K11 K12
ExtMCUDa5 ExtMCUDa6 ExtMCUDa7 MCUGenIODa0 MCUGenIODa1 MCUGenIODa2 MCUGenIODa3 GND MCUGenIODa4 MCUGenIODa5 MCUGenIODa6 MCUGenIODa7 MCURdX VCC_CORE MCUWrX ROM1SelX RAMSelX IRON MCUGenIO1 DSPXF
MCU data bus MCU data bus MCU data bus General purpose I/O port General purpose I/O port General purpose I/O port General purpose I/O port Ground
I/O I/O I/O I/O O MCU MEMORY
2 2 2 2 2
Input Input Input Input 1
MCU Data in 16bit mode MCU Data in 16bit mode MCU Data in 16bit mode MCU Data in 16bit mode
General purpose I/O port General purpose I/O port General purpose I/O port General purpose I/O port MCU Read strobe
Core VCC in 3325c10 O O O O I/O O MCU MEMORY MCU ROM MCU RAM IR Mod 2 2 2 2 2 2 1 1 1 1 Input, pullup 1 pullup PR0201
Power MCU write strobe ROM chip select RAM chip select IR control General purpose I/O port External flag Special cell Power
SCVCC
RFClk RFClkGnd I VCXO Input Input
System clock from VCTCXO System clock reference ground input SIM card detection
K13
SIMCardDetX
I
Input
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Ball Name Pin Type Connected to/from Drive req. mA
PAMS Technical Documentation
Reset State Note Explanation
J10 D9 D11 G12 C9 E12 E13 J13 C5 B6 F11
SCGND
BuzzPWM O BUZZER 2 0
Special cell Ground Buzzer PWM control LEAD Power O VIBRA 2 0 Vibra PWM control Ground I/O I/O O I/O UIF 2 2 2 4 Input, pullup Input, pullup 1 Tri State external pullup IO VCC in 3325c10 I Input Accessory TX data, Flash_TX Power NonMBUS accessory connection detector Headset detection interrupt Accessory RX data, Flash_RX Ground I/O 2 Input, pulldown Input, external pullup 1 0 Core VCC in 3325c10 O CCONT 2 1 pulldown PD1001 external pullup General purpose I/O port MBUS, Flash clock pullup PR1001 pullup PR1001 General purpose I/O port General purpose I/O port
LEADVCC
VibraPWM GND MCUGenIO3 MCUGenIO2 KBLights AccTxData VCC_IO HookDet
F10 D6 D5 G10
HeadDet AccRxData GND MCUGenIO4
I I
Input Input
B5
MBUS
I/O
2
E11 D13 B7 C10 F13 B10
VCXOPwr SynthPwr VCC_CORE GenCCONTCSX
O O
CCONT CCONT
2 2
VCXO regulator control Synthesizer regulator control Power Chip select to CCONT LEAD Ground
LEADGND
GenSDIO I/O CCONT, UIF 2 Input, external pullup/ down external pullup/down depending on how to boot
Serial data in/out
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Ball Name Pin Type O I/O Connected to/from CCONT, UIF CCONT Drive req. mA 2 2 Reset State 0 0 Note
NSM2 System Module
Explanation
A10 C11 J12 B13 B12 A13 D10 A12 B11 A11 D12 H10 C13 C12 H12
GenSClk SIMCardData GND PURX CCONTInt Clk32k VCC_IO SIMCardClk SIMCardRstX SIMCardIOC SIMCardPwr
Serial clock SIM data Ground
I I I
CCONT CCONT CCONT
Input Input Input IO VCC in 3325c10
Power Up Reset CCONT interrupt Sleep clock oscillator input Power SIM clock SIM reset SIM data in/out control SIM power control LEAD Power
O O O O
CCONT CCONT CCONT CCONT
2 2 2 2
0 0 0 0
LEADVCC
RxPwr TxPwr TestMode O O I 2 2 0 0 Input, pulldown 2 COBBA 2 0 0 IO VCC in 3325c10 I I I O COBBA COBBA COBBA COBBA COBBA COBBA COBBA COBBA Core VCC in 3325c10 4 Input Input Input 1 pulldown PD0201
(RX regulator control) (TX regulator control) Test mode select
H13 B9 K7 A9 B8 A8 C6 A6 A7 C7 D7 G1
ExtSysResetX PCMTxData VCC_IO PCMRxData PCMDClk PCMSClk COBBAClk COBBACSX COBBASD IData QData VCC_CORE
O O
System Reset Transmit data, DX Power Receive data, RX Transmit clock, CLKX Transmitframe sync, FSX COBBA clock, 13 MHz COBBA COBBA COBBA COBBA Power
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Ball Name Pin Type O O O O O O O O O Connected to/from RF RF RF CRFU RF HAGAR HAGAR HAGAR HAGAR Drive req. mA 2 2 2 2 2 2 2 2 2
PAMS Technical Documentation
Reset State 0 0 0 0 0 0 0 0 0 Note Explanation
C1 B4 A4 A5 A3 B3 B1 B2 A2
DSPGenOut3 DSPGenOut2 DSPGenOut1 DSPGenOut0 FrACtrl SynthEna SynthClk SynthData TxPA
DSP general purpose output DSP general purpose output DSP general purpose output DSP general purpose output RF front amplifier control Synthesizer data enable Synthesizer clock Synthesizer data Power amplifier control
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Memories
MAD memory configuration The MAD2WD1 used in NSM2 contains 16 kW RAM, and 80 kW ROM memory. Memory The MCU program code resides in an external flash program memory, which size is 16Mbits (1024k x 16bit). The MCU work (data) memory size is 2048 kbits (256k x 16bit). Flash and SRAM memory chips are packed in same combo memory package. The BusController (BUSC) section in the MAD decodes the chip select signals for the external memory devices and the system logic. BUSC controls internal and external bus drivers and multiplexers connected to the MCU data bus. The MCU address space is divided into access areas with separate chip select signals. BUSC supports a programmable number of wait states for each memory range. Program and Data Memory The MCU program code resides in the program memory. The program memory is 16Mbits (1024k x 16bit) Flash memory. The flash memory has a power down pin that should be kept low, during the power up phase of the flash to ensure that the device is powered up in the correct state, read only. The power down pin is utilized in the system sleep mode by connecting the ExtSysResetX to the flash power down pin to minimize the flash power consumption during the sleep. Nonvolatile data memory is implemented with program (Flash) memory. Special EEPROM emulation (EEEMmu) software is utilized. Work Memory The work memory is a static RAM of size 2096k (256k x 16). The memory contents are lost when the baseband voltage is switched off. All retainable data must be stored into the data memory when the phone is powered down. MCU Memory Requirements
Device FLASH SRAM Organization Access Time ns 1024kx16 256kx16 120 120 Wait States Used 1 1 Remarks uBGA 48 uBGA 48
MCU Memory Map MAD2 supports maximum of 4GB internal and 4MB external address space. External memories use address lines MCUAd0 to MCUAd21 and E Nokia Mobile Phones Ltd.
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8bit/16bit databus. The BUSC bus controller supports 8 and 16bit access for byte, double byte, word and double word data. Access wait states (0, 1 or 2) and used databus width can be selected separately for each memory block. Flash Programming The phone have to be connected to the flash loading adapter so that supply voltage for the phone and data transmission lines can be supplied from/to the adapter. When adapter switches supply voltage to the phone, the program execution starts from the BOOT ROM and the MCU investigates in the early startup sequence if the flash prommer is connected. This is done by checking the status of the MBUSline. Normally this line is high but when the flash prommer is connected the line is forced low by the prommer. The flash prommer serial data receive line is in receive mode waiting for an acknowledgement from the phone. The data transmit line from the baseband to the prommer is initially high. When the baseband has recognized the flash prommer, the TXline is pulled low. This acknowledgement is used to start to toggle MBUS (FCLK) line three times in order that MAD2 gets initialized. This must be happened within 15 ms after TX line is pulled low. After that the data transfer of the first two bytes from the flash prommer to the baseband on the RXline must be done within 1 ms. When MAD2 has received the secondary boot byte count information, it forces TX line high. Now, the secondary boot code must be sent to the phone within 10 ms per 16 bit word. If these timeout values are exceeded, the MCU (MAD2) starts normal code execution from flash. After this, the timing between the phone and the flash prommer is handled with dummy bites. A 5V programming voltage is supplied inside the transceiver from the battery voltage with a switch mode regulator (5V/30mA) of the CCONT. The 5V is connected to VPP pin of the flash.
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NSM2 System Module
CCONT pin (PurX) MAD pin (FCLK (MBUS)) MAD pin 109 (FRX (FRxData))
MAD pin (FTX (FTxData))
SRAM D221 (Chip Sel) FLASH D210 (Chip Sel)
CCONT pin (PurX)
MAD pin (FCLK (MBUS))
MAD pin (FRX (FRxData))
MAD pin (FTX (FTxData))
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PAMS Technical Documentation
COBBA GJP ASIC provides an interface between the baseband and the RFcircuitry. COBBA performs analogue to digital conversion of the receive signal. For transmit path COBBA performs digital to analogue conversion of the transmit amplifier power control ramp and the inphase and quadrature signals. A slow speed digital to analogue converter will provide automatic frequency control (AFC). COBBA is at any time connected to MAD asic with two interfaces, one for transferring TX and RX data between MAD and COBBA and one for transferring codec RX/TX samples. Real Time Clock Requirements for a real time clock implementation are a basic clock (hours and minutes), a calender and a timer with alarm and power on/off function and miscellaneous calls. The RTC will contain only the time base and the alarm timer but all other functions (e.g. calendar) will be implemented with the MCU software. The RTC needs a power backup to keep the clock running when the phone battery is disconnected. The backup power is supplied from a rechargable polyacene battery that can keep the clock running some ten minutes. If the backup has expired, the RTC clock restarts after the main battery is connected. The CCONT keeps MCU in reset until the 32kHz source is settled (1s max). The CCONT is an ideal place for an integrated real time clock as the asic already contains the power up/down functions and a sleep control with the 32kHz sleep clock, which is running always when the phone battery is connected. This sleep clock is used for a time source to a RTC block. RTC backup battery charging CHAPS has a current limited voltage regulator for charging a backup battery. The regulator derives its power from VOUT so that charging can take place without the need to connect a charger. The backup battery is only used to provide power to a real time clock when VOUT is not present so it is important that power to the charging circuitry is derived from VOUT and that the charging circuitry does not present a load to the backup battery when VOUT is not present. It should not be possible for charging current to flow from the backup battery into VOUT if VOUT happens to be lower than VBACK. Charging current will gradually diminish as the backup battery voltage reaches that of the regulation voltage.
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NSM2 System Module
RF Module
This RF module takes care of all RF functions of EGSM/DCS1800 dualband engine. RF circuitry is located on one side of the 8 layer tranceiver PCB. PCB area for the RF circuitry is about 15 cm2. The RF design is based on the first dualband direct conversion RFIC "Hagar". So there is no intermediate frequency and that means the number of component is much lover than before and there shall be much less interference problems than previously. EMC emissions are taken care of using metallized plactic shield, which screens the whole transceiver. Internal screening is realized with isolated partitions. At least the VCO is isolated. The baseband circuitry is located on the same side of the same board.
Maximum Ratings
Parameter Battery voltage, idle mode Regulated supply voltage Voltage reference Operating temperature range Absolute maximum battery voltage Rating 4.2 V 2.8 +/ 3% V 1.5 +/ 1.5% V 10...+55 deg. C 4.8 V
RF Characteristics
Item Receive frequency range Transmit frequency range Duplex spacing Channel spacing Number of RF channels Power class Number of power levels Values (EGSM / DCS1800) 925 ... 960 MHz / 1805 ... 1880 MHz 880 ... 915 MHz / 1710 ... 1785 MHz 45 MHz / 95 MHz 200 kHz 174 / 374 4 (EGSM900) / 1 (DCS1800) 15 / 16
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RF Frequency Plan
925960 MHz 18051880 MHz
HAGAR
Isignal Qsignal
RX
f f/2 f/2
f
f f/2 PLL f f/2
26 MHz
VCTCXO
3420 3840 MHz
880915 MHz 17101785 MHz
Isignal Qsignal
TX
DC characteristics
Regulators Transceiver has a multi function power management IC at baseband section, which contains among other functions, also 7 pcs of 2.8 V regulators. All regulators can be controlled individually with 2.8 V logic directly or through control register. In GSM direct controls are used to get fast switching, because regulators are used to enable RFfunctions. VREF_2 from CCONT IC and RXREF from COBBA IC are used as the reference voltages for HAGAR RFIC, VREF_2 (1.5V) for bias reference and RXREF (1.2V) for RX ADC's reference.
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3.9 V
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2 mA
Power Distribution Diagram
PAMS Technical Documentation
BATTERY
1.76 A
VBATT
PA
Vpc (Hagar) VXOENA SYNPWR
VR VR VR 3 4 5 vsyn_1 vsyn_2 vtx
6 mA
VR 6
VR 7
V5V
VREF
vref_2 4.7V Reg HAGAR bias ref
LNA
20 mA
VCTCXO +buff.
COBBA analog
20 mA
RX: 26 mA TX: 29 mA 7.7 mA 1.3 mA
RX: 18.5 mA TX: 31.5 mA 67 mA 1.6 mA
VCO
NSM2 System Module
HAGAR RFIC RX / TX parts PLL
TXC TXP
NSM2 System Module
PAMS Technical Documentation
RF Functional Description
Architecture contains one RFIC, dualband PA module, VCOmodule, VCTCXO module and discrete LNA stages for both receive bands.
VREF_2 1.5 V RXREF 1.2 V 13 MHz to ASIC
SERIAL CTRL BUS
BIAS
PLL
f
HAGAR
f/2
f
f/2
f
f f/2
f/2
26 MHz
f
f/2
VCXO
SHF VCO
TXC
TXP
PCN
TXIP TXIN TXQP TXQN
AFC
Q
I
Diplexer
EGSM SAW
buffer EGSM PCN ANT SW
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dual PA
PAMS Technical Documentation
NSM2 System Module
Frequency synthesizer
VCO frequency is locked with PLL into stable frequency source, which is a VCTCXOmodule ( voltage controlled temperature compensated crystal oscillator ). VCTCXO is running at 26 MHz. Temperature effect is controlled with AFC ( automatic frequency control ) voltage. VCTCXO is locked into frequency of the base station. AFC is generated by baseband with a 11 bit conventional DAC in COBBA. PLL is located in HAGAR RFIC and is controled via serial bus from COBBAIC (baseband). There are 64/65 (P/P+1) prescaler, N and Adivider, reference divider, phase detector and charge pump for the external loop filter. SHF local signal, generated by a VCOmodule ( VCO = voltage controlled oscillator ), is fed to prescaler. Prescaler is a dual modulus divider. Output of the prescaler is fed to N and Adivider, which produce the input to phase detector. Phase detector compares this signal to reference signal (200kHz), which is divided with reference divider from VCTCXO output. Output of the phase detector is connected into charge pump, which charges or discharges integrator capacitor in the loop filter depending on the phase of the measured frequency compared to reference frequency. Loop filter filters out the pulses and generates DC control voltage to VCO. Loop filter defines step response of the PLL ( settling time ) and effects to stability of the loop, that's why integrator capacitor has got a resistor for phase compensation. Other filter components are for sideband rejection. Dividers are controlled via serial bus. SDATA is for data, SCLK is serial clock for the bus and SENA1 is a latch enable, which stores new data into dividers.
R
freq. reference AFCcontrolled VCTCXO LP
f ref f_out / M PHASE DET. CHARGE PUMP Kd VCO Kvco
f_out
M
M = A(P+1) + (NA)P= = NP+A
LOsignal is generated by SHF VCO module. VCO has double frequency in DCS1800 and x 4 frequency in EGSM compared to actual RF channel frequency. LO signal is divided by two or four in HAGAR (depending on system mode). E Nokia Mobile Phones Ltd.
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NSM2 System Module
PAMS Technical Documentation
Receiver
Receiver is a direct conversion, dualband linear receiver. Received RF signal from the antenna is fed via RFantenna switch to 1st RX dualband SAW filter and discrete LNAs (low noise amplifier), separate LNA branches for EGSM900 and DCS1800. Gain selection control of LNAs comes from HAGAR IC. Gain step is activated when RFlevel in antenna is about 43 dBm. After the LNA amplified signal (with low noise level) is fed to bandpass filter (2nd RX dualband SAW filter). RX bandpass filters defines how good are the blocking characteristics against spurious signals outside receive band and the protection against spurious responses. These bandpass filtered signals are then balanced with baluns. Differential RX signal is amplified and mixed directly down to BB frequency in HAGAR. Local signal is generated with external VCO. VCO signal is divided by 2 (DCS1800) or by 4 (EGSM900). PLL and dividers are in HAGARIC. From the mixer output to ADC input RX signal is divided into I and Qsignals. Accurate phasing is generated in LO dividers. After the mixer DTOS amplifiers convert the differential signals to single ended. DTOS has two gain stages. The first one has constant gain of 12dB and 85kHz cut off frequency. The gain of second stage is controlled with control signal g10. If g10 is high (1) the gain is 6dB and if g10 is low (0) the gain of the stage is 4dB. The active channel filters in HAGAR provides selectivity for channels (3dB @ +/100 kHz typ.). Integrated base band filter is activeRCfilter with two offchip capacitors. Large RCtime constants needed in the channel select filter of direct conversion receiver are produced with large offchip capacitors because the impedance levels could not be increased due to the noise specifications. Baseband filter consists of two stages, DTOS and BIQUAD. DTOS is differential to singleended converter having 8dB or 18dB gain. BIQUAD is modified SallenKey Biquad. Integrated resistors and capacitors are tunable. These are controlled with a digital control word. The correct control words that compensate for the process variations of integrated resistors and capacitors and of tolerance of off chip capacitors are found with the calibration circuit. Next stage in the receiver chain is AGCamplifier, also integrated into HAGAR. AGC has digital gain control via serial mode bus from COBBA IC. AGCstage provides gain control range (40 dB, 10 dB steps) for the receiver and also the necessary DC compensation. One 10 dB AGC step is implemented in DTOS stages. DC compensation is made during DCN1 and DCN2 operations (controlled via serial bus). DCN1 is carried out by charging the large external capacitors in AGC stages to a voltage which cause a zero dcoffset. DCN2 set the signal offset to constant value (RXREF 1.2 V). The RXREF signal (from COBBA GJP) is used as a zero level to RX ADCs. Single ended filtered I/Qsignal is then fed to ADCs in COBBAIC. Input level for ADC is 1.4 Vpp max.
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NSM2 System Module
Transmitter
Transmitter chain consists of final frequency IQmodulator, dualband power amplifier and a power control loop. I and Qsignals are generated by baseband also in COBBAASIC. After post filtering (RCnetwork) they go into IQmodulator in HAGAR. LOsignal for modulator is generated by VCO and is divided by 2 or by 4 depending on system mode, EGSM/DCS1800. After modulator the TXsignal is amplified and buffered. There are separate outputs for both EGSM and DCS1800. HAGAR TX output level is 5 dBm minimum. Next TX signals are converted to single ended by discrete baluns. EGSM and DCS1800 branches are compined at a diplexer. In EGSM branch there is a SAW filter before diplexer to attenuate unwanted signals and wideband noise from the Hagar IC. The final amplication is realized with dualband power amplifier. It has one 50 ohm input and two 50 ohm outputs. There is also a gain control, which is controlled with a power control loop in HAGAR. PA is able to produce over 2 W (3 dBm input level) in EGSM band and over 1 W (6 dBm input level) in DCS1800 band into 50 ohm output. Gain control range is over 35 dB to get desired power levels and power ramping up and down. Harmonics generated by the nonlinear PA are filtered out with the diplexer inside the antenna switchmodule. Power control circuitry consists of discrete power detector (common for EGSM and DCS1800) and error amplifier in HAGAR. There is a directional coupler connected between PA output and antenna switch. It is a dualband type and has input and outputs for both systems. Dir. coupler takes a sample from the forward going power with certain ratio. This signal is rectified in a schottkydiode and it produces a DCsignal after filtering. This detected voltage is compared in the erroramplifier in HAGAR to TXCvoltage, which is generated by DAconverter in COBBA. TXC has got a raised cosine form (cos4 function), which reduces switching transients, when pulsing power up and down. Because dynamic range of the detector is not wide enough to control the power (actually RF output voltage) over the whole range, there is a control named TXP to work under detected levels. Burst is enabled and set to rise with TXP until the output level is high enough, that feedback loop works. Loop controls the output via the control pin in PA to the desired output level and burst has got the waveform of TXCramps. Because feedback loops could be unstable, this loop is compensated with a dominating pole. This pole decreases gain on higher frequencies to get phase margins high enough. Power control loop in HAGAR has two outputs, one for both freq. bands.
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NSM2 System Module
DIR.COUPLER
PAMS Technical Documentation
PA
RF_OUT
K cp
R1 DETECTOR
RF_IN
K PA
K
det
R2
K = R1/R2
ERROR AMPLIFIER R C DOMINATING POLE
TXC
AGC strategy
AGCamplifier is used to maintain output level of the receiver in certain range. AGC has to be set before each received burst, this is called pre monitoring. There is 50 dB accurate gain control (10 dB steps) and one larger step (~30 dB) in LNA. LNA AGC step size depends on channel with some amount. RSSI must be measured accurately on range 48...110 dBm. After 48 dBm level MS reports to base station the same reading. Production calibration is done with two RFlevels, LNA gain step is not calibrated.
AFC function
AFC is used to lock the transceivers clock to frequency of the base station. AFCvoltage is generated in COBBA with 11 bit DAconverter. There is a RCfilter in AFC control line to reduce the noise from the converter. Settling time requirement for the RCnetwork comes from signalling, how often PSW (pure sine wave) slots occur. They are repeated after 10 frames, meaning that there is PSW in every 46 ms. AFC tracks base station frequency continously, so transceiver has got a stable frequency, because changes in VCTCXOoutput don't occur so fast (temperature). Settling time requirement comes also from the start uptime allowed. When transceiver is in sleep mode and "wakes" up to receive mode, there is only about 5 ms for the AFCvoltage to settle. When the first burst
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NSM2 System Module
comes in system clock has to be settled into +/ 0.1 ppm frequency accuracy. The VCTCXOmodule requires also 5 ms to settle into fina