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System Module US8
NSE6
Block Diagram of UIF
VIBRA UISwitch Buzzer cntrl Blight cntl MICP MICN XMIC SGND XEAR EARP EARN PWR Slide detect PWR FLIP EAR Vibra cntl Headset conn. MIC
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3/A31
System Module US8
NSE6
Circuit Diagram of UIF
(Version 7.0 Edit 218) for layout version 07
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3/A32
System Module US8
NSE6
Block Diagram of Baseband
2M
16M
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3/A33
System Module US8
NSE6
Circuit Diagram of Baseband
(Version 7.0 Edit 105) for layout version 07
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3/A34
System Module US8
NSE6
Circuit Diagram of Power Supply (Version 7.0
Edit 257) for layout version 07
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3/A35
System Module US8
NSE6
Circuit Diagram of SIM Connectors (Version 7.0
Edit 71) for layout version 07
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3/A36
System Module US8
NSE6
Circuit Diagram of CPU Block (Version 7.0
Edit 208) for layout version 07
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3/A37
System Module US8
NSE6
Circuit Diagram of Audio
(Version 7.0 Edit 126) for layout version 07
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3/A38
System Module US8
NSE6
Circuit Diagram of IR Module (Version 7.0
Edit 96) for layout version 07
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3/A39
System Module US8
NSE6
RF Block Diagram
SUMMA
TQFP32 TQFP48
PAmodule
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3/A310
System Module US8
NSE6
Circuit Diagram of RF Block (Version
1.0 Edit 244) for layout version 07
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3/A311
System Module US8
NSE6
Layout Diagram of US8 Top (Version 07)
Layout Diagram of US8 Bottom (Version 07)
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3/A312
System Module US8
NSE6
Testpoints of US8 Top (Version 07)
Testpoints of US8 Bottom (Version 07)
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3/A313
System Module US8
testpoint ref J101 J104 J108 J220 J223 J225 J226 J227 J228 J235 J251 J256 J500 name FBUS_TX CCONTCSX (CCONT chip select) CHRG_CTRL V5V CCONTINT (charger, RTC interrupt) EXTSYSRESETX VCXOPWR PURX (power on reset) SLEEPCLK (32kHz clock) ROM1SELX AGND COBBADAX Control voltage for UHF VCO module G600 condition active state active state charger connected active state interrupt power on power on power up/down power on active state pcb ground active state channel 60 channel 1 channel 124 dclevel pulsed DC (0V72.8V) pulse active 0V, nonactive 2.8V pulsed DC (0V/2.8V) nominal 5.0V (min 4.8V, max 5.2V) pulse active 2.8V, nonactive 0V reset state 0V, normal state 2.8V active state 2.8V, nonactive 0V reset state 0V, normal state 2.8V pulsed DC (0V/2.8V) pulse active 0V, nonactive 2.8V 0V pulse active 0V, nonactive 2.8V 2.25 +/ 0.25 V > 0.8 V < 3.7 V typ. 2.0 2.2 V min 0.5 / max 4.0 V 2.8 V min 2.7 / max 2.85 V 95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain 95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain typ ca. 1.0 1.1 V pulsed min. 0.7 / max. 1.4 V typ. 50 mVpp balanced voltage at 13 MHz aclevel
NSE6
J504 J508 J534&J536
Control voltage for VHF VCO circuit VSYN_2 ( regulated supply for PLLS ) 13 MHz IF output to N250
J538
13 MHz output from Z620 to N620
typ. ca. 1.5 V pulsed
typ. ca 600 uVrms
J542 J554 J556 J558 J560
VHF VCO output ( 232 MHz ) TXC ( TX power control voltage ) TXP ( TX enable ) TXQP ( other half of balanced Qsignal ) TXIP ( other half of balanced Isignal )
@level 19 typ. ca. 0.6 V pulse @level 5 typ ca. 1.8 V pulse 2.8 V logic level pulse, ( max. 0.8 V "0" / min 2.0 V "1" ) 0.8 V pulsed 0.8 V pulsed
typ. 400 mVpp. > 100 mVpp required
400 mVpp 400 mVpp
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3/A314