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Compal confidential
Schematics Document Mobile Merom uFCPGA with Satna Rosa Platform
2007-07-30
REV:0.2

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3

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4

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/07/26
Title

Compal Electronics, Inc.
Cover Sheet
Rev 1.0 Sheet
E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 1 of 42

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Compal confidential
File Name : LA-4031P
ZZZ1

Spartan 1.1 (Merom +Crestline+ICH8)
Fan Control
page 4

P CB
1

Mobile Yonah/Merom uFCPGA-478 CPU Socket P
page 4,5,6

1

Thermal Sensor ADM1032AR
page 4

Clock Generator ICS9LPRS355
page 15

FSB
H_A#(3..31) 533/667/800MHz H_D#(0..63)

CRT/TV-OUT
page 16

NB Crestline
page 7,8,9,10,11,12

DDR2 -400/533/667
Dual Channel

DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
page 13,14

LVDS Conn
page 17
2

2

USB Card Reader DMI USB Conn PCI BUS PCI-E BUS LED
page 28
3

page 27

page 27

USB2.0 AC-LINK/Azalia

SB ICH8
page 18,19,20,21

Audio Conexant CX20561-12Z
page 24 SATA

MODEM AMOM CX20548

page 25

Realtek RTL8100CL
page 23

SATA HDD Connector
page 22

AMP & Audio Jack ENE P3017 page 26
3

RTC CKT.
page 19

RJ45/11 CONN
page 23

Mini-Card WLAN
page 22

PATA Master

IDE ODD Connector
page 22

LPC BUS

Power On/Off CKT.
page 28

ENE KB926
page 30

SPI

SPI ROM 25LF080A page 29

4

DC/DC Interface CKT.
page 31

Touch Pad CONN.
page 28

Int.KBD
page 30
4

Power Circuit DC/DC
Page 32,33,34,35,36,37,38

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/07/26
Title

Compal Electronics, Inc.
Block Diagram
Rev 1.0 Sheet
E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B C D

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 2 of 42

A

5

4

3

2

1

Voltage Rails
+5VS power plane +B
D

+3VS +5VALW +3VALW +1.5VS +1.8V +1.25VS +0.9V +VCCP +CPU_CORE
D

State

Symbol Note :
: means Digital Ground

S0 S1 S3 S5 S4/AC S5 S4/ Battery only S5 S4/AC & Battery don't exist
C

O O O O O

O O O O

O O O

O O

: means Analog Ground @ : means just reserve , no build [email protected] : means just reserve for debug.

X X X X

X X X

X X

X

C

External PCI Devices
DEVICE
LAN

IDSEL #
AD17

REQ/GNT #
0

PIRQ
A

B

SMBUS Control Table

B

I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)

SOURCE

INVERTER

BATT

SERIAL EEPROM

THERMAL SENSOR (CPU) ADM1032

SODIMM

CLK CHIP

MINI CARD

LCD

HEX
A0 A4 D2

ADDRESS
10100000 10100100 11010010

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_CK_CLK1 SMB_CK_DAT1 LCD_CLK LCD_DAT

KB925 KB925

X X X X

V X X X

V X X X

X V X X

X X V X

X X V X

X X V X

X X X V
A

ICH8

Crestline

A

BOM: 43152432L03(965GM) & 43152432L04(960GML) with card reader BOM: 43152432L01(965GM) & 43152432L02(960GML) without card reader
Security Classification

Compal Secret Data
2007/03/26 Deciphered Date 2006/07/26
Title Size Date:

Jump-Short:

PJP?

Compal Electronics, Inc.
Notes List
Document Number

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

LA-4031P
Wednesday, October 24, 2007
1

Rev 1.0 Sheet 3 of 42

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4

3

2

1

D

D

7

H_A#[3..16] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H_A20M# H_F ERR# H _IGNNE# H_STPCLK# H _INTR H _NMI H_SMI#

JP2A

CONTROL

7 7 7 7 7 7 7
C

H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35]

J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK#

H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

H_ADS# H_ BNR# H_BPRI# H _DEFER# H_D RDY# H_DBSY# H_BR0# H_I ERR# H_INIT# H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_T RDY# H_HIT# H_HITM#

H_ADS# 7 H_BNR# 7 H_BPRI# 7 H_DEFER# 7 H_D RDY# 7 H_DBSY# 7 H_BR0# H_INIT# 7 19 C2 R10 56_0402_5% 2 1 XDP_TDI XDP_TMS R2 R3

XDP/ITP SIGNALS

U1

THERMAL
PROCHOT# THERMDA THERMDC THERMTRIP# D21 A24 B25 C7

H_PROCHOT# H_THERMDA_R R14 1 H_THERMDC_R R15 1 H_THERMTRIP#

R13 2 1 68_0402_5%

1
H_THERMDA C4

VDD D+ DTHERM#

SCLK SDATA ALERT# GND

8 7 6 5

SMB_EC_CK2 SMB_EC_DA2

1

7 19 19 19 19 19 19 19

H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#

A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]

2200P_0402_50V7K H_THERMTRIP# 7,19 +3VS R16

L_THERM#

4

1

2 0_0402_5% 2 0_0402_5%

H_THERMDA H_THERMDC

1

2

H_THERMDC

3

2

H CLK
BCLK[0] BCLK[1] A22 A21

10K_0402_5% CLK_CPU_BCLK CLK_CPU_BCLK# CLK_CPU_BCLK 15 CLK_CPU_BCLK# 15

Address:100_1100

B

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
RESERVED

30 SMB_EC_DA2 30 SMB_EC_CK2

SMB_EC_DA2 SMB_EC_CK2
B

For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm.

PWM Fan Control circuit
+3VS R405 1 0_0402_5% 2

+5VS

SP02000D000 S W-CONN ACES 85204-02001 2P P1.25 ACES_85204-02001_2P

Merom Ball-out Rev 1a [email protected] +VCCP SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3

2

1

1

2

R17 @ 56_0402_5%

1

ADDR GROUP 0 ADDR GROUP 1

+VCCP

1 1

2 2

15_0402_5% 39_0402_1%

+VCCP

XDP_TRST# XDP_TCK

R7 R8

1 1

2 2

560_0402_5% 27_0402_5%

H_LOCK# 7 H_RESET# 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7 H_HIT# 7 H_HITM# 7

1

0.1U_0402_16V4Z 2

RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#

C

Thermal Sensor ADM1032ARMZ
+3VS XDP_TCK XDP_TDI XDP_TMS XDP_TRST# DBRESET# 1 @ R413 2 0_0402_5% R414 1 2 0_0402_5% C3 0.1U_0402_16V4Z XDP_DBRESET# XDP_DBRESET# 20 H_PROCHOT# 37 +VCCP

2

+3VS

1
R426 10K_0402_5% @

2

ICH

1

2

ADM1032ARMZ-2REEL_MSOP8

R427 10K_0402_5% @

JP3 D1 RB751V_SOD323

1

C5 4.7U_0805_10V4Z

1

C6 0.1U_0402_16V4Z

2

2

1 2 3 4

1 2 G1 G2

@ R416 10K_0402_5%

+3VS

ACES_85204-02001 [email protected] F AN

2 2

1 2 5 6

2

5

D Q1 G

1
@ D26 RLZ5.1B_LL34

@ U2

H_PROCHOT#

A

3

TC7SH00FU_SSOP5

4

3 1 OCP# @ Q2 MMBT3904_SOT23
C

30 OCP# 20 L_THERM# @ R415 0_0402_5% 1 2 THERM#

FAN_PWM THERM#

INB INA

P

B E

1 2

O G

4

3

2

S

SI3456BDV-T1-E3_TSOP6

A

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
Merom(1/3)-AGTL+/XDP
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 4 of 42

5

4

3

2

1

+VCC_CORE 7 H_D#[0..15] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H _DINV#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H _DINV#1 JP2B H_D#[32..47] 7 JP2C H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H _DINV#2 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H _DINV#3 COMP0 COMP1 COMP2 COMP3 R22 54.9_0402_1% 2 1 R23 27.4_0402_1% 2 1 R24 54.9_0402_1% 2 1 R25 27.4_0402_1% 2 1 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# H_DPRSTP# 7,19,37 H_DPSLP# 19 H_DPWR# 7 H_PWRGOOD 19 H_CPUSLP# 7 H_PSI# 37

+VCC_CORE

D

7 7 7 7

H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31]

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 B22 B23 C21

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL[0] BSEL[1] BSEL[2]

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3]

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6

H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 H_D#[48..63] 7

C

7 7 7 R20 R21 C8

H_DSTBN#1 H_DSTBP#1 H_DINV#1

H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7

1 1 1 2

V_CPU_GTLREF TEST1 2 @ 1K_0402_5% TEST2 2 @ 1K_0402_5% TEST3 T1 TEST4 @ 0.1U_0402_16V4Z TEST5 T2 TEST6 T3 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

MISC

Merom Ball-out Rev 1a [email protected]

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs CPU_BSEL 166
B

CPU_BSEL2 0 0

CPU_BSEL1 1

CPU_BSEL0 1 0

200

1

Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
.

AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
VCCSENSE VSSSENSE

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

37 37 37 37 37 37 37

1
C9

10U_0805_6.3V6M C10

1

2

2

VCCSENSE 37 VSSSENSE 37

Near pin B26
B

Merom Ball-out Rev 1a [email protected]

+VCCP

Length match within 25 mils. The trace width/space/other is 20/7/25.

1

R27 1K_0402_1% V_CPU_GTLREF

2

+VCC_CORE R28 100_0402_1% 2

1

1
R29 2K_0402_1%

VCCSENSE

R30 100_0402_1% 1 2

VSSSENSE

Close to CPU pin AD26 within 500mils.
A

2

Close to CPU pin within 500mils.
A

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
Merom(2/3)-AGTL+/PWR
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 5 of 42

0.01U_0402_16V7K

15 15 15

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

DATA GRP 3

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02]

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26
R18 2 2 R19 0_0402_5% 1 1 0_0402_5%

DATA GRP 2

DATA GRP 0

D

DATA GRP 1

+VCCP

C

1
+ C7 220U_6.3V_M

2

+1.5VS

5

4

3

2

1

+VCC_CORE

1
Place these capacitors on L8 (North side,Secondary Layer)
D

C11 10U_0805_6.3V6M

1

C12 10U_0805_6.3V6M

1

C13 10U_0805_6.3V6M

1

C14 10U_0805_6.3V6M

1

C15 10U_0805_6.3V6M

1

C16 10U_0805_6.3V6M

1

C17 10U_0805_6.3V6M

1

C18 10U_0805_6.3V6M
D

2
JP2D

2

2

2

2

2

2

2

C

B

A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3

VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

+VCC_CORE

1
Place these capacitors on L8 (North side,Secondary Layer)

C19 10U_0805_6.3V6M

1

C20 10U_0805_6.3V6M

1

C21 10U_0805_6.3V6M

1

C22 10U_0805_6.3V6M

1

C23 10U_0805_6.3V6M

1

C24 10U_0805_6.3V6M

1

C25 10U_0805_6.3V6M

1

C26 10U_0805_6.3V6M

2

2

2

2

2

2

2

2

+VCC_CORE

1
Place these capacitors on L8 (Sorth side,Secondary Layer)

C27 10U_0805_6.3V6M

1

C28 10U_0805_6.3V6M

1

C29 10U_0805_6.3V6M

1

C30 10U_0805_6.3V6M

1

C31 10U_0805_6.3V6M

1

C32 10U_0805_6.3V6M

1

C33 10U_0805_6.3V6M

1

C34 10U_0805_6.3V6M

2

2

2

2

2

2

2

2

+VCC_CORE

1
Place these capacitors on L8 (Sorth side,Secondary Layer)

C35 10U_0805_6.3V6M

1

C36 10U_0805_6.3V6M

1

C37 10U_0805_6.3V6M

1

C38 10U_0805_6.3V6M

1

C39 10U_0805_6.3V6M

1

C40 10U_0805_6.3V6M

1

C41 10U_0805_6.3V6M

1

C42 10U_0805_6.3V6M
C

2

2

2

2

2

2

2

2

Mid Frequence Decoupling

Near CPU CORE regulator

ESR <= 1.5m ohm Capacitor > 1980uF

+VCC_CORE 220U_D2_2V_Y_LESR9M 1000U 2.5V M H80 LESR8M
B

1
C45 + 220U_D2_2V_Y_LESR9M C46

1
+

1
C47 + C48

1
+ C49

1
+

2

2

2

2

2

220U_D2_2V_Y_LESR9M

220U_D2_2V_Y_LESR9M

@

Place these inside socket cavity on L8 (North side Secondary)
+VCCP

Merom Ball-out Rev 1a [email protected] .

1

C50 0.1U_0402_16V4Z

1

C51 0.1U_0402_16V4Z

1

C52 0.1U_0402_16V4Z

1

C53 0.1U_0402_16V4Z

1

C54 0.1U_0402_16V4Z

1

C55 0.1U_0402_16V4Z

2

2

2

2

2

2

A

A

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
Merom(3/3)-GND&Bypass
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 6 of 42

5

4

3

2

1

5

H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SW NG H_RCOMP H_SCOMP H_SCOMP# 4 5 H_RESET# H_CPUSLP# H_RESET# H_CPUSLP#

U3A

H_A#[3..35] 4

U3B

D

C

+VCCP

DMI

E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B3 C2 W1 W2 B6 E5

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP H_SCOMP H_SCOMP# H_CPURST# H_CPUSLP#

DDR

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_ADSTB#0 H_ADSTB#1 H_ BNR# H_BPRI# H_BR0# H _DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_D RDY# H_HIT# H_HITM# H_LOCK# H_T RDY# H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 15 CLK_MCH_BCLK# 15 H_DPWR# 5 H_D RDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4

For Crestline: 20ohm For Calero: 80.6ohm
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1 AV29 BB23 BA25 AV23 AW30 BA23 AW25 AW23 BE29 AY32 BD39 BG37 BG20 BK16 BG16 BE13 BH18 BJ15 BJ14 BE16 BL15 BK14 BK31 BL31 AR49 AW4
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT0 M_ODT1 M_ODT2 M_ODT3 SMRCOMP SMRCOMP# SMRCOMP_VOH SMRCOMP_VOL M_CLK_DDR0 13 M_CLK_DDR1 13 M_CLK_DDR2 14 M_CLK_DDR3 14 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 13 13 14 14 13 13 14 14

2.2U_0805_16V4Z C56

+1.8V

1

2
C57

2

R31 1K_0402_1%

1

1

SMRCOMP_VOH

P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

0.01U_0402_16V7K

RSVD

DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB

2

D

1
R32 3.01K_0402_1% NA lead free SMRCOMP_VOL 0.01U_0402_16V7K 2.2U_0805_16V4Z

1
C58 C59

1

R33 1K_0402_1%

2

2

13 DDR_A_MA14 14 DDR_B_MA14 +3VS R36 PM_EXTTS#0

2

1

10K_0402_5% R37 PM_EXTTS#1

CLK

2

1

10K_0402_5% R38 CLKREQ#_B

H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34

RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

MUXING

DDR_CS0_DIMMA# 13 DDR_CS1_DIMMA# 13 DDR_CS2_DIMMB# 14 DDR_CS3_DIMMB# 14 M_ODT0 M_ODT1 M_ODT2 M_ODT3 R34 R35 13 13 14 14

1

2

+1.8V 30_0402_1% 1 1 30_0402_1%

2 2

2

0927_Change from 20 ohm to 30 ohm.
V_DDR_MCH_REF

HOST

DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#

B42 C42 H48 H47 K44 K45

CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_MCH_DREFCLK 15 CLK_MCH_DREFCLK# 15 MCH_SSCDREFCLK 15 MCH_SSCDREFCLK# 15 CLK_MCH_3GPLL 15 CLK_MCH_3GPLL# 15
C

2 <>

1

10K_0402_5%

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 C FG5 C FG6 C FG7 C FG8 C FG9 CFG10 CFG11 CFG12 CFG13 CFG16 CFG18 CFG19 CFG20

AN47 AJ38 AN42 AN46 AM47 AJ39 AN41 AN45 AJ46 AJ41 AM40 AM44 AJ47 AJ42 AM39 AM43

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 20 DMI_TXN1 20 DMI_TXN2 20 DMI_TXN3 20 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 20 20 20 20 20 20 20 20 20 20 20 20

R39 54.9_0402_1% 2 1

R40 54.9_0402_1% 2 1

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2

K5 L2 AD13 AE13 M7 K3 AD2 AH11 L7 K2 AC2 AJ10 M14 E13 A11 H13 B12 E12 D7 D8

H _DINV#0 H _DINV#1 H _DINV#2 H _DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2

H_DINV#0 5 H_DINV#1 5 H_DINV#2 5 H_DINV#3 5 H_DSTBN#0 5 H_DSTBN#1 5 H_DSTBN#2 5 H_DSTBN#3 5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 4 4 4 4 4 4 4 4 5 5 5 5

15 MCH_CLKSEL0 15 MCH_CLKSEL1 15 MCH_CLKSEL2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T44 T14 T15

GRAPHICS VID

P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

CFG

B

H_ VREF

B9 A9

H_AVREF H_DVREF
CRESTLINE_1p0

layout note: Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20

MISC

1

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

+1.8V

+VCCP +VCCP

R43 1K_0402_1%

221_0603_1%

1K_0402_1%

C61 0.1U_0402_16V4Z

13,14,35 V_DDR_MCH_REF

1

1

V_DDR_MCH_REF

BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
CRESTLINE_1p0

ME

CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF

AM49 AK50 AT43 AN49 AM50

CL_CLK0 CL_DATA0 M_PWROK CL_RST# CL_VREF

1

20 PM_BMBUSY# 5,19,37 H_DPRSTP# 13 PM_EXTTS#0 14 PM_EXTTS#1 20,30 PM_PWROK 18,22 PLT_RST# 4,19 H_THERMTRIP# 20,37 DPRSLPVR

PM_BMBUSY# G41 H_DPRSTP# L39 PM_EXTTS#0 L36 PM_EXTTS#1 J36 PM_PWROK AW49 PLT_RST# AV20 H_THERMTRIP# N20 DPRSLPVR G36

PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN

E35 A39 C38 B39 E36

T16 T17 T18 T19 T20 +1.25VM_AXD

B

CL_VREF

0.1U_0402_16V4Z 1 C60

1
R42 392_0402_1%

SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2

H35 K36 G39 G40 A37 R32 1
R47

CLKREQ#_B MCH_IC H_SYNC#

CLKREQ#_B 15 MCH_ICH_SYNC# 20

1

2

R44

R45

1

R46 1K_0402_1%

1

R48 0_0402_5%
A

2

2

2

1
C62

1

2

2

2

2

0.1U_0402_16V4Z C63

R50 24.9_0402_1% 2 1

0925_Stuff R43 and R46.

1

2K_0402_1%

1

100_0402_1%

R49

R51

2

A

0.1U_0402_16V4Z H_ VREF

2

H_RCOMP

2

20K_0402_5%

H_SW NG

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
CRESTLINE(1/6)-AGTL+/DMI/DDR2
Rev 1.0 Sheet
1

within 100 mils from NB
5

Near B3 pin
4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 7 of 42

2

2

2

PM NC

CL_CLK0 20 CL_DATA0 20 M_PWROK 20,30 CL_RST# 20

R41 1K_0402_1%

5

4

3

2

1

D

D

13 DDR_A_D[0..63] D DR_A_D0 D DR_A_D1 D DR_A_D2 D DR_A_D3 D DR_A_D4 D DR_A_D5 D DR_A_D6 D DR_A_D7 D DR_A_D8 D DR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U 3D

14 DDR_B_D[0..63]

U3E D DR_B_D0 D DR_B_D1 D DR_B_D2 D DR_B_D3 D DR_B_D4 D DR_B_D5 D DR_B_D6 D DR_B_D7 D DR_B_D8 D DR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

C

B

AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
CRESTLINE_1p0

SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

BB19 BK19 BF29 BL17 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BE18 AY20 BA19

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_CAS# DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_RAS# SA_RCVEN# DDR_A_WE#

DDR_A_BS0 13 DDR_A_BS1 13 DDR_A_BS2 13 DDR_A_CAS# 13 DDR_A_DM[0..7] 13

A

DDR_A_DQS[0..7] 13

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVEN# SA_WE#

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 13

DDR_A_RAS# 13 T22 DDR_A_WE# 13

AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
CRESTLINE_1p0

SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVEN# SB_WE#

AY17 BG18 BG36 BE17 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 AV16 AY18 BC17

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_CAS# DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_RAS# SB_RCVEN# DDR_B_WE#

DDR_B_BS0 14 DDR_B_BS1 14 DDR_B_BS2 14 DDR_B_CAS# 14 DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

MEMORY

MEMORY

B

DDR_B_DQS#[0..7] 14

C

DDR_B_MA[0..13] 14

SYSTEM

DDR

DDR

SYSTEM

DDR_B_RAS# 14 T21 DDR_B_WE# 14

B

A

A

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
CRESTLINE((2/6)-DDR2 A/B CH
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 8 of 42

5

4

3

2

1

Strap Pin Table
010 = FSB 800MHz CFG[2:0] FSB Freq select 011 = FSB 667MHz Others = Reserved
D

U 3C BKLT_CTRL 17 ENABLT +3VS ENABLT R53 1 R54 1 LCD_CLK LCD_DATA ENAVDD

CFG5 (DMI select)
PEGCOMP R52 24.9_0402_1% 1 2 +VCCP

0 = DMI x 2 1 = DMI x 4 Reserved 0 = Reserved 1 = Mobile CPU

D

2 10K_0402_5% 2 10K_0402_5%

For Crestline:2.4kohm For Calero: 1.5Kohm

17 LCD_CLK 17 LCD_DATA 17 ENAVDD

J40 H39 E39 E40 C37 D35 K40 L41 L43 N41 N40 D46 C45 D44 E42 G51 E51 F49 G50 E50 F48 G44 B47 B45 E44 A47 A45

*

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2

PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

N43 M43 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44 M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

CFG6 CFG7 (CPU Strap)

PEGCOMP trace width and spacing is 20/25 mils.

2 R55

1 2.4K_0402_1%
LVDSACLVDSAC+ LVDSBCLVDSBC+ LVDSA0LVDSA1LVDSA2LVDSA0+ LVDSA1+ LVDSA2+ LVDSB0LVDSB1LVDSB2LVDSB0+ LVDSB1+ LVDSB2+

* * *

CFG8 (Low power PCIE) CFG9 (PCIE Graphics Lane Reversal) CFG[11:10] CFG[13:12] (XOR/ALLZ)

0 = Normal mode 1 = Low Power mode 0 = Reverse Lane 1 = Normal Operation Reserved 00 01 10 11 = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation (Default)

17 17 17 17 17 17 17

LVDSACLVDSAC+ LVDSBCLVDSBC+ LVDSA0LVDSA1LVDSA2-

17 17 17 17 17 17 17 17 17

LVDSA0+ LVDSA1+ LVDSA2+ LVDSB0LVDSB1LVDSB2LVDSB0+ LVDSB1+ LVDSB2+

GRAPHICS

LVDS

*
C

C

CFG[15:14] CFG16 (FSB Dynamic ODT)

Reserved 0 = Disabled 1 = Enabled

PCI-EXPRESS

* *

CFG[18:17] SDVO_CTRLDATA

Reserved 0 = No SDVO Device Present 1 = SDVO Device Present 0 = Normal Operation (Lane number in Order) 1 = Reverse Lane

16 16 16

TV_COMPS TV_LUMA TV_CRMA

TV_COMPS TV_LUMA TV_CRMA

E27 G27 K27 F27 J27 L27

TVA_DAC TVB_DAC TVC_DAC TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 TV_DCONSEL_1

TV

+3VS

R56

2.2K_0402_5% 1 2

M35 P33

CFG19 (DMI Lane Reversal)

* *

CFG20 (PCIE/SDVO concurrent)

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

16 16
B

CRT_B CRT_G CRT_R

CRT_B CRT_G CRT_R

16

H32 G32 K29 J29 F29 E29 K33 G35 F33 C32 E33 1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CFG[17:3] have internal pull up CFG[19:18] have internal pull down
B

VGA

16 16 16 16

3VDDCCL 3VDDCDA CRT_HSYNC CRT_VSYNC

3VD DCCL 3VDD CDA CRT_HSYNC CRT _VSYNC 1.3K_0402_1%

R57

For Crestline:1.3kohm For Calero: 255ohm

A

2

CRESTLINE_1p0

A

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
CRESTLINE((3/6)-VGA/LVDS/TV
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 9 of 42

5

4

3

2

1

+3VS +3VS_DAC_BG +3VS BLM18PG181SN1D_0603 2 1 R59 0.1U_0402_16V4Z R58

VCCSYNC

10mA
0.1U_0402_16V4Z

2 1 0_0603_5% 1
C64

+

0925_Change C439 from 0.47uF to 4.7uF.
D

5mA
+3VS_DAC_BG

+3VS_DAC_CRT

+3VS BLM18PG181SN1D_0603 2 1 R62 0.1U_0402_16V4Z

A30 B32

CRT

C71 220U_6.3V_M 2

C72

VTT

C75

C76

C77

PLL

+1.8V_TXLVDS

1000P_0402_50V7K 1 C82

A41 B41

VCCA_LVDS VSSA_LVDS

A LVDS

AXD

0.1U_0402_16V4Z C85

A PEG

AXF

A SM

C65 0.022U_0402_16V7K C73 0.022U_0402_16V7K

+1.25VS_DPLLB +VCCP

1
C66

1

1
C439 4.7U_0603_6.3V6K

R60

+V1.25VS_AXF

+1.25VS

2

850mA
U3H

1

2

+1.25VS

1

2
R61 0_0603_5%

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z

2

2

2

10U_FLC-453232-100K_0.25A_10%

J32

VCCSYNC VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 VCCA_DAC_BG VSSA_DAC_BG VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

80mA
+3VS_DAC_CRT

A33 B33

80mA
+1.25VS_DPLLA +1.25VS_DPLLB +1.25VM_HPLL +1.25VM_MPLL

B49

1
C74

1

80mA
H49

50mA
AL2

2

2

150mA
AM2

10mA

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22

U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 AT23 AU28 AU24 AT29 AT25 AT30 AR29

1

1

1

1

4.7U_0805_10V4Z

C67

C68

C69

C70

1

1

2

2

2

2
D

2

+1.25VS_DMI 0.47U_0603_10V7K 4.7U_0805_10V4Z 2.2U_0805_16V4Z

+1.25VS 10U_0805_10V4Z

+1.8V_SM_CK R64 10U_0805_10V4Z

+1.8V

1

1

1

1
0.1U_0402_16V4Z C81

2
R63 0_0603_5%

1

2

0.1U_0402_16V4Z

1

1

2

2

2

1U_WIM32251R0KZF_10% 1 C80

C78

C79

1

2

2

2

2
+1.25VM_AXD

+3VS_PEG_BG +3VS R66 2 1 0_0603_5%

200mA
VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 VCC_AXD_NCTF VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI
1U_0603_10V4Z 10U_0805_10V4Z

R65

5mA
1

2 K50 K49
+1.25VS_PEGPLL 20 mils

1 2 0_0805_5% 1 1
C83 C84

+1.25VS +1.25VS_PEGPLL L1 BLM18PG121SN1D_0603 2 1 0.1U_0402_16V4Z 10U_0805_10V4Z +1.25VS

VCCA_PEG_BG VSSA_PEG_BG VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2 VCCD_CRT VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS_1 VCCD_LVDS_2

+1.5VS_TVDAC R67 1 2 0_0805_5%

+1.5VS 0.1U_0402_16V4Z

2

2

C89 0.022U_0402_16V7K

2

U51 AW18 AV19 AU19 AU18 AU17 AT22 AT21 AT19 AT18 AT17 AR17 AR16 BC29 BB29

350mA
B23 B21 A21
+V1.25VS_AXF

1

1

1
C88

1

C86

C87

POWER

+1.25VM_A_SM +1.25VS R68 1 2 0_0805_5%

100mA
AJ50
+1.25VS_DMI

2

2

2

2

950mA
1 1 1

C

120mA

C90 + 220U_6.3V_M R71

C91

C92

C93

SM CK

1

2

10U_0805_10V4Z

2

4.7U_0805_10V4Z

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

BK24 BK23 BJ24 BJ23

C

+1.8V_SM_CK

+1.25VM_HPLL +1.25VS_DPLLA

2

+1.25VM_A_SM_CK 1U_0603_10V4Z

2 1U_0603_10V4Z
0.1U_0402_16V4Z

100mA

R69

R70

+1.25VS

2 1 0_0603_5% 1
C99

A CK

100mA
10U_0805_10V4Z 1U_0603_10V4Z

VCC_TX_LVDS VCC_HV_1 VCC_HV_2

A43 C40 B40 AD511200mA W50 W51 V49 V50 AH50250mA AH51

+1.8V_TXLVDS +3VS_HV

1

2

+1.25VS

2 1 MBK2012121YZF_0805
C97 0.1U_0402_16V4Z

10U_0805_10V4Z

10U_FLC-453232-100K_0.25A_10%

40mA
+3VS_TVDACA

100mA
0.1U_0402_16V4Z

1

1

1

1

C95

C96

40mA 40mA

HV

1

1

1

+3VS_TVDACB +3VS_TVDACC

TV

2

2

2

2

PEG

C25 B25 C27 B27 B28 A28

C98 10U_0805_10V4Z

75mA
+1.5VS_TVDAC +1.5VS_QDAC +1.25VM_HPLL +1.25VS_PEGPLL

N28 AN2

DMI

50mAM32 25mAL29 5mA

D TV/CRT

U48

VTTLF

LVDS

C100

C101

C102

1450mA
+VCC_PEG

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

1

2

2

2

2

C103

2

0.1U_0402_16V4Z

250mA 100mA 150mA
J41 H42

VCC_RXR_DMI_1 VCC_RXR_DMI_2 VTTLF1 VTTLF2 VTTLF3

+VCCP

+1.25VM_MPLL R73 +1.25VS

20mils
A7 F2 AH1
0.47U_0603_10V7K C108 0.47U_0603_10V7K C109 0.47U_0603_10V7K C110

+VCC_PEG R72 2 1 0_0805_5% C104 220U_6.3V_M 10U_0805_10V4Z

2 1 MBK2012121YZF_0805
C106 0.1U_0402_16V4Z

1
+

1

1

1

C105

+1.8V_LVDS

C107 10U_0805_10V4Z

1

1

1

2

2

2

2

+3VS_TVDACC
B

+3VS BLM18PG181SN1D_0603 2 1 R74 0.1U_0402_16V4Z

CRESTLINE_1p0

2

2

2

B

+3VS_TVDACA

C111 0.022U_0402_16V7K C115 0.022U_0402_16V7K

1
C112 C116

1

+VCCP_D

2

2

+VCCP +3VS +1.5VS_QDAC +3VS BLM18PG181SN1D_0603 2 1 R78 0.1U_0402_16V4Z R77 +1.5VS

2

R75 1 2 1 10_0402_5% CH751H-40PT_SOD323-2

D2

R76 2 1 0_0402_5%

+3VS_HV

2 1 100_0603_1%
+1.8V_TXLVDS R79

C113 0.022U_0402_16V7K

0.1U_0402_16V4Z

1
C114

1

1

1

1022_Change R64, R79 from 0 ohm to 1uH/400mA inductor.
1
+1.8V

2

2

2

2

2

1U_WIM32251R0KZF_10% C118 1000P_0402_50V7K

1

1
C117 10U_0805_10V4Z

2
+1.8V_LVDS
A

2

+3VS_TVDACB

+3VS BLM18PG181SN1D_0603 2 1 R80

A

R81

2 1 0_0603_5% 1

+1.8V

C121 0.022U_0402_16V7K

C119 10U_0805_10V4Z

0.1U_0402_16V4Z

C120 1U_0603_10V4Z

1

1
C122

1

2

2

2

2

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
CRESTLINE(4/6)-PWR
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 10 of 42

5

4

3

2

1

+VCCP U3G +VCCP

VCC_AXG=7700mA

VCC=1260mA
AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
R82 1 2 0_0603_5%

+VCCP
D

U3F

VCC=1260mA
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50

VCC CORE

VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

R30

VCC_13

1
+

1

1

1

1

POWER
3720mA
+1.8V 0.01U_0402_16V7K C133 10U_0805_10V4Z 10U_0805_10V4Z C132

2

2

2

2

2

VCC NCTF

1
C131 220U_6.3V_M +

1

1

2

2

2

2

1

C

VSS SCB

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

A3 B2 C1 BL1 BL51 A51

+VCCP

VCC_AXM=970mA

1

1

VCC AXM NCTF

2

2

B

10U_0805_10V4Z 220U_6.3V_M

1

1

1

1

1

VCC GFX

AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

VCC AXM

VCC_AXM=970mA
10U_0805_10V4Z 10U_0805_10V4Z C135

VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

+VCCP

VCC_AXG=7700mA
+VCCP 10U_0805_10V4Z 0.1U_0402_16V4Z

C138 1U_0603_10V4Z

1

1 C137 + 2

C139

1
C140

1
C141

1

2

2

2

2

CRESTLINE_1p0

VCC SM LF

2

2

2

2

2

R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

VCC GFX NCTF

POWER

AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

0.1U_0402_16V4Z

1 C123

1

C124

1

C125
D

2

2
0.22U_0603_10V7K

2
4.7U_0805_10V4Z

0.22U_0402_10V4Z C127

0.22U_0603_10V7K C128

0.1U_0402_16V4Z C129

VSS NCTF

VCC SM

C126 220U_6.3V_M

10U_0805_10V4Z

C130 C136

C134

C

B

C142 0.22U_0402_10V4Z

C143 0.22U_0402_10V4Z

C144 0.1U_0402_16V4Z

C145 0.1U_0402_16V4Z

C146 0.1U_0402_16V4Z

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

AW45VCCSM_LF1 BC39 VCCSM_LF2 BE39 VCCSM_LF3 BD17 VCCSM_LF4 BD4 VCCSM_LF5 AW8 VCCSM_LF6 AT6 VCCSM_LF7 1

C147 0.1U_0402_16V4Z

C148 0.1U_0402_16V4Z

C149 0.22U_0603_10V7K

C150 0.22U_0603_10V7K

C151 0.47U_0603_10V7K

C152 1U_0603_10V4Z

C153 1U_0603_10V4Z

1

1

1

1

1

1

2

2

2

2

2

2

2

A

A

CRESTLINE_1p0

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
CRESTLINE((5/6)-PWR/GND
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 11 of 42

5

4

3

2

1

U 3I

D

C

B

A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

U 3J

C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

D

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
C

VSS

B

CRESTLINE_1p0

CRESTLINE_1p0
A A

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
CRESTLINE((6/6)-PWR/GND
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 12 of 42

5

4

3

2

1

+1.8V 8 DDR_A_DQS#[0..7] 8 DDR_A_D[0..63] 8 DDR_A_DM[0..7] 8 DDR_A_DQS[0..7] 7,8 DDR_A_MA[0..14] D DR_A_D4 D DR_A_D1 DDR_A_DQS#0 DDR_A_DQS0 D DR_A_D2 D DR_A_D3 D DR_A_D8 DDR_A_D14 DDR_A_DQS#1 DDR_A_DQS1 D DR_A_D9 DDR_A_D15 +1.8V DDR_A_D16 DDR_A_D17 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z JP4

+1.8V V_DDR_MCH_REF 2.2U_0805_16V4Z 0.1U_0402_16V4Z V_DDR_MCH_REF 7,14,35

D

Layout Note: Place near JP34

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
0.1U_0402_16V4Z

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204

D DR_A_D6 D DR_A_D0 DDR_A_DM0 D DR_A_D5 D DR_A_D7 DDR_A_D13 DDR_A_D12 DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_D11 DDR_A_D10

1

1

2

M_CLK_DDR0 7 M_CLK_DDR#0 7

C154

C155
D

2

DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D23 DDR_A_D22 DDR_A_D28 DDR_A_D25 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D31 DDR_A_D30 DDR_CKE1_DIMMA DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13 DDR_A_BS1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# 7 M_ODT0 7 DDR_CKE1_DIMMA 7
C

1 1
C165 + C156 220U_6.3V_M

1

1

1

1

1

1

1

1

1

1

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D29 DDR_A_D24 DDR_A_DM3 DDR_A_D26 DDR_A_D27

PM_EXTTS#0 7

C157

C158

C159

C160

C161

C162

C163

2

2

2

2

2

2

2

2

@

C164

C443

C444

2

@

2

2

2

C

7 DDR_CKE0_DIMMA 8 DDR_A_BS2

DDR_CKE0_DIMMA DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1 DDR_A_D37 DDR_A_D36 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D35 DDR_A_D32 DDR_A_D40 DDR_A_D44 DDR_A_DM5 DDR_A_D41 DDR_A_D46 DDR_A_D49 DDR_A_D48

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9V

8 8

DDR_A_BS0 DDR_A_WE#

8 DDR_A_CAS# 7 DDR_CS1_DIMMA# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 7 M_ODT1

1

1

1

1

1

1

1

1

1

1

1

1

1

DDR_A_D39 DDR_A_D38 DDR_A_DM4 DDR_A_D34 DDR_A_D33 DDR_A_D45 DDR_A_D43
B

2
C166

2
C167

2
C168

2
C169

2
C170

2
C171

2
C172

2
C173

2
C174

2
C175

2
C176

2
C177

2
C178

B

DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D47 DDR_A_D42 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 M_CLK_DDR1 7 M_CLK_DDR#1 7

+0.9V RP1 DDR_A_MA3 DDR_A_MA10 RP3 DDR_A_MA8 DDR_A_MA5 RP5 RP2 56_0404_4P2R_5% 1 DDR_CKE0_DIMMA 2 DDR_A_BS2 56_0404_4P2R_5% 1 DDR_A_MA7 2 DDR_A_MA6 56_0404_4P2R_5% 1 DDR_A_MA12 2 DDR_A_MA9 56_0404_4P2R_5% 1 DDR_A_MA4 2 DDR_A_MA2

1 2 1 2

4 3

4 3

Layout Note: Place these resistor closely JP34,all trace length Max=1.5"

DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D54 DDR_A_D50 DDR_A_D61 DDR_A_D60 DDR_A_DM7 DDR_A_D59 DDR_A_D58 14,15 CLK_SMBDATA 14,15 CLK_SMBCLK +3VS 2.2U_0805_16V4Z CLK_SMBDATA CLK_SMBCLK

56_0404_4P2R_5% RP4 4 4 3 3

56_0404_4P2R_5% RP6 DDR_A_RAS# 1 4 4 DDR_CS0_DIMMA# 2 3 3 RP7 DDR_A_MA1 DDR_A_BS0 RP9 DDR_A_WE# DDR_A_CAS#
A

1 2 1 2

56_0404_4P2R_5% RP8 4 4 3 3

R83 10K_0402_5% 2 1

1
C179

C180

1

R84 10K_0402_5% 2 1

56_0404_4P2R_5% RP10 56_0404_4P2R_5% 4 4 1 DDR_A_MA0 3 3 2 DDR_A_BS1

RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5% DDR_CS1_DIMMA# 2 3 4 1 M_ODT0 M_ODT1 1 4 3 2 DDR_A_MA13 56_0404_4P2R_5% RP13 56_0404_4P2R_5% 4 1 DDR_CKE1_DIMMA 2 3 2 DDR_A_MA14 56_0402_5%

2

2

FOX_ASOA426-M4R-TR [email protected]

A

SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4 FOX_AS0A426-M4R-TR_200P

SO-DIMM A

DDR_A_MA11 R85

1

Security Classification Issued Date 2007/03/26

Compal Secret Data
Deciphered Date 2006/03/10
Title

Compal Electronics, Inc.
DDRII-SODIMM SLOT1
Rev 1.0 Sheet
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2

Size Document Number Custom LA-4031P Date: Wednesday, October 24, 2007 13 of 42

5

4

3

2

1

8 DDR_B_DQS#[0..7] 8 DDR_B_D[0..63] 8 DDR_B_DM[0..7] 8 DDR_B_DQS[0..7] 7,8 DDR_B_MA[0..14] D DR_B_D0 D DR_B_D1 DDR_B_DQS#0 DDR_B_DQS0
D

+1.8V

+1.8V

V_DDR_MCH_REF JP5 2.2U_0805_16V4Z 0.1U_0402_16V4Z

V_DDR_MCH_REF 7,13,35

Layout Note: Place near JP10

D DR_B_D2 D DR_B_D3 D DR_B_D8 D DR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11

+1.8V

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202

D DR_B_D5 D DR_B_D4 DDR_B_DM0 D DR_B_D6 D DR_B_D7 DDR_B_D12 DDR_B_D13 DDR_B_DM1 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_D14 DDR_B_D15

1
C181

1
C182

2

2

D

M_CLK_DDR3 7 M_CLK_DDR#3 7

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

1

1

1

1

1

1

DDR_B_D17 DDR_B_D20 C191 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D28 DDR_B_D25 DDR_B_DM3 DDR_B_D30 DDR_B_D31

DDR_B_D21 DDR_B_D16 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D26 DDR_B_D24 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D29 DDR_B_D27
C

C183

C184

C185

C186

C187

C188

C189

C190

PM_EXTTS#1 7

2

2

2

2

2

2

2

2

2

C

7 DDR_CKE2_DIMMB

DDR_CKE2_DIMMB DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_CKE3_DIMMB DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 DDR_B_MA13

DDR_CKE3_DIMMB 7

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

8

DDR_B_BS2

+0.9V

8 8 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

DDR_B_BS0 DDR_B_WE#

DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_CS3_DIMMB# M_ODT3 DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35

DDR_B_BS1 8 DDR_B_RAS# 8 DDR_CS2_DIMMB# 7 M_ODT2 7

8 DDR_B_CAS# 7 DDR_CS3_DIMMB#

0.1U_0402_16V4Z

1

1

1

1

1

1

1

1

1

1

1

1

1

7

M_ODT3

2
C192

2
C193

2
C194

2
C195

2
C196

2
C197

2
C198

2
C199

2
C200

2
C201

2
C202

2
C203

2
C204

DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D39 DDR_B_D38 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 M_CLK_DDR2 M_CLK_DDR#2 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 R86 M_CLK_DDR2 7 M_CLK_DDR#2 7
B

B

DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49

+0.9V RP14 1 2 RP15 56_0404_4P2R_5% DDR_B_MA9 1 DDR_B_MA12 2

DDR_B_MA1 DDR_B_MA3 DDR_B_BS0 DDR_B_MA10 DDR_B_MA0 DDR_B_BS1

Layout Note: Place these resistor closely JP10,all trace length Max=1.5"

4 3

4 3

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D51 DDR_B_D50 DDR_B_D56 DDR_B_D61 DDR_B_DM7 DDR_B_D59 DDR_B_D58 13,15 CLK_SMBDATA 13,15 CLK_SMBCLK +3VS 2.2U_0805_16V4Z CLK_SMBDATA CLK_SMBCLK 0.1U_0402_16V4Z

RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5