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Chapter 1 General System Description
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Chapter 1 General System Description
1.1. Hardware Specification............................................................. 3
1.2. Software Specification.............................................................. 17
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Chapter 1 General System Description
1.1 Hardware Specification.
A. CPU
Intel Centrino Dothan Processor
The Intel Centrino Dothan processor is manufactured on Intel's advanced 0.09 micron
process technology with copper interconnect. The processor maintains support for MMX TM
technology and Streaming SIMD instructions and full compatibility with IA-32 software. The high
performance core features architectural innovations like Micro-op Fusion and Advanced Stack
Management that reduce the number of micro-ops handled by the processor. This results in more
efficient scheduling and better performance at lower power. The on-die 32-kB Level 1 instruction
and data caches and the 2-MB Level 2 cache with Advanced Transfer Cache Architecture enable
significant performance improvement over existing mobile processors. The processor also features
a very advanced branch prediction architecture that significantly reduces the number of
mispredicted branches. The processor's Data Prefetch Logic speculatively fetches data to the L2
cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and improved
performance.
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.
The new packed double-precision floating-point instructions enhance performance for applications
that require greater range and precision, including scientific and engineering applications and
advanced 3-D geometry techniques, such as ray tracing.
The Intel Centrino Dothen processor's 400-MHz processor system bus utilizes a split-transaction,
deferred reply protocol. The 400-MHz processor system bus uses Source-Synchronous Transfer
(SST) of address and data to improve performance by transferring data four times per bus clock
(4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver
addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus.
Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2
Gbytes/second. The processor system bus uses Advanced Gunning Transceiver Logic (AGTL+)
signal technology, a variant of GTL+ signalling technology with low power enhancements.
The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic
switching between multiple voltage and frequency points instead of two points supported on
previous versions of Intel SpeedStep technology. This results in optimal performance without
compromising low power. The processor features the Auto Halt, Stop-Grant, Deep Sleep, and
Deeper Sleep low power states.
The Intel Centrino Dothan processor utilizes socketable Micro Flip-Chip Pin Grid Array
(Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package
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Chapter 1 General System Description
technology. The Micro-FCPGA package plugs into a 478-hole, surface-mount, Zero Insertion
Force (ZIF) socket, which is referred to as the mPGA478M socket.The Intel Centrino Dothan
processor at Highest Frequency Mode (HFM) core frequencies of 1.60 ,1.70, 180 ,1.90 AND 2.0
GHz.
B. Core Logic NB Intel GMCH 855GME (Montara)
The Intel 855GME chipset graphics and memory controller hub (GMCH) is also an Intel
Centrino mobile technology component. Intel ® CentrinoTM mobile technology with integrated
wireless LAN capabilities was designed specifically for wireless notebook PCs delivering
outstanding mobile performance and enabling extended battery life, and thinner, lighter designs.
The Intel 855GME GMCH components provide the processor interface, DDR SDRAM interface,
display interface, and Hub interface. The Intel 855GME also has an option for AGP external
graphics port, in addition to integrated graphics support for added board flexibility options.
Intel 855GME Chipset GMCH
The Intel 855GME GMCH is in a 732-pin Micro-FCBGA package and contains the
following functionality listed below:
AGTL+ host bus supporting 32-bit host addressing with Enhanced Intel SpeedStep
technology support.
Supports a single channel of DDR SDRAM memory
System memory supports DDR200/266/333 MHz (SSTL_2) DDR SDRAM
Display Core frequency at 133MHz, 200MHz or 250 MHz
Render Core frequency at 100/133/166/200MHz or 250 MHz
Provides supports four display ports: one progressive scan analog monitor, dual
channel LVDS interface and two DVO port.
Processor Host Interface
The Intel 855GME GMCH is optimized for the Intel DOTHAN Pentium M processor,
Key features of the front side bus (FSB) are:
Support for a 400-MHz system bus frequency.
Source synchronous double pumped address (2X)
Source synchronous quad pumped data (4X)
Front side bus interrupt delivery
Low voltage swing Vtt (1.05V)
Dynamic Power Down (DPWR#) support
Integrates AGTL+ termination resistors on all of the AGTL+ signals
Supports 32-bit host bus addressing allowing the CPU to access the entire 4 GB of the
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GMCH memory address space.
An 8-deep, In-Order queue
Support DPWR# signal
Supports one outstanding defer cycle at a time to any particular I/O interface
GMCH System Memory Interface
The GMCH system memory controller directly supports the following:
One channel of PC1600/2100/2700 SO-DIMM DDR SDRAM memory
DDR SDRAM devices with densities of 128-Mb, 256-Mb, and 512-Mb technology
Up to 1 GB (512-Mb technology) with two SO-DIMMs
The GMCH system memory interface supports a thermal throttling scheme to selectively
throttle reads and/or writes. Throttling can be triggered either by the on-die thermal sensor, or
by preset write bandwidth limits. Read throttle can also be triggered by an external input pin.
The memory controller logic supports aggressive Dynamic Row Power Down features to help
reduce power and supports Address and Control line Tri-stating when DDR SDRAM is in an
active power down or in self refresh state.
The GMCH system memory architecture is optimized to maintain open pages (up to
16-kB
page size) across multiple rows. As a result, up to 16 pages across four rows is supported. To
complement this, the GMCH will tend to keep pages open within rows, or will only close a
single bank on a page miss. The GMCH supports only four bank memory technologies.
Graphics Features
The GMCH IGD provides a highly integrated graphics accelerator delivering high
performance 2D, 3D,and video capabilities. With its interfaces to UMA using a DVMT
configuration, an analog display, a LVDS port, and two digital display ports (e.g. flat panel),
the GMCH can provide a complete graphics solution.
The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs).
The BLT engine provides the ability to copy a source block of data to a destination and
perform raster operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or
another destination. Performing these common tasks in hardware reduces CPU load, and thus
improves performance.
High bandwidth access to data is provided through the system memory interface. The
GMCH uses Tiling architecture to increase system memory efficiency and thus maximize
effective rendering bandwidth. The Intel 855GME GMCH improves 3D performance and
quality with 3D Zone rendering technology. The Intel 855GME GMCH also supports Video
Mixer rendering, and i-Cubic filtering.
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Chapter 1 General System Description
Display Features
The Intel 855GME GMCH has four display ports, one analog and three digital. With these
interfaces, the GMCH can provide support for a progressive scan analog monitor, a
dedicated dual channel LVDS LCD panel, and two DVO devices. Each port can transmit
data according to one or more protocols. The data that is sent out the display port is selected
from one of the two possible sources, Pipe A or Pipe B.
1. GMCH Analog Display Port
Intel 855GME GMCH has an integrated 350-MHz, 24-bit RAMDAC that can
directly drive a progressive scan analog monitor pixel resolution up to 1600x1200 at
85-Hz refresh and up to 2048x1536 at 75-Hz refresh. The Analog display port can be
driven by Pipe A or Pipe B.
2. GMCH Integrated LVDS Port
The Intel 855GME GMCH have an integrated dual channel LFP Transmitter
interface to support LVDS LCD panel resolutions up to UXGA The display pipe
provides panel up-scaling to fit a smaller source image onto a specific native panel size,
as well as provides planning and centering support. The LVDS port is only supported on
Pipe B. The LVDS port can only be driven by Pipe B, either independently or
simultaneously with the Analog Display port. Spread Spectrum Clocking is supported:
center and down spread support of 0.5%, 1%, and 2.5% utilizing an external SSC clock.
3. GMCH Integrated DVO Ports
The DVO B/C interface is compliant with the DVI Specification 1.0. When
combined with a DVI compliant external device (e.g. TMDS Flat Panel Transmitter,
TV-out encoder, etc.), the GMCH provides a high-speed interface to a digital or analog
display (e.g. flat panel, TV monitor, etc.). The DVO ports are connected to an external
display device. Examples of this are TV-out encoders, external DACs, LVDS
transmitters, and TMDS transmitters. Each display port has control signals that may be
used to control, configure and/or determine the capabilities of an external device.
The GMCH provides two DVO ports that are each capable of driving a 165-MHz
pixel clock at the DVO B or DVO C interface. When DVO B and DVO C are combined
into a single DVO port, then an effective pixel rate of 330 MHz can be achieved. The DVO
B/C ports can be driven by Pipe A or Pipe B. If driven on Pipe B, then the LVDS port must
be disabled.
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Chapter 1 General System Description
Intel 855GME GMCH AGP Interface
The Intel 855GME has support for a single AGP component is supported by the AGP
interface. The AGP buffers operate only in 1.5-V mode. They are not 3.3-V tolerant.
The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x Fast Writes. AGP
semantic cycles to DDR SDRAM are not snooped on the host bus. PCI semantic cycles to
DDR SDRAM are snooped on the host bus. The GMCH/MCH support PIPE# or SBA[7:0]
AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0]
mechanism must be selected during system initialization. Both upstream and downstream
addressing is limited to 32-bits for AGP and AGP/PCI transactions. The GMCH/MCH
contains a 32-deep AGP request queue. High priority accesses are supported. All accesses
from the AGP/PCI interface that fall within the Graphics Aperture address range pass
through an address translation mechanism with a fully associative 20 entry TLB. Accesses
between AGP and hub interface are limited to memory writes originating from the hub
interface destined for AGP. The AGP interface is clocked from a dedicated 66-MHz clock
(GLCKIN). The AGP-to-host/core interface is asynchronous.
The AGP interface should be powered-off or tri-stated without voltage on the interface
during ACPI S3 or APM Suspend to RAM state.
Hub Interface
A proprietary interconnect connects the GMCH to the ICH4-M. All communication
between the GMCH and the ICH4-M occurs over the Hub interface 1.5. The Hub interface
runs at 66 MHz (266-MB/s).
Address Decode Policies
Host initiated I/O cycles are positively decoded to the GMCH configuration space and
subtractively decoded to Hub interface. Host initiated system memory cycles are positively
decoded to DDR SDRAM and are again subtractively decoded to Hub interface if under 4
GB. System memory accesses from Hub interface to DDR SDRAM will be snooped on the
FSB.
GMCH Clocking
The GMCH has the following clock input/output pins:
400-MHz, spread spectrum, low voltage differential BCLK, BCLK# for front side
bus (FSB)
66-MHz, 3.3-V GCLKIN for Hub interface buffers
Six pairs of differential output clocks (SCK[5:0], SCK[5:0]#), 200/266/333 MHz, 2.5
V for system memory interface
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Chapter 1 General System Description
48-MHz, non-Spread Spectrum, 3.3-V DREFCLK for the Display Frequency
Synthesis
48-MHz or 66-MHz, Spread Spectrum, 3.3-V DREFSSCLK for the Display
Frequency Synthesis
Up to 85-MHz, 1.5-V DVOBCCLKINT for TV-Out mode
DPMS clock for S1-M
Clock Synthesizer chips are responsible for generating the system host clocks, GMCH
display clocks, Hub interface clocks, PCI clocks, SIO clocks, and FWH clocks. The host
target speed is 400 MHz. The GMCH does not require any relationship between the BCLK
Host clock and the 66-MHz clock generated for Hub interface; they are asynchronous to each
other. The Hub interface runs at a constant 66-MHz base frequency. Table 2 indicates the
frequency ratios between the various interfaces that the GMCH supports.
System Interrupts
The GMCH supports both the legacy Intel 8259 Programmable Interrupt delivery
mechanism and the Intel Pentium M processor and Intel Celeron M processor FSB interrupt
delivery mechanism. The serial APIC Interrupt mechanism is not supported.
The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub
nterface write uffers when an Interrupt Acknowledge cycle is forwarded from the system bus
to the Hub interface.
PCI MSI interrupts are generated as memory writes. The GMCH decodes upstream
memory writes to he range 0FEE0_0000h - 0FEEF_FFFFh from the Hub interface as
message based interrupts. The MCH forwards the memory writes along with the associated
write data to the system bus as an nterrupt Message transaction. Since this address does not
decode as part of main system memory, the rite cycle and the write data do not get forwarded
to system memory via the write buffer. The GMCH rovides the response and HTRDY# for
all Interrupt Message cycles including the ones originating from he GMCH. The GMCH also
supports interrupt redirection for upstream interrupt memory writes.
For message based interrupts, system write buffer coherency is maintained by relying on
strict ordering f memory writes. The GMCH ensures that all memory writes received from a
given interface prior to an nterrupt message memory write are delivered to the system bus for
snooping in the same order that they ccur on the given interface.
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C. Core Logic SB Intel ICH4 M 82801DBM
The ICH4 provides extensive I/O support. Functions and capabilities include:
PCI Local Bus Specification, Revision 2.2-compliant with support for 33-MHz PCI
operations.
PCI slots ( supports up to 6 Req/Gnt pairs)
ACPI Power Management Logic Support
Enhanced DMA Controller, Interrupt Controller, and Timer Functions
Integrated IDE controller supports Ultra ATA100/66/33
USB host interface with support for 6 USB ports; 3 UHCI host controllers; 1 EHCI
high-speed
USB 2.0 Host Controller
Integrated LAN Controller
System Management Bus (SMBus) Specification, Version 2.0 with additional support for
I2C
devices
Supports Audio Codec '97, Revision 2.3 specification (a.k.a., AC '97 Component
Specification, Revision 2.3). Link for Audio and Telephony codecs (up to 7 channels)
Low Pin Count (LPC) interface
Firmware Hub (FWH) interface support
Alert On LAN* (AOL) and Alert On LAN 2* (AOL2)
Hub Architecture
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become
significant. With AC '97, USB 2.0, and Ultra ATA/100, coupled with the existing USB, I/O
requirements could impact PCI bus performance. The chipset's hub interface architecture
ensurethat the I/O subsystem; both PCI and the integrated I/O features (IDE, AC `97, USB
etc.), receive adequate bandwidth. By placing the I/O bridge on the hub interface (instead of
PCI), the hub architecture ensures that both the I/O functions integrated into the ICH4 and
he PCI peripherals obtain the bandwidth necessary for peak performance.
PCI Interface
The ICH4 PCI interface provides a 33-MHz, Rev. 2.2 compliant implementation. All PCI
signals are 5-V tolerant, except PME#. The ICH4 integrates a PCI arbiter that supports up to
six external PCI bus masters in addition to the internal ICH4 requests.
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IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard
disks and ATAPI devices. Each IDE device can have independent timings. The IDE interface
supports PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100 Mbytes/sec.
It does not consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers
for optimal transfers.
The ICH4's IDE system contains two independent IDE signal channels. They can be
electrically isolated independently. They can be configured to the standard primary and
secondary channels (four devices). There are integrated series resistors on the data and
control lines
Low Pin Count (LPC) Interface
The ICH4 implements an LPC Interface as described in the LPC 1.0 specification.Low Pin
Count (LPC) Bridge function of the ICH4 resides in PCI Device 31:Function 0. In addition
The LPC bridge interface function, D31:F0 contains other functional units including MA,
Controllers, Timers, Power Management, System Management, GPIO, and RTC.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 03 are hardwired to 8-bit, count-by-byte
transfers, and channels 57 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.The ICH4
supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA DMA. LPC
DMA and PC/PCI DMA use the ICH4's DMA controller. The PC/PCI protocol allows
CI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PCI
EQ#/GNT# pairs.LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encodings n LAD[3:0] from the host. Single, Demand, Verify, and Increment
modes are supported on the LPC interface. Channels 03 are 8 bit channels. Channels 57
are 16 bit channels. Channel 4 is reserved as a generic bus master request.The timer/counter
block contains three counters that are equivalent in function to those found in one 82C54
programmable interval timer. These three counters are combined to provide the system
timer function, and speaker tone. The 14.31818-MHz oscillator input provides the clock
source for these three counters.
The ICH4 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
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incorporates the functionality of two 82C59 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the ICH4 supports a serial interrupt scheme.All of the registers in these modules
can be read and restored. This is required to save and restore system state after power has
been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt Controller (PIC)
described in the previous section, the ICH4 incorporates the Advanced Programmable
Interrupt Controller
(APIC).
Universal Serial Bus (USB) Controller
The ICH4 contains an Enhanced Host Controller Interface (EHCI) compliant host
controller that supports USB high-speed signaling. High-speed USB 2.0 allows data
transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The ICH4 also
contains three Universal Host Controller Interface (UHCI) controllers that support USB
full-speed and low-speed signaling.The ICH4 supports 6 USB 2.0 ports. All six ports are
high-speed, full-speed, and low-speed capable. ICH4's port-routing logic determines
whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller.
LAN Controller
The ICH4's integrated LAN Controller includes a 32-bit PCI controller that proenhanced
scatter-gather bus mastering capabilities and enables the LAN Controller to perform hig
speed data transfers over the PCI bus. Its bus master capabilities enable the component
process high-level commands and perform multiple operations; this lowers processor
utilization by off-loading communication tasks from the processor. Two large transmit and
receive FIFOs of 3 kB each help prevent data underruns and overruns while waiting for bus
accesses. This enables the integrated LAN Controller to transmit data with minimum
interframe spacing (IFS).
The LAN Controller can operate in either full duplex or half duplex mode. In full duplex
mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism.
RTC
The ICH4 contains a Motorola* MC146818A-compatible real-time clock with 256bytesof
battery-backed RAM. The real-time clock performs two key functions: keeping track of the
time of day and storing system data, even when the system is powered down. The RTC
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operates on a 32.768 KHz crystal and a separate 3-V lithium battery that provides up to seven
years of protection. The RTC also supports two lockable memory ranges. By setting bits in
the configuration space,two 8-byte ranges can be locked to read and write accesses. This
prevents unauthorized reading of passwords or other system security information.
The RTC also supports a date alarm that allows for scheduling a wake up event up to 30
days in advance, rather than just 24 hours in advance.
GPIO
Various general purpose inputs and outputs are provided for custom system design. The
number of inputs and outputs varies depending on ICH4 configuration.
Enhanced Power Management
The ICH4's power management functions include enhanced clock control, local andglobal
monitoring support for 14 individual devices, and various low-power (suspend) states (e.g.,
Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit
permits software-independent entrance to low-power states. The ICH4 contains full support
for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0.
System Management Bus (SMBus 2.0)
The ICH4 contains an SMBus Host interface that allows the processor to communicatwith
SMBus slaves. This interface is compatible with most I 2 C devices. Special I 2 C commands
are implemented.The ICH4's SMBus host controller provides a mechanism for the processor
to initiatecommunications with SMBus peripherals (slaves). Also, the ICH4 supports slave
functionality,including the Host Notify protocol. Hence, the host controller supports eight
command protocols of the SMBus interface (see System Management Bus (SMBus)
Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word,
Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
Manageability
The ICH4 integrates several functions designed to manage the system and lower the total
cost of ownership (TC0) of the system. These system management functions are designed to
report errors, diagnose the system, and recover from system lockups without the aid of an
external
microcontroller.
TCO Timer. The ICH4's integrated programmable TCO Timer is used to detect system
locks.The first expiration of the timer generates an SMI# that the system can use to
recover from a software lock. The second expiration of the timer causes a system reset to
recover from a hardware lock.
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Processor Present Indicator. The ICH4 looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the ICH4 will
reboot the system.
ECC Error Reporting. When detecting an ECC error, the host controller has the ability
to send one of several messages to the ICH4. The host controller can instruct the ICH4 to
generate either an SMI#, NMI, SERR#, or TCO interrupt.
Function Disable. The ICH4 provides the ability to disable the following functions:
AC '97 Modem, AC '97 Audio, IDE, LAN, USB, or SMBus. Once disabled, these
functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts
or power management events are generated from the disable functions.
Intruder Detect. The ICH4 provides an input signal (INTRUDER#) that can be attached
to a switch that is activated by the system case being opened. The ICH4 can be
programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal.
SMBus 2.0. The ICH4 integrates an SMBus controller that provides an interface to
manage peripherals (e.g., serial presence detection (SPD) and thermal sensors) with host
notify capabilities.
Alert On LAN*. The ICH4 supports Alert On LAN* and Alert On LAN* 2. In response
to a TCO event (intruder detect, thermal event, processor not booting) the ICH4 sends a
message over the SMBus. A LAN controller can decode this SMBus message and send a
message over the network to alert the network manager
.
AC '97 2.3 Controller
The Audio Codec '97, Revision 2.3 specification defines a digital interface that can beusto
attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or a
combination of ACs and MC. The AC '97 specification defines the interface between thsystem
logic and the audio or modem codec, known as the AC '97 Digital Link.By using an audio
codec, the AC '97 digital link allows for cost-effective, high-quality, integrated audio on Intel's
chipset-based platform. In addition, an AC '97 soft modem can be implemented with the use of
a modem codec. Several system options exist when implementing AC '97. The
ICH4-integrated digital link allows several external codecs to be connected to the ICH4. The
system designer can provide audio with an audio codec, a modem with a modem codec, or an
integrated audio/modem codec. The digital link is expanded to support three audio codecs or
two audio codecs and one modem codec.The modem implementations for different countries
must be taken into consideration, because telephone systems may vary. By using a split design,
the audio codecs can be on-board and the modem codec can be placed on a riser.
The digital link in the ICH4 supports the Audio Codec '97, Revision 2.3 specification, so it
supports three codecs with independent PCI functions for audio and modem. Microphone and
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left and right audio channels are supported for a high quality, two-speaker audio solution. Waon
Ring from Suspend also is supported with the appropriate modem codec.The ICH4 expands the
audio capability with support for up to six channels of PCM audio output (full AC3 decode).
Six-channel audio consists of Front Left, Front Right, Back Left, Back Right,Center, and
Subwoofer for a complete surround-sound effect. ICH4 has expanded support for three
audio codecs on the AC '97 digital link.
D. Clock Generator
The Main clock ICS950813 is a chip clock solution for PC Notebook design using Intel
855GME style chipsets. It provides all the necessary clocks signals for such a system.
Features:
Provides standard frequencies and additional 3%, 5% and 10% over-clocked frequencies
Supports spread spectrum modulation:
No spread, Center Spread (±0.3%, ±0.55%), or Down Spread (-0.5%, -0.75%)
Offers adjustable PCI early clock via latch inputs
Selectable 1X or 2X strength for REF via I 2 C interface
Programmable group to group skew
Linear programmable frequency and spreading %
Efficient power management scheme through PD#,CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through I 2 C interface.
E. Memory
System Memory
255/259II1 Support PC 1600/2100/2700 128MB/256MB/512MB/1GB DDR 200/266/333
SDRAM that Extending two un-buffer Double-side:
Directly supports one DDR SDRAM channel, 64-bits wide (72-bits with ECC)
Supports 200/266/333-MHz DDR SDRAM devices with max of two, double-sided
SO-DIMMs (four rows populated) with unbuffered PC1600/PC2100/PC2700 DDR
SDRAM.
Supports 128-Mbit, 256-Mbit, and 512-Mbit technologies providing maximum capacity
of 1 GB with x16 devices.
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All supported devices have four banks
Supports up to 16 simultaneous open pages
Supports page sizes of 2-kB, 4-kB, 8-kB, and 16-kB. Page size is individually selected for
every row
UMA support only
128MB 0 128MB
256MB 0 256MB
512MB 0 512MB
0 128MB 128MB
0 256MB 256MB
0 512MB 512MB
128MB 128MB 256MB
256MB 256MB 512MB
512MB 512MB 1024MB
Mini PCI (Wireless LAN)
Product Name : 11Mbps Wireless LAN Mini-PCI Card.
Model Number : Intel PRO/Wireless 2100 LAN.
Host Interface : 32-bit type III A miniPCI.
Operating Voltage: 3.3V+-5%.
Frequency Band : 2.4~2.4835GHz (subject to local regulation).
Standards : IEEE802.11b, Bluetooth* co-existence capability.
F. PCMCIA
The OZ711MC1 is a single socket PC Card controller that also support Smart Cards and flash
media cards. The OZ711MC1 is enhance with O2Micro's patent pending MultiMediaBayTM
technology, enabling a single passive adapter that supports all four flash media formats -
SmartMediaTM, Memory StickTM, MultiMediaCard (MMC) and SD Memory Card.
The OZ711MC1 also provides a secondary Optional Dedicated Reader (ODR) interface that
can support a Smart Card socket, a MMC/SD Card socket, or a Memory Stick socket. The
software drivers that support the optional dedicated reader are identical to those required for the
PC Card socket extensions for MultiMediaBayTM.
The OZ711MC1 provides a SmartMediaTM reader fully compliant with the SmartMediaTM
Standard, Millennium Version, released in 2000 by the SSFDC forum. The reader supports the
unique identifier extension for SDMI, 3Vand 5V SmartMediaTM cards in any capacity from
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Chapter 1 General System Description
1MB to 128MB including MASK ROM versions. The integrated MMC/SD Memory Card and
Memory Stick reader transfers data at an operating frequency of 16.5MHz and supports all
capacities of these media formats and Memory Stick cards.
PC Card/PCI Features
Compliant with PCI Local Bus Specification version 2.3
PC 2001 Compliant and Win XP Compatible
Support hot insertion/removal of all 5V/3.3V PC Cards
Flash Media Features
Optional Sideband Dedicated Reader for MMC/SD/MS/MS PRO
SmartMediaTM Standard 2000 (Millennium) Compliant
Support SD Memory Card CPRM Security Mode
Support all Voltages and All Capacities of Media
G. BIOS
The 255/259II1 using AMI system BIOS, and support PnP, APM 1.2 and ACPI 2.0 function.
Both of System and VGA BIOS are flashed in a 4Mbit EEPROM, The Flash ROM in the 32-pin
PLCC package, there are three of suppliers for BIOS:
EON (EN29LF040-70)
AMIC (A29040L-70)
Hyundai (HY29F040A-70)
H. IEE1394
Description
The Texas Instruments TSB43AB22 device is an integrated 1394a-2000 OHCI
PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus
Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995,
IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable
of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s,
and 400M bits/s. TheTSB43AB22 device provides two 1394 ports that have separate cable bias
(TPBIAS). The TSB43AB22 device also supports the IEEE Std 1394a-2000 power-down
features for battery-operated applications and arbitration enhancements.
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Chapter 1 General System Description
An advanced CMOS process achieves low power consumption and allows the
TSB43AB22 device to operate at PCIclock rates up to 33 MHz.
The TSB43AB22 PHY-layer requires only an external 24.576-MHz crystal as a reference for
the cable ports. An external clock may be provided instead of a crystal. An internal oscillator
drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz
reference signal. This reference signal is internally divided to provide the clock signals that
control transmission of the outbound encoded strobe and data information. A 49.152-MHz
clock signal is supplied to the integrated LLC for synchronization and is used for
resynchronization of the received data.
Data bits to be transmitted through the cable ports are received from the integrated LLC and
are latched internally in synchronization with the 49.152-MHz system clock. These bits are
combined serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s
(referred to as S100, S200, or S400 speeds, respectively) as the outbound data-strobe
information stream.
Features
The TSB43AB22 device supports the following features:
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial
bus and IEEE Std1394a-2000
Fully interoperable with FireWire and i.LINK implementations of IEEE Std
1394Compliant with Intel Mobile Power Guideline 2000
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset,
multispeed concatenation, arbitration acceleration, fly-by concatenation, and port
disable/suspend/resume
Power-down features to conserve energy in battery-powered applications include:
automatic device power down during suspend, PCI power management for link-layer, and
inactive ports powered down
Ultralow-power sleep mode
Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and
400M bits/s
I. Hard Disk Unit
The Primary Master HDD supporting PIO Mode 0,1,2,3,4 and Ultra DMA 33/66/100.
Vendor: Toshiba, Fujitsu, IBM
Capacity: Support 20/40GB or above HDD
Thickness: 9.5mm/2.5"
Host Interface: Fast IDE Interface
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Chapter 1 General System Description
J. Optical Device
The Secondary Master also supporting ATAPI CD-ROM Device as follow:
Secondary Master:
1. COMBO (DVD+R/CD-RW)
2. DVD
3. CD-R or CD-R/W
4. CD-ROM
K. Keyboard
Key Board Matrix: 255/259II1 (Follow 755CA K/B matrix)
Travel: 3.0±0.3mm
Contact Resistance: 500 ohm Maximum
Keycap pull off force: Function Key ¡Ù 800g; Normal Key ¡Ù 800g
Switch Life: 5 Million cycles
L. Audio Sub System
The VT1612A 20-bit architecture audio codec conforms to the AC'97 2.2 and S/PDIF
specifications. The VT1612A integrates Sample Rate Converters and can be adjusted in 1 Hz
increments. The analog mixer circuitry integrates a stereo enhancement to provide a pleasing
3D surround sound effect for stereo media. Four stereo and 2 mono audio inputs provided by
the VIA VT1612A enable connections to a wide range of audio inputs such as microphones,
line inputs, and phone connections. Sample rate converters in the VIA VT1612A can be
adjusted in 1Hz increments providing maximum recording manipulation capabilities, and
hardware VU peak meters are provided for PCM streams.
For maximum ease of integration the VIA VT1612A is designed with aggressive power
management to achieve low power consumption. When used with a 3.3v analog power supply,
the power consumption can be further reduced.
Audio codec Features
AC'97 2.2 compliant codec
20-bit architecture stereo full-duplex £U.codec
1Hz resolution VSR (Variable Sampling Rate)
Integrated IEC958 line driver for S/PDIF output
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Chapter 1 General System Description
S/PDIF compressed digital or LPCM audio out
3D stereo expansion for simulated surround
20-bit architecture independent rate stereo ADC/
Hardware VU peak meters for PCM streams
4 stereo, 2 mono analog line-level inputs
Alt. line-level output with volume control, or
Headphone Amplifier with Thermal Protection
Low Power consumption mode
Exceeds Microsoft® WHQL logo requirements
3.3V digital, 3.3 or 5V analog power supply
M. Touchpad Unite
The Synaptics Touch Pad include two inputs for button switches: Left and Right button,
special firmware that permits the Touch Pad to be initialized into 4-byte wheel Mouse mode. In
this mode the Touch Pad communicates with the PS/2 host as though it were a Microsoft
IntelliMouse. The Touch Pad also includes the standard Synaptics' enhanced mode of operation,
6-byte mode.
Scrolling is implemented in the firmware of this Touch Pad. When it is initialize into Wheel
Mouse mode the firmware will decode a finger gesture on the right hand edge of the Touch Pad
as intent to scroll.
N. LED Indicator Unite
There are seven LED indicators on 255/259II1 The function describe as follows :
1. Caps Lock : Green color for Caps Lock function is active.
2. Num Lock : Green color for Num Lock function is active.
3. Scroll Lock : Green color for Scroll lock function is active.
4. HDD/CD-ROM : Green color for HDD/CD-ROM is active.
5. WLAN : Green color for LAN is active.
6. SUSPEND LED : Green active flash color for the system active at suspend mode.
7. Power/Charge LED : Green color for system power on, orange active flash color for
bttery charging.
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Chapter 1 General System Description
O. Modem
MM320 use Silicon based DAA chip set that provides a digital, low-cost, solid-state
interface to a telephone line. They eliminate the need for an analog front end (AFE), and
isolation transformer, relays, opto-isolator, and 2- to 4-wire hybrid. The products dramatically
reduce the number of discrete components and cost required to achieve compliance with FCC
Part 68. MM320 comply with AC'97 / MC'97 interface specification Rev. 2.1.
Power Consumption: Less than 100mW
Modem mode speed: 56Kb/p maximum
Compatibility: Bell 103, Bell 212A, ITU-T V.21, V.32bis, V.34, V.90, V.92
Transmission Way: Full Duplex
Fax mode speed: 14.4Kbps
P. Super I/O (Embedded Controller IT8510E)
The IT8510E is a highly integrated embedded controller with system functions suitable for
mobile system applications. The IT8510E directly interfaces to the LPC bus and provides ACPI
embedded controller function, keyboard controller (KBC) and matrix scan, external flash
interface for system BIOS and EC code, PWM, ADC and SmartAuto Fan control for hardware
monitor, PS/2 interface for external keyboard/mouse devices, RTC and system wake up
functions for system power management. It also supports the external flash ( or EPROM) to be
shared by the host and EC side.
The key features as follows :
Compatible with the LPC specification v1.1.
Supports I/O read/write.
Serial IRQ.
Supports 71-bit GPIO.
8042 style KBC interface.
Up to 4M bytes Flash space shared by the host.
4 PS/2 interface.
SM Bus spec. 2.0 .
Full duplex UART.
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Chapter 1 General System Description
Q. LAN PHY (RTL8100C(L) )
The RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller
that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE
802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports
the Advanced Configuration Power management Interface (ACPI), PCI power management for
modern operating systems that are capable of Operating System Directed Power Management
(OSPM) to achieve the most efficient power management possible.
The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the
RTL8100C(L) can be shut down temporarily according to user requirements or when the
RTL8100C(L) is in a power down state with the wakeup function disabled. In addition, when
the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then both
the analog and digital parts stop functioning and the power consumption of the RTL8100C(L)
will be negligible. The RTL8100C(L) also supports an auxiliary power auto-detect function,
and will auto-configure related bits of their own PCI power management registers in PCI
configuration space.
The key features as follows :
10 Mb/s and 100 Mb/s operation
Compliant to PCI Revision 2.2
Supports ACPI, PCI power management
Compliant to PC99/PC2001 standard
Supports Wake-On-LAN function
Includes a programmable, PCI burst size and early Tx/Rx threshold.
Supports Full Duplex Flow Control (IEEE 802.3x)
R. TV OUT Chrontel CH7011
The CH7011 is a display controller device which accepts a digital graphics input signal, and
encodes and transmits data to a TV output (analog composite, s-video or RGB). The device
accepts data over one 12-bit wide variable voltage data port which supports five different data
formats including RGB and YCrCb.
The TV-Out processor will perform non-interlace to interlace conversion with scaling and
flicker filters, and encode the data into any of the NTSC or PAL video standards. The scaling
and flicker filter is adaptive and programmable to enable superior text display. Eight graphics
resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan
capability in all modes. A high accuracy low jitter phase locked loop is integrated to create
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Chapter 1 General System Description
outstanding video quality. Support is provided for Macrovision TM and RGB bypass mode
which enables driving a VGA CRT with the input data.
Chrontel CH7011 Features
TV output supporting graphics resolutions up to 1024x768 pixels
Macrovision TM 7.1.L1 copy protection support
Programmable digital interface supports RGB and YCrCb
True scale rendering engine supports underscan in all TV output resolutions
Enhanced text sharpness and adaptive flicker removal with up to 7 lines of
filtering
Support for all NTSC and PAL formats
Provides CVBS, S-Video and SCART (RGB) outputs
TV Programmable power management
10-bit video DAC outputs
Fully programmable through serial port
Complete Windows and DOS driver support
Low voltage interface support to graphics device
Offered in a 64-pin LQFP package
S. Hot-key definition
Fn + F1 (SMI): Standby
Fn + F3 (SMI): Audio Mute
Fn + F4 (SMI): Toggle LCD/CRT display
Fn + F5 (SMI): Volume increase
Fn + F6 (SMI): Volume decrease
Fn + F7 (SMI): Brightness more lightness
Fn + F8 (SMI): Brightness more darkness
T. System LED Indicator
Caps Lock (on/off)
Num Lock (on/off)
Scroll Lock (on/off)
HDD/CDROM (on/off)
Power on (on/off)
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Chapter 1 General System Description
Suspend (flash/off)
Power Switch (on/off)
Wireless LAN Switch (on/off)
Q. Power Plan
+1.05V/(VCCP): Main power for CPU I/O.
+1.5V: main power for SB ICH4-M(LAN logic).
+1.5VS: Power for SB ICH4-M and NB GMCH 855GM.
+1.8VS/(VCCA_1.8): Source power of VCCA_1.8 (VCCA_1.8 for CPU power).
+1.25VS: Power for NB GMCH 855GM and DDR Termination.
+1.35VS: Power for NB GMCH 855GM.
+A3V: Analog power source provide for LAN.
+3V: +3V Main power provide for ICH-4(LAN I/O),AC97,IEEE1394,
+3VS: Power for Audio/NB/SB/CAR BUS.
+3V_AUX: 3V auxiliary power that provide for EC,ICH-4
+3VS_CLK: Power for CLK GEN ICS 950813.
+5V: 5V Main Power Source that provide for USB port, Card BUS,
+5VS: Power for AMP, CODEC, HDD, CD-ROM, ICH-4, Card BUS.
+5V_AUX: 5V auxiliary power that exist regardless the system is power on or off.
+12V: 12V Main Power Source that is provided for Card BUS, and switch on power source.
+2.5V: Main Power that provide 2.5V for SDRAM/LAN/NB 855GM chipset.
ADAP_IN: Power supply from AC adapter that provide 20V for Main Power.
CPU_CORE: Main Power Source that provide multiage Voltage for P4/Celeron Mobil,
Dothan
LCDVCC: Main power source provide 3VS for LCD Panel.
VCCRTC: Real Time Clock Power Source
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Chapter 1 General System Description
1.2 Software Specicification
A. System Memory
The System consists of DDR SDRAM memory on 64-bit bus and the size options are
8/16/32/64/128/256/512MB on each DIMM slot. The BIOS will automatically detect the amount of
memory during the POST. But the total RAM size can be used by user must be substrated by the size
of the video shared memory.
B. Enhanced IDE
The enhanced IDE specification has defined many data transfer modes as following:
1. Ultra DMA-33/66/100
2. Which transfer mode will be set depend on the used devices, core chip IDE interface
and BIOS supported. This model's BIOS support all the data transfer modes above,
and it will auto detect and initialize it during POST.
C. Audio
The audio controller is integrated in ICH4-M and through the AC97 data line to external CODEC
(VIA VT1612A) to reduce the noise caused by PCB's layout. However the H/W architecture is, the
BIOS will recognize it as a PCI device and initialize it in PCI bus initialization. The PCI legacy
audio mode is not to be supported.
D. Modem
The system can use all of the modem that is AC97' compliance and the MDC form factor. During
POST need to detect the existence and setting proper registers in south bridge.
E. PCMCIA
The system BIOS need to support some devices (especially the LAN card) need to work in
Pure-DOS, such as MS-DOS 6.22.
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Chapter 1 General System Description
F. Keyboard Controller
The system uses the ITE IT8510E as the keyboard controller and ACPI embedded controller.
Following will summarize all the features of keyboard firmware.
External Keyboard and Auxiliary Device Support Standard AT or OADG Support
IBM PS/44 Numeric Keypad Support and PS/2 Style Auxiliary Device Support.
Internal Keyboard and Auxiliary Device Support and Internal Pointing Device Support.
Internal Keyboard Scan Code Controller Support and Internal Numeric Keypad Support.
Simultaneous Operation of Internal and External Devices
Simultaneous Operation of internal and External Keyboards
Simultaneous Operation of Internal and External Auxiliary
Device Hot Pluggability
Dynamic Internel Numeric KeyPad (internal numeric keypad will disable automatically with
external PS/2 keyboard)
Hot Pluggability of External PS/2 Devices (Keyboard or Mouse) and Hot Port Swapping
Embedded Controller 128-Pin LQFP package
LPC System Interface
JTAG On-Board Flash and System Flash Tool Support.
ACPI Embedded Controller Power Management Event Control.
Internal 8 x 16 Keys Matrix Scanning include JAPANESE and KOREA Keyboard.
Single Pin Keys Support .
PS/2 Interface External 2 Ports Support and one internal PS/2 Touch-PAD support.
On-Board Keyboard LEDs NumLock,CapsLock, ScrollLock Support.
System Power On/Off ATX Power Sequence Control.
System BIOS Strap Pin.
System BIOS ROM Flash Protect.
FAN DAC or PWM Control.
Battery Low/Very Low Beep Control
LID Function Support.
Function Hotkey and Quick Keys Support.
LCD Backlight Brightness Adjust.
System SmartBattery Li-Ion Charger Control.
Direct LEDs Support.
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Chapter 1 General System Description
G. Power Management
Each system (or model) may have different PM model and state definition. For clear, see the following table:
PM Mode Definitions
Full-On The CPU run in full speed and all the devices are power on. The system can respond to all applications
with maximum performance.
1. The system in the state S0.
2. The CPU in the state C0.
3. All the devices in the state D0.
Idle This mode is similar to Full-On except the CPU will change to C1 or C2 state depend on the OS, to
save CPU power consumption.
1. The system in the state S0.
2. The CPU in the state C1 or C2.
3. All the devices in the state D0.
Suspend The state is more power saving than above, the CPU will change to C3 state and most of power
consumption parts will enter to suspend or idle mode.
1. The system in the state S3.
2. The CPU in the state C3.
3. HDD, CDROM and LCD enter to suspend mode, otherwise in state D0.
SOFF/STD The state is the most power saving mode, all of the parts in the system will power off, except the
keyboard controller enter to idle mode continuously to control the battery charging and monitor power
button.
Note: Before enter to S4, the OS or BIOS will save all of data or registers in the parts.
1. The system in the state S5 or S4.
2. The CPU and all of devices power off.
H. The backlight control of LCD
The LCD panel is another key parts that will consume more power of the notebook system, so there
is a way to reduce the power consumption on battery only, e.i. reduce the brightness of backlight
when end-user plug out the AC adaptor.
The backlight is controled through the KBC controller, and it is divide into 5 levels from
darkest to brightest. The KBC bios know the status of power source and the current backlight's
brightness any time. When the AC adaptor plug out, the KBC will reduce the brightness one or two
level automatically.
There is another approach to control the backlight, it will be turn off when LCD cover
close(LID switch), conversly, it will be turn on when LCD cover open.
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