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TABLE OF CONTENTS
1. INTRODUCTION................................................................................................................... 7
2. TUNER.................................................................................................................................... 7
2.1. General description of TDTC-G101D: ....................................................................... 7
2.2. Features of TDTC-G101D: ......................................................................................... 7
2.3. Pinning: ....................................................................................................................... 8
3. AUDIO AMPLIFIER STAGE WITH MP7722...................................................................... 8
3.1. General Description..................................................................................................... 8
3.2. Features ....................................................................................................................... 8
3.3. Applications ................................................................................................................ 9
3.4. Absolute Ratings ......................................................................................................... 9
3.4.1. Electrical Characteristics......................................................................................... 9
3.4.2. Operating Specifications ....................................................................................... 10
3.5. Pinning ...................................................................................................................... 10
4. POWER STAGE ................................................................................................................... 11
5. MICROCONTROLLER (MSTAR) ...................................................................................... 11
5.1. General Descripction................................................................................................. 11
5.2. General Features........................................................................................................ 11
6. SIL9185 3:1 HDMI 1.3 Switch ............................................................................................. 13
6.1. General Desription .................................................................................................... 13
6.2. Features ..................................................................................................................... 13
6.3. Absolute Maximum Ratings...................................................................................... 13
6.4. Pinning ...................................................................................................................... 14
7. QAM DEMODULATOR STV0297E................................................................................ 15
7.1. General Desription .................................................................................................... 15
7.2. Features ..................................................................................................................... 16
7.3. Absolute Maximum Ratings...................................................................................... 16
7.4. Pinning ...................................................................................................................... 17
8. HY5DV281622DT-5 DDR SDRAM 128M ......................................................................... 17
8.1. General Description................................................................................................... 17
8.2. Features ..................................................................................................................... 18
8.3. Absolute Maximum Ratings...................................................................................... 18
8.4. Pinning ...................................................................................................................... 19
9. IS42S16100C1 SDRAM ....................................................................................................... 19
9.1. General Description................................................................................................... 19
9.2. Features ..................................................................................................................... 19
9.3. Pinning ...................................................................................................................... 20
10. SAW FILTER ................................................................................................................... 20
10.1. IF Filter for Audio Applications Epcos K9656M .............................................. 20
10.1.1. Standart: ................................................................................................................ 20
10.1.2. Features: ................................................................................................................ 20
10.1.3. Pin configuration: .................................................................................................. 21
10.1.4. Frequency response: .............................................................................................. 21
10.2. IF Filter for Video Applications Epcos K3958M............................................... 22
10.2.1. Standart: ................................................................................................................ 22
10.2.2. Features: ................................................................................................................ 22
10.2.3. Frequency response: .............................................................................................. 22
11. 2048-Bits Serial EEPROM 24LC02 .............................................................................. 23
11.1. General Description............................................................................................... 23
11.2. Features ................................................................................................................. 23
11.3. Electrical Specifications ........................................................................................ 24
11.4. Pinning .................................................................................................................. 25
12. 32K Smart Serial EEPROM 24C32 ............................................................................... 25
12.1. General Description............................................................................................... 25
12.2. Features ................................................................................................................. 25
11.3 Absolute Maximum Ratings and Electrical Characteristics...................................... 26
11.4 Pinning ...................................................................................................................... 27
13. 512K CMOS Serial Flash MX25L512........................................................................... 28
13.1. General Description............................................................................................... 28
13.2. Features ................................................................................................................. 28
11.3 Absolute Maximum Ratings...................................................................................... 29
14. Integrated DVB-T Receiver .............................................................................................. 30
13.1 General Description................................................................................................... 30
13.2 Features ..................................................................................................................... 31
13.3 Absolute Maximum Rating and Electrical Characteristics ....................................... 33
15. IC DESCRIPTIONS.......................................................................................................... 35
15.1. LM1117 ................................................................................................................. 35
15.1.1. General Description............................................................................................... 35
15.1.2. Features ................................................................................................................. 35
15.1.3. Applications .......................................................................................................... 35
15.1.4. Absolute Maximum Ratings.................................................................................. 35
15.1.5. Pinning .................................................................................................................. 36
15.2. 74HCT4053 ........................................................................................................... 36
15.2.1. General Description............................................................................................... 36
15.2.2. Features ................................................................................................................. 36
15.2.3. Applications .......................................................................................................... 36
15.2.4. Absolute Maximum Ratings.................................................................................. 37
15.2.5. Pinning .................................................................................................................. 37
15.3. NUP4004M5 ......................................................................................................... 37
15.3.1. General Description............................................................................................... 37
15.3.2. Features ................................................................................................................. 38
15.3.3. Absolute Maximum Ratings.................................................................................. 38
15.3.4. Pinning .................................................................................................................. 38
15.4. FDN336P............................................................................................................... 39
15.4.1. General Description............................................................................................... 39
15.4.2. Features ................................................................................................................. 39
15.4.3. Absolute Maximum Ratings.................................................................................. 39
15.4.4. Pinning .................................................................................................................. 39
15.5. TL062 -.................................................................................................................. 40
15.5.1. General Description............................................................................................... 40
15.5.2. Features ................................................................................................................. 40
15.5.3. Absolute Maximum Ratings.................................................................................. 40
15.5.4. Pinning .................................................................................................................. 41
15.6. PI5V330 ................................................................................................................ 41
15.6.1. General Description............................................................................................... 41
15.6.2. Features ................................................................................................................. 41
15.6.3. Absolute Maximum Ratings.................................................................................. 41
15.6.4. Pinning .................................................................................................................. 42
15.7. AZC099-04S ......................................................................................................... 42
15.7.1. General Description............................................................................................... 42
15.7.2. Features ................................................................................................................. 42
15.7.3. Absolute Maximum Ratings.................................................................................. 43
15.7.4. Pinning .................................................................................................................. 43
15.8. TDA1308............................................................................................................... 43
15.8.1. General Description............................................................................................... 43
15.8.2. Features ................................................................................................................. 43
15.8.3. Absolute Maximum Ratings.................................................................................. 44
15.8.4. Pinning .................................................................................................................. 44
15.9. ST3222 .................................................................................................................. 44
15.9.1. General Description............................................................................................... 44
15.9.2. Features ................................................................................................................. 44
15.9.3. Absolute Maximum Ratings.................................................................................. 45
15.9.4. Pinning .................................................................................................................. 45
15.10. LM358D ................................................................................................................ 45
15.10.1. General Description........................................................................................... 45
15.10.2. Features ............................................................................................................. 46
15.10.3. Absolute Maximum Ratings.............................................................................. 46
15.10.4. Pinning .............................................................................................................. 47
15.11. 74LCX244 ............................................................................................................. 47
15.11.1. General Description........................................................................................... 47
15.11.2. Features ............................................................................................................. 47
15.11.3. Absolute Maximum Ratings.............................................................................. 47
15.11.4. Pinning .............................................................................................................. 48
15.12. 74LCX245 ............................................................................................................. 48
15.12.1. General Description........................................................................................... 48
15.12.2. Features ............................................................................................................. 48
15.12.3. Absolute Maximum Ratings.............................................................................. 49
15.12.4. Pinning .............................................................................................................. 49
15.13. FSA3157................................................................................................................ 49
15.13.1. General Description........................................................................................... 49
15.13.2. Features ............................................................................................................. 50
15.13.3. Absolute Maximum Ratings.............................................................................. 50
15.13.4. Pinning .............................................................................................................. 50
15.14. FMS6145............................................................................................................... 51
15.14.1. General Description........................................................................................... 51
15.14.2. Features ............................................................................................................. 51
15.14.3. Absolute Maximum Ratings.............................................................................. 51
15.14.4. Pinning .............................................................................................................. 51
15.15. MT48LC4M16A2TG8E........................................................................................ 52
15.15.1. General Description........................................................................................... 52
15.15.2. Features ............................................................................................................. 52
15.15.3. Absolute Maximum Ratings.............................................................................. 52
15.15.4. Pinning .............................................................................................................. 53
15.16. MP1583 ................................................................................................................. 53
15.16.1. General Description........................................................................................... 53
15.16.2. Features ............................................................................................................. 54
15.16.3. Absolute Maximum Ratings.............................................................................. 54
15.16.4. Pinning .............................................................................................................. 54
15.17. MP2112 ................................................................................................................. 55
15.17.1. General Description........................................................................................... 55
15.17.2. Features ............................................................................................................. 55
15.17.3. Absolute Maximum Ratings.............................................................................. 55
15.17.4. Pinning .............................................................................................................. 55
15.18. STLITE49M .......................................................................................................... 56
15.18.1. General Description........................................................................................... 56
15.18.2. Features ............................................................................................................. 56
15.18.3. Absolute Maximum Ratings.............................................................................. 56
15.18.4. Pinning .............................................................................................................. 57
15.19. MAX809LTR ........................................................................................................ 58
15.19.1. General Description........................................................................................... 58
15.19.2. Features ............................................................................................................. 58
15.19.3. Absolute Maximum Ratings.............................................................................. 58
15.19.4. Pinning .............................................................................................................. 59
16. SERVICE MENU SETTINGS.......................................................................................... 59
16.1. Video Setup ........................................................................................................... 59
16.2. AudioSetup............................................................................................................ 59
16.3. Service Scan/Tuning Setup ................................................................................... 61
16.4. Options .................................................................................................................. 62
16.5. External Source Settings ....................................................................................... 64
16.6. Preset ..................................................................................................................... 64
16.7. NVM Edit .............................................................................................................. 64
16.8. Programming ......................................................................................................... 64
16.9. Diagnostic.............................................................................................................. 65
16.10. Product Info........................................................................................................... 65
17. SOFTWARE UPDATE DESCRIPTION.......................................................................... 65
16.1 17MB35 Analog Part Software Update With Bootloader Procedure ...................... 65
16.2 17MB30 HDCP key upload procedure. ................................................................... 68
16.3 17MB35 Digital Software Update From SCART ..................................................... 69
16.4 17MB35 Digital Software Update From USB .......................................................... 74
18. BLOCK DIAGRAMS ....................................................................................................... 74
18.1. General Block Diagram......................................................................................... 74
18.2. Power Management............................................................................................... 76
18.3. Integrated DVB-T Receiver Block Diagram......................................................... 77
18.4. MSTAR Block Diagram........................................................................................ 78
1. INTRODUCTION
17MB35 Main Board consists of MSTAR concept. This IC is capable of handling Audio
processing, video processing, Scaling-Display processing, 3D comb filter, OSD and text
processing, 8 bit dual LVDS transmitter.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards
as B/G, D/K, I/I', and L/L' including German and NICAM stereo.
Sound system output is supplying 2x10W (10%THD) for stereo 8 speakers.
Supported peripherals are:
1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)
1 Side AV (SVHS, CVBS, HP, R/L_Audio) (Common)
2 SCART sockets(Common)
1 YPbPr (Common)
1 PC input(Optional)
4 HDMI 1.3 input(2 HDMI inputs are common, 4 inputs are optional)
1 Stereo audio input for PC(Common)
1 Line out(Common)
1 Subwoofer out(Common)
1 S/PDIF output(Common)
1 Side S-Video(Optional)
1 Headphone(Common)
1 Common interface(Optional)
1 Digital USB(Opional)
1 Analog USB(Opional)
1 RS232(Optional)
1 Smart card connector(Optional)
2. TUNER
A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR
CH). The tuning is available through the digitally controlled I2C bus (PLL). Below you
will find info on the Tuner in use.
2.1. General description of TDTC-G101D:
The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to
863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.
2.2. Features of TDTC-G101D:
Digital Half-NIM tuner for COFDM
Covers 3 Bands(From 48MHz to 862MHz for COFDM,
From 45.25MHz to 863.25MHz for CCIR CH)
Including IF AGC with SAW Filter
Bandwidth Switching (7/8 MHz) possible
DC/DC Converter built in for Tuning Voltage
Internal(or External) RF AGC, Antenna Power Optional
2.3. Pinning:
3. AUDIO AMPLIFIER STAGE WITH MP7722
3.1. General Description
17MB35 uses a 20W Class D Stereo Single Ended Audio Amplifer for audio. The
MP7722 is a stereo 20W Class D Audio Amplifier. It is one of MPS' second generation of
fully integrated audio amplifiers which dramatically reduces solution size by integrating
the following:
180m power MOSFETs
Startup / Shutdown pop elimination
Short circuit protection
Mute / Standby
The MP7722 utilizes a single ended output structure capable of delivering 2 x 20W into
4 speakers. MPS Class D Audio Amplifiers exhibit the high fidelity of a Class A/B
amplifier at efficiencies greater than 90%. The circuit is based on the MPS' proprietary
variable frequency topology that delivers low distortion, fast response time and operates
on a single power supply.
3.2. Features
2 x 20W Output at VDD = 24V into a 4 load
THD+N = 0.06% at 1W, 8
93% Efficiency at 20W
Low Noise (190µV Typical)
Switching Frequency Up to 1MHz
9.5V to 24V Operation from a Single Supply
Integrated Startup and Shutdown Pop Elimination Circuit
Thermal and Short Circuit Protection
Integrated 180m Switches
Mute/Standby Modes (Sleep)
Thermally Enhanced 20-Pin TSSOP Package with Exposed Pad
3.3. Applications
Surround Sound DVD Systems
Televisions
Flat Panel Monitors
Multimedia Computers
Home Stereo Systems
3.4. Absolute Ratings
3.4.1. Electrical Characteristics
3.4.2. Operating Specifications
3.5. Pinning
4. POWER STAGE
The DC voltages required at various parts of the chassis and inverters are provided by a
main power supply unit. The power supply generates 33V, 24V, 12V, 5V, 3,3V and 5V,
3,3V stand by mode DC voltages. Power stage which is on-chasis generates 1,26V
stand by voltage and 8V, 2,6V, 1,8V and 1V supplies for other different parts of the
chassis.
5. MICROCONTROLLER (MSTAR)
5.1. General Descripction
The MST6WB7GQ-3 is a high performance and fully integrated IC for multi-
function LCD monitor/TV with resolutions up to full HD (1920x1080). It is
configured with an integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI
receiver, a multi-standard TV video and audio decoder, two video de-interlacers, two
scaling engines, the MStarACE-3 color engine, an on-screen display controller, an 8-bit
MCU and a built-in output panel interface. By use of external frame buffer, PIP/POP is
provided for multimedia applications. Furthermore, 3-D video decoding and processing
are fulfilled for high-quality TV applications. To further reduce system costs, the
MST6WB7GQ-3 also integrates intelligent power management control capability for
green-mode requirements and spread-spectrum support for EMI management.
5.2. General Features
LCD TV controller with PIP/POP display functions
Input supports up to UXGA & 1080P
Panel supports up to full HD (1920x1080)
TV decoder with 3-D comb filter
Multi-standard TV sound demodulator and decoder
10-bit triple-ADC for TV and RGB/YPbPr
10-bit video data processing
Integrated DVI/HDCP/HDMI compliant receiver
High-quality dual scaling engines & dual 3-D video de-interlacers
3-D video noise reduction
Full function PIP/PBP/POP
MStarACE-3 picture/color processing engine
Embedded On-Screen Display (OSD) controler engine
Built-in MCU supports PWM & GPIO
Built-in dual-link 8/10-bit LVDS transmitter
5-volt tolerant inputs
Low EMI and power saving features
296-pin LQFP
NTSC/PAL/SECAM Video Decoder
Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM
Automatic TV standard detection
Motion adaptive 3-D comb filter for NTSC/PAL
8 configurable CVBS & Y/C S-video inputs
Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip
Macrovision detection
CVBS video output
Video IF for Multi-Standard Analog TV
Digital low IF architecture
Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution
Maximum IF analog gain of 37dB in addition to digital gain
Programmable TOP to accommodate different tuner gain to optimize noise and
linearity performance
Multi-Standard TV Sound Decoder
Supports BTSC/NICAM/A2/EIA-J demodulation and decoding
FM stereo & SAP demodulation
L/Rx4, mono, and SIF audio inputs
L/Rx3 loudspeaker and line outputs
Supports sub-woofer output
Built-in audio output DAC's
Audio processing for loudspeaker channel, including volume, balance, mute,
tone, EQ, and virtual stereo/surround
Optional advanced surround available (Dolby1, SRS2, BBE3... etc)
Digital Audio Interface
I2S digital audio input & output
S/PDIF digital audio input & output
HDMI audio channel processing capability
Programmable delay for audio/video synchronization
Analog RGB Compliant Input Ports
Three analog ports support up to UXGA
Supports HDTV RGB/YPbPr/YCbCr
Supports Composite Sync and SOG (Sync-on-Green) separator
Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port
Two HDMI input ports with built-in switch
Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color
resolution
Single link on-chip DVI 1.0 compliant receiver
High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver
6. SIL9185 3:1 HDMI 1.3 Switch
6.1. General Desription
The SiI9185A is the first generation of TMDS switch device supporting Revision 1.3 of
the HDMI Specification (HDMI Consortium; June 2006). With three HDMI inputs and a
single output, the SiI9185A provides a low-cost method of adding additional HDMI ports
to the latest Digital TVs. New DTVs can easily connect to the many HDMI sources
coming on the market, including DVDs, STB, game consoles, PCs, camcorders, and
digital still cameras. The SiI9185A is a fully HDMI compliant device providing a simple,
lowcost method of retransmitting protected digital audio and video, giving end-users a
truly all-digital experience. Built-in backward compatibility with DVI 1.0 allows HDMI
systems to connect to any DVI 1.0 source. The SiI9185A provides additional integrated
features to help lower system cost and provide enhanced features to the end consumer.
To lower system cost, the SiI9185A provides a complete solution for switching sink-side
HDMI signals. This includes DDC switching, individual HPD control, and 5V sense. The
addition of these features eliminates additional external components, helping to lower
cost. For source-side applications, the SiI9185A DDC switching can be bypassed with
an external 4-channel I2C-bus switch(e.g., Texas Instruments PCA95445) to allow clock
stretching.
6.2. Features
Three-input, single-output HDMI switcher
Integrated TMDS® receiver and transmitt cores capable of receiving and
transmitting 2.25 Gbps:
Support 60 Hz, 12-bit or 720p/1080i, 120 Hz, 12-bit
Builcable support even at deep-color resolutions
Pre-emphasi
DVI 1.0, HDCP 1.1 and HDM compliant receiver and transmitter
Uses HDMI-compliant TMDS core recovery and retransmission, unlike TMDS
switches, which use high-spee analog switches and degrade TMDS signals
Built-in Cons support:
HDM lowers cost for adding CEC support to DTV
Integra requirements on system microcontrolle speeds design
6.3. Absolute Maximum Ratings
6.4. Pinning
7. QAM DEMODULATOR STV0297E
7.1. General Desription
The STV0297E is a complete single-chip QAM (quadrature amplitude modulation)
demodulation and FEC (forward error correction) solution that performs sampled IF to
transport stream (MPEG-2 or MPEG-4) block processing of QAM signals. It is intended
for the digital transmission of compressed television, sound, and data services over
cable. It is fully compliant with ITU-T J83 Annexes A/C or DVB-C specification
bitstreams (ETS 300 429, "Digital broadcasting systems for television, sound and data
services Framing structure, channel coding and modulation - Cable Systems"). It can
handle square (16, 64, 256-QAM) and non-square (32, 128-QAM) constellations.
Japanese DBS systems require a transport stream multiplex frame (TSMF) layer to
carry digital signals over cable systems. When the recovered transport stream is a
multiplex frame, the STV0297E post-processes it to extract a single transport stream.
Automatic detection of the TSMF layer is provided. The chip integrates an analog-to-
digital converter that delivers the required performance to handle up to 256-QAM signals
in a direct IF sampling architecture, thus eliminating the need for external
downconversion.
7.2. Features
Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams
Processes Japanese transport stream multiplex frame (TSMF)
High-performance integrated A/D converter suitable for direct IF architecture in all
QAM (quadrature amplitude modulation) modes
Supports 16, 32, 64, 128 and 256 point constellations
Small footprint package: (10 x 10 mm²)
Very low power consumption
Full digital demodulation
Variable symbol rates
Front derotator for better low symbol rate performance and relaxed tuner
constraints
Integrated matched filtering
Robust integrated adaptive pre and post equalizer
On-chip FEC A/C with ability to bypass individual blocks
10 programmable GPIO
Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs)
Integrated signal quality monitors, plus lock indicator and interrupt function
mapped to GPIO pin
Improved signal acquisition
System clock generated on-chip from quartz crystal
Low frequency crystal operations 4, 16, 25 - 30 MHz
4 I2C addresses
Easy control and monitoring via 2-wire fast I2C bus
7.3. Absolute Maximum Ratings
7.4. Pinning
8. HY5DV281622DT-5 DDR SDRAM 128M
8.1. General Description
The Hynix HY5DV281622 is a 134,217,728-bit CMOS Double Data Rate(DDR)
Synchronous DRAM, ideally suited for the point-to-point applications which requires high
bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations
referenced to both rising and falling edges of the clock. While all addresses and control
inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2.
8.2. Features
3.3V for VDD and 2.5V for VDDQ power supply
All inputs and outputs are compatible with SSTL_2 interface
JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers
when write (centered DQ)
Data(DQ) and Write masks(DM) latched on the both rising and falling edges of
the data strobe
All addresses and control inputs except Data, Data strobes and Data masks
latched on the rising edges of the clock
Write mask byte controls by LDM and UDM
Programmable /CAS latency 3 / 4 supported
Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Full, Half and Matched Impedance(Weak) strength driver option controlled by
EMRS
8.3. Absolute Maximum Ratings
8.4. Pinning
9. IS42S16100C1 SDRAM
9.1. General Description
ISSI's 16Mb Synchronous DRAM IS42S16100C1 is organized as a 524,288-word x 16-
bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising
edge of the clock input.
9.2. Features
Clock frequency: 200, 166, 143 MHz
Fully synchronous; all signals referenced to a positive clock edge
Two banks can be operated simultaneously and independently
Dual internal bank controlled by A11 (bank select)
Single 3.3V power supply
LVTTL interface
Programmable burst length (1, 2, 4, 8, full page)
Programmable burst sequence:Sequential/Interleave
4096 refresh cycles every 64 ms
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write operations capability
Burst termination by burst stop and precharge command
Byte controlled by LDQM and UDQM
Industrial temperature up to 143 MHz
Packages 400-mil 50-pin TSOP-II, 60-ball fBGA
Lead-free package option
9.3. Pinning
10. SAW FILTER
10.1. IF Filter for Audio Applications Epcos K9656M
10.1.1. Standart:
B/G
D/K
I
L/L'
10.1.2. Features:
TV IF audio filter with two channels
Channel 1 (L') with one pass band for sound carriers at 40,40 MHz (L') and 39,75
MHz (L'- NICAM)
Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35
MHz and 33,40 MHz
10.1.3. Pin configuration:
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output
10.1.4. Frequency response:
10.2. IF Filter for Video Applications Epcos K3958M
10.2.1. Standart:
B/G
D/K
I
L/L'
10.2.2. Features:
TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
Constant group delay
Pin configuration:
1 Input
2 Input - ground
3 Chip - carrier ground
4 Output
5 Output
10.2.3. Frequency response:
11. 2048-Bits Serial EEPROM 24LC02
11.1. General Description
The 24LC01/02 is a 1K/2K-bit serial read/write non-volatile memory device using the
CMOS floating gate process. Its 1024/2048 bits of memory are organized into 128/256
words and each word is 8 bits. The device is optimized for use in many industrial and
commercial applications where low power and low voltage operation are essential. Up to
eight HT24LC01/02 devices may be connected to the same two-wire bus. The
HT24LC01/02 is guaranteed for 1M erase/write cycles and 40-year data retention.
11.2. Features
Operating voltage: 2.4V~5.5V
Low power consumption
Operation: 5mA max.
Standby: 5mA max.
Internal organization
1K (HT24LC01):128´8
2K (HT24LC02): 256´8
2-wire serial interface
Write cycle time: 5ms max.
Automatic erase-before-write operation
Partial page write allowed
8-byte Page write modes
Write operation with built-in timer
Hardware controlled write protection
40-year data retention
106 erase/write cycles per word
8-pin DIP/SOP package
8-pin TSSOP (HT24LC02 only)
Commerical temperature range (0°C to +70°C)
11.3. Electrical Specifications
11.4. Pinning
12. 32K Smart Serial EEPROM 24C32
12.1. General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable
PROM. This device has been developed for advanced, low power applications such as
personal communications or data acquisition. The 24C32 features an input cache for
fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed
4K-bit block of ultra-high endurance memory for data that changes frequently. The
24C32 is capable of both random and sequential reads up to the 32K boundary.
Functional address lines allow up to eight 24C32 devices on the same bus, for up to
256K bits address space. Advanced CMOS technology makes this device ideal for low-
power non-volatile code and data applications. The 24C32 is available in the standard 8-
pin plastic DIP and 8-pin surface mount SOIC package.
12.2. Features
Voltage operating range: 4.5V to 5.5V
Peak write current 3 mA at 5.5V
Maximum read current 150 µA at 5.5V
Standby current 1 µA typical
Industry standard two-wire bus protocol, I2C compatible
Including 100 kHz and 400 kHz modes
Self-timed write cycle (including auto-erase)
Power on/off data protection circuitry
Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance
Block, 1,000,000 E/W cycles guaranteed for Standard Endurance Block
8 byte page, or byte modes available
1 page x 8 line input cache (64 bytes) for fast write loads
Schmitt trigger, filtered inputs for noise suppression
Output slope control to eliminate ground bounce
2 ms typical write cycle time, byte or page
Up to 8 chips may be connected to the same bus for up to 256K bits total
memory
Electrostatic discharge protection > 4000V
Data retention > 200 years
8-pin PDIP/SOIC packages
Temperature ranges: Commercial (C): 0°C to +70°C, Industrial (I): -40°C to
+85°C
11.3 Absolute Maximum Ratings and Electrical Characteristics
11.4 Pinning
13. 512K CMOS Serial Flash MX25L512
13.1. General Description
The MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as
65,536 x 8 internally. The MX25L512 feature a serial peripheral interface and software
protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the
device is enabled by CS# input. The MX25L512 provide sequential read operation on
whole chip. After program/erase command is issued, auto program/ erase algorithms
which program/ erase and verify the specified page or sector/block locations will be
executed. Program command is executed on page (256 bytes) basis, and erase
command is executes on chip or sector (4K-bytes). To provide user with ease of
interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via
WIP bit. When the device is not in operation and CS# is high, it is put in standby mode
and draws less than 10uA DC current. The MX25L512 utilize MXIC's proprietary
memory cell, which reliably stores memory contents even after 100,000 program and
erase cycles.
13.2. Features
GENERAL
Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
524,288 x 1 bit structure
16 Equal Sectors with 4K byte each
Any Sector can be erased individually
Single Power Supply Operation
2.7 to 3.6 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
High Performance
Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial
clock (30pF + 1TTL Load)
Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ;
1s(typ.) and 2s(max.)/chip(512Kb)
Low Power Consumption
Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and
4mA(max.) at 33MHz
Low active programming current: 15mA (max.)
Low active erase current: 15mA (max.)
Low standby current: 10uA (max.)
Deep power-down mode 1uA (typical)
Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
Input Data Format
1-byte Command code
Block Lock protection
The BP0~BP1 status bit defines the size of the area to be software protected
against Program and Erase instructions.
Auto Erase and Auto Program Algorithm
Automatically erases and verifies data at selected sector
Automatically programs and verifies data at selected page by an internal
algorithm that automatically times the program pulse widths (Any page to be
programed should have page in the erased state first)
Status Register Feature
Electronic Identification
JEDEC 2-byte Device ID
RES command, 1-byte Device ID
HARDWARE FEATURES
SCLK Input
Serial clock input
SI Input
Serial Data Input
SO Output
Serial Data Output
WP# pin
Hardware write protection
HOLD# pin pause the chip without diselecting the chip
PACKAGE
8-pin SOP (150mil)
All Pb-free devices are RoHS Compliant
11.3 Absolute Maximum Ratings
14. Integrated DVB-T Receiver
13.1 General Description
CT216T is a highly integrated single chip for DVB-T compliant STB solution. Compared
with Cheertek's previous generations of STB receiver devices. CT216T further interates
COFDM demodulator USB 2.0 HS host controller, memory card reader, 1/2-bit SPIFlash
interface, audio DAC, PWM in/out and SAR-ADC functions. In additiont special
enhangements are provided such as MPEG-4 video decoding, 16-bit OSD with anti-
flickering, HW JPEG decoding, flesh tone and black-white extensions, and improvement
of small video quality.
CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA
compliant de-scrambler, RISC MPUs, MPEG-1/2/4 AV decoder, digital T\/ encoder,
audio DACs, USB 2.0 HS host controller, memory card reader, smart card reader, CI
controller and other peripherals.
Cli216T is designed in focus on the market of single tuner input product which makes, it
a cost effective solution. Supports include free to air, conditional access for SC (Smart
card) and CI portable devices, PVR, LCD TV, and other DVB-T applications.
13.2 Features
COFDM Demodulator
ETSI EN 300 744 DVB-T NorDig Unified 1.0.3, and D-book compliant
Automatic spectral inversion, detection
Integrated ADC
Direct IF (36.167 MHz or 43.75 MHz) or low IF (4.57 MHz) supported
Single IF AGC or dual RF/lF AGC controls with modulabon
Impulsive noise cancellation
Carrier acquisition range: ±400 kHz (extensible to ±600 kHz in 8MHz BW)
Adjacent channel interference (ACI) filter,for supporting 6, 7, and 8MHz channels
with one 8MHz analog filter
Co-channel interterence (CCl) supression
RF signal strength monitor
MPU
Three 32-bit RISC MPU run up to 166MHz with total 448DMIPS
8KB I-Cache and 8KB D-Cache
Two general purpose timers
Watchdog timer
DSU for source level debug
Memory
6-bit SDRAM controller supports up to 32MB (16MB for l28-pin)
Unified memory architecture
Parallel flash (216-pin only)
1/2-bit SPI flash
Transport De-multiplexing
TS, PES, and ES demultiplexing
OneTS path
CI CAM interface (216-pin only)
32 general purpose PID filters
32 Section filters
CRC-32 accelerator
DVB-CSA de-scramblers
Video Decoding and Processing
MPEG-2 MP@ML
MPEG-4 SP&ASP
PAL/NTSC format conversion
3:2 pull down
Zoom in/out from 1/16X to 16X
HW JPEG decode
4/8/16-bit OSD with anti-flickering
On chip NTSC/PAL TV encoder
CVBS, S-VHS, and component video
VBI insertion for Teletext, CC and WSS
ITU-R BT.601 and ITU-R BT.656 outputs
Flesh tone extension
Black/white extension,
Audio Decoding and Processing
MPEG-1: layer 1/2/3
MPEG-2: layer 1/2
Decode MPEG-2 and MPEG-1 audio at sampling frequency of 16K, 22.05K, 24K,
32K, 44.1K, and 48KHz
Decode CU-DA at sampling frequency of 44.1 KHz
SPDIF out for AC-3 by-pass
Embedded 2 channels audio DAC for L/R outputs
Digital mute control and volume adjustment
OSD(On Screen Display)
There are total 9 display planes: border; background. video. RS1 (Rectangle Strip
1), RS2, OSD, RS3, RS4, and cursor.
4/8l16-bit OSD with anti-flickering and anti-flutter
Support alpha-blending per color
Adjustable brightness control in window
Bitmap OSD
Support horizontal pixel duplication to enlarge bitmap automatically
Support sub-region redraw to facilitate bitmap display.
Digitnal TV Encoder
NTSC-M, PAL-B, D, G, H, I, Nc, M encoding
Four video DACs to provide 6 configuration output: modes
Support CVBS, S-VHS. and component video outs
VBI insertion for Teletext, CC and WSS
Color burst amplitude control
Programmable sync. level
On chip, color-bar generator
High Speed I/O
USB 2.0 HS host controller
Memory card reader with SD, MMC, and MS interfaces
Compliant with SD spec. 1.1 and MMC spec. 4.0 with 1-bit & 4-bit modes.
Compliant with Memory Stick Pro format spec. 1.02 and Memory stick format
spec 1.43 with 1-bit and 4-bit modes.
Peripherals
Up to 3 full duplex UART with 16-byte FIFO
2-wire serial (2WS) in master mode .. .
Up to 2 IS0-7816 compliant SC (1 in 128-pin, can also be used as UART)
5 digits 7-Segrnent LED control
5x3 two-dimension key scan
2 SAR-ADC input
4 PWM input/output
1 HW IR command decode
GPIO
Electrical and Physical Characteristics
Capable of using single 27MHz clock input crystal
1.8V and 3.3V dual power supply
Power standby mode
PQFP-128 (CT216T-Z) or LQFP-216 (CT216T-R) package
13.3 Absolute Maximum Rating and Electrical Characteristics
15. IC DESCRIPTIONS
15.1. LM1117
15.1.1. General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at
800mA of load current. It has the same pin-out as National Semiconductor's industry
standard LM317. The LM1117 is available in an adjustable version, which can set the
output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10F
tantalum capacitor is required at the output to improve the transient response and
stability.
15.1.2. Features
Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
Space Saving SOT-223 Package
Current Limiting and Thermal Protection
Output Current 800mA
Line Regulation 0.2% (Max)
Load Regulation 0.4% (Max)
Temperature Range
LM1117 0°C to 125°C
LM1117I -40°C to 125°C
15.1.3. Applications
2.85V Model for SCSI-2 Active Termination
Post Regulator for Switching DC/DC Converter
High Efficiency Linear Regulators 15
32" TFT TV Service Manual 10/01/2005
Battery Charger
Battery Powered Instrumentation
15.1.4. Absolute Maximum Ratings
15.1.5. Pinning
15.2. 74HCT4053
15.2.1. General Description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin
compatible with the HEF4053B. It is specified in compliance with JEDEC standard no.
7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer
with a common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs
(Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1
to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of
S1 to S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to
S3 and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5
V for 74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between
VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
15.2.2. Features
Low ON resistance:
80 W (typical) at VCC - VEE = 4.5 V
70 W (typical) at VCC - VEE = 6.0 V
60 W (typical) at VCC - VEE = 9.0 V
Logic level translation:
To enable 5 V logic to communicate with ±5 V analog signals
Typical `break before make' built in
Complies with JEDEC standard no. 7A
ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM
EIA/JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
15.2.3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
15.2.4. Absolute Maximum Ratings
15.2.5. Pinning
15.3. NUP4004M5
15.3.1. General Description
This 5-Pin bi-directional transient suppressor array is designed for applications requiring
transient overvoltage protection capability. It is intended for use in transient voltage and
ESD sensitive equipment such as computers, printers, cell phones, medical equipment,
and other applications. Its integrated design provides bi-directional protection for four
separate lines using a single TSOP-5 package. This device is ideal for situations where
board space is a premium.
15.3.2. Features
Bi-directional Protection for Four Lines in a Single TSOP-5 Package
Low Leakage Current
Low Capacitance
Provides ESD Protection for JEDEC Standards JESD22
Machine Model = Class C
Human Body Model = Class 3B
Provides ESD Protection for IEC 61000-4-2, 15 kV (Air), 8 kV (Contact)
This is a Pb-Free Device
15.3.3. Absolute Maximum Ratings
15.3.4. Pinning
15.4. FDN336P
15.4.1. General Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),
organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C
bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM
data clocked out from the rising edge of the signal applied on VCLK. The device will
switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL
pin. The ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power
supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
15.4.2. Features
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
2.5V to 5.5V SINGLE SUPPLY VOLTAGE
400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE
TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP PERFORMANCES
15.4.3. Absolute Maximum Ratings
15.4.4. Pinning
15.5. TL062 -
15.5.1. General Description
Low-power JFET-input operational amplifier
15.5.2. Features
Very Low Power Consumption
Typical Supply Current . . . 200 µA (Per Amplifier)
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Common-Mode Input Voltage Range Includes VCC+
Output Short-Circuit Protection
High Input Impedance . . . JFET-Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate . . . 3.5 V/µs Typ
15.5.3. Absolute Maximum Ratings
15.5.4. Pinning
15.6. PI5V330
15.6.1. General Description
Pericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the
Company.s advanced CMOS low-power technology, achieving industry leading
performance. The PI5V330 is a true bidirectional Quad 2-channel
multiplexer/demultiplexer that is recommended for both RGB and composite video
switching applications. The VideoSwitch. can be driven from a current output RAMDAC
or voltage output composite video source. Low ON-resistance and wide bandwidth
make it ideal for video and other applications. Also this device has exceptionally high
current capability which is far greater than most analog switches offered today. A single
5V supply is all that is required for operation. The PI5V330 offers a high-performance,
low-cost solution to switch between video sources. The application section describes the
PI5V330 replacing the HC4053 multiplier and buffer/amplifier.
15.6.2. Features
High-performance, low-cost solution to switch between video sources
Wide bandwidth: 200 MHz
Low ON-resistance: 3
Low crosstalk at 10 MHz: .58 dB
Ultra-low quiescent power (0.1 µA typical)
Single supply operation: +5.0V
Fast switching: 10 ns
High-current output: 100 mA
Packages available:
16-pin 300-mil wide plastic SOIC (S)
16-pin 150-mil wide plastic SOIC (W)
16-pin 150-mil wide plastic QSOP (Q)
15.6.3. Absolute Maximum Ratings
15.6.4. Pinning
15.7. AZC099-04S
15.7.1. General Description
AZC099-04S is a high performance and low cost design which includes surge rated
diode arrays to protect high speed data interfaces. The AZC099-04S family has been
specifically designed to protect sensitive components, which are connected to data and
transmission lines, from over-voltage caused by Electrostatic Discharging (ESD),
Electrical Fast Transients (EFT), and Lightning.
AZC099-04S is a unique design which includes surge rated, low capacitance steering
diodes and a unique design of clamping cell which is an equivalent TVS diode in a
single package. During transient conditions, the steering diodes direct the transient to
either the power supply line or to the ground line. The internal unique design of clamping
cell prevents over-voltage on the power line, protecting any downstream components.
AZC099-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2,
Level 4 (± 15kV air, ±8kV contact discharge).
15.7.2. Features
ESD Protect for 4 high-speed I/O channels
Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air),
±8kV (contact) IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O, 40A for Power
IEC 61000-4-5 (Lightning) 4A (8/20s)
5V operating voltage Low capacitance : 1.0pF typical
Fast turn-on and Low clamping voltage
Array of surge rated diodes with internal equivalent TVS diode
Small package saves board space
Solid-state silicon-avalanche and active circuit triggering technology
15.7.3. Absolute Maximum Ratings
15.7.4. Pinning
15.8. TDA1308
15.8.1. General Description
The TDA1308; TDA1308A is an integrated class-AB stereo headphone driver contained
in an SO8, DIP8 or a TSSOP8 plastic package. The TDA1308AUK is available in an 8
bump wafer level chip-size package (WLCSP8). The device is fabricated in a 1 mm
Complementary Metal Oxide Semiconductor (CMOS) process and has been primarily
developed for portable digital audio applications. The difference between the TDA1308
and the TDA1308A is that the TDA1308A can be used at low supply voltages.
15.8.2. Features
Wide temperature range
No switch ON/OFF clicks
Excellent power supply ripple rejection
Low power consumption
Short-circuit resistant
High performance
High signal-to-noise ratio
High slew rate
Low distortion
Large output voltage swing
15.8.3. Absolute Maximum Ratings
15.8.4. Pinning
15.9. ST3222
15.9.1. General Description
The ST3222 is a 3V powered EIA/TIA-232 and V.28/V.24 communications interface with
low power requirements and high data-rate capabilities. ST3222 has a proprietary low
dropout transmitter output stage providing true RS-232 performance from 3 to 3.6V
power supplies. The device requires only four small 0.1mF standard external capacitors
for operating from 3V supply. The ST3222 has two receivers and two drivers. The
ST3222 features a 1mA shutdown mode that reduces power consumption and extends
battery life in portable systems. Its receivers can remain active in shutdown mode,
allowing external devices such as modems to be monitored using only 1mA supply
current. The device is guaranteed to run at data rates of 250Kbps while maintaining RS-
232 output levels.
15.9.2. Features
300mA SUPPLY CURRENT
250Kbps MINIMUM GUARENTEED DATA RATE
6V/ms MINIMUM GUARANTEED SLEW RATE
MEET EIA/TIA-232 SPECIFICATIONS DOWN TO 3V
AVAILABLE IN SO-18 AND TSSOP20
15.9.3. Absolute Maximum Ratings
15.9.4. Pinning
15.10. LM358D
15.10.1. General Description
The LM158 series consists of two independent, high gain, internally frequency
compensated operational amplifiers which were designed specifically to operate from a
single power supply over a wide range of voltages. Operation from split power supplies
is also possible and the low power supply current drain is independent of the magnitude
of the power supply voltage. Application areas include transducer amplifiers, dc gain
blocks and all the conventional op amp circuits which now can be more easily
implemented in single power supply systems. For example, the LM158 series can be
directly operated off of the standard +5V power supply voltage which is used in digital
systems and will easily provide the required interface electronics without requiring the
additional ±15V power supplies. The LM358 and LM2904 are available in a chip sized
package (8-Bump micro SMD) using National's micro SMD package technology.
15.10.2. Features
Available in 8-Bump micro SMD chip sized package,
Internally frequency compensated for unity gain
Large dc voltage gain: 100 dB
Wide bandwidth (unity gain): 1 MHz (temperature compensated)
Wide power supply: Single supply: 3V to 32V or dual supplies: ±1.5V to ±16V
Low supply current drain (500 µA)--essentially independent of supply voltage
Low input offset voltage: 2 mV
Input common-mode voltage range includes ground
Differential input voltage range equal to the power supply voltage
Large output voltage swing
15.10.3. Absolute Maximum Ratings
15.10.4. Pinning
15.11. 74LCX244
15.11.1. General Description
The LCX244 contains eight non-inverting buffers with 3-STATE outputs. The device may
be employed as a memory address driver, clock driver and bus-oriented
transmitter/receiver. The LCX244 is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal environment. The LCX244 is
fabricated with an advanced CMOS technology to achieve high speed operation while
maintaining CMOS low power dissipation.
15.11.2. Features
5V tolerant inputs and outputs
2.3V to 3.6V VCC specifications provided
6.5ns Tpd max. (VCC=3.3V), 10µA ICCmax.
Power down high impedance inputs and outputs
Supports live insertion/withdrawal
±24mA output drive (VCC=3.0V)
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500mA
ESD performance:Human body model>2000V, Machine model>200V
Leadless DQFN package
15.11.3. Absolute Maximum Ratings
15.11.4. Pinning
15.12. 74LCX245
15.12.1. General Description
The LCX245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and
is intended for bus oriented applications. The device is designed for low voltage (2.5V
and 3.3V) VCC applications with capability of interfacing to a 5V signal environment.
The T/R input determines the dire