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1
Colour television
Chassis
A8.0E
Training Manual
Contents
Introduction Mechanical Control Power supply Video processing Synchronization Audio processing Horizontal deflection Vertical deflection Teletext + On-Screen Display Widescreen view modes
Published by TG9872 Television Service Department Printed in The Netherlands Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips
2 3 9 24 34 48 50 56 75 78 84
5 4822 727 21648
©Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips Published by TG9872 Television Service DepartmentPrinted in The Netherlands 5 4822 727 21648
2
INTRODUCTION Block diagram
A8.0E
INTRODUCTION Block diagram
1125 TUNER
7150-A IF
YC PIP PANEL Y Y/CVBS IO PANEL C C Y COMB FILTER PANEL C Y C 7150-0 VIDEO PROCESSING Y U V
DW PANEL
YU V
YU V
YUV PANEL
7150-C RGB PROCESSING
RGB AMP SCAVEM
R G B
RGB SWITCH
SIF QSS PANEL AM
SOUND PROCESSING
AUDIO AMPLIFIER
TOP CONTROL PANEL
OSD/TXT CONTROLS
I2C
7150-D SYNC
LINE DRIVE
LOT
220V
SUPPLY SMPS
EW+ PANORAMA PANEL
+140 +33 +14 +8 +15 +5 +5 - STBY
FRAME AMPLIFIER
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·
·
·
· ·
·
·
·
A Switched Mode Power Supply (SMPS) is used to supply the line deflection stage (+140), the sound output stage (+15) and a number of other low voltages (+14V, +8V, +5V and +5V Standby) The controls located on the mono carrier are activated by the keyboard and RC5 signals from the remote control receiver. The internal control is via I2C. The 38.9 MHz IF video signal coming from the tuner is fed to the TDA884x (IC7150). This IC incorporates the video processing circuitry (PAL, NTSC and SECAM), synchronisation and geometry control. The sound processing section of the set is multi standard and uses a MSP3410 (mono, 2CS stereo and NICAM). In some stereo sets (mainly NICAM and FM DK) the QSS panel (Quasi Split Sound) will be applied to improve the SIF signal The CRT-panel contains integrated RGB amplifiers and SCAVEM circuitry. The RGB signals are then transmitted to the picture tube via the RGB amplifiers. The horizontal and vertical deflection signals (line and frame) are amplified in the driver stages, which drive the deflection coils. In all sets except 21" E/W correction is needed which is accommodated on a separate panel. For 16:9 sets the panorama circuitry is also accommodated on this panel
Personal notes
A8.0E
Mechanical Chassis Set-up
3
Mechanical Chassis Set-up
POWER SUPPLY HOR. DEFLECTION + LINE OUTPUT VERTICAL DEFLECTION TUNER + VIF
A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 A13 A14 A15 H
N B C D P M
TOP CONTROL PANEL VIDEO PROCESSING CRT PANEL SYNC EAST WEST PANEL RGB PROCESSING EW + PANORAMA PANEL CONTROLS TXT/EPG PANEL TRANSPARANT OSD SIDE AV PANEL AUDIO PROCESSING NICAM/2CS/FM/AM AUDIO OUTPUT
J I
QSS-DK PANEL QSS (BGLI NICAM)
IO SWITCHING FRONT AV FRONT CONTROL
E
I/O SCART PANEL MAINS FILTER PANEL
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The A8 chassis uses the mono carrier format, however separate modules are utilised for East/West, I/O, Side AV, QSS, Teletext, mains filter and top control. · The mono carrier panel is doublesided, it incorporates SMDs on the solder side. · the control part · video signal processing · source select(front/rear) · IF · sound processing · audio amplifier · horizontal and vertical deflection · power supply · front control(IR, LED) · teletext in the micro-processor. The following miscellaneous panels may be fitted on the mono carrier: · QSS panel · YUV panel · COMB. Filter panel · E/W Panel · OSD panel · incredible sound panel The other external panels are: · Top Control panel · Side AV panel
· · · ·
Mains filter panel I/O panel. PIP panel/ DW panel The CRT panel (contains the RGB amplifier circuit and SCAVEM)
·
·
4
Mechanical Removing the separate mains filter
A8.0E
Removing the separate mains filter
1
2
CL 86532017_101.eps 231298
In order to remove the rear cover from the A8, all screws at the side, the bottom and the top of the rear cover have to be removed. The screws near the I/O cinch connectors should NOT be removed.
·
lift the panel from its bracket
CAUTION!
Remember to disconnect the subwoofer connector !! Unplug the mains power before working on the separate mains filter. CAUTION: The mains filter board carries permanent mains voltage (even when the mains switch is turned off).
Disconnect the separate mains filter panel
To disconnect the separate mains filter bracket from the chassis tray: · · firmly depress the click (with a screwdriver) in the chassis tray (1) push the mains filter bracket in the direction of the CRT
Remove the separate mains filter panel
To remove the separate mains filter panel from its bracket: · push the 2 clips at the right hand side of the mains filter bracket outside (2)
A8.0E
Mechanical Removing the chassis
5
Removing the chassis
1 1
M1 6
2
CL 86532017_102.eps 231298
Service position without the need for a large table or workbench To remove the chassis tray from the cabinet: · · disconnect the degaussing coil (connector M16 on the mono carrier) pull the clips (1) backwards and pull the chassis tray as indicated (2)
Personal notes
The chassis tray should be turned 90 degrees counter clock wise and flipped over to access the copper side of the mono carrier.
6
Mechanical Environment independent position
A8.0E
Environment independent position
2
1
NEL IO PA KET C BRA
3
A
B
CL 86532033_052.AI 180698
For home repair the chassis tray with mono carrier can be fixed in the cabinet. · · · turn the chassis tray 90 degrees counter clock wise (1) flip the tray with the I/O panel towards the CRT (2) press (the hook of) the chassis tray firmly into the designated hole in the cabinet bottom (3) and pull the chassis tray forward (the speaker cables may have to be disconnected)
Personal notes
A8.0E
Mechanical Accessing the I/O panel
7
Accessing the I/O panel
4 4 3 2
(4X)
1
L
S
P
CL 86532017_104.eps 231298
To access the copper side of the IO panel: · · push the clips (1) in the direction of the CRT (If the clips are broken, the I/O panel can also be screwed to chassis tray) slide the I/O panel bracket (2) to its horizontal position
Personal notes
To remove the I/O panel from its bracket: · remove the 2 screws on the connector side of the panel (3) and (4).
8
Mechanical Repairing the mono carrier
A8.0E
Repairing the mono carrier
2
1
CL 86532033_054.AI 180698
For full access to the component and copper side of the mono carrier, it can be removed from the chassis tray. · · push the clicks of the chassis tray outwards (1) lift the mono carrier from the tray (2).
Personal notes
A8.0E
CONTROLS User Menu
9
CONTROLS User Menu
1 2 3 4 5
AV INCREDIBLE GAME INC. SURR. A/CH
1 4 7
SMART
2 5 8 0
3 6 9
SMART
6 7 8 9 10
MENU
SURF
CH
11
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The complete control of TV sets with a A8 chassis is performed via menus. Selections within the menus are made by the arrow keys on the remote control (cursor control).
Personal notes
On the remote control the "smart controls" for picture and sound are present. Pressing one of these buttons will give a pre-programmed change of various audio or picture settings at the same time.
10
CONTROLS Installation
A8.0E
Installation
Installation
· · ·
Automatic (ACI, ATS) Manually DST (RC7150)
Install.eps 231298
Installation of the A8 can be done via the installation menu or via the Dealer Service Tool (DST); 1. With the Installation-menu the installation of the TV can be performed in two ways: · Automatic: The complete TV band is searched and all transmitters are installed. · Manually: The frequencies have to be given for all program numbers. 2. With the RC7150 Dealer Service Tool (DST) · The RC7150 can install a complete TV program table in a single operation.
Personal notes
A8.0E
CONTROLS Dealer Service Tool (DST)
11
Dealer Service Tool (DST)
RC7150
Service Features
Entering the Service Alignment Mode
-
Entering the Service Default Mode Defined settings for tuning and control
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The dealer service tool (DST, RC7150) is a remote control, especially developed for the dealer and service engineer. · Dealer functions With the DST complete program tables can be transmitted to the TV. 10 different tables can be stored in the DST, e.g. for 10 different areas.
Downloading program tables from DST into the TV.
Programming tables into the DST can be performed in two ways: · From the TV (GFL only). If a GFL TV is installed with a complete table of program information the complete table can be transmitted to the DST. As use is being made of the dealer link, the DST must be held at a short distance(within 10 cm) from the IR transmitter LED (next to the stand-by led). With a DST interface (22AV1376). This is a computer interface that can be used with the accompanying computer program to input tables in the computer and transmit these tables to the DST. Service features of the DST for the A8 Activating the Service Alignment Mode. By pressing the "ALIGN" key on the DST the Service Alignment Mode SAM) is activated. Activating Service Default Mode. By pressing the "DEFAULT" key on the DST the Service Default Mode (SDM) is activated.
·
·
12
CONTROLS Service Default Mode (SDM)
A8.0E
Service Default Mode (SDM)
SERVICE DEFAULT MODE
Shortcircuit 9040 & 9041 on the SSP Press the "default" key on the RC7150
Tuner tuned to 475.25 MHz All linear settings in "mid" position Volume set to "low"
CL 86532033_014.AI 160698
Entering the Service Default Mode (SDM):
By transmitting the "DEFAULT" command with the RC7150 Dealer Service Tool. By shorting the jumpers 9040 & 9041 while switching on the set with mains switch.
Personal notes
Exiting the Service Default Mode (SDM): Switch the set to stand-by (the error buffer is also cleared)
Specification of the Service Default Mode (SDM)
Default values of the following must be set according; · · · · Tune to 475.25MHz. PAL/Secam sets Tune to channel 3 (61.25 MHz) for NTSC sets All linear setting at 50%, except volume at 25% Disable service unfriendly modes; Timer Off Sleeptimer Off Hospitality disabled No-ident timer disabled Parental lock disabled The default system (for multi system sets) will be set according to the signal source input at the antenna.
·
A8.0E
CONTROLS Service Default Mode (SDM)
13
Service Default Mode (SDM)
SDM Menu
SDM ERR nn nn nn nn nn nn SDM BRIGHTNESS COLOUR CONTRAST SHARPNESS COLOUR TEMP
+
MENU
PICTURE SOUND FEATURES INSTALL
SDM
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Others features of SDM
· · · · Error codes OSD can be switched on and off with OSD button Switch to user menu by pressing MENU button LED blinks with info of the error in error buffer Start channel search by pressing "P+" button on the remote control
Personal notes
14
CONTROLS Service Alignment Mode (SAM)
A8.0E
Service Alignment Mode (SAM)
SERVICE ALIGNMENT MODE
From SDM via "Vol +" & "Vol -" Press thre "ALIGN" key on RC7150 (DST)
Service Menu
1 n n n n E R R O P R E O A E R P L L A T I 2 A 8 0 E U 1 - 1 . 0 n n n n n n n n n n n n n n n n n O S I G A D D E F A U L T E B U F F E R O N S N M E N T S 3 5 2 6 3 - 2 - 2 3 n n n n n n n n n n 4 5 S A M
n n n
n n n
6
CL 86532033_039.AI 231298
Entering the Service Alignment Mode (SAM
· · During normal operation and SDM by transmitting the "ALIGN" command with the RC7150 Dealer Service Tool. By pressing and holding VOL+ & VOL- keys on the local keyboard for 2 sec. while in SDM
Specification of the Service Alignment Mode (SAM)
1. 2. 3. 4. 5. 6. Operating hour counter (in hexadecimal) Software version Software of separate teletext controller Error code buffer (maximum the last 6 error codes) Option bytes (7 bytes possible) Sub menus · Erase buffer · Option codes · Alignments and geometry information · Reload default values
Specification of the Service Alignment Mode (SAM)
1. Operating hour counter ( in Hexadecimal) 2. Software version 3. Software of separate teletext controller; NOT implemented for A/P. 4. Error code buffer (maximum the last 6 error codes 5. Option bytes (7 bytes possible 6. Sub menus Erase buffer Option codes Alignments and geometry information Reload default values
Error code buffer
Error code Error description Possible defective components E/W Vertical circuit defective,line o/p stage.
0 1
No error detected E/W and/or Vert. protection active/X-ray protection. High beam protection active Reserved
Exiting the Service Alignment Mode (SAM)
· The SAM will be left by the stand-by command. In case the set is switched "off" and "on" again with the mains switch, the set will start up in the SDM again.
2
CRT amplifier circuit or picture tube -
3
A8.0E
CONTROLS Service Alignment Mode (SAM)
5V protection active +5V supply line is low or short circuit IC7150, + 8V supply.
15
4
Personal notes
5
BiMOS s/w protection active or BiMOS register is corrupted BiMOS IIC error General IIC error Main uP internal RAM error OSD generator IIC error NVM addressing error NVM IIC error Histogram IICerror
6 7 8
IC7150 IIC bus s/c or o/c IC7000
9 10 11 12
IC7101 on OSD panel IC7088 IC7088 IC7770 or YUV interface panel IC7430 or IC7437 (BTSC) U1125 IC7350 on PIP panel U1126 or U1127 on PIP panel IC7007 on EPG panel/ IC6 on Guide Plus panel IC7110
13 14
Reserved Sound processor IIC error Reserved Main tuner IIC error PIP processor IIC error 2nd tuner PIP IIC error
15 16 17 18
19
EPG uP/Guide Plus uP IIC error NV-clock IIC error Reserved EPG processor IIC internal RAM error
20 21 22
IC7007 on EPG panel
The error code buffer is written from left to right and contains all errors detected since the last time the buffer is erased. An example can be: ERROR:0 0 0 0 0 0:No error code detected ERROR:6 0 0 0 0 0:Error code 6 is last and only detected ERROR:5 6 0 0 0 0:Error code 6 is first detected, error code 5 last detected · · The last error detected (actual) is indicated on the left hand side. By leaving the SAM with the "standby" function or ERASE BUFFER function the error buffer is reset.
16
CONTROLS Service Alignment Mode (SAM)
A8.0E
Service Alignment Mode (SAM)
Service Alignment Mode
HORSHIFT: HORWIDTH: SERV.BLANK: VERSHIFT: VERHEIGHT: VERSLOPE: EW PARABO: EW TRAPEZ: EW CORNER: VER S-COR: VERZOOM:
Horizontal shift Horizontal width Service blanking Vertical shift Vertical amplitude Vertical linearity E-W parabola E-W trapezium E-W corner Vertical S-correction Vertical zoom
Alignments
· · · · · Selection of the desired alignment by the up/down cursor Change of the selected alignment by the left/right cursor The following alignments are possible (alignments for geometry are for the 4:3 picture format) A value between 0 and 63 can be given for all software alignments Important! Any changed values will only be stored if the geometry menu is exited by pressing the MENU button.
Personal notes
Easy way to adjust vertical geometry (4 X 3) 1. 2. 3. 4. Set vert. S-correction value to 13 Set vert. zoom value to 25 Set vert. blanking to "ON" Adjust vert. slope till test pattern centre line touches the centre edge 5. Adjust the vertical shift and height until the test pattern best fits the screen.
A8.0E
CONTROLS Service Alignment Mode (SAM)
17
Service Alignment Mode (SAM)
SAM Menu
P S F I
I O E N
C U A S
T N T T
U R E D U R E S A L L
B C C S C
R O O H O
I L N A L
G O T R O
H U R P U
S A M T N E S S R A S T N E S S R T E M P 3 5 2 6 3 - 2 - 2 3 n n n n n n n n n n 4 5 S A M
MENU
1 n n n n E R R O P R E O A 6 E R P L L A T I
2
MENU
L O A D N O W D O N ' T L O A D
A 8 0 E U 1 - 1 . 0 n n n n n n n n n n n n n n n n n O S I G A D D E F A U L T E B U F F E R O N S N M E N T S
n n n
n n n O O S A A B 6 B 7 T O R E L K n n n n n n O N O F F
MENU
MENU MENU
G G W T B
E E H U T
O O I N S
M M T E C
E T R Y E T R Y S W E T O N E R S O U N D
H H S V V
O O E E E
R R R R R
S W V S W
H I . H I
I D B I D
F T L F T
n n T n n H A N K I N G n n T n n H
n n n n
MENU
C O L D
R n n n
G n n n
B n n n
MENU
I I A A A
F P L L F P L L G C F A F B
n n n n n n n n n n n
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Options
· Setting of individual options. Selection of the desired "option to be changed" by the up/down cursor. Change of the selected option (ON/OFF) by the left/right cursor or By keying the decimal values in the option bytes 1~7 item The options are activated immediately after they are stored and powered up.
Personal notes
·
Reload Default
By selecting LOAD NOW, the current values stored in the non volatile memory will be over written. Caution: It is used only when the non volatile memory data is corrupted and no other way to recover. Default values are activated when the set is restarted
18
CONTROLS Microprocessor
· ·
A8.0E
Introduction
Microprocessor
Hardware and software diversity.
Europe sets:
· · Master micro processor 83C770 (64k ROM). Slave micro processor on TEXT/EPG panel, dedicated for EPG (Electronic Programming Guide) and Teletext decoding.
PN3:Pal/Multi; NO teletext; English and Arabic PT1:Pal/Multi WITH teletext; English, Malay and Chinese NG1:NTSC; 2CS sound; English and Korean NB1:NTSC; BTSC sound; English and Taiwanese
X = (main version number) Y = (subversion number)
Software identification of a separate Teletext micro controller (DDDD E FF) (not applicable for A8.0A)
Latam and USA standard sets:
· Single micro processor 83C770 (64k ROM). Complete controls including Closed Caption decoding.
NVM
The NVM used for storing the default settings is ST24W16 is 16 KB and is interfaced with the main micro using the S/W I2C bus. This is to avoid any data corruption in the NVM data by controlling the Write CLock of the NVM by the main micro.
Low end USA sets:
· Single micro processor 83C570 (48k ROM).
Asia/Pacific TXT sets:
Personal notes
· Single micro processor SAA5297(masked) or SAA5499 (OTP).Complete controls TXT decoding.
Asia/Pacific NON-TXT sets:
· Single micro processor 83C770 (64K ROM)
Software diversity:
Version Region EUROPE A8EU1.1: Western Europe without EPG A8EU1.2 : Eastern Europe A8EU1.3 : Western Europe with EPG USA A8US1.1 : USA (all) LATAM A8LA1.1 : LATAM (all) Software identification of the main micro controller (A80BBCX.Y) · · A80 is the chassis name for A8.0A BBC is 2 letter and 1 digit combination to indicate the software type and the supported languages: PN1:Pal/Multi; NO teletext; English, Malay and Chinese PN2:Pal/Multi; NO teletext; English and Hindi
A8.0E
CONTROLS Microprocessor
19
Software control lines
Microprocessor
SOFTWARE CONTROL LINES DESCRIPTION for the main micro processor Logic 0 is : 0 V Logic 1 is : +5V
Pin 4: SEL _PIP_FRNT_RR 0 0 1 1
Pin 9: SEL_PIP_R1R2 0 1 0 1
PIP Source Selection REAR1 REAR2 FRONT INTERNAL
Pin 1: PAN_SWITCH/+5V_CNTRL
OUTPUT Activates 16:9 feature (EUROPE only) Activates+5V supply for the PIP board (USA only)
Pin 5: SEL_IF_TRAP_MAIN or L/L'
OUTPUT Select the MAIN IF TRAP and Sound Traps also.
Pin 1: PAN_SWITCH 0 1
Status Default Super Wide Selected in 16:9 sets
Pin 5: SEL_IF_TRAP_MA IN 0 1
A/P
Europe
ON - for NTSC M OFF - for others
ON - for othrs OFF - SECAM L'
Pin 1: +5V CNTRL 1 0
Status +5V OFF +5V ON
Pin 6: POSNEG_QSS or SEL_INCRED
OUTPUT Selects the positive and negative demodulation mode for the QSS IC during SECAM L reception (Europe only). Selects the Incredible Stereo feature (USA only)
Pin 2 & 3: SYS2 and SYS1
OUTPUT Selects the XTALS and Combfilters.
Pin 6: 0 Pin 2: SYS2 0 1 0 1 Pin 3: SYS1 0 0 1 1 System PAL M PAL B,G,H,I,D,K NTSC M PAL N 1
Status - POSNEG_QSS POSITIVE (SECAM L/ L') NEGATIVE (Others)
Status - INCRED Incredible stereo is on
Incredible stereo is off
Pin 7: SDM
INPUT Service Default Mode is activated by shorting this pin to GND.
Pin 4 & 9: SEL_PIP_FRNT_RR & SEL_PIP_R1R2
(valid for PIP sets) OUTPUTS Selects the PIP video source from rear I/O, main or front.
Pin 8 & 14: SEL_MAIN_R1R2 & SEL_MAIN_FRNT_RR
OUTPUTS Selects the MAIN video source from INTERNAL, FRONT or REAR.
20
CONTROLS Microprocessor
A8.0E
Pin 14: SEL_MAIN_FRNT_ RR 0
Pin 8: SEL_MAIN_R1R2
MAIN Source Selection
Pin 10: Function AFC_TUNE R2 Output of Analog tp Digital Converter 0
ADC
Input DC voltage
0
REAR1 (AV2/ SVHS) REAR2 (AV1)
0 - 0.5 1 1.5 2 2.5 3 3.5 4 4.5
0 1
1 0
1-2 FRONT (AV3/ SVHS) INTERNAL 3-4 5-6 7-8 9 - 10 11 - 12 13 - 14
1
1
Note: For Multimedia and Institutional TV Interface pin 8 will be configured as TV CLK.
Pin 9: STAT2 or SEL_PIP_R1R2
(valid for non PIP sets) ADC input. Detects the presence of SCART2 Video source (CVBS) and also whether it is 4:3 or 16:9 video source.
15
Input Controls the Eco Double Window.
Pin 9: STAT2 ADC VALUES 0-4 5 - 10 11 - 15
Status - SCART2 Video Internal Video External 16:9 External 4:3
Pin 10: SYS_ECO_DW 0 1
System Status 50 Hz 60 Hz
Note: For Multimedia and Institutional TV Interface this pin will be configured as DATA IN.
Pin 10: STAT_EXT 1/ AFC_TUNER2/ SYS_ECO_DW
ADC input Comparator to sense different DC levels from I/O to indicate the presence of an EXTERNAL SCART video sources (CVBS), 4:3 or 16:9 SCART video.
Pin 11: FRNT_CNTRL
INPUT ADC Connected to the keyboard and protection line PROT_E_W. The keys are read by applying a unique voltage.
Input DC Voltage Pin 10: STAT1 ADC VALUES 0-4 5 - 10 11 - 15 Status - SCART1 Video Internal Video External 16:9 External 4:3 0 1V5 2V1 2V7 3V4 4V 5V
Function ketboard read Protection Program Up Program Down Menu (not forLatam) Volume Up Volume Down No Key Pressed
ADC input (Valid for NTSC-M) Indicates for the 2nd tuner PIP application for Y/C PIP and named AFC_TUNER2.
A8.0E
CONTROLS Microprocessor
0 1 MUTE OFF MUTE ON
21
Pin 12: POR2
OUTPUT Provides Power On Reset pulse during start-up for 2nd microp (both EPG and non-EPG boards used in Europe sets) and GEMSTAR decoder boards used for USA sets. For 2nd micro-p board the POR2 is high for at least 2 machine cycles when the oscillator is running and then go back to LOW. For Gemstar the POR2 must go from LOW to HIGH and remain HIGH during start-up Note: For Multimedia and Institutional TV Interface this pin will be configured as DATA IN.
Pin 18 : STAT_HP
INPUT. To sense the presence of a Head Phone jack.
Pin 18: STAT_HP 0 1
Status Headphone NOT connected Headphone connected
Pin 14: SEL_MAIN_FRNT_RR
See pin 8
Pin 19: STBY
OUTPUT To switch between standby and normal operation.
Pin 15: SVHS_MODE
OUTPUT Select/deselect the external SVHS or the CVBS inputs
Pin 19: STBY Pin 15: SVHS_MODE 0 1 Select SVHS CVBS 1 0
TVStatus In Stand-by Mode in Normal Operation
Pin 20: LED
OUTPUT
Pin 16: DEGAUS
OUTPUT Controls the DEGAUS circuit in the Power Supply block. During power ON this pin gives low going pulse for 2 seconds.
Pin 20 0
Europe LED brighter = Standby LED dimmer = normal operation
AP/Latam LED lighted = Standby LED OFF = normal operation
USA LED lighted = normal LED OFF = Standby
1 Pin 16: DEGAUS '0' for 2 seconds and then goes to '1'
Pin 17: AMP_MUTE1
OUTPUT Mutes the Audio Output Amplifier
Pin 21 SAA5297/P83C770: SEL_GAIN_SPLIT/ SEL_TUNER1_2
OUTPUT Selects the gain of the antenna splitter of the 2nd tuner for PIP (A/P and LATAM sets only).
Pin 17: AMP_MUTE1
Status
22
CONTROLS Microprocessor
Output
A8.0E
Pin 21: SEL_GAIN_SPLIT 0 1
Attenuation OFF ON Pin 51: RGB_KILL 0 1 Status Default Kill External RGB
OUTPUT Selects between the MAIN tuner 1 and MAIN tuner 2. (USA and 2 Tuner PIP sets only).
Pin 52 of P83C770 : FFBL_EXT/4_NORMA_SEL
Pin 52: FFBL-EXT Pin 21: SEL_TUNER1-2 0 1 Tuner 1 Tuner 2 0 Not selected Selected Selected Not selected 1
Status RGB present on the SCART No RGB on the SCART
Pin 30 P83C770: RMT_LOC_DATA
OUTPUT Signal: DATA to the REMOTE LOCATOR circuit (USA only), others this pin is pulled to "high" via 3063.
For LATAM sets this pin is used to select the respective crystals 4 or 2/3 Norma sets. This is configured by hardware as LOW or HIGH depending on the crystals connected to the BiMOS.
Pin 52: 4 NORMA_SEL 0 1
Status Selects 4 Norma Selects 2 or 3 Norma
Pin 46 for SAA5297 and P83C770 : WRITE_CTRL
OUTPUT
OTHER PIN DETAILS
Pin 13: Ground
Selects the global write protection control of the EEPROM (IC7088).
Ground line for digital circuits for SAA5297 and P83C770 Pin 22: VSSA (For SAA5297 and P83C770 ) Ground line for analog circuits Pin 23: Ground Input CVBS from which closed caption for USA/LATAM or TEXT data for EUROPE/AP is to be extracted. A positive going 1V (peak-to-peak) input is required. Pin 24: STN For P83C770 and CVBS1 for SAA5297
Pin 47 SAA5297/P83C770 : SCL_EEPROM
Clock output EEPROM I2C bus.
Pin 48 SAA5297/P83C770 : SDA_EEPROM
Data in - output EEPROM I2C bus.
Pin 49 SAA5297/P83C770 : SCL
Clock output of master I2C bus. For a survey of all connected ICs to this bus see the diagram "I2C overview" in the service manual.
For SAA5297 this data slicer decoupling capacitor input, connect to VSSA via a 100 nF capacitor (C2054). Pin 25: BLACK & BLK (For SAA5297 and P83C770 )
Pin 50 SAA5297/P83C770 : SDA
Data in - output of master I2C bus. CVBS signal black level reference, connected to VSSA via 100 nF capacitor (C2055). Pin 26: IREF (For SAA5297 and P83C770 )
Pin 51: RGB_KILL
(Valid for SCART sets !)
A8.0E
CONTROLS Microprocessor
For SAA5297 this pin is connected to crystal oscillator gnd. For P83C770 this pin is the Digital Ground.
23
CVBS signal reference current input, connect to VSSA via a 27K resistor (R3058) Pin 27: TEST (For SAA5297 and P83C770 )
Pin 41 for SAA5297 and P83C770 : XTALIN This pin is connected to +5V via 10 K Ohms resistor (R3060) This is XTAL oscillator INPUT pin Pin 28: TEST (For SAA5297 and P83C770 ) Pin 42 for SAA5297 and P83C769 : XTALOUT This pin is connected to Digital gnd for SAA5297. For P83C770 this pin is pulled to high via 3061. Pin 29: TEST (For SAA5297 and P83C770 ) This pin is connected to +5V via 10 K Ohms resistor (R3062). Pin 31: RGBREF & REFH (For SAA5297 and P83C770 ) For SAA5297 this is the DC input voltage to define the output HIGH level on the RGB pins, For P83C770 this is the data slicer reference high capacitor input connected to VSSA via 100 nF capacitor (C2070). Pin 32 to 35 (For SAA5297 and P83C770 ): FBL, R, G and B Outputs 'RED', 'GREEN' and 'BLUE' deliver the colour components for the OSD, while output 'Blanking' is used as a fast blanking signal to insert R, G and B signals in the television picture. The output polarity of all four pins is active high. Pin 36: HSYNC for OSD /TXT (For SAA5297 and P83C770 ) This signals is derived from the deflection part to get a stable OSD picture on the television screen. The 'HSYNC' pins is supplied with active low horizontal sync pulses (polarity is software programmable). Pin 37: VSYNC for OSD/TXT (For SAA5297 and P83C770) This signal is derived from the deflection part to get a stable OSD picture on the television screen. The 'VSYNC' pin is supplied with active low vertical sync pulses (polarity is software programmable). Pin 38 for P83C770 & SAA5297 : VDDA This pin is connected to +5VA Pin 39: VDDT for SAA5297 & VDD_P P83C770 For SAA5297 this pin is connected to +5V Teletext power supply. For P83C770 this pin is the Digital periphery power supply. Pin 40: OSCGND for SAA5297 & VSS_D for P83C770 This is XTAL oscillator OUTPUT pin. All internal timing of the micro-controller is derived from this oscillator The oscillator frequency has to be 12MHz. Pin 43 for SAA5297 and P83C769 : POR 'POR' is used to reset the micro-controller after a power-on reset. This reset signal has to be HIGH until a stable 5V supply voltage is available and then it goes LOW. Also when the supply voltage drops below the minimum required voltage the micro-controller has immediately to be reset via pin 'POR'. Pin 44 for SAA5297 and P83C770: VDDM For SAA5297 and P83C770 this pin is +5V micro-controller power supply. Pin 45 for SAA5297 and P83C770 : RC-5 This input pin is connected to an RC5 remote control receiver(TFMS5360). The input should be high when no remote control signal is received. Pin 52 for SAA5297 and P83C770: N.C For SAA5297 and P83C770 this pin can be used as an I/O port and is not connected. Pulled to "high".
Some hints on problem solving
No LED or IIC activity - Check for the +5V_STBY and the POR pulse Set always in standby - Check +8V of BiMOS LED Blinking - The set may be on protection. Check pin 11 No LED blinking to RC5 - Check NVROM No OSD/TXT - Check H sync on pin 36 No TXT- Check CVBS_TXT on pin 23 and +5V at pin 39.
24
POWER SUPPLY Degaussing
A8.0E
POWER SUPPLY Degaussing
*3908
+t ZPB 2
PTC
1
3
2
}
M16
TO DEGAUSSING COIL
1
*3906
PTC
*9950
0132
TO F15 OF MAINS FILTER
{
M15
2
1 3
2 4 +13V
10K 3910 BZX79-C3V3 6920 1N4148 6935 13V4
3911 4K7 13V4
6992 BZX79-C9V1
DEGAUS
A8-05
1
*
9999 3
BC557B 7900 0V RELAY SWITCHER
3950
2M2
G5P-1
1901 1N4148
4
6904 22n
2
1
2908
CL 86532033_011.AI 160698
The degaussing circuit is activated whenever the TV set is turned on. So from normal off to on and from stand-by to on the degaussing circuit is activated. During start-up the signal degaus (A8-05) is high which blocks TS7900. After start-up of the uP the signal degaus (A8-05) becomes low for 3 seconds which forces TS7900 in conduction. Now the +13V is put on the coil of the relay and switch G5P-1 is closed. The degaussing current passes through the degaussing coil. After three seconds, DEGAUS goes high, 7900 turns off , 1901 is deenergised and no current passes through the degaussing coil at normal operation due to the fact that switch G5P-1 is opened. PTC 3906 is present in 220V sets and PTC 3908 is present in 110V sets.
Personal notes
A8.0E
POWER SUPPLY General information
25
General information
CL 86532033_049.AI 160698
26
POWER SUPPLY General information
A8.0E
The A8 power supply is a Switch Mode Power Supply(SMPS) with minimum voltage switch. The topology is a flyback converter with primary current sensing, secondary voltage sensing and mains input Voltage measuring. The power supply is built with IC 7902 which has a built-in MOSFET and control circuit. The frequency ranges for normal operation are 25kHz to 130kHz (full range) and 40kHz to 130kHz (single range and 120V). The SMPS works in discontinuous mode, so with a T-on, T-off and a Tdead. The FET is switched on during T-dead when the voltage at the drain of the built-in FET (IC7902 pin 3) is minimal due to oscillation of C2913 and the primary inductance of T5912. This is reducing the switching losses.
Personal notes
Output voltages
· · · · +14V (For Line Circuit and input voltage for stabilizer 7908) : +13.5V. If +14V and +8V are not present check 1905. +33V (For Tuner) : +33V. Created via R3994 and zenerdiode 6955 Vbat (Battery Voltage for Line Output Stage) : +140V (9917 present) or +130V (9918 present). +8V (Bimos Supply ) : +8.3V. Output voltage from stabilizer 7908. This voltage is decreased in standby to 2V3. In standby TS7909 is conducting and switching R3933 parallel to R3932. This will decrease the output voltage of 7908. +5Vstby (P Supply) : +5.1V. This voltage is also present during standby. If this voltage and +5V are missing check 1906. If the voltage at pin 1 and 2 of IC7907 are present replace 7907. +5V (For Tuner, QSS, BTSC or ITT etc) : +5.1V. This voltage is disabled when the +13V is not present at pin 3 of IC7907. +13V is generated by the line-output circuit. So when the line-output circuit is working correctly the +5V is enabled and the POR signal is generated to start the set. +15V ( Audio Supply) : +18V or +14V
·
·
·
A8.0E
POWER SUPPLY Control circuitry
27
Control circuitry
DEMAGNITIZING DETECTION CIRCUIT
2904 2n2
1N5062
3902
9954
9952 1R5
2905
2n2
* *
*
6933
*9956 *
3905 -t NTC
4
6903 GBU4J 3
*
1
*
1N5062
6931
1N5062 2
* 6930
P1 290V (301V)
2906
470u
2911
100K
3995
22n
*
*
6932
1N5062
* 5912
1 2 3
TRANSFORMER
18 17 16 15 14 13 12 11 10
*
*
BYD33M 6906
*
100P 2971
4 5 6 7
5911
*
*
P3
100K
3941
3917
2M2
* * * 3959
3R3
8 9
*
6908 BYD33J P2
2920
10n 2912
* 17V6 (15V6) *7902 STR-F6626
4 1
VIN OCFB GND D S
47u
3920
2
2966
3n3
(301V) 290V 3
2913
3962
*
P5 6911 BYD33J
*
1K5 2914 1n5
P4
100mHz
3991
3922
2915
470p
680R
3924
0R1
5906
*
*
2K7
1V6 (0V7)
5
0V (0V)
1n5
3K3
*
BYD33J
6910
*
CL 86532033_005.AI 030898
Mains input circuit
The mains voltage is rectified by bridge rectifier D6903 or D6930 ,D6931 ,D6932, D6933 and filtered by C2906 . The DC voltage across C2906 is the DC input voltage for the SMPS at pin 6 of transformer T5912.
Start-up circuit
IC7902 is started when the voltage present at pin 4 is high enough. When the set is switched on, C2912 is charged through start-up resistor R3917. When the voltage across C2912 reaches 16V (Typical), the control circuit of IC 7902 starts to operate.
R3924 increases due to the increase of the drain current. When the voltage of pin 1 of IC7902 reaches the threshold voltage Vth(1) =0.73V, the MOSFET turns off. The voltage of pin 8 of T5912 becomes now positive . Power supply flybacks at this moment (so energy is released at the secondary side). Voltage applied at pin1 of 7902 is determined by the turn ratio of the transformer T5912 and R3962, R3991 ( Typical voltage is 3.5V) . This voltage is higher than threshold voltage Vth(2) (1.37V). Until the transformer is demagnetized, this voltage remains high. Once the energy stored in the transformer is fully transferred to the secondary side, the voltage at pin1 of IC7902 drops below the threshold voltage Vth1 after a certain delay time and a new cycle starts.
After the control circuit starts its operation, power is supplied by smoothing and rectifying the voltage of the supply winding ( 89 ) of T5912. The supply winding reaches the operation voltage before the voltage of C2912 drops below the shutdown voltage. Consequently, the control circuit can continue its operation.
Control circuit and oscillation phase
IC 7902 has two internal comparators . The thresholds of these two comparators are 0.73V and 1.37V. During T-on , the MOSFET inside IC7902 is conducting . The voltage across
28
POWER SUPPLY Control circuitry
A8.0E
Control circuitry
SECONDARY VOLTAGE MEASUREMENT 2
(7V7) 2V9 11V5 (10V) 4 TCDT1101G 7950 (15V6) 5 17V6 1 2 REGULATOR OPTO-COUPLE 12V5 (11V) PIN 2 OF IC 7904 (MEASURING OUTPUT VOLTAGE) 13V
* 5912
1 2 3 4 5 6 7
TRANSFORMER
18 17 16 15 14 13 12 11 10
*
6908 2920 10n 2912 47u BYD33J P2
3959 8 3R3 9
*
D S
3920
2 2913 1n5
2966
3n3
(301V) 290V 3
3962
*
P5 6911 BYD33J 3991
*
1K5 2914 1n5
P4
100mHz
3922 2915 470p 680R
3924
*
CL 86532033_003.AI 030898
0R1
5906
*
*
2K7
0V (0V)
3K3
*
6910
P3
17V6 (15V6) 7902 STR-F6626 4 VIN 1 OCFB GND 1V6 5 (0V7)
BYD33J
*
A8.0E
POWER SUPPLY Control circuitry
29
Regulation
Control circuitry
Secondary voltage sensing
IC7902 (SMPS IC) and 7950 (Opto-Coupler ) form the secondary voltage regulation circuit. The error amplifier feedback is fed to the control circuit (7902, pin 1) by the optocoupler. The feedback is realized as follows:
Personal notes
When the output voltage Vbat increases (decrease of the load ), the voltage at the base of the internal transistor of IC7904 increases. As a result, the collector current of the internal transistor of IC7904 and the current through the diode in the opto-coupler 7950 increases. At the same time, Vce of the transistor part of 7950 decreases. Therefore, the voltage across C2915 increases. This will shorten the T-on time of the MOSFET of IC7902 The opposite story is valid for an increasing load (decrease of the output voltage Vbat). In case of a short-circuit between pin 3 and 2 of IC7902 check snubber circuit 2911, 6906,2971 and R3995.
30
POWER SUPPLY Control circuitry
A8.0E
Control circuitry
PRIMARY - CURRENT MEASUREMENT
2904 2n2
1N5062
3902
9954
9952 1R5
2905
2n2
* *
*
6933
*9956 *
3905 -t NTC
4
6903 GBU4J 3
*
1
*
1N5062
6931
1N5062 2
* 6930
P1 290V (301V)
2906
470u
2911
100K
3995
22n
*
*
6932
1N5062
* 5912
1 2 3
TRANSFORMER
18 17 16 15 14 13 12 11 10
*
*
BYD33M 6906
*
100P 2971
4 5 6 7
5911
*
*
P3
100K
3941
3917
2M2
* * * 3959
3R3
8 9
*
6908
2920
10n 2912
47u
BYD33J P2
* 17V6 (15V6) *7902 STR-F6626
4 1
VIN OCFB GND D S
3920
2
2966
3n3
(301V) 290V 3
2913
3962
*
P5 6911 BYD33J
*
1K5 2914 1n5
P4
100mHz
3991
3922
2915
470p
680R
3924
0R1
5906
*
*
2K7
1V6 (0V7)
5
0V (0V)
1n5
3K3
*
BYD33J
6910
*
CL 86532033_006.AI 160698
Primary current measurement
The current through the MOSFET of IC7902 is also going through R3924 which increases the voltage on C2915 and so the voltage on pin1 of IC7902. This will shorten the on-time of the MOSFET.
Personal notes
A8.0E
POWER SUPPLY Control circuitry
31
Control circuitry
MEASURING MAINS - VOLTAGE
2904 2n2
1N5062
3902
9954
9952 1R5
2905
2n2
* *
*
6933
*9956 *
3905 -t NTC
4
6903 GBU4J 3
*
1
*
1N5062
6931
1N5062 2
* 6930
P1 290V (301V)
2906
470u
2911
100K
3995
22n
*
*
6932
1N5062
* 5912
1 2 3
TRANSFORMER
18 17 16 15 14 13 12 11 10
*
*
BYD33M 6906
*
100P 2971
4 5 6 7
5911
*
*
P3
100K
3941
3917
2M2
* * * 3959
3R3
8 9
*
6908 BYD33J P2
2920
10n 2912
* 17V6 (15V6) *7902 STR-F6626
4 1
VIN OCFB GND D S
47u
3920
2
2966
3n3
(301V) 290V 3
2913
3962
*
P5 6911 BYD33J
*
1K5 2914 1n5
P4
100mHz
3991
3922
2915
470p
680R
3924
0R1
5906
*
*
2K7
1V6 (0V7)
5
0V (0V)
1n5
3K3
*
BYD33J
6910
*
CL 86532033_004.AI 030898
Control due to the mains voltage
A sample of the rectified voltage is fed to pin 1 of IC7902 by using potential divider resistors R3924, R3922 and R3941. The higher the input voltage, the more the transformer current is limited. In this way the maximum power of the power-supply is limited.
Personal notes
32
POWER SUPPLY Control circuitry
A8.0E
Control circuitry
2904
2n2
1N5062
3902
9954
9952 1R5
2905
2n2
* *
*
6933
*9956 *3905-t
NTC
4
6903 GBU4J 3
*
1
*
1N5062
6931
1N5062 2
* 6930
P1 290V (301V)
2906
470u
2911
100K
3995
22n
*
*6932
1N5062
* 5912
1 2 3
TRANSFORMER
18 17 16 15 14 13 12 11 10
*
*
BYD33M 6906
*
100P 2971
4 5 6 7
5911
*
*
P3
100K
3941
3917
2M2
* * *
3959 3R3
8 9
*
6908
2920
10n 2912
47u
BYD33J P2
P6
* 17V6 (15V6) *7902 STR-F6626
4 1
VIN OCFB GND D S
3920
2
2966
3n3
(301V) 290V 3
2913
3962
*
P5 6911 BYD33J
*
1K5 2914 1n5
P4
100mHz
3991
P6 POWER
3922
2915
470p
680R
3924
0R1
5906
*
*
2K7
1V6 (0V7)
5
0V (0V)
1n5
3K3
*
BYD33J
6910
5V / div AC 0.2ms / div
*
CL 86532033_007.AI 180698
Protection
IC7902 has a latch circuit which latches when the thermal shutdown circuit or the over voltage shutdown protection circuit becomes active. The Latch circuit continues to stop the operation of the power supply when overvoltage protection or thermal shutdown circuit are or were in operation. As long as the sustaining current of the latch circuit is supplied via R3917 (start-up resistor) the power supply circuit sustains OFF. A restart can be arranged by switching off the mains voltage and subsequently switching on again. If IC7902 is in protection the oscilloscope wave form P3 can be measured at pin 4 of IC7902.
secondary output which is caused when the control circuit is open . Check in this case IC7904, IC7950 and the +142V.
Power supply Under-voltage behavior
In the event of a secondary voltage being short-circuited or excessively loaded, the voltage on winding 8-9 of T5912 is decreasing and so is the voltage of pin 4 of IC7902. When this voltage drops below the shutdown voltage, IC7902 stops operating. This will enable an increase of the voltage on pin4 via R3917. Under voltage can be identified by the supply rhythmically re starting.
Thermal protection
The thermal shutdown circuit triggers the latch circuit when the frame temperature of IC7902 exceeds 140C (typ).
Over-voltage protection
The over-voltage protection circuit, triggers the internal latch circuit of IC7902 when the voltage across C2912 exceeds 22.0V (typ). Since the voltage across C2912 is supplied from the drive winding (8-9) of the transformer and this voltage is proportional to the output voltage, it prevents overvoltage at the
A8.0E
POWER SUPPLY Low power stand-by
33
Low power stand-by
(7V7) 2V9 11V5 (10V)
P6
TCDT1101G 7950 (15V6) 5 17V6 1
12V5 (11V)
3976
1K8
4
2
REGULATOR OPTO-COUPLE
3944
*
820R
3926
4K7
=H =L
10K BZX79-C10 3947
6940
STBY
A8-01
3948
3946
5K6
3945
*
3943
2919
1m
*
(-1V5) 0V6 7961 BC847B
7962 BC847B
*
*
7963 BC847B
*
*
0V OSCILLATOR (0V6) +5V_STBY
CL 86532033_010.AI 080698
LOW POWER STANDBY CONTROL
ON-OFF SWITCH OSCILLATOR
CL 86532033_010.AI 160698
To create a very low power consumption during standby, the SMPS is forced in burst mode. An oscillator formed by TS7961, TS7962, C2945, C2946, R3945 and D6940. During normal operation this oscillator is blocked by TS7910 via TS7963. During standby the oscillator is activated. The output of the oscillator is present at the collector of TS7960. When TS7960 is conducting, current is flowing through the diode of opto-coupler 7950 and the transistor part of IC7950 becomes saturated, which causes the voltage across C2915 to raise above 3V. This will prevent the oscillator of IC7902 from oscillation. Without any switching of the FET of IC7902 no switching losses will occur which will decrease the power consumption in standby. When TS7960 turns off, the SMPS will start working again. So in standby the power consumption will be low but the ripple on the output voltage will be higher. This is no problem due to the fact that the set is not operating.
Personal notes
22K
0V6 (0V)
3965
11V5 (0V6)
10K 0V (0V7) 7960 0V BC847B (7V2)
0V (0V6)
7910 *BC847B
*
22K
* 2947 1n
* * *3949 *2945 33n
* * *2946
100n
82K
13V5 (0V3)
5K6
34
VIDEO PROCESSING Tuner
A8.0E
VIDEO PROCESSING Tuner
Tuners The TELE9-087A for PAL MULTI. The TELE9-108A for PAL MULTI China. The TELH9-205A for NTSC-M only sets
The A8 chassis uses a PLL controlled tuner. The tuners are full band, but dependent on the system (PAL/SECAM/NTSC) the tuning range is as follows
Positive modulation system SECAM L' frequency range 44.75-110.25 MHz 110.25-890.00 MHz
Pal frequency range SECAM L Band low mid high frequency range 44.75-150.25 MHz (E2-S7) 150.25-426.50 MHz (S8-S36) 426.50-890.00 MHz (S37-E69) System B,G,H L I NTSC frequency range L' (band I) Band low mid high off-air/cable channels D,K China 55.25-127.25 MHz M 133.25-361.25 MHz 367.25-801.25 MHz 45.75 42.17 41.25 38. 0 33.57 31.5 32.15 33.9 38.33 40.4 picture 38.9 38.9 38.9 colour 34.47 34.47 34.47 sound1 33.4 32.4 32.9 32.35 sound2 33.16
Systems B,G,H,I,L,L',D, K,M and N can be received with the A8 chassis. Be aware that for most pattern generators the maximum tuning frequency is 860.00 MHz. At pin 9 of the tuner 33V (+VT =Voltage Tuning) has to be present for tuning a channel. This 33V is derived (via R3994 68k and D6955 33V zener diode) from Vbat (+140V) from main power supply (diagram A1).
A8.0E
VIDEO PROCESSING Block diagram video path without PIP
35
Block diagram video path without PIP
TELE9-087A OSD/TXT/SCART etc TUNER IF CVBS+SIF IF SOUND BPF SOUND TRAP FBL R G B
TDA884X
RGB PROCESSING +SWITCH
R G B TO CRT
SIF (to sound proc..) SWITCH
CVBS_INT CVBS_EXT
CHROMA PROCESSING
MATRIX
CVBS_MON YC/CVBS_EXT YC/CVBS_EXT YC/CVBS_EXT COMB (opt.)
Y
C
Y U V TDA9178 (opt.)
(NOT FOR EUROPE) (NOT FOR EUROPE) CVBS_MON
bdwithoutpip_k.eps 231298
The single chip TDA8844 (IC7150) processor is used to perform the following tasks: IF-detector, CVBS and SVHS source select, luminance and chrominance separator, PAL/ NTSC/SECAM chrominance decoder, video controller and horizontal & vertical sync/geometry-processor. The difference with previous TV-processors is that the SECAMdecoder is integrated and also the delay-line. Three video-signal flow diagrams are possible in the A8 chassis: · · · video path without PIP video path with YUV PIP (for Latam/AP) video path with YC PIP (for Taiwan/Korea)
Personal notes
The IF signal is fed to pin 54 of IC7150 (TDA8844). The demodulated CVBS is available on pin 6 and fed back to pin 13 for I/O-switching. The selected video-signal on pin 38 is fed to I/O SCART/Cinch and optional a comb-filter. Without combfilter is the video-signal internally processed, but the front-end signal can always be measured on pin 38 IC7150 to check correct tuning. YUV is fed to the TDA9178 (pin 28, 29, 30) and then from here to the RGB matrix via pins 27, 31 and 32.
36
VIDEO PROCESSING IF Demodulation (IC7150-A)
A8.0E
IF Demodulation (IC7150-A)
The video-signal is demodulated by means of a PLL carrier regenerator (no external LC-circuit anymore only a RC-network on pin 5 which determines the IF-loop filter). Internal there is a frequency detector and a phase detector. During acquisition the frequency detector will tune the VCO to the right frequency. The initial adjustment of the oscillator is realized via the IIC-bus. In the service menu IF-PLL is indicated, but this alignment has no effect anymore.
level). As R3131 is shortened, the AGC time-constant is shortly reduced giving a faster response.
Automatic Frequency Control (AFC)
The TDA8844 IC incorporates an alignment free IF-PLL concept which facilitates automatic frequency control via the I2C control. As a result of using this method, a separate AFC control control voltage is no longer required. Complete control is therefore accomplished via software. For search tuning two input signals (internally in the TDA8844) are used: video IDENT and AFC. If a transmitter is tuned the IDENT is valid and a digital AFC level is followed (as long as the IDENT is valid). Automatic Channel Installation (ACI) is possible with the A8 chassis. All channels will be stored according to the ACI-data. This data is a hidden (not selectable for the customer) txtpage(s). If ACI is not used by the cable network then the auto-store procedure is used. For Europe the channels found will be stored beginning from max. program number downwards. For Asian Pacific the channels found will be stored beginning from program 1 upwards.
Automatic Gain Control (AGC)
AGC control is used to maintain a constant signal at the tuneramplifiers when the incoming signal on pin 49 and 48 of TDA8844 becomes too high (above the take-over level). The take-over level (limiting point) of the AGC-control can be adjusted via I2C in the service menu. For negative modulation (BGIDKM systems have all negative modulation) the AGC circuit detects the top-sync level. The AGC DC signal from pin 54 TDA8844 is fed to pin 1 of the tuner. In normal situations (not at program switching) the AGC DC signal is smoothed by C2126 and R3126. To enable a fast AGC control at program switching, D6130 or D6131 shorten R3131 at high AGC peaks (a program switch gives a fast change from low to high or from high to low HF
A8.0E
VIDEO PROCESSING IF Demodulation (IC7150-A)
37
For Germany, Austria, UK and Switzerland, the stored channels will be stored according to a table in the software (ATS).
Personal notes
Sound trap
The baseband CVBS signal (pin 6 of TDA8844), with a nominal value of 2Vpp, also contains the sound signals (FM demodulated mono sound for intercarrier sound processing; see Audio Processing) at a subcarrier of 4.5 / 5.5 / 6.0 / 6.5 MHz. These sound signal are filtered out by the sound trap crystals 1167,1168 and (selectable) 1165. Crystal 1167 is a 5.5 /5.75 MHz or triple trap 5.5/5.75/6.5 MHz ceramic filter, and crystal 1165 is a 4.5 MHz (for NTSC-M) ceramic filter (crystal 1168 is reserved and can be used as a 6.0 MHz sound trap for PAL/ NICAM I, or NTSC-M sound trap of 4.5MHz). For audio various concepts are possible: BASICFM mono/ AM mono NICAMFM stereo / NICAM BG/I/L'/M 2CS onlyFM mono/stereo BTSCmono/stereo and SAP (Second Audio Program)
BASIC
For the BASIC set, the FM-sound is demodulated by IC7150 (TDA8844). The baseband video-signal is fed via bandpass filter 1158 to pin 1 of IC7150. The mono output is pin 15. For AM-sound comes from Quasi Split Sound pin 10 IC7401 (TDA9810 on QSS-panel). The demodulated AM-signal is directly fed to the amplifier.
NICAM, AM Sound
The IF-output from the tuner is also fed to the QSS-panel (Diagram I). On the QSS-panel are two SAW filters used depending on system L/L'. Also the IC is internally switched via pin 7 because of different IF-sound frequencies. The demodulated AM-sound is available at pin 6 and fed to IC7430 (MSP3410D) for further sound selection. The IF-sound output pin10 IC7401 is fed to the MSP3410D. This IC can demodulate NICAM, 2CS and MONO signals.
2CS
The baseband output from IC7150 pin 6 is fed to the MSP3400C (without NICAM) for further demodulation.
BTSC/AV stereo
The baseband signal from IC7150 pin6 is fed to IC7437 (TDA9855) for decoding and sound processing. One of the rear cinch inputs, and the signal from the front cinch connectors is selected by IC7436 (HEF4052). The selected signal is fed to the TDA9855 (pin 12 and 41).
38
VIDEO PROCESSING I/O switching with SCART REAR I/O panel
A8.0E
I/O switching with SCART REAR I/O panel
The block diagram below shows the I/O switching from the external inputs for sets with a SCART REAR I/O panel ( see Diagram E). The input of SCART1 is CVBS + RGB + LR and the output is always the video (+ sound) signal from the tuner (CVBS_INT). The input of SCART2 is YC + CVBS + LR. The output signal on SCART2 is CVBS_MON (+ sound), except when SCART2 is selected as the source for the main picture. Then the output on SCART2 is CVBS_INT (+ sound). SEL-MAIN-R1R2 is the selection between SCART1 (R1) and SCART2 (R2) via IC7100-A. With SEL-FRNT-RR selection is made between front and rear (IC7250 chassis).
Personal notes
A8.0E
VIDEO PROCESSING RGB - switching
39
RGB - switching
In A8 there 4 possible RGB sources: · · · · TXT and/or OSD from uP OSD from PCF8515 OSD generator EPG External RGB from SCART or Guide Plus (GEMSTAR)
·
The RGB_KILL signal is used to overrule an external RGB source from SCART.
Status signals
There are 3 status signals which come from SCART REAR I/O panel. With the information which comes from these status signals the set is set to the correct mode.
In previous chassis there was also RGB from PIP possible. In the A8 chassis the PIP/DW panel is in the YUV or Y/C signal path (see also the block diagram of the video path). The TDA8844 has only one RGB input, so switching between the different RGB sources is needed. The figure below shows the RGB switching. · · · All sets have RGB_TXT and/or RGB_OSD from uP. Only AP sets have the PCF8515 (separate OSD-IC) If the set has TXT from uP and OSD from PCF8515, these RGB sources are connected together via diodes and then connected to the input of TDA8844 directly. The software should make sure that there is no OSD during TXT. Jumpers A are in. For EPG sets a separate TXT/EPG processor (IC7007 diagram S) is used. The RGB of the EPG and OSD from (P are connected together via diodes and then connected to the input of TDA8844 directly. Jumpers A are in. For sets with external RGB (SCART), the selection between RGB_TXT/OSD and RGB_EXT is done with a IC7275 (TDA8601) RGB-switch.
STATUS SIGNAL STAT1
DESCRIPTION
Remark
CVBS status from pin 8 of SCART1. . This is fed to uP pin 10
0 - 2V: internal CVBS 4.5 - 7.0V: 16:9 aspect ratio 9.0 - 12V: 4:3 aspect ratio 0 - 2V: internal CVBS 4.5 - 7.0V: 16:9 aspect ration 9.0 - 12V: 4:3 aspect ratio >0.9V is RGB mode
STAT2
CVBS status from pin 8 of SCART2.
·
This is fed to uP pin 9. FBL RGB status from pin 16 of SCART1
·
40
VIDEO PROCESSING Chrominance Processing
A8.0E
Chrominance Processing
TO/FROM COMB-FILTER
C_COMB Y_COMB
C_EXT 4201 Y_CVBS_EXT +8V 8V3 V5 Y_CVBS_MON 7176 BC847B 2V3 3175 100R V4 FOR WITHOUT COMB FILTER 9200 V7
V6
560R
3176
1V7 EXT. CVBS BUFFER
2180
100n
2181
100n
7150-B TDA8844 2176 17 470n 3V4 V2
CVBS_INT
2V3 38
1V2 10
3V4 11
COMB_ON 0V4 33 28 2V6 Y_OUT
V8a
Y 2177 470n 13 3V7 9 6V6
SANDCASTLE
PAL/INTSC
29 2V3 B_Y_OUT 30 2V3 R_Y_OUT
V8b
SY 16 2V5 35 * 4192 2V3
* 4195
1192
34
2V5
4V7
36
3197
V8c
1190
2196
2197
1189
2187
2188
2186
220n
22n
2u2
1191
*
2189 15p
*
2191 15p
*
2192 15p
*
2190 15p
33K
4190
*
* *7191
* * 3191
33K
* 3194
*
+8V
* 7190 BFS20 * 3190
33K
* * 3192
33K
BFS20
*7192 BFS20 * 7189 BC847B SYS1 PAL M PAL BG NTSC M PAL N 0 0 1 1 SYS2 0 1 0 1
* 3189
33K
33K
SYS2
4198
*
SYS1
* 7193 BC847B
* 3193
100n
1n
100K
CL 86532063_006.eps 040898
Chrominance
The chrominance signal is internally applied to the PAL/NTSC/ SECAM chrominance decoder inside IC7150-B. Also the 64 µS delay line is integrated in the TDA8844. Chrominance can also be fed in on pin 10 from COMB-filter or SCART and luminance on pin 11. The chrominance demodulator determines whether a PAL, NTSC or SECAM signal is present and subsequently decodes its R-Y and B-Y signals. For LATAM there are three BI-NORMA versions, one TRINORMA and one FOUR-NORMA. Depending on the version a 3.6MHz x-tal or a 4.4MHz x-tal is connected to pin 35 of the BI-MOS. During INITIALIZATION of the BIMOS the XA,XB control bits have to be set in order to get a correct calibration of the BIMOS. If the XA,XB setting does not tally with the x-tal connected to pin 35, the line output transistor can be killed. So, this can not be done via a software option!! A option jumper between pin 52 of the uP and ground is used to distinguish between the x-tals connected to the BIMOS.
Personal notes
A8.0E
VIDEO PROCESSING Chrominance Processing
41
Chrominance Processing
BI- TRI and FOUR NORMA configuration
SET VERSION BI-NORMA-M BI-NORMA-B BI-NORMA-N TRI-NORMA FOUR-NORMA possible systems PAL-M/NTSC-M PAL-BG/NTSC-M PAL-N/NTSC-M PAL-M/PAL-N/NTSC-M PAL-M/PAL-N/PALBG/NTSC-M x-tal on pin 34 1x 3.6MHz 1x 3.6MHz 1x 3.6MHz 1x 3.6MHz 3x 3.6MHz x-tal pin 35 1x 3.6MHz 1x 4.4MHz 1x 3.6MHz 2x 3.6MHz 1x 4.4MHz pin 52 high low high high low
The crystals are also used as a reference for the line frequency (sync diagram A6). This means in case of colour problems (only black/white) the crystal could cause the symptom. Replace the crystal only by an original one! In case of only black-white the problem can also be the loop filter on pin 36 IC7150. So not always the IC causes the problem but mostly components around the IC. A defective crystal: no synchronisation! The DC-level of the CVBS-signal (pin13 front-end signal and pin17 from SCART) is also very important. In case this level is not correct than the symptom could be no picture.
Personal notes
42
VIDEO PROCESSING Chrominance Processing
A8.0E
SCL 3335 7150-C TDA8844
SDA 3336 RGB_SW_OFF
BAS216 6300
V12a RO 21 1V9 3306 47R V12b 3309 47R 3310 V12c 47R 3311 47R 3312 10K
BAS216 6301
BAS216
SCL
SDA
6302
7100R 8100R 3V4 3V
1V9 M30 1 1V8 1V9 2 3 4 5V9
BCI
V9a Y_IN B_Y_IN R_Y_IN V9c V9b 2V6 2V3 2V3 27 31 32 LUMIN BYI RYI
G-Y MATRIX RGB
GO 20
1V8
3307 47R
BO 19
1V9
3308 47R
5
BLKIN 18 RI 23 GI 24 BI 25 RGBIN BCLIN 26 22
5V2
3303
2K2 3304
2K2 3305
2302
47p 2301
47p 2300
2K2
G_IN
R_IN
B_IN
3V7 3V5 0V2
M12A
****
+8VB TO M12B & M13B OF TRANSPARENT OSD A9 OR TO M12C & M13C OF
3V5 3V5
9222
2293
2294
2292
3325
**** M13A
CONTROLS A8 WHEN OSD PANEL IS PRESENT
180k
47n
47n
47n
AVE. BEAM - CURRENT LIMITER
V10a 12 R_OUT 11 FROM SEPARATE TXT-IC WHEN PRESENT G_OUT V10c 2V2 V10b 6328 BAS216 3331 47K EHT_INFO
2322
2323
4u7
2V2
2321
100n
B_OUT
FBL_OUT
3V6 100R
3293
1K
7325 BC857B
1V7
6325
22K
13
0V2
3323
3292
22R
2K2
10
3327
+8V
3330
2V2
150K
3326
1u
47p
3324 180k
BAS216 LOT SATURATION LIMITER
CL 86532063_004.eps 040898
YUV
The demodulated video-signal can be checked on pins 28,29,30 IC7150 and is fed to pins 27,31,32. In this path the YUV panel can be inserted. Without this panel, the jumpers 4225/4226/4227 are in. On the YUV-panel TDA9178 is used, which can control various picture improvements: histogram processing, colour transient improvement and luminance transient improvement. The TDA8844 is able to perform the following picture enhancements: · Sets without TDA9178; for sets without TDA9178 the Dynamic Skin Control and the Blue Stretch is controlled in theTDA8844. There is no Green Enhancement. Sets with TDA9178: for sets with TDA9178 the Dynamic Skin Control and Green Enhancement are controlled in the TDA9178. The Blue Stretch is controlled in the TDA8844 and the Blue Stretch of the TDA9178 is switched off. Green Enhancement. Is intended to shift low saturated green colours towards more saturated green colours. This shift is effective for only that part of the picture that matches with low saturated green. Blue stretch. For parts of the picture that are white, the colour temperature is changed a little bluish coloured white to give a brighter impression.
·
Dynamic Skin Control. Skin tones are very sensitive for hue errors, because the human eye has an absolute feeling for skin tones. To make a picture look free of hue error, the goal is to make sure that skin tones are put at a correct colour.
When the TDA9178 is used then the noise reduction is also available. The action of the noise reduction has also influence on the sharpness control. IF a noisy signal is received then the noise reduction should be high and sharpness low and also vice versa: Good picture: DNR=low; sharpness= high; Bad(noisy) picture: DNR=high; sharpness=low
·
·
·
TO C30 OF CRT PANEL B
***
A8.0E
VIDEO PROCESSING Chrominance Processing
43
7101 PCA8515P 21 VDD 12 VSS 13 RESET_
FROM UC 7000 EXT/INT DATA SWITCHING BUFFER CHAR SIZE REGISTER/ CONTROL WRITE ADDRESS COUNTER ADDRESS BUFFER SELECTOR DISPLAY CHAR RAM DISPLAY ROM VERTICAL POSITION REGISTER/ COUNTER 5 CONTROL SIGNALS
CONTROL REGISTER P00 17 I/O PORT BUFFERS P01 19 P04|ACM 2
SLC
9 SCL|SCLK 8 SDA|SIN
I 2 C SLAVE RECEIVER OR HIGH-SPEED I/O BUFFER HORIZONTAL POSITION REGISTER/ COUNTER
SDA
14 E 15 HIO_|I2C
AVDD 24
5 C
PLL OSC
INSTRUCTION DECODER INTERNAL
AVSS 23
7 HSYNC 6 VSYNC
CSYNC SEPAR
SYNCHRONOUS
CIRCUIT
CRYSTAL OSCILLATOR
TESTING CIRCUITRY
DISPLAY CONTROL AND OUTPUT STAGE
ACM-VOB2
GVOW1
RVOW0
BVOW2
11
10
4
3
16 18 20 1
FBVOB
XTA2O
IVOW3
XTA1I
TST1
TST2
22
R G B FB TO RGB SWITCH 7275
9.4
CL 86532033_017.AI 160698
OSD-IC7101
See also chapter "Teletext and On-Screen Display. 253 fonts are possible with 4 different sizes, foreground/ background colours, shadow. This IC is fitted on a separate panel. On the connector O06 Hand V-sync are fed in for stable OSD and for OSD-positioning. What has to displayed is transmitted via I2C. The RGB-outputs and fast-blanking are fed to IC7275 via connector O05. TXT/EPG (diagram P) uses a separate microprocessor for Europe, because in these countries features like ACI/FLOF/ TOP are used. These features need also some memory and that was not enough available in the main microprocessor IC7000. In the circuit diagram P two versions are indicated: the SAA5262 and SAA5263: Both support also ACI and the SAA5263 can do the 'simple' Electronic Program Guide (EPG) feature. The commercial name for EPG is NextView: (this part is also described in the MG98/MD2.2 TM)
NexTView is a feature with which it is possible to retrieve a program listing with one press of the button. NexTView (Simple Program Guide): For each program, during installation the user should indicate on which teletext page the program guide can be found. This teletext page is then displayed when the nexTView command is given. This feature only requires a software modification and no hardware modification in the set. For each program the page number in which this information is contained has to be given.
44
VIDEO PROCESSING Chrominance Processing
A8.0E
+8V
3336 4R7
2226
100n 2225
7770 TDA9178
13 12 2
NC
10 23 24 18 20
GND VCC SOUT 21
10u
7150-C
Y - IN B - Y - IN R - Y - IN
Y - IN
6 YIN 8 UIN 9 VIN 22 CF
SDA
LUMA PROCESSING CHROMA PROCESSING CONTROL SPECTRAL PROC ADC
V12c
V12b
V12a
YOUT 19 UOUT 17 VOUT 16
WINDOW
27 31 32 G-Y MATRIX RGB
21 20 19 18
1M30 2M30 3M30 5M30
R G B BCI
1C30 2C30 3C30 5C30 TO CRT PANEL
U - IN V - IN
ADR
DEC
SCL
AD1
AD2
AD3
SC
FBL_TXT_OSD
14 11 7
15 3
4
5
1 RES
+8V
R_TXT_OSD G_TXT_OSD B_TXT_OSD
26 25 24 23
RGB_SW_OFF
SDA
3338
3339
SANDCASTLE
SCL
8
7
3337
100n
2227
0R
SDA
SCL
CL 86532063_005.eps 040898
RGB-dematrixing
RGB dematrixing dematrixes the -(R-Y), -(B-Y) and the Y signals into RGB signals. Contrast, saturation and brightness control are realized via I2C (for an external RGB-source brightness and contrast is also controlled).
If the beam current becomes excessive there is a possibility of CRT damage. If the voltage on pin 22 is reduced then also the contrast is decreased. The EHT-info is fed to R3331/3324. Via TS7325 a fast PWL is realized and via D6328 the average PWL because of RC-time C2322/3331. The voltage on pin 22 is also dependent of the contrast setting in the picture menu.
FBL-IN
Via the FBL-IN fast blanking signals on pin 26 of IC7150-C, both the fast blanking and the RGB source select is realized: · When FBL-IN at pin 26 is higher than 4V DC, IC7119-4C is in the OSD mode (only the FBL-IN coming from the OSD generator of the µP gives 8V DC). If pin 26 is higher than 4V DC, the RGB output pins 19-20-21 of the video controller are made high-ohmic, so RGB OSD info from the µP can be inserted. This mode is not used in A8. When FBL-IN at pin 26 is between 0V9 and 4V DC, IC7150C is in the external RGB mode. RGB from TXT or SCART can be inserted at pins 23,24,25. When FBL-IN at pin 26 is lower than 0V9 DC, IC7119-4C is in the internal RGB mode.
Transparent OSD only Europe
See diagram A7/A9 Can be achieved by controlling the peak white limit. To facilitate this the circuitry of diagram A9 is added. The fast blanking (FBL1) is fed to the collector of TS7361 to make a box with reduced contrast. To the base of the TS7361 is FBL2 fed. This makes the OSDblanking and the OSD is inserted via the RGB-lines from the µP to the RGB-inputs (23-26). In the circuit diagram A7 there is an option for soft clipper with TS7316/TS7318/TS7320. This has also effect on the PWL pin 22. If one of the voltages of the RGB-drive is too high then TS7320 conducts to reduce contrast. In this case the peak white limit via the EHT-info has less function, because the peaks are now limited by the soft clipper.
· · ·
Peak white limit (PWL)
See diagram A7
A8.0E
VIDEO PROCESSING Chrominance Processing
45
By using diodes 6300, 6301 and 6302 the RGB outputs can be switched of very fast. At switch-off these diodes will conduct so the RGB-drive is made high. In order to prevent a very bright Raster the vertical deflection is forced to the very top of the picture tube. Additionally by using this method switch off spot suppression is also achieved.
Personal notes
Cut-off control/white drive
The picture tube is continuously adjusted to prevent visible ageing of the picture tube. In this way the customer has always a perfect picture. This is so-called 'Continuous Cathode Calibration'. The function is realized by means of two-point black level stabilization. By inserting two levels for each gun and comparing the result with 2 different reference circuits the drive is controlled. With two different reference currents the influence of picture tube parameters like the spread in cut-off voltage can be eliminated. The measurement of the "high" and the "low" current of the 2point stabilization circuit is carried out in 2 consecutive fields. The leakage current is measured in each field, The maximum allowable leakage current is 100uA. The current is measured via Beam Current Information (BCI) that is fed back to pin 18 of IC7150-C. When the TV is switched-on the RGB output signals are blanked and the black current loop will try to set the right picture tube bias levels and then there is RGB-drive.
46
VIDEO PROCESSING CRT panel
A8.0E
CRT panel
VDD 6 MIRROR 1 TDA6107Q MIRROR 4 CURRENT SOURCE 1x THERMAL PROTECTION CIRCUIT Vl(1), Vl(2), Vl(3) 1, 2, 3 Rl Ra 3x CASCODE 2 Rl VIP REFERENCE MIRROR 3 DIFFERENTIAL STAGE 6 Io(m) 3x 1x 9, 8, 7 Voc(3), Voc(2), Voc(1) MIRROR 5 CASCODE 1
MIRROR 2 4
CL 86532033_028.AI 160698
RGB amplifier
The RGB amplifier (7830) is located on the CRT-panel. This integrated RGB video amplifier has three amplifier channels inside and is intended to drive the three cathodes of the colour CRT. The main features of IC TDA6107 are : · · This amplifier is connected to 200V only because 13V reference is generated internally. Black current stabilization output is also generated internally and this signal goes directly to the BiMOS feedback input (see diagram A7). Thermal protection.
'Continuous Cathode Calibration', pr