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om .c 4U et Inc. Techwell, he aS at TW9906 Enhanced 3x10-bit Multi.D w w Standard Comb Filter Video Decoder w
With YCbCr Input Support
m o .c U t4 Techwell Confidential. Information may change e without notice. e h S ta a .D w w w
TECHWELL, INC.
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Disclaimer This document provides technical information for the user. Techwell, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Techwell, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Techwell, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. REV.B 11/01/2005
om .c 4U et he aS at .D w w w
TW9906
Introduction and Features .........................................................5 Functional Description...............................................................6 Overview ..................................................................................7 Analog Front-end .....................................................................7 Video Source Selection........................................................7 Clamping and Automatic Gain Control ................................8 Analog to Digital Converter ..................................................8 Sync Processing ......................................................................8 Horizontal sync processing ..................................................8 Vertical sync processing ......................................................9 Color Decoding ........................................................................9 Y/C separation......................................................................9 Color demodulation ..............................................................9 Automatic Chroma Gain Control........................................10 Low Color Detection and Removal....................................10 Automatic standard detection ............................................10 Component Processing .........................................................11 Luminance Processing.......................................................11 Sharpness...........................................................................11 CTI ......................................................................................11 The Hue and Saturation.....................................................11 Power Management ..............................................................11 Control Interface.....................................................................11 Down-scaling and Cropping...............................................12 TW9906 Down-Scaling ......................................................12 TW9906 Cropping ..............................................................13 Two Wire Serial Bus Interface...............................................15 Output Interface .....................................................................17 ITU-R BT.656 .....................................................................17 VIP (Video Interface Port) ..................................................17 Control Signals ...................................................................18 Vertical timing diagram.......................................................18 HSYNC ...............................................................................21 HACTIVE ............................................................................21 VSYNC ...............................................................................21 FIELD..................................................................................21 Horizontal Down Scaling Output........................................21 Vertical Down Scaling Output ............................................22 VBI Data Processing..............................................................23 Raw VBI data output ..........................................................23 VBI Data Slicer ...................................................................24 Sliced VBI Data output format............................................24 Sliced VBI ANC data packet format 0(ANCMODE=0)......25 Sliced VBI ANC data packet format 1(ANCMODE=1)......26 Closed Captioning ANC data packet.................................26 525 Lines WSS (CGMS Copy Generation Management System) ANC data packet..................................................27 625 Line WSS (Wide-Screen Signaling) ANC data packet27 625 Teletext-A ANC data packet .......................................28 625 Teletext-B ANC data packet .......................................28 525 Teletext-B ANC data packet .......................................29 625 Teletext-C and 525 Teletext-C ANC data packet ......29 625 Teletext-D and 525 Teletext-D ANC data packet ......30 Line16 VPS (Video Program System) ANC data packet..30 VITC (Vertical Interval Time Code) ANC data packet.......31 Gemstar 1X ANC data packet ...........................................31 Gemstar 2X ANC data packet ...........................................32 Sliced VBI RAM HOST Access .........................................32 Sliced VBI RAM Control.....................................................32 Teletext TTX Filter Control .................................................33 Teletext Framing Code checking.......................................33 EDS Packet Decoder .........................................................34 Interrupt Control..................................................................34 Audio clock generation ..........................................................35 Test Modes ............................................................................37 Filter Curves...........................................................................38 Decimation filter..................................................................38 Anti-alias Filter Curve .........................................................38 Chroma Band Pass Filter Curves......................................39 Luma Notch Filter Curve for NTSC and PAL/SECAM......40 Chrominance Low-Pass Filter Curve ................................40 Horizontal Scaler Pre- Filter curves...................................41 Vertical Interpolation Filter curves......................................41 Peaking Filter Curves.........................................................42 Control Register........................................................................43 TW9906 Register SUMMARY...........................................43 0x00 Product ID Code Register (ID)..............................49 0x01 Chip Status Register I (STATUS1)........................49 0x02 Input Format (INFORM).........................................50 0x03 Output Format Control Register (OPFORM) ........51 0x04 HSYNC Delay Control ...........................................51 0x05 Output Control I......................................................52 0x06 Analog Control Register (ACNTL).........................53 0x07 Cropping Register, High (CROP_HI) ....................53 0x08 Vertical Delay Register, Low (VDELAY_LO) ........54 0x09 Vertical Active Register, Low (VACTIVE_LO) ......54 0x0A Horizontal Delay Register, Low (HDELAY_LO)...54 0x0B Horizontal Active Register, Low (HACTIVE_LO) .54 0x0C Control Register I (CNTRL1).................................55 0x0D Vertical Scaling Register, Low (VSCALE_LO).....55 0x0E Scaling Register, High (SCALE_HI) .....................55 0x0F Horizontal Scaling Register, Low (HSCALE_LO).56 0x10 BRIGHTNESS Control Register (BRIGHT) ..........56 0x11 CONTRAST Control Register (CONTRAST) .......56 0x12 SHARPNESS Control Register I (SHARPNESS) 56 0x13 Chroma (U) Gain Register (SAT_U) .....................57 0x14 Chroma (V) Gain Register (SAT_V)......................57 0x15 Hue Control Register (HUE)..................................57 0x16 .................................................................................57 0x17 Vertical Sharpness (VSHARP)..............................58 0x18 Coring Control Register (CORING).......................58 0x19 VBI Control Register (VBICNTL)...........................58 0x1A Analog Control II....................................................59 0x1B Output Control II ....................................................60 0x1C Standard Selection (SDT) .....................................61 0x1D Standard Recognition (SDTR)..............................62 0x1E Component Video Format (CVFMT) ....................62 0x1F Test Control Register (TEST)................................63 0x20 Clamping Gain (CLMPG) ......................................63 0x21 Individual AGC Gain (IAGC)..................................64 0x22 AGC Gain (AGCGAIN) ..........................................64 0x23 White Peak Threshold (PEAKWT)........................64 0x24 Clamp level (CLMPL)..............................................64 0x25 Sync Amplitude (SYNCT).......................................64 0x26 Sync Miss Count Register (MISSCNT).................65 0x27 Clamp Position Register (PCLAMP) .....................65 0x28 Vertical Control I (VCNTL1)...................................65 0x29 Vertical Control II (VCNTL2)..................................65 0x2A Color Killer Level Control (CKILL).........................66 0x2B Comb Filter Control (COMB).................................66 0x2C Luma Delay and H Filter Control (LDLY)..............66 0x2D Miscellaneous Control I (MISC1)..........................67 0x2E LOOP Control Register (LOOP) ...........................67 0x2F Miscellaneous Control II (MISC2) .........................68 0x30 Macrovision Detection (MVSN) .............................69 0x31 Chip STATUS II (STATUS2) ................................69 0x32 H monitor (HFREF)................................................70 0x33 CLAMP MODE (CLMD) ........................................70 0x34 ID Detection Control (IDCNTL)..............................70 0x35 Clamp Control I (CLCNTL1) ..................................71 0x40 Audio Clock Increment (ACKI) ..............................71 0x41 Audio Clock Increment (ACKI) ..............................71 0x42 Audio Clock Increment (ACKI) ..............................71 0x43 Audio Clock Number (ACKN)................................72 0x44 Audio Clock Number (ACKN)................................72 0x45 Audio Clock Number (ACKN)................................72
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0x46 Serial Clock Divider (SDIV)....................................72 0x47 Left/Right Clock Divider (LRDIV) ...........................72 0x48 Audio Clock Control (ACCNTL).............................73 0x50 FILLDATA...............................................................73 0x51 SDID .......................................................................73 0x52 DID..........................................................................74 0x55 VVBI........................................................................74 0x56~6A LCTL6~LCTL26..................................................75 0x6B HSGEGIN ..............................................................75 0x6C HSEND ..................................................................75 0x6D OVSDLY ................................................................75 0x6E OVSEND................................................................76 0x6F VBIDELAY..............................................................76 0x94 F2VCNT..................................................................77 0x95 F2VDELAY_LO......................................................77 0x96 F2VACTIVE_LO.....................................................77 0x97 STATUS1MODE....................................................77 0x98 STATUS2MODE....................................................78 0x99 STATUS3MODE....................................................78 0x9A INTRAWCLEAR ....................................................78 0x9B TTXF1MASKPAT1 ................................................79 0x9C TTXF1MASKPAT2 ................................................79 0x9D TTXF1MASKPAT3 ................................................79 0x9E TTXF1MASKPAT4 ................................................79 0x9F TTXF1MASKPAT5 ................................................80 0xA0 TTXF2MASKPAT1 ................................................80 0xA1 TTXF2MASKPAT2 ................................................80 0xA2 TTXF2MASKPAT3 ................................................80 0xA3 TTXF2MASKPAT4 ................................................81 0xA4 TTXF2MASKPAT5 ................................................81 0xA5 TTXFILCTL ............................................................81 0xA6 TTXFRMASK.........................................................82 0xA7 TTXFRPAT ............................................................82 0xA8 GEM2XMASK_LO.................................................82 0xA9 GEM2X_HI.............................................................82 0xAA GEM2XPAT_LO....................................................83 0xAB SVBIERRORMODE.............................................83 0xAD FTHRESHOLD......................................................83 0xAE LINENUMBERINT.................................................84 0xAF VBIREGLOAD .......................................................84 0xB0 INT1MASK.............................................................84 0xB1 INT2MASK.............................................................84 0xB2 INT3MASK.............................................................85 0xB3 INT1CLEAR ...........................................................85 0xB4 INT2CLEAR ...........................................................85 0xB5 INT3CLEAR ...........................................................85 0xB6 INT1RAWSTATUS................................................86 0xB7 INT2RAWSTATUS................................................87 0xB8 INT3RAWSTATUS................................................88 0xB9 INT1STATUS.........................................................88 0xBA INT2STATUS ........................................................89 0xBB INT3STATUS ........................................................89 0xBC SVBIWCOUNT......................................................89 0xBD CCF1DATA1 .........................................................89 0xBE CCF1DATA2 .........................................................90 0xBF CCF2DATA1..........................................................90 0xC0 CCF2DATA2..........................................................90 0xC1 VITCFRAME1........................................................90 0xC2 VITCFRAME2........................................................90 0xC3 VITCSEC1 .............................................................91 0xC4 VITCSEC2 .............................................................91 0xC5 VITCMIN1 ..............................................................91 0xC6 VITCMIN2 ..............................................................91 0xC7 VITCHOUR1..........................................................91 0xC8 VITCHOUR2..........................................................91 0xC9 VITCCRC...............................................................92 Following 0xCA-0xDB registers are under 625-line system detection. ............................................................................92 0xCA WSS_LO ...............................................................92 0xCB WSS_HI ................................................................93 0xCC VPSDATA1 ...........................................................93 0xCD VPSDATA2 ...........................................................93 0xCE VPSDATA3 ...........................................................93 0xCF VPSDATA4 ...........................................................94 0xD0 VPSDATA5............................................................94 0xD1 VPSDATA6............................................................94 0xD2 VPSDATA7............................................................94 0xD3 VPSDATA8............................................................94 0xD4 VPSDATA9............................................................95 0xD5 VPSDATA10..........................................................95 0xD6 VPSDATA11..........................................................95 0xD7 VPSDATA12..........................................................95 0xD8 VPSDATA13..........................................................95 0xD9 VPSSCODE1 ........................................................96 0xDA VPSSCODE2........................................................96 0xDB TFCODE ...............................................................96 Following 0xCA-0xDB Registers are under 525 line system detection. ............................................................................96 0xCA WSS_LO ...............................................................96 0xCB WSS_HI ................................................................97 0xCC GEM2XF1FRAME_LO.........................................97 0xCD GEM2XF1FRAME_HI ..........................................97 0xCE GEM2XF1DATA1 .................................................98 0xCF GEM2XF1DATA2 .................................................98 0xD0 GEM2XF1DATA3..................................................98 0xD1 GEM2XF1DATA4..................................................98 0xD2 GEM1XF1DATA1..................................................98 0xD3 GEM1XF1DATA2..................................................99 0xD4 GEM2XF2FRAME_LO .........................................99 0xD5 GEM2XF2FRAME_HI...........................................99 0xD6 GEM2XF2DATA1..................................................99 0xD7 GEM2XF2DATA2..................................................99 0xD8 GEM2XF2DATA3................................................100 0xD9 GEM2XF2DATA4................................................100 0xDA GEM1XF2DATA1 ...............................................100 0xDB GEM1XF2DATA2 ...............................................100 0xDC VCHIPRA............................................................101 0xDD VCHIPG ..............................................................101 0xDE TFCODE .............................................................102 0xDF SVBIRDATA........................................................102 0xE0 EDSSTATUS.......................................................103 0xE1 EDSDATA1..........................................................103 0xE2 EDSDATA2..........................................................104 0xE3 EDSDATA3..........................................................104 0xE4 EDSDATA4..........................................................104 0xE5 EDSDATA5..........................................................104 0xE6 EDSDATA6..........................................................105 0xE7 EDSDATA7..........................................................105 0xE8 EDSDATA8..........................................................105 0xE9 EDSDATA9..........................................................105 0xEA EDSDATA10 .......................................................106 Pin Diagram .............................................................................107 Pin Description.....................................................................108 Analog Interface Pins.......................................................108 Two Wire Interface Pins...................................................108 Video Timing Unit Pins.....................................................108 Clock Interface Pins .........................................................109 Power and Ground Pins...................................................110 Parametric Information ..........................................................111 AC/DC Electrical Parameters..............................................111 Clock Timing Diagram......................................................113 Application Information ........................................................114 Video Input Interface ........................................................114 A/D Converter...................................................................114 Clamping/AGC .................................................................114 Clock Generation .............................................................114
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Power-Up......................................................................... 114 Application Schematics...................................................... 115 PCB Layout Considerations............................................ 116 80-pin TQFP Package Mechanical Drawing ..................... 117 Copyright Notice .......................................................... 118 Disclaimer ....................................................................... 118 Life Support Policy ...................................................... 118
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TW9906
TW9906 3x10-bit Multi-Standard Comb Filter Video Decoder with YCbCr Component Input
Introduction and Features
Techwell's TW9906 is a high quality NTSC/PAL,/SECAM multi-standard video decoder plus YCbCr component inputs designed for multimedia applications. TW9906 uses the mixed-signal 2.5V/3.3V CMOS technology to provide a low-cost and low-power integrated solution. Minimum external components are required due to its integrated analog front-end containing anti-aliasing filter, AGC, clamping, and three 10-bit high speed ADCs. For composite inputs, an adaptive comb filter and luma/chroma processing produce exceptionally high quality pictures using proprietary techniques. A high quality internal scaling engine offers arbitrarily filtered down scaling of the output video. Its VBI capability is enhanced with builtin VBI slicer, filter, FIFO and VBI data pass-through function to support common data services. The main features of the TW9906 are
· NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N combination), PAL (60), SECAM support with automatic format detection · Advanced synchronization processing for VCR trick mode and weak signal · Software selectable analog inputs allows any of the following combinations: · Up to five composite video inputs · Four composite, one S-video or one YCbCr input. · Two composite, two S-Video or two YCbCr inputs. · Three composite, one S-Video and one YCbCr input. · Programmable hue, brightness, saturation, contrast, and sharpness · Blue stretch · Image enhancement with 2D peaking and CTI. · Automatic color control and color killer · IF compensation filter · Detection of level of copy protection according to Macrovision standard · YCbCr input supports 480i/576i and sub-sampled 480p/576p with auto-detection.
· Video Output
· Support both free-running and line-locked clock outputs · Programmable output cropping · High quality horizontal filtered scaling with arbitrary scale down ratio · VMI 1.4 compatible 10-bit or 20-bit pixel interface · ITU-R 601 or ITU-R 656 compatible output YCbCr(4:2:2) output format · VBI slicer supporting industrial standard data services with data packet filter capability · Built-in VBI FIFO for convenient access through host interface · VBI data pass through, raw ADC data for IntercastTM · Field locked audio clock generator
· Miscellaneous
· Two wire MPU serial bus interface · Power-down mode · Typical power consumption 0.25W · Single 27MHz crystal for all standards · Supports 24.54MHz and 29.5MHz crystal for high quality square pixel format · 3.3V / 5V tolerant I/O · 2.5V / 3.3V Power Supply · 80 pin TQFP package
· Three 10-bit ADCs with clamping circuit and anti-aliasing
filter.
· Fully programmable static or automatic gain control for the
Y channel
· Programmable white peak control for the Y channel · Adaptive 4H comb filter for the best image quality.
· PAL delay line for color phase error correction · Digital sub-carrier PLL for accurate color decoding · Digital Horizontal PLL and advanced synchronization processing for non-standard video signals
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Analog Video In
CIN (1) VIN (0) CIN (0) VIN (1)/MUX4 YBOUT MUX3 MUX0
TW9906
TECHWELL, INC.
2 Wire Serial Bus Clock MUX
Anti-alias Filter Anti-alias Filter Anti-alias Filter
Functional Description
Line-lock clock Generator AGC/Cla Clamp Clamp
27 Mhz
SIAD0 SCLK SDAT
MUX
MUX
10-bit ADC
10-bit ADC
10-bit ADC
Figure 1: TW9906 Block Diagram
6
VBI Slicer VBI FIFO Sync Filter Filter
U Y
Filter
Chroma Demodulation
V
Audio Clock
VBI Pass through
4-H adaptive comb filter Y/C separation
Luma/Chroma processor
Video output Interface
H/V Down Scaler/Cropping
PDN
ASCLK
CLKX1
CLKX2
AMCLK
VSYNC
HSYNC
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AMXCLK INTREQ
FIELD DVALID
MPOUT
ALRCLK
VD(19:0)
TW9906 Overview
Techwell's TW9906 is a high quality NTSC/PAL/SECAM video decoder that is designed for multimedia applications. It uses the mixed-signal 2.5V/3.3V CMOS technology to provide a lowpower integrated solution. The TW9906 analog front-end is equipped with three separate analog channels that enable it to accept all three possible analog video signal standards: composite, S-video or YCbCr component video. All channels include an analog multiplexer (MUX) for maximum flexibility in software controlled input selection. It is possible to connect up to five composite inputs at one time and allow the software to switch between them. Alternatively several combinations of composite inputs and S-Video component inputs may be switched under software control. (Four input channels of any format can be accommodated with but there is a maximum of 2 S-Video inputs or 2 component inputs.) The front-end contains all the necessary circuits to simplify the system design. The built-in three high quality 10-bit analog-to-digital converters (ADCs) convert inputs into digital signals for processing. The TW9906 uses proprietary adaptive 4H comb filter for chroma and luma separation to achieve high video quality. The image enhancement includes horizontal and vertical peaking, CTI and BCS control. The advanced synchronization processing can produce stable pictures for non-standard signal such as those produced by VCR trick mode. The high quality scaler uses multi-tap poly-phase decimation filter to accurately scale down the image with minimum phase error. It can be programmed to scale-down the output picture to an arbitrary ratio with cropping. The TW9906 supports flexible pixel interface. It outputs YCbCr (4:2:2) data stream over 10-bit or 20-bit data path. It also supports both free-running clock and line-locked clock output. A 2-wire serial MPU interface is used to simplify system integration. All the functions can be controlled through this interface.
Analog Front-end
The analog front-end converts analog video signals to the required digital format. There are three analog channels with clamping circuits and ADCs. The Y channel has 5-input multiplexer, and a variable gain amplifier for automatic gain control (AGC). Its five inputs are identified as MUX0, MUX1, MUX2, MUX3 and MUX4(share the same pin with VIN1). The C channel has a 2-input multiplexer. Its two inputs are identified as CIN0 and CIN1. The V channel is similar to C channel. Its input is VIN0 and VIN1. Both the C and V channel are internally clamped to the zero level of the bipolar input source when enabled. Video Source Selection All analog signals should be AC-coupled to these inputs. The Y channel analog multiplexer selects one of the five inputs MUX[0-4]. MUX[0-4] can be connected to composite video inputs or the Y signal of an S-Video or component input. When decoding a S-Video input, the Y signal should connect to one of the MUX inputs and the C signal to CIN0 or CIN1.
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When decoding a component input, in addition to the Y signal, the C signal should connect to CIN0 or CIN1, and V signals should be connect to VIN0 or VIN1 pins. Software selectable analog inputs allow several possible input combinations: 1. Up to Five composite video inputs. 2. Four composite, one S-video or one component input. 3. Three composite, two S-Video inputs. 4. Three composite, one S-Video and one component input. The input video signals in any certain channel maybe momentarily connected together through the equivalent of a 200 ohm resistor during multiplexer switching. Therefore, the multiplexer cannot be used for switching on a real-time pixel-by-pixel basis. Clamping and Automatic Gain Control All three analog channels have built-in clamping circuit that restore the signal DC level. The Y channel restores the back porch of the digitized video to a level of 60 or a programmable level. Both C(Pb) and V(Pr) channel restores the back porch of the digitized video to a level of 128. This operation is automatic through internal feedback loop. The Automatic Gain Control (AGC) of the Y channel adjusts input gain so that the sync tip is at a desired level. A programmable white peak protection logic is included to prevent saturation in the case of abnormal proportion between sync and white peak level. Analog to Digital Converter TW9906 contains three 10-bit pipelined ADCs that consume less power than conventional flash ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite input or the Y signal of the S-Video input. The second ADC digitizes the C signal when decoding S-video signal. The third ADC digitizes the Pr( or V ) signal when decoding the component input.
Sync Processing
The sync processor of TW9906 detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-video or component signal. The processor contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from VCR fast forward or backward. Horizontal sync processing The horizontal synchronization processing contains a sync separator, a phase-locked-loop (PLL), and the related decision logic. The horizontal sync detector detects the presence of a horizontal sync tip by examining low-pass filtered input samples whose level is lower than a threshold. After sufficient low levels are detected, a horizontal sync is recognized. Additional logic is also used to avoid false detection on glitches. The horizontal PLL locks onto the extracted horizontal sync in all conditions to provide jitter free image output. From there, the PLL also provides orthogonal sampling raster for the down stream processor. The PLL has free running frequency that matches the standard raster frequency. It also has wide lock-in range for tracking any non-standard video signal.
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Vertical sync processing The vertical sync separator detects the vertical synchronization pattern in the input video signals. In addition, the actual sync determination is controlled by a detection window to provide more reliable synchronization. It achieves the functionality of a PLL without the complexity of a PLL. An option is available to provide faster responses for certain applications. The field status is determined at vertical synchronization time. When the location of the detected vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field start. Otherwise, it indicates an even field. The field logic can also be controlled to toggle automatically while tracking the input.
Color Decoding
Y/C separation The color-decoding block contains the luma/chroma separation for the composite video signal and multi-standard color demodulation. For NTSC and PAL standard signals, the luma/chroma separation can be done either by comb filter or notch/band-pass filter combination. For SECAM standard signals, adaptive notch/band-pass filter is used. The default selection for NTSC/PAL is comb filter whenever it is permitted. In the case of comb filter, the TW9906 separates luma (Y) and chroma (C) of a NTSC composite video signal using a proprietary 4H adaptive comb filter. The filter uses a four-line buffer. Adaptive logic combines the upper-comb and the lower-comb results based on the signal changes among the previous, current and next lines. This technique leads to good Y/C separation with small cross luma and cross color at both horizontal and vertical edges. Due to the 90-degree phase difference on adjacent lines of a PAL chroma signal, the 4H line memory are used to provide an excellent PAL comb filter performance. Due to the line buffer used in the comb filter, there is always two lines processing delay in the output except the component input mode which has only one line delay. If notch/band-pass filter is selected, the characteristics of the filters are shown in the filter curve section. Color demodulation The color demodulation for NTSC and PAL standard is done by first quadrature mixing the chroma signal to the base band. The mixing frequency is equal to the sub-carrier frequency for NTSC and PAL. After the mixing, a low-pass filter is used to remove carrier signal and yield chroma components. The low-pass filter characteristic can be selected for optimized transient color performance. For the PAL system, the PAL ID or the burst phase switching is identified to aid the PAL color demodulation. For SECAM, the mixing frequency is 4.286Mhz. After the mixer and low-pass filter, it yields the FM modulated chroma. The SECAM demodulation process therefore consists of low-pass filter, FM demodulator and de-emphasis filter. The filter characteristics are shown in filter curve section. During the FM demodulation, the chroma carrier frequency is identified and used to control the SECAM color demodulation. The sub-carrier signal for use in the color demodulator is generated by direct digital synthesis PLL that locks onto the input sub-carrier reference (color burst). This arrangement allows any substandard of NTSC and PAL to be demodulated easily with single crystal frequency.
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During S-video operation, the Y signal bypasses the comb filter. The C(Pb) signal connects directly to the color demodulator. During component input operation, all the chroma processing and color demodulator blocks are bypassed. Automatic Chroma Gain Control The Automatic Chroma Gain Control (ACC) compensates for reduced amplitudes caused by highfrequency loss in video signal. In the NTSC/PAL standard, the color reference signal is the burst on the back porch. This color-burst amplitude is calculated and compared to standard amplitude. The chroma (Cx) signals are then increased or decreased in amplitude accordingly. The range of ACC control is 6db to +24db. Low Color Detection and Removal For low color amplitude signals, black and white video, or very noisy signals, the color will be "killed". The color killer uses the burst amplitude measurement to switch-off the color when the measured burst amplitude falls below a programmed threshold. The threshold has programmable hysteresis to prevent oscillation of the color killer function. The color killer function can be disabled by programming a low threshold value. Automatic standard detection The TW9906 has build-in automatic standard discrimination circuitry. The circuit uses burst-phase, burst-frequency and frame rate to identify NTSC, PAL or SECAM color signals. The standards that can be identified are NTSC (M), NTSC (4.43), PAL (B, D, G, H, I), PAL (M), PAL (N), PAL (60) and SECAM (M). Each standard can be included or excluded in the standard recognition process by software control. The exceptions are the base standard NTSC and PAL, which are always enabled. The identified standard is indicated by the Standard Selection (SDT) register. Automatic standard detection can be overridden by software controlled standard selection. TW9906 supports all common video formats as shown in Table 1. Table 1. Video Input Formats Supported by the TW9906
Format NTSC-M NTSC-Japan (1) PAL-B, G, N PAL-D PAL-H PAL-I PAL-M PAL-CN SECAM PAL-60 NTSC (4.43) Lines 525 525 625 625 625 625 525 625 625 525 525 Fields 60 60 50 50 50 50 60 50 50 60 60 Fsc 3.579545 MHz 3.579545 MHz 4.433619 MHz 4.433619 MHz 4.433619 MHz 4.433619 MHz 3.575612 MHz 3.582056 MHz 4.406MHz 4.250MHz 4.433619 MHz 4.433619 MHz Country U.S., many others Japan Many China Belgium Great Britain, others Brazil Argentina France, Eastern Europe, Middle East, Russia China Transcoding
Notes: (1). NTSC-Japan has 0 IRE setup.
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TW9906 Component Processing
Luminance Processing The TW9906 adjusts brightness by adding a programmable value (in register BRIGHTNESS) to the Y signal. It adjusts the picture contrast by changing the gain (in register CONTRAST) of the Y signal. The TW9906 video decoder also performs a coring function. It can force all values below a certain level, programmed in the Coring Control Register, to zero. This is useful because human eyes are sensitive to variations in nearly black images. Changing levels near black to true black, can make the image appears clearer. Sharpness The TW9906 also provides a sharpness control function through control registers. It provides the control in 16 steps up to +12db. The center frequency of the enhancement curve is selectable by software control. It also provides a high frequency coring function to minimize the amplification of high frequency noise. The coring level is adjustable through the Coring Control register. The same function can also be used to soften the images. This can be used to provide noise reduction on noisy signal. To further enhance the image, a programmable vertical peaking function is provided for up to +6db of enhancement. A programmable coring level can be adjusted to minimize the noise enhancement. CTI The TW9906 provides the Color Transient Improvement function to further enhance the image quality. The CTI enhance the color edge transient without any overshoot or under-shoot. The Hue and Saturation When decoding NTSC signals, TW9906 can adjust the hue of the chroma signal. The hue is defined as a phase shift of the subcarrier with respect to the burst. This phase shift can be programmed through a control register. The color saturation can be adjusted by changing the gain of Cb and Cr signals for all NTSC, PAL and SECAM formats. The Cb and Cr gain can be adjusted independently for flexibility.
Power Management
The TW9906 can be put into power-down mode in which its clock is turned off for most of the circuits. The Y, C(Pb) and V(Pr) path can be separately powered down.
Control Interface
The TW9906 registers are accessed via 2-WIRE SERIAL MPU interface. It operates as a slave device. Serial clock and data lines, SCL and SDA, transfer data from the bus master at a rate of 400 Kbits/s. The TW9906 has one serial interface address select pins to program up to two unique serial addresses TW9906. This allows as many as two TW9906 to share the same serial bus. Reset signals are also available to reset the control registers to their default values.
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TW9906
Down-scaling and Cropping The TW9906 provides two methods to reduce the amount of output video pixel data, downscaling and cropping. The downscaling provides full video image at lower resolution. Cropping provides only a portion of the video image output. All these mechanisms can be controlled independently to yield maximum flexibility in the output stream. TW9906 Down-Scaling The TW9906 can independently reduce the output video image size in both horizontal and vertical directions using arbitrary scaling ratios up to 1/16 in each direction. The horizontal scaling employs a dynamic 6-tap 32-phase interpolation filter for luma and a 2-tap 8-phase interpolation filter for chroma because of the limited bandwidth of the chroma data. The vertical scaling uses simple line dropping algorithm. Therefore, the use of non-integer vertical scaling ration is not recommended. Downscaling is achieved by programming the horizontal scaling ratio register (HSCALE) and vertical scaling ratio register (VSCALE). When outputting unscaled video, the TW9906 will output CCIR601 compatible 720 pixels per line or any number of pixels per line as specified by the HACTIVE register. The standard output for Square Pixel mode is 640 pixels for 60 Hz system and 768 pixels for 50 Hz systems. If the number of output pixels required is smaller than 720 in CCIR601 compatible mode or the number specified by the HACTIVE register, the 12-bit HSCALE register, which is the concatenation of two 8-bit registers SCALE_HI and HSCALE_LO, is used to reduce the output pixels to the desired number. Following is an example using pixel ratio to determine the horizontal scaling ratio. These equations should be used to determine the scaling ratio to be written into the 12-bit HSCALE register assuming HACTIVE is programmed with 720 active pixels per line: NTSC: PAL: Where: HSCALE = [720/Npixel_desired] * 256 HSCALE = [(720/Npixel_desired)] * 256 Npixel_desired is the nominal number of pixel per line.
For example, to output a CCIR601 compatible NTSC stream at SIF resolution, the HSCALE value can be found as: HSCALE = [(720/320)] * 256 = 576 = 0x0240 However, to output a SQ compatible NTSC stream at SIF resolution, the HSCALE value should be found as: HSCALE = [(640/320)] * 256 = 512 = 0x200 In this case, with total resolution of 768 per line, the HACTIVE should have a value of 640. The vertical scaling determines the number of vertical lines output by the TW9906. The vertical scaling register (VSCALE) is a 12-bit register, which is the concatenation of a 4-bit register SCALE_HI and an 8-bit register VSCALE_LO. The maximum scaling ratio is 16:1. Following equations should be used to determine the scaling ratio to be written into the 12-bit VSCALE register assuming VACTIVE is programmed with 240 or 288 active lines per field. 60Hz system: 50Hz system: VSCALE = [240/ Nline_desired] * 256 VSCALE = [288/ Nline_desired] * 256
Where: Nline_desired is the number of active lines output per field.
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TW9906
The scaling ratios for some popular formats are listed in Table 2. TW9906 Cropping Cropping allows only subsection of a video image to be output. The VACTIVE signal can be programmed to indicate the number of active lines to be displayed in a video field, and the HACTIVE signal can be programmed to indicate the number of active pixels to be displayed in a video line. The start of the field or frame in the vertical direction is indicated by the leading edge of VSYNC. The start of the line in the horizontal direction is indicated by the leading edge of the HSYNC. The start of the active lines from vertical sync edge is indicated by the VDELAY register. The start of the active pixels from the horizontal edge is indicated by the HDELAY register. The sizes and location of the active video are determined by HDELAY, HACTIVE, VDELAY, and VACTIVE registers. These registers are 8-bit wide, the lower 8-bits is, respectively, in HDELAY_LO, HACTIVE_LO, VDELAY_LO, and VACTIVE_LO. Their upper 2-bit shares the same register CROP_HI. The Horizontal delay register (HDELAY) determines the number of pixels delay between the leading edge of HSYNC and the leading edge of the HACTIVE. Note that this value is referenced to the unscaled pixel number. The Horizontal active register (HACTIVE) determines the number of active pixels to be output or scaled after the delay from the sync edge is met. This value is also referenced to the unscaled pixel number. Therefore, if the scaling ratio is changed, the active video region used for scaling remain unchanged as set by the HACTIVE register, but the valid pixels output are equal or reduced due to down scaling. In order for the cropping to work properly, the following equation should be satisfied. HDELAY + HACTIVE < Total number of pixels per line. For NTSC output at 13.5 MHz pixel rate, the total number of pixels is 858. The HDELAY should be set to 106 and HACTIVE set to 720. For PAL output at 13.5 MHz rate, the total number of pixels is 864. The HDELAY should be set to 108 and HACTIVE set to 720. The Vertical delay register (VDELAY) determines the number of lines delay between the leading edge of the VSYNC and the start of the active video lines. It indicates number of lines to skip at the start of a frame before asserting the VACTIVE signal. This value is referenced to the incoming scan lines before the vertical scaling. The number of scan lines is 525 for the 60Hz systems and 625 for the 50Hz systems. The Vertical active register (VACTIVE) determines the number of lines to be used in the vertical scaling. Therefore, the number of scan lines output is equal or less than the value set in this register depending on the vertical scaling ratio. In order for the vertical cropping to work properly, the following equation should be observed. VDELAY + VACTIVE < Total number of lines per field Table 2 shows some popular video formats and its recommended register settings. The CCIR601 format refers to the sampling rate of 13.5 MHz. The SQ format for 60 Hz system refers to the sampling rate of 12.27 MHz, and the SQ format for 50 Hz system refers to the use of sampling rate of 14.75 MHz.
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TW9906
Scaling Ratio
Format
Total Resolution 780x525 858x525 944x625 864x625 390x262 429x262 472x312 432x312 195x131 214x131 236x156 216x156
Output Resolution 640x480 720x480 768x576 720x576 320x240 360x240 384x288 360x288 160x120 180x120 192x144 180x144
HSCALE values 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400
VSCALE (frame) 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400
1:1
2:1 (CIF)
4:1 (QCIF)
NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601
Table 2. HSCALE and VSCALE value for some popular video formats.
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TW9906 Two Wire Serial Bus Interface
Start Condition SDA
St
SCL
Figure 2. Definition of the serial bus interface bus start and stop
Device ID (1-7)
Index (1-8)
SDAT SCLK Start Condition Ack Ack
Device ID (1-7)
R/W
Data (1-8)
Re-start Condition
Ack
Stop Nack Condition
Figure 3. One complete register read sequence via the serial bus interface
Device ID (1-7)
R/W
Index (1-8)
Data (1-8)
SDAT SCLK Start Condition Ack Ack Ack Stop Condition
Figure 4. One complete register write sequence via the serial bus interface
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TW9906
The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW9906 registers. SCLK is the serial clock and SDAT is the data line. Both lines are pulled high by resistors connected to VDD. ICs communicate on the bus by pulling SCLK and SDAT low through open drain outputs. In normal operation, the master generates all clock pulses, but control of the SDAT line alternates back and forth between the master and the slave. For both read and write, each byte is transferred MSB first, and the data bit is valid whenever SCLK is high. The TW9906 is operated as a bus slave device. It can be programmed to respond to one of two 7bit slave device addresses by tying the SIAD0 (Serial Interface ADdress) pins either to VDD or VSS (See Table 3.). If the SIAD0 pin is tied to VDD, then the least significant bit of the 7-bit address is a "1". If the SIAD0 pin is tied to VSS then the least significant bit of the 7-bit address is a "0". The most significant 6-bits are fixed. The 7-bit address field is concatenated with the read/write control bit to form the first byte transferred during a new transfer. If the read/write control bit is high the next byte will be read from the slave device. If it is low the next byte will be a write to the slave. When a bus master (the host microprocessor) drives SDA from high to low, while SCL is high, this is defined to be a start condition (See Figure 2.). All slaves on the bus listen to determine when a start condition has been asserted. After a start condition, all slave devices listen for the their device addresses. The host then sends a byte consisting of the 7-bit slave device ID and the R/W bit. This is shown in Figure 3. (For the TW9906, the next byte is normally the index to the TW9906 registers and is a write to the TW9906 therefore the first R/W bit is normally low.) After transmitting the device address and the R/W bit, the master must release the SDAT line while holding SCLK low, and wait for an acknowledgement from the slave. If the address matches the device address of a slave, the slave will respond by driving the SDAT line low to acknowledge the condition. The master will then continue with the next 8-bit transfer. If no device on the bus responds, the master transmits a stop condition and ends the cycle. Notice that a successful transfer always includes nine clock pulses. To write to the internal register of theTW9906, the master sends another 8-bits of data, the TW9906 loads this to the register pointed by the internal index register. The TW9906 will acknowledge the 8-bit data transfer and automatically increment the index in preparation for the next data. The master can do multiple writes to the TW9906 if they are in ascending sequential order. After each 8-bit transfer the TW9906 will acknowledge the receipt of the 8-bits with an acknowledge pulse. To end all transfers to the TW9906 the host will issue a stop condition. Serial Bus Interface 7-bit Slave Address 1 0 0 0 1 0 SIAD0 Read/Write bit 1=Read 0=Write
Table 3 TW9906 serial bus interface 7-bit slave address and read write bit A TW9906 read cycle has two phases. The first phase is a write to the internal index register. The second phase is the read from the data register. (See figure 3). The host initiates the first phase by sending the start condition. It then sends the slave device ID together with a 0 in the R/W bit position. The index is then sent followed by either a stop condition or a second start condition. The second phase starts with the second start condition. The master then resends the same slave device ID with a 1 in the R/W bit position to indicate a read. The slave will transfer the contents of the desired register. The master remains in control of the clock. After transferring eight bits, the slave releases and the master takes control of the SDAT line and acknowledges the receipt of data
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TW9906
to the slave. To terminate the last transfer the master will issue a negative acknowledge (SDAT is left high during a clock pulse) and issue a stop condition.
Output Interface
ITU-R BT.656 ITU-R BT.656 defines strict EAV/SAV Code, video data output timing, H blanking timing, and V Blanking timing. In this mode, VD[19:10] pins are only effective and VCLK pin should be used for data clock signal. Table 4 shows EAV/SAV Code format. MSB of forth byte in EAV/SAV code must be "1" in ITU-R BT.656 standard. For that reason, VIPCFG Register bit must be set to "1". Table 4. ITU-R BT.656 SAV and EAV code sequence VD19 VD18 VD17 VD16 VD15 VD14 1 1 1 1 1 1st byte 1 0 0 0 0 0 2nd byte 0 0 0 0 0 0 3rd byte 0 F V H V XOR H F XOR H 4th byte *C
H = 0 - SAV, 1 EAV
VD13 1 0 0 F XOR V
VD12 VD11 VD10 1 1 1 0 0 0 0 0 0 F XOR V XOR H 0 0 *C is set by VIPCFG register bit.
V = 1 blanking, 0 elsewhere
F = 0 field 1, 1 field 2
For complete IRU-R BT.656 standard, following registers are required. Table 5.ITU-R BT.656 Register set up. Register 525 line system 625 line system 1 1 MODE 0 0 LEN 0x012 0x018 VDELAY 0X0F4 0x120 VACTIVE 0x2D0 0x2D0 HACTIVE 1 1 HA_EN 1 1 VIPCFG 1 0 NTSC656
ITU-R BT.656 for 525-line system has 244 video active lines in odd field and 243 vide active lines in even field. NTSC656 register bit controls this video active line length. VIP (Video Interface Port) Video port in VIP standard is the upgraded standard that has more functions in addition to ITU-R BT.656. Invalid data is set to 0x00 during the period from SAV to EAV if CTL656 register is set to "1" for this VIP application. In case of Vertical down Scaling mode, invalid line does NOT have EAV/SAV code by default setting. This mode is most popular in current VIP application. TW9906 also supports all line EAV/SAV output modes optionally. In this case, VSCTL register should be set to "1". All data will be 0x00 invalid data from SAV to EAV on invalid line in this mode. Starting position of vertical active output video line is programmable by VDELAY register. The number of active video lines is also programmable by VACTIVE register.
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TW9906
Control Signals TW9906 outputs various control signals. VSYNC and FIELD are vertical timing control signals. HSYNC and DVALID are horizontal timing control signals. These control signals are mainly used on 601 mode (MODE register bit is set to "0".). Vertical timing diagram FIGURE 5 shows typical vertical timing for 60Hz/525 lines system. Figure 7 shows typical vertical timing for 50Hz/625 lines system. On Figure 7,VDELAY register is 19DEC(0x13) and VACTIVE register is 241DEC(0x0F1). Figure 8 shows typical NTSC-M setting. On Figure 8, VDEALY register is 24 decimal (0x18) and VACTIVE register is 286 decimal (0x11E). FIGURE 6 shows typical PALB setting. The leading edge of VACTIVE is controlled by VDELAY register value. The length of video active lines is controlled by VACTIVE register value. As shown on Figure 7 and 8, output video data stream has 2 lines vertical delay compared to input VIDEO line timing.
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TW9906
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
INPUT VIDEO
TECHWELL, INC.
VDELAY 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
HSYNC
HACTIVE
VSYNC
FIELD
VACTIVE
OUTPUT VIDEO
523
524
525
1
- Odd field -
19
3 266 267 268 269 270 271 272 273 274 275 276 277 278 279 4 5 6 7 8 9 10 11 12 13 14 15 16 17 280 VDELAY 1 264 265 266 267 268 269 270 2 3 4 5 6 7 8 271 9 272 10 273 11 274 12 275 13 276 14 277 15 278
1
2
18 281
19 282
20 283
21 284
22 285
23 286
24 287
262
263
264
265
INPUT VIDEO
HSYNC
HACTIVE
VSYNC
FIELD
VACTIVE
OUTPUT VIDEO
16 279
17 280
18 281
19 282
20 283
21 284
22 285
261
262
263
- Even field F ig u r e 7 .V e r t ic a l t im in g d ia g r a m f o r 6 0 H z /5 2 5 lin e s y s t e m
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TW9906
622
623
624
625
1
2
3
4
5
6
7
8
9
10
11
....
20 25 26
21
22
23
24
INPUT VIDEO
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VDELAY 622 623 624 625 1 2 3 4 5 6 7 8 9 ... 18 19 20 21 22 23 24
HSYNC
HACTIVE
VSYNC
FIELD
VACTIVE
OUTPUT VIDEO
620
621
- Odd field 1 311 312 313 314 315 316 317 318 319 320 321 322 323 324 2 3 4 5 6 7 8 9 10 11 ... ... 20 333 21 334 22 335 23 336 24 337 25 338 26 339
20
VDELAY 1 309 310 311 312 313 314 315 2 3 316 4 317 5 318 6 319 7 320 8 321 9 322 ... ...
310
INPUT VIDEO
HSYNC
HACTIVE
VSYNC
FIELD
VACTIVE
OUTPUT VIDEO
18 331
19 332
20 333
21 334
22 335
23 336
24 337
308
- Even field F ig u r e 8 .V e r t ic a l t im in g d ia g r a m f o r 5 0 H z /6 2 5 lin e s y s t e m
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TW9906
HSYNC The leading edge of HSYNC signal is synchronized to input Video horizontal sync timing. The start position of HSYNC signal is programmable by HSBEGIN register. The end position of HSYNC signal is also programmable by HSEND registers. HACTIVE HACTIVE signal is generated by video decoding process. The active clock period is equal to (HACTIVE register value x 2) clkx2 clock period. VSYNC The leading edge of VSYNC signal is synchronized to vertical sync pulse of input Video. The leading edge position of VSYNC signal is programmable by OVSDLY register on a per clkx2 clock basis. The trailing edge of VSYNC signal is in the middle of HSYNC "1" period in odd field and in the middle of HSYNC "0" period in even field. The trailing edge of VSYNC changed on line 10 in 525 lines system and on line 7 in 625-line system as default. This line number is programmable by OVSEND register on a per line basis. FIELD Figure 7 and Figure 8 show field signal output assuming default OFDLY register 2H.The line output timing of FIELD signal is programmable by OFDLY register value (1H to 6H). If OFDLY is set to 0H, FILED signal is synchronized to the leading edge of VSYNC signal. If OFDLY is set to 7H, FIELD signal is synchronized to the leading edge of VACTIVE signal. Default FIELD signal shows the ITU-R BT.656 field timing in 656 output video stream by OFDLY register 2H. Horizontal Down Scaling Output TW9906 generates Horizontal down scaling output data. Figure 9 shows 10 bit mode Horizontal Down Scaling output timing and Figure 10 shows 20 bit mode Horizontal Down Scaling output timing. As shown Figure 9 and Figure 10, Horizontal Down Scaled data are generated by continuous data stream. The trailing edge of DVALID signal changes with the trailing edge of HACTIVE signal. Data value from the leading edge of HACTIVE to the leading edge of DVALID is programmable by CNTL656 register. If CNTL656 is set to "1", all Y and CbCr data will be 0x00. If CNTL656 is set to "0", all Y data will be 0x10 and all CbCr data will be 0x80. VIP application normally uses 0x00 data as invalid data. Figure9 and Figure 10 show 360 active pixels output timing after horizontal downscaling.
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TW9906
VCLK HACTIVE DVALID
HACTIVE x 2 VCLK 360x2 VCLK
VD[19:10]
0x000
Cb0
Y0
Cr0
Y1
Cb2
...
Cb358
Y358
Cr358
Y359
Figure 9. 10 bit mode Horizontal Down Scaling Output
VCLK HACTIVE DVALID
HACTIVE VCLK 360 VCLK
VD[19:10] VD[9:0]
0x000
Y0
Y1
... ...
Y358
Y359
0x000
Cb0
Cr0
Cb358
Cr358
Figure 10. 20 bit mode Horizontal Down Scaling Output
Vertical Down Scaling Output TW9906 generates Vertical Down Scaling output data. Figure 11 shows its timing. As shown on Figure 11, HACTIVE is NOT generated on invalid line as default (VSCTL is "0"). If VSCTL is set to "1", HACTIVE is generated on every lines during VACTIVE active period. DVALID is not generated on invalid lines in each setting. Invalid lines for Vertical down scaling are generated during VACTIVE active period. If MODE bit is set to "1" for VIP mode, EAV/SAV codes are not generated on those lines without HACTIVE signal. All CbCr data will be 80H and all Y data will be 10H the same as H-blanking data in ITU-R BT.656 data stream.
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TW9906
HSYNC HACTIVE DVALID VACTIVE LVALID (OPTION)
Figure 11. Vertical Dow n Scaling Output
VBI Data Processing
Raw VBI data output TW9906 supports raw VBI data output. Raw VBI data output has the same vertical line delay timing as video output. Horizontal output timing is also programmable by VBIDELAY register. Raw VBI data is generated during HACTIVE active period (from SAV to EAV) as Video data output. Total pixel number of raw VBI data per line is twice as many as HACTIVE register value. If VBI EN register is set to "1", all vertical blanking output while VACTIVE is inactive will be raw VBI data output. If VVBI registers are set to more than "1", the VVBI number lines from top video active lines will also be raw VBI data output lines.
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TW9906
VBI Data Slicer The following VBI standards are supported by VBI Data slicer. In TW9906, VBI Data slicing is controlled by registers LCTL6 to LCTL26. Registers LCTL6 to LCTL26, which control the slicing process itself, define what Data Type to be decoded. The Data Type can be specified on a line by line basis for line6 to line26 and for even and odd field depending on the detected TV system standard. The setting for LCTL26 is valid for the rest of the corresponding field. Normally, no text data 0H (video data) should be selected to render the VBI Data slicer inactive during active video. LCTL26 is useful for Full-Field Teletext mode in the case of NABTS. NABTS is 525 Teletext-C. Japan's MOJI is 525 Teletext-D. Didon Antiope is 625 Teletext-A. VBI Data slicer supports up to Physical layer, Link layer in ITU-R BT.653-2. Japan's EIAJ CPR-1204, shown as 525 WSS, has the same physical layer protocol as that of CGMS. The Default VBI Data Slicer is in power-down reset status. PdnSVBI register must be set to 1 for VBI Data Slicer goes into normal mode. The sliced VBI data is embedded in the ITU-R BT.656 output stream, using the intervals between the End of Active Video (EAV) and the Start of Active Video (SAV) of each line, and formatted according to ITU-R BT.1364 Ancillary data packet Type 2. Data Type shows the register setting value in LCTLn registers.
VBI Standards STANDARD TYPE TV Systems (lines/freq) 625/50 525/60 625/50 525/60 625/50 525/60 625/50 525/60 626/50 525/60 625/50 525/60 525/60 525/60 625/50 625/50 Bit Rate (Mbits/s) 6.9375 5.727272 5.734375 5.727272 5.6427875 5.727272 0.500 0.503 5 0.447443 1.8125 1.7898 1.007 0.503 5 6.203125 Modulation Data Type
625 Teletext-B 525 Teletext-B 625 Teletext-C 525 Teletext-C 625 Teletext-D 525 Teletext-D 625 CC 525 CC 625 WSS 525 WSS(CGMS) 625 VITC 525 VITC Gemstar 2x Gemstar 1x VPS 625 Teletext-A
NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ Bi-phase NRZ NRZ NRZ NRZ NRZ Bi-phase NRZ
1H 1H 2H 2H 3H 3H 4H 4H 5H 5H 6H 6H 7H 8H 9H AH
Sliced VBI Data output format After 4 bytes of EAV code, sliced VBI ANC data packets are generated by following format DID, SDID, DC, IDI1, IDI2, CS, and BC. Two types of ANC packet format are supported. Following Tables show two types of ANC packet format. All sliced VBI ANC packet format can be changed by ANCMODE register. In following Tables, all type of sliced VBI ANC packet with ANCMODE=1 as examples. If ANCMODE=0, all type of sliced VBI ANC packet have format 0 type.
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TW9906
Sliced VBI ANC data packet format 0(ANCMODE=0)
BYTE No. 1 2 3 4 5 6 7 8 9 10 11 12 13 . . 4N+6 4N+7 4N+8 D7 MSB 0 1 1 NEP NEP NEP 0 D6 0 1 1 EP EP EP 0 D5 0 1 1 0 SDID5 DC5 D4 D3 D2 D1 0 1 1 DID1 SDID1 DC1 D0 LSB 0 1 1 DID0 SDID0 DC0 DESCRIPTION Ancillary data flag
CS7 0
CS6 0
0 0 0 1 1 1 1 1 1 1 0 DID2 SDID4 SDID3 SDID2 DC4 DC3 DC2 Video line #[7:0] 0 Data Macth1 Mach2 Error Sliced VBI Data byte 1 Sliced VBI Data byte 2 Sliced VBI Data byte 3 Sliced VBI Data byte 4 Sliced VBI Data byte 5 . . Sliced VBI Data byte last or FILLDATA CS5 CS4 CS3 CS2 0 0 0 0
Video line #[9:8]
DID SDID DC IDI1. UDW1 IDI2. UDW 2 Sliced VBI Data No.1. UDW3 Sliced VBI Data No.2. UDW4 Sliced VBI Data No.3 UDW5 Sliced VBI Data No.4. UDW6 Sliced VBI Data No.5. UDW7
CS1 0
CS0 0
Sliced VBI Data Last or FILLDATA. UDW 4N CS BC
EP is Even Parity of bits 5 to 0 in same 1 byte. NEP is inverted EP in same 1 byte. DID: 91h: Sliced data of VBI lines of field 1. 53h: Sliced data of lines 24 to end of field 1. 55h: Sliced data of VBI lines of field 2. 97h: Sliced data of lines 24 to end of field 2. SDID[5:0]: 0h: Teletext(A,B,C,D) 1h: CC(525,625) 2h: WSS(525,625) 3h: VITC(525,6256) 4h: VPS(625 only),Gemstar2x(NTSC only) 5h: Gemstar1x(NTSC only) DC[5:0]: The number of DWORDs beginning with byte9 through 4N+8.Each DWARD is 4 bytes. IDI1: Transaction video line number[7:0] IDI2: Bit1-0 - Transaction video line number[9:8] Bit2 - Match 2 flag. Bit3 - Match 1 flag. Bit4 1 if an error was detected in teletext packet.0 if no error was detected. CS: Sum of D7-D0 of UDW3 through UDW4N. FILLDATA is FILLDATA register value. FILLDATA is inserted after last valid bytes to make 4N number byte stream sometimes.
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TW9906
Sliced VBI ANC data packet format 1(ANCMODE=1)
BYTE No. 1 2 3 4 5 6 7 8 9 10 11 12 13 . . 4N+6 4N+7 4N+8 D7 MSB 0 1 1 NEP NEP NEP OP OP D6 0 1 1 EP EP EP FID LN2 D5 0 1 1 0 SDID5 DC5 LN8 LN1 D4 D3 D2 D1 0 1 1 DID1 SDID1 DC1 LN4 DT1 D0 LSB 0 1 1 DID0 SDID0 DC0 LN3 DT0 DESCRIPTION Ancillary data flag
NCS6 OP
CS6 0
0 0 0 1 1 1 1 1 1 DID4 DID3 DID2 SDID4 SDID3 SDID2 DC4 DC3 DC2 LN7 LN6 LN5 LN0 DT3 DT2 Sliced VBI Data byte 1 Sliced VBI Data byte 2 Sliced VBI Data byte 3 Sliced VBI Data byte 4 Sliced VBI Data byte 5 . . Sliced VBI Data byte last or FILLDATA CS5 CS4 CS3 CS2 BC5 BC4 BC3 BC2
DID SDID DC IDI1. UDW1 IDI2. UDW 2 Sliced VBI Data No.1. UDW3 Sliced VBI Data No.2. UDW4 Sliced VBI Data No.3 UDW5 Sliced VBI Data No.4. UDW6 Sliced VBI Data No.5. UDW7
CS1 BC1
CS0 BC0
Sliced VBI Data Last or FILLDATA. UDW 4N CS BC
EP is Even Parity of bits 5 to