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Digital Processor / Digital Mixer

SERVICE MANUAL

Models: IQ-USM 810
Some models may be exported under the name Amcron.Ž

Š2000 by Crown International, Inc., P.O. Box 1000, Elkhart, Indiana 46515-1000 U.S.A. Telephone: 219-294-8000. Trademark Notice: Distributed IntelligenceTM and IQ for WindowsTM are trademarks and Crown Ž, IQŽ, and IQ System Ž are registered trademarks of Crown International, Inc. Other trademarks are the property of their respective owners.

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The information furnished in this manual does not include all of the details of design, production, or variations of the equipment. Nor does it cover every possible situation which may arise during installation, operation or maintenance. If you need special assistance beyond the scope of this manual, please contact the Crown Technical Support Group. Mail: P.O. Box 1000 Elkhart IN 46515-1000 Shipping: Plant 2 SW 1718 W. Mishawaka Road Elkhart IN 46517 Phone: (800) 342-6939 / (219) 294-8200 FAX: (219) 294-8301

CAUTION
TO PREVENT ELECTRIC SHOCK DO NOT REMOVE TOP OR BOTTOM COVERS. NO USER SERVICEABLE PARTS INSIDE. REFER SERVICING TO QUALIFIED SERVICE PERSONNEL. DISCONNECT POWER CORD BEFORE REMOVING REAR INPUT MODULE TO ACCESS GAIN SWITCH.

AVIS
Ŕ PRÉVENIR LE CHOC ÉLECTRIQUE N'ENLEVEZ PAS LES COUVERTURES. RIEN DES PARTIES UTILES Ŕ L'INTÉRIEUR. DÉBRANCHER LA BORNE AVANT D'OUVRIR LA MODULE EN ARRIČRE.

WARNING
TO REDUCE THE RISK OF ELECTRIC SHOCK, DO NOT EXPOSE THIS EQUIPMENT TO RAIN OR MOISTURE!

The lightning bolt triangle is used to alert the user to the risk of electric shock.

The exclamation point triangle is used to alert the user to important operating or maintenance instructions.

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Revision History
Revision Number
Rev. A

Date
04-2000

Comments
Initial Printing

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Table of Contents
1 Introduction ............................................................................ 1-1
1.1 Introduction ................................................................................ 1-1 1.2 The IQ-USM 810 ........................................................................ 1-1 1.3 Warranty ..................................................................................... 1-1

2 Specifications ......................................................................... 2-1 3 Circuit Theory ........................................................................ 3-1
3.1 Overview .................................................................................... 3-1 3.2 Power Supply ............................................................................. 3-1 3.3 Input ........................................................................................... 3-1 3.3.1 Input Analog Processing ................................................... 3-1 3.3.2 Clock Signals .................................................................... 3-2 3.3.3 A/D Conversion ................................................................. 3-2 3.3.4 DC Voltages ...................................................................... 3-4 3.4 Output ........................................................................................ 3-4 3.4.1 Clock Buffers ..................................................................... 3-4 3.4.2 DAC Conversion ................................................................ 3-4 3.4.3 Output Analog Processing ................................................ 3-4 3.5 SHARC Processing .................................................................... 3-5 3.5.1 +3.3V Power Supply .......................................................... 3-5 3.5.2 Clocks ............................................................................... 3-5 3.5.3 Reset ................................................................................. 3-5 3.5.4 System Control Interface ................................................... 3-5 3.5.5 PLDs .................................................................................. 3-6 3.5.6 Bus Arbitration ................................................................... 3-6 3.5.7 Bus Utilization .................................................................... 3-6 3.5.8 DSP Processing ................................................................ 3-6 3.5.9 Audio Routing .................................................................... 3-8 3.6 System Controller ....................................................................... 3-8 3.6.1 Control Processing ............................................................ 3-9 3.6.2 RS232 .............................................................................. 3-10 3.6.3 Crown Bus Loop .............................................................. 3-10 3.6.4 Real Time Clock .............................................................. 3-10 3.6.5 Front Panel ...................................................................... 3-10 3.6.6 Control Port ..................................................................... 3-10 3.7 Front Display ............................................................................ 3-10

4 Maintenance ........................................................................... 4-1
4.1 General Information.................................................................... 4-1 4.2 Definitions ................................................................................... 4-1 4.3 Required Test Equipment .......................................................... 4-1 4.4 Message String Syntax .............................................................. 4-2
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Table of Contents
4.5 Standard Initial Conditions ........................................................ 4-2 4.6 Test Procedures ......................................................................... 4-2 4.7 Typical Measurements ............................................................... 4-7 4.8 Test/Debug Objects ................................................................... 4-7 4.9 Display Test Patterns ................................................................. 4-8 4.10 Error Codes .............................................................................. 4-9 4.11 Troubleshooting FAQs ............................................................. 4-9

5 Parts Information ................................................................... 5-1
5.1 General Information .................................................................. 5-1 5.2 Ordering and Receiving Parts .................................................. 5-1 5.2.1 Terms ..................................................................................... 5-1 5.2.2 Shipment ................................................................................ 5-1

6 Exploded View Parts ............................................................. 6 -1 7 Module and Schematic Information ..................................... 7 -1 8 Module Parts .......................................................................... 8-1
PWA 126451-3 PWA 126690-3 PWA 126693-4 PWA 126744-3 PWA 128045-1 PWA 128047-3 PWA 128047-4 PWA 128049-1 PWA 128051-3 ................................................................................. 8-3 ............................................................................... 8-13 ............................................................................... 8-47 ............................................................................... 8-59 ............................................................................... 8-65 ............................................................................... 8-75 ............................................................................... 8-87 ............................................................................... 8-99 ............................................................................. 8-117

9 Schematics ............................................................................ 9-1

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1 Introduction
1.1 Introduction
This manual contains complete service information on the CrownŽ IQ-USM 810 Digital Processor/Digital Mixer. It is designed to be used in conjunction with the Reference Manual; however, some important information is duplicated in this Service Manual in case the Reference Manual is not readily available. NOTE: THE INFORMATION IN THIS MANUAL IS INTENDED FOR USE BY AN EXPERIENCED TECHNICIAN ONLY!

Outputs and eight AUX Audio Outputs. The Main and AUX Audio Output sections further process the signal with individually adjustable signal delay and filters along with an Ambient-Leveler and a high performance Output Limiter for system protection. A Multi-Function Control Port implements analog and digital I/O for control and monitor by simple potentiometer and switch wall controllers and indicator panels. All of the IQ-USM 810 parameters are backed up via reliable FLASH memory. System configurations may be stored for recall from any of thirty-two system presets from the front panel control or via IQ for Windows software.

1.2 The IQ-USM 810
The Crown IQ-USM 810 is an 8x10 mixer/processor that provides unique dual input processing paths. As an IQŽ component, it can be controlled by an IQ SystemŽ, and with its distributed intelligenceTM capability, continue to operate even when an IQ System is not connected. The IQ-USM 810 can also act as a system interface to other IQ components. The IQ-USM 810 features high-quality 24-bit A/D and D/A converters along with 240MIPS of full 32-bit floating point DSP for optimum dynamic range. The dual input processing paths include a full complement of signal processing features, including advanced algorithms for gating, auto-leveling, filtering, compression and automixing. A full 8x8 Matrix Mixer allows any combination of routing and mixing from any input to any output. The Matrix Mixer outputs are routed to the two Main Audio

1.3 Warranty
Each Reference Manual contains basic policies as related to the customer. In addition, it should be stated that this service documentation is meant to be used only by properly trained personnel. Because most Crown products carry a 3-Year Full Warranty (including round trip shipping within the United States), all warranty service should be referred to the Crown Factory or Authorized Warranty Service Center. See the applicable Reference Manual for warranty details. To find the location of the nearest Authorized Warranty Service Center or to obtain instructions for receiving Crown Factory Service, please contact the Crown Technical Support Group (within North America), or your Crown/Amcron Importer (outside North America). If you are an Authorized Warranty Service Center and have questions regarding the warranty of a product, please contact the Crown Factory Service Manager or the Crown Technical Support Group.

Crown Customer Service
Technical Support Group Factory Service Parts Department Mailing Address: P.O. Box 1000, Elkhart IN 46515 Shipping Address: Plant 2 S. W. 1718 W. Mishawaka Rd., Elkhart IN 46517 Phone: (219) 294-8200 Toll Free: (800) 342-6939 Fax: (219) 294-8301 http://www.crownaudio.com

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Figure 1.1 IQ-USM 810 Front and Rear Views

1-2 Introduction

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2 Specifications
General
Front Panel Controls: Front-panel switches select IQ Address, Baud Rate, factory default preset (P00), and any of 32 user-defined presets (P01P32). Rear-Panel Controls: A 3-position selector switch (mic/line/phantom) and a calibrated gain control for each input. Connectors: Crown Bus: RJ-45 for input/output, RJ-45 for daisy output, RS232: DB9F computer interface for both component and interface modes. Multi-function Port: DB37M for analog inputs, digital inputs, digital outputs, +5VDC, +10VDC and Ground. Audio Inputs and Outputs: 3-pin male removable barrier block connectors, Euro-style cable connector supplied. AC Power: IEC320 connector for AC power cord. Display: A blue front-panel Enable indicator lights to show that the unit is plugged in and AC power is being supplied. An amber front-panel Data Signal Presence Indicator (DATA) flashes whenever commands addressed to the IQ-USM 810 are received. A green front-panel Interface indicator lights when the IQ-USM 810 is being used as system interface. A three-digit digital display indicates the IQ-USM 810's initialization sequence by displaying each processor's name as it comes online, indicates the presently selected preset, indicates the IQ address and baud rate while those parameters are being adjusted, indicates when a parameter has been stored in flash memory, and when any parameter is varied from its value within the currently selected preset. Ladder Display: A front panel, sixteen-segment LED display matrix can be set to three different operating modes: Level Meter, Input Gate Status, and Infinity Pattern. Power Requirements: 100VAC to 240VAC, 35VA nominal. Protection: if communication is lost, the unit will continue to function with the last commands received.

1 stop bit; 8 data bits; no parity. Crown Bus Interface Type: Optically isolated 20 mA current loop. Operation: Half-duplex. Transmission Distance: Variable from 200 to 3000 feet (61 to 914 meters), depending upon wire capacitance. Typically 1000 feet (305 meters) using shielded twisted-pair wire, #26 AWG or larger. Can be extended with an IQ Repeater.

Audio
Phantom Voltage: +24VDC at 10 mA. Input Gain Range: +20 dB to 12 dB. Digital Sampling: 24 bit, 48 kHz. Input Impedance: 20 k ohms balanced, 10 k ohms unbalanced. Dynamic Range: Greater than 100 dB (A-weighted, 20 Hz20 KHz). Frequency Response: ą 0.5 dB, 20 Hz20 kHz. Common Mode Rejection: 50 dB (typical). Crosstalk: Greater than 80 dB at 10 kHz. Total Harmonic Distortion: Less than 0.05% THD + N (1 kHz, 0 dBu). Output Impedance: 100 ohms balanced, 50 ohms unbalanced. Max Input Level: +32 dBu (line) or +7 dBu (mic). Max Output Level: +20 dBu.

Control Port
Power Supply: +5VDC and +10VDC outputs are provided. The total output current is limited to 1A. Outputs Logic Low: less than 0.1V. Logic High: 10V (via internal pull-up). Output Current is limited to 10mA max per pin. Inputs Input Impedance: greater than 50 k ohms. Logic Low: less than 0.5V. Logic High: greater than 5V. Analog Range: 0 to 10V (for inputs 9-16 only). Max Input Voltage: 25V.

RS232 Data Communication
Baud Rate: Selectable to 19.2 K, 38.4 K, 57.6 K, or 115.2 K BAUD. Data Format: Serial, binary, asynchronous; 1 start bit; 1 stop bit; 8 data bits; no parity.

Mechanical
Weight: 13 pounds, 4 ounces (6.1 kg). Dimensions: 19-inch (483-cm) standard rack mount width (EIA RS-310-B), 16-inch (40.6-cm) depth behind mounting surface, and 3.5-inches (8.9-cm) height.

Crown Bus Data Communication
Data Rate: 38.4 K BAUD. Data Format: Serial, binary, asynchronous; 1 start bit;

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3 Circuit Theory
3.1 Overview
This section explains operation of the IQ-USM 810 circuitry. Please refer to the IQ-USM 810 Reference Manual and IQ for Windows help files for information about the IQ-USM 810 features and operation. The IQ-USM 810 consists of a universal power supply and 5 PWAs (see Figure 3.1). Each PWA has a particular function and initial troubleshooting should focus on attempting to determine which PWA is causing the malfunction. The PWAs are not unit-dependent, so a known good working PWA or unit can be used to pinpoint which PWA is faulty.

3.3 Input
The input Printed Wire Assembly (PWA) is located at the back of the unit on the bottom. It offers eight balanced input audio channels via 3 pin connectors. Figure 3.2 shows the block diagram of the input PWA. The PWA is composed of the following sections: Input Analog Processing, Clock Signals, A/D Conversion, and DC Voltages.

3.3.1 Input Analog Processing
Each input channel has analog processing that provides filtering, line/mic switching, phantom power, optional input transformer isolation, and variable gain control. The balanced output of each analog channel is fed to a shared A/D converter. All eight analog input channels are identical (Figure 3.3). The balanced analog input is RF filtered by FB100, FB101, C102, and C103. Capacitors C100 and C101 provide filtering to ensure that no noise from the unit goes out. R100-102 provide a 10 k ohm balanced input impedance in the line mode. Switch SW100 provides switching between Phantom, Line, and Mic modes. ˇ Phantom: SW100 shorts R103/C104 and R104/ C105 to allow the phantom DC voltage (+24VDC) to be available on the input connector. In addition, no gain reduction is provided on the input path. R105 & R106 allows current limiting of the phantom voltage.

3.2 Power Supply
The universal power supply used by the IQ-USM 810 resides underneath the System Controller at the back of the unit. It receives AC input from the IEC filter located on the back panel and supplies +15V, 15V, and +5VDC to the System Controller. There is a fuse located on the supply and should be checked if the power supply is suspected. Replace fuse with the same rated type only.

Figure 3.1 Overall Block Diagram

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Figure 3.2 Input PWA Block Diagram ˇ Line: In Line mode, both the coupling capacitors (C104 & C105) and the series resistors (R103 & R104) are in the signal path. The capacitors block the phantom voltage from the input while the series resistors work as a voltage divider with R105 & R106 to provide a 17.7x (25 db) reduction in gain. ˇ Mic: The coupling capacitors are provided to block the phantom power, but the series resistors are shorted, allowing full gain through the input channel. L100/C106 (L101/C107) provide an additional low-pass filter. C108 & C109 provide coupling to the variable gain preamp, except when the optional input isolation transformer (T100) is in place. Q100 and Q101 form a differential amplifier whose gain is adjusted by R111. U100B provides a filtered differential to single-ended conversion. U101C provides a gain reduction and biases the input signal to +2.2VDC. The output bias voltage of the A/D converter's pin 15 is fed to the op amp to bias the signal to the A/D's bias point. Lack of voltage at pin15 is an indication that the A/D converter is either in reset or is not being clocked. generates a 12.288 MHz signal (256Fs). This clock is buffered by U3 and provides separate outputs to each of the A/D converters, the Output PWA for the DAC's, and to the SHARC PWA for distribution to the optional CobraNetTM (CNET) PWA. U1 normally acts as the generator of the Serial Clock and the Frame Clock. Serial Clock provides the timing of the serial audio data, 3.032 MHz (64Fs), and Frame Clock is the actual sampling clock frequency, 48 kHz (Fs). U1 monitors the CNET line from the SHARC PWA immediately out of reset. If the pin is low, it acts as a master source and begins providing Serial Clock and Frame Clock to U4 & U5 for buffering and distribution. If U1 senses a high on the CNET pin out of reset, it operates in slave mode like the other A/D converters and waits for Serial and Frame Clocks from the CNET PWA.

3.3.3 A/D Conversion
Each A/D converter processes 2 input channels. Full scale input signals are 2.82Vp-p and are sampled at a 48-kHz rate with 24-bit resolution. The converters are reset by the DSP's by the IO_RST line with a low being reset. The converters provide an I2S 32-bit time-division multiplexed data audio stream. The most significant 24 bits are linear PCM (two's complement) audio data followed by 8 bits of converter peak hold data that is unŠ2000 Crown International, Inc.

3.3.2 Clock Signals
The master oscillator for the audio signals is Y1, which 3-2 Circuit Theory

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Figure 3.3 Input Analog Processing Circuitry (one channel)
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Figure 3.4 Audio Data and Clock Signals used. This data is routed to the SHARC PWA for processing (ADC1-4). Figure 3.4 shows the audio data and its relationship to the clock signals. Each DAC takes a 2 channel I2S 32-bit time-division multiplexed data audio stream from the SHARC PWA and converts it at a 24-bit, 48-kHz rate (Figure 3.4). Like the A/D converter, the audio output of the DAC is biased positive by 2.2V and a full signal is 2.82Vp-p.

3.3.4 DC Voltages
The Input PWA receives +/15V and +5V from the System Controller. +15V from P900 is filtered and then regulated by a low dropout regulator, U900. R900 & R901 set the output voltage of the regulator at +14.5V. The 15V is processed similarly by U901. The +5V is filtered separately for the digital portion of the PWA than the analog side. The phantom power voltage is generated by U902. +15V from P900 drives L904 while Q900 acts as a switch to charge L904. R905 acts as a current sense and limits the output current of the phantom power by reducing the voltage at currents over 50 mA. R904 & R908 set the output voltage at about +26V. U902 is driven from a 96-kHz clock provided by U10. This ensures that the switching supply is synced to the sampling frequency of the converters (2Fs). During reset, U902 will run at a slightly lower frequency due to the lack of an input clock.

3.4.3 Output Analog Processing
All ten analog output channels are identical (Figure 3.6). The balanced output of the DAC drives a unity gain amplifier that also filters the audio signal. The singleended output is fed to U101A which provides gain of either 1.2 (+10 dbu) or 3.9 (+20 dbu). Z100 is normally open, which provides a +20 dbu output for a full scale signal from the DAC. U101C provides a gain reduction of 2, then U101D inverts the signal and provides the other balanced output. An output impedance of 50 ohms is provided by the series resistors while the output ferrite bead provides RF filtering to ensure isolation. Optional isolation transformers are available on the Main outputs by removing the series resistors and placing the transformers.

3.4 Output
The Output PWA sits on top of the Input PWA and provides 10 audio outputs; Main A/B and AUX 1-8. The Output PWA receives all of its signals from the Input PWA via a 26-pin ribbon cable. Functionality can be divided into Clock Buffers, DAC Conversion, and Output Analog Processing. A block diagram of the Output PWA is shown in Figure 3.5.

3.4.1 Clock Buffers
Three clock buffers, U1-3, accept the Master (12.288 MHz), Serial (3.032 MHz), and Frame (48 kHz) clocks from the Input PWA and provide separate outputs to each of the five DAC's.

3.4.2 DAC Conversion

Figure 3.5 Output PWA Block Diagram
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Figure 3.6 Output Analog Processing Circuitry (one channel)

3.5 SHARC Processing
The SHARC PWA sits in the center of the chassis and is the DSP engine that provides all of the signal processing for the unit. At the core of this processing is four Analog Devices ADSP-21065L SHARC 32-bit floating point DSP's running at an internal rate of 60 MHz. Full speed SDRAM interface is provided. Figure 3.8 shows the block diagram of the SHARC PWA. Features include a +3.3V Power Supply, Clocks, Reset, System Controller Interface, PLD's, Bus Arbitration, Bus Utilization, DSP Processing, and Audio Routing.

3.5.1 +3.3V Power Supply
The entire SHARC PWA utilizes +3.3V by taking the +5V from P1 and converts it to +3.3V using a 300-kHz switching supply IC, U29. Q2 & Q3 work with U29 to control the charging of L1. R200 current senses the supply for overload protection. C27 & C113 provide output filtering of the supply.

ceives commands from the System Controller (SH_A02, \HCS, HR/W) to load data and addresses into these latches. Once the data is in the latches, U23 communicates with Arbiter PLD U24 (\SYSBR, \SYSBG, \RD, \WR) to request access to the SHARC bus. There are no non-volatile memory resources on the SHARC PWA, so the System Controller stores the SHARC firmware and downloads it during boot. The System Controller boots each SHARC in succession by loading code into SRAM and into each SHARC via the Interface. Once all four SHARC have been booted, they are allowed to begin audio processing. If the System Controller encounters any problems during the boot process, it will display an error code on the front panel display. These error codes are shown in the table in Figure 3.7:

3.5.2 Clocks
Oscillator Y1 provides a 30-MHz clock to buffer U3 for distribution to all SHARC's, SRAM, and other circuitry.

3.5.3 Reset
U8 monitors both the +5V and +3.3V power supplies and places the SHARC's into reset if either supply droops. In addition, the System Controller uses U8 to reset the SHARC's using pulldown via D1. Switch S1 allows manual reset of the SHARC's for troubleshooting. Q1 monitors the reset line to the SHARC's and lights LED E5 when the SHARC's are not in reset. The active low \RST line resets all four SHARC's and the PLD's (U9, U11, U23, U24, and U30).

E1 E2 E3 E4 E5 E10 E11 E12 E13 E22 E23 E24 E25

UART failed system controller power-on self test RAM failed system controller power-on self test Application code in flash failed CRC test Flash verify error Unrecoverable firmware error SHARC 0 interface hardware error (timeout, etc.) SHARC 1 interface hardware error (timeout, etc.) SHARC 2 interface hardware error (timeout, etc.) SHARC 3 interface hardware error (timeout, etc.) SHARC 0 software watchdog timeout SHARC 1 software watchdog timeout SHARC 2 software watchdog timeout SHARC 3 software watchdog timeout

Figure 3.7 System Controller Error Codes Note: Errors 1-9 are for power-up self test and other miscellaneous errors. Errors 10-25 are errors related to the SHARC subsystem.

3.5.4 System Controller Interface
Communications between the System Controller and SHARC processors occurs through a series of latches (U12-22) that provide address and data. PLD U23 reŠ2000 Crown International, Inc.

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Figure 3.8 SHARC PWA Block Diagram The System Controller will display the error code, then begin the boot process again. By watching the boot process on the front display, the error code can be read at the end of the boot process before the next boot begins.

3.5.7 Bus Utilization
The Arbiter PLD also works with the Bus Utilization PLD, U30, to monitor each SHARC processor and determine how much of the available SHARC bus bandwidth each is using. The Arbiter tells the Utilization PLD on an individual bus cycle basis when each SHARC is on the bus (UTILIN0-5) and this information is fed to the individual SHARC's pulse width modulation inputs (UTILOUT0-3) for calculation of bus access time. This information is then reported to the System Controller when requested.

3.5.5 PLDs
There are five Programmable Logic Devices (PLD) on the SHARC PWA (U9, U11, U23, U24, and U30). These IC's are programmed on the PWA and can be reprogrammed. They have common control and clock lines (ETCK, ETMS) and are daisy-chained by having each output (TDO) tied to the next PLD's input (TDI). P3 allows connection to the external PLD programmer.

3.5.8 DSP Processing
As stated, the four SHARC processors (U25-28) are the core of the DSP engine. These processors are 208-pin Plastic Quad Flat Packs (PQFP) and the pinout is shown in Figure 3.9. Each SHARC has a specific task in the audio processing chain. SHARC 0 (U25) processes the input audio for channels 1-4, while SHARC 1 (U27) is tasked with the input audio processing for channels 5-8. Two channel serial audio data from the Input Router, U9, is sent to the appropriate SHARC's serial port along with audio clock signals Serial Clock (SCK) and Frame Clock (FS). The input audio is stored by the SHARC until 16 samples are accumulated, then this audio "brick" is processed.

3.5.6 Bus Arbitration
The 32-bit data and 24-bit address busses of the SHARC PWA are shared between the System Controller and the four SHARC processors. Shared SRAM memory (U5-6) is also available to all processors. The Arbiter PLD, U24, polices which has access to the bus through the use of control signals such as bus requests (\HBR, \SYSBR, \BR0-3), bus grants (\HBG, \SYSBG, \BG0-3), and SHARC chip selects (\CS0-3). It regulates which and when each processor has control of the bus to ensure there is no contention. 3-6 Circuit Theory

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Figure 3.9 SHARC Pinout The time allotted for the SHARC to process this audio data is 330us (16 samples x 48-kHz). At that point the next audio brick has been collected and is ready for processing. The processed output audio brick is then deposited into SRAM (U5, U6). The audio bricks are then taken by the Output SHARC's for mixing and output processing. SHARC 2 (U26) processes Main A and Outputs 1-4 while SHARC 3 (U28) is responsible for Main B and Outputs 5-8. If additional delay is required, the bricks are allowed to remain in SDRAM before processing. The minimum delay through the audio processing is as follows:
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ˇ A/D Conversion ˇ 5x "brick" delay ˇ DAC Conversion ˇ Total Delay

667us 1667us 520us 2854us

This delay is constant and not dependent upon the particular processing being done. SDRAM provides a high speed synchronous memory resource. Only the four SHARC processors have access to SDRAM and they are responsible for the access and maintenance of it. Each SHARC monitors the

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bus and accesses SDRAM when it is available. The SHARC blocks access to the bus through the use of the \SDLOCK pin during SDRAM transfers. SDRAM is utilized only for audio delay processing and has no firmware. If audio is available at the input SHARC's, but is not being seen by the output SHARC's, a good place to begin troubleshooting would be with SDRAM. The System Controller periodically accesses the SHARC's to query about meter data. As discussed, the System Controller utilizes the Interface to ask and receive this data.

3.5.9 Audio Routing
Serial audio from the Input PWA is sent to the SHARC PWA for processing. ADC1-4 is fed to PLD U9 for routing to the input SHARC's, U25 & U27. Serial digital audio from the optional CobraNet PWA is also available as CNET_TX1-4. The Input Router sends the appropriate serial audio data to the input SHARC's as directed by the System Controller via SHARC 1. A serial control link (IN_MOSI, IN_SPICK) tells the Input Router which of the serial digital inputs are to be sent to each SHARC's serial ports. The Input Router is also responsible for buffering the audio clocks. By sensing the CNET input from the CNET PWA, the Input Router can tell if the CNET PWA is con-

nected. If CNET is available, the CNET PWA is responsible to provide the Serial and Frame Clocks. The PLD accepts the CNET audio clocks and routes them to the SHARC's and Input PWA. If the CNET PWA is not connected, the audio clocks from the Input PWA are accepted and routed to the SHARC's. The Output Router, U11, is responsible for sending the serial audio outputs of the output SHARC's to the appropriate place. Five output lines, DAC1-5, allow 10 audio channels to be sent to the Output PWA for DAC conversion. In addition, four output lines, CNET_RX1-4, allow 8 audio channels to be directed to the optional CNET PWA for inclusion onto the CNET system. The Output Router is programmed by SHARC 2 via OUT_MOSI & OUT_SPICK.

3.6 System Controller
The System Controller PWA sits on the one side of the chassis and is supported over the power supply. It is responsible for the coordination and communication with the outside world, non-volatile memory storage of all code, and various other functions. The System Controller's tasks includes Control Processing, RS232, Crown Bus loop, Real-Time Clock, Front Panel, and Control Port. Figure 3.10 shows a block diagram for the System Controller PWA.

Figure 3.10 System Controller Block Diagram 3-8 Circuit Theory
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3.6.1 Control Processing
The brain of the System Controller PWA is the Motorola 68HC12 microcontroller, U15. The 112pin QFP pinout is shown in Figure 3.11. The HC12 has a Background Debug Mode (BDM) connection that allows access to the internal workings of the microcontroller. By connecting a pod to P9 and placing the HC12 in BDM mode, the HC12 can be accessed. This function is not used in normal operation or troubleshooting, and the BDM jumper should be left in the NORM position. The HC12 provides all of the processing for the control of the IQ-USM 810. U16 provides sensing of the +5V power supply and brings the HC12 out of reset once the supply is stable. Switch S1 allows resetting of the controller externally. Q17 monitors the reset line and LED E1 is lit whenever the processor is not in reset. Crystal Y2 provides the 14.7456-MHz clock for the

HC12. The clock is buffered by U5D and is provided to dual UART U2 for baud rate creation. When the HC12 comes out of reset, it looks to the flash memory (U13) and begins its boot process. Due to the slow response of flash memory, normal code processing is carried out in SRAM. The HC12 copies its firmware out of flash memory into SRAM (U14) and once complete, jumps to SRAM and begins code processing. The HC12 initializes the dual UART and looks for a break on the RS232 input. If a break is detected, it activates its loader routine and waits for 'S' records from the RS232 port to be downloaded to flash memory. This process allows external programming of firmware revisions. If no break is detected, the HC12 begins loading the SHARC firmware from flash memory into SHARC memory via the System Controller Interface. U8 and U9 provide buffering to the SHARC PWA via P1.

Figure 3.11 68HC12 microcontroller Pinout
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The HC12 firmware uses a real time operating system (RTOS) to make efficient use of the HC12's processing capability. Various tasks are given priorities, and the RTOS supervises what task has control of the processor at any particular time.

3.6.2 RS232
As mentioned, the RS232 port is used to load firmware into flash memory. UART U2 provides the serial port interface to the HC12. The baud rate is programmed by the HC12 as directed by the front panel (19.2 k to 115 kbps) and the clock is generated from the 14-MHz clock. The 8-bit parallel interface to the UART is controlled by the U_RD (read), U_CS (chip select), and FLSH_WE (write) lines. Internal registers control various functions such as baud rate, fifo usage, etc. The serial I/O of the UART is buffered by RS232 Tx/Rx driver U1. This buffer takes the +5V and creates the +/12V needed for RS232 levels. These signals are available on the DB9F connector, J1, which is available on the back panel of the chassis. The other half of dual UART U2 is used as a serial interface to the optional CNET PWA. It connects to the CNET PWA via SHARC connector P1.

RTC_CS (chip select) and periodically queries the RTC to get or set the time. Capacitor C25 is a 1F supercap that allows the RTC to continue to keep time after the unit is powered down. The RTC senses the loss of power and automatically switches to the capacitor to provide power. The capacitor can keep the RTC running for up to 45 days without external power. While the unit is powered, the RTC trickle charges the capacitor.

3.6.5 Front Panel
The HC12 interfaces the Front Display PWA via P6. The three front panel switches are sensed by the HC12 and display of the front panel LED's are controlled via a serial interface; SCK, MOSI, MISO, and LED_CS. Two display IC's on the Front Display PWA interface both the discrete LED's and the triple 7-segment display.

3.6.6 Control Port
The control port interface allows external signals or events to control objects within the box. Additionally, outputs allow signaling of object status to the outside. The DB37M connector P7 provides back panel access. +5V, +10V, and GND is also provided via the connector. Regulator U18 takes the +15V and provides +10V out. The external power is protected by resettable fuses limited to 1 A. The HC12 interfaces the output buffers through latches U6 and U7. These 16 outputs drive NPN transistors that provide 10V @ 10 mA to the outside. Ferrite beads and transient voltage suppressors (TVS) protect the output circuits. The digital inputs are buffered by NPN transistors that allow current drive of the inputs. Voltages up to +25VDC can be used to drive these inputs. The transistor buffers drive a latch that the HC12 polls to collect the input status. U4 is used by the HC12 to address the particular I/O latch it wishes to query. The analog inputs allow a 0 to +10VDC input to be digitized by the HC12's eight 8-bit A/D converters. A voltage divider ensures that the HC12's inputs will not be overdriven.

3.6.3 Crown Bus Loop
The HC12 has two serial ports and one of them is used for the interface to the Crown Bus loop hardware. This is a fixed 38.4-kbps baud rate and uses a dual RJ45 connector J2 to the back panel. In normal operation, data detected at the input of the Crown Bus loop hardware is sent back out via U19A & B, U20B, and U21A. When the HC12 wants to communicate, MSTR0 is pulled high and the TX0 goes out to the Crown Bus loop. R142 provides 20 mA of current to the OUT+ line during normal operation. Communication occurs by interrupting the OUT path via D4 and U21A. The input of the Crown Bus loop is buffered by optoisolator U17 which senses the 20-mA current and sends the signals to the HC12 (RX0) and directs it back out the Crown Bus loop via U19A. Relay K1 provides paths to the I/O circuitry while the IQ-USM 810 is powered. When the unit is turned off, the relay allows the Crown Bus loop to pass through the unit to prevent Crown Bus loop communication from being interrupted.

3.7 Front Display
The Front Display PWA has the three front panel switches, triple 7-segment display, Input Status LED's, Enable, Data, and Interface LED's. The three switches are sensed and processed directly by the HC12 on the System Controller PWA. The two IC's, U1 & U2, control all of the front panel LED's by switching the LED's at a 20%, 1-kHz rate. The serial control from the HC12 tells the IC's which LED's to light.

3.6.4 Real Time Clock
U11 is a Real Time Clock (RTC) IC that provides timing to the HC12 for scheduling of real time events. U11 has an internal oscillator provided by 32-kHz crystal Y1. The HC12 communicates with the RTC via a serial interface composed of RTCLK (serial clk), RTC (data), and

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4 Maintenance
4.1 General Information
This chapter provides test procedures to be used to verify operation of this IQ component. Minimum specifications for proof of performance are given with each procedure. Procedures are in suggested format and the exact test need not be performed; however, the test conditions and results must be verified for proof of performance. These tests, though meant for verification and alignment, may also be very helpful in troubleshooting. For best results, the tests should be performed in order.

ˇ CT: IQ Message data byte count. A part of the IQ string that indicates the number of bytes in its message portion. Note: This byte is automatically inserted when using IQ Util in enhanced mode. ˇ CS: Ucode Message Checksum. The last byte of a Ucode string containing the check sum of the entire message. Note: This byte is automatically inserted when using IQ Util in enhanced mode.

4.3 Required Test Equipment
Audio sine-wave generator (Output amplitude accuracy better than ą0.5 dB) Oscilloscope Audio THD+N analyzer True RMS AC voltmeter DC voltmeter Audio multiplexer (balanced) or other means of switching the audio generator to the eight mixer inputs. Audio multiplexer (balanced) or other means of switching the ten mixer outputs to the Audio analyzer and RMS voltmeter. PC running applicable IQ Ucode compatible software Crown IQ Interface IQ-INT II or equivalent Crown IQ standard 2000' test cables Method of generating TTL Control Port inputs. Method of generating analog Control Port inputs. Method of measuring the Control Port outputs. Method of measuring the phantom power outputs.

4.2 Definitions
ˇ IQ Ucode Protocol: The Protocol used by IQ2 products for communication on the Crown IQ Bus. ˇ DA: IQ Ucode Device Address. A part of the Ucode string that identifies it as pertaining to a particular device. The DA for the IQ-USM 810 is set by the front panel controls. At first power up the IQ-USM 810 defaults to address $01. ˇ DT: IQ Ucode Device Type Identifier. A part of an Ucode string that identifies it as pertaining to a particular type of Ucode component. The DT for the IQ-USM 810 is $19. ˇ AK: IQ Message Acknowledgment. This byte is present in all Ucode device to host messages. It indicates if the last host to device message was correctly formatted.

WARNING
Circuitry is ESD sensitive. When servicing the IQ component, the technician must have approved ESD protection. Proper grounding straps and test equipment are required. Failure to use proper protection will result in component failure.

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4.4 IQ Message String Syntax
4.4.1 Host to Device Messages
The following syntax is used for host to device messages: Send: XX XX XX XX XX; Description XX: A byte of the message explicitly given in hexadecimal. XX: A byte of the message as defined by the two-letter codes in Section 4.2. Description: A short phrase to indicate the function of the message string. The description is added for reference only. It is not sent as part of the Ucode message.

Send the load preset command: Send: DA DT CT B4 7F 09 01 CS; Load preset
Note: The load preset command must be sent within approximately 2 seconds of the select preset command. Note: Preset 32 may also be selected using the front panel controls.

1) Use the "" and "" buttons to select preset 32. (Display shows P32.) 2) Press "SEL" button.

4.6.2 OUTPUT NOISE

Spec: LINE mode: 75 dBu and 80 dBu, 22 Hz to 22 kHz bandwidth.
Note: The test and printed specifications do not match. The printed specifications are for an "A" weighted 20-Hz to 22-kHz bandwidth. Production tests do not use "A" weighted filtering.

4.4.2 Device to Host Messages
The following syntax is used for device to host messages. Return String: XX XX XX XX XX XX: A byte of the message explicitly given in hexadecimal. XX: A byte of the message as defined by the two-letter codes in Section 4.2. XX: A byte of the returned message that requires range testing in accordance to the associated test.

Initial Conditions: Inputs terminated at 50 W balanced. Bandwidth = 22 Hz to 22 kHz. Procedure: Verify each main and AUX output meets spec.

4.6.3 FREQUENCY RESPONSE
Spec: +0.1, 0.6 dB from 20 Hz to 20 kHz. Initial Conditions: Normalized to a reference of a 1 kHz, 0 dBu signal. Procedure: Verify each main and AUX output meets spec with one of the following methods: A 10+ point, logarithmically spaced, sweep. Testing at these frequencies: 20 Hz, 100 Hz, 500 Hz 1 kHz, 5 Hz, 10 kHz, and 20 kHz.

4.5 Standard Initial Conditions
The following tests assume this setup unless stated otherwise. Unit under test built and programmed as documented, less top cover and labels. Preset 32 loaded Inputs set to line mode. Input potentiometers set to 0 dB. Unit under test powered by 120VAC Unit under test connected to test computer via the RS232 connector with constant IQ communication at 115.2 K baud. Output Impedance of Audio Sine-wave Source: 50 W balanced. Audio Output Load: 10 kW balanced.

4.6.4 HARMONIC DISTORTION
Spec: < 0.030 % and > 0.001 % THD+N, with a 22 Hz to 22 kHz bandwidth. Initial Conditions: Input signal: 1 kHz, 0 dBu. Procedure: Verify each main and AUX output meets spec.

4.6.5 COMMON MODE REJECTION
Spec: >40 dB at 60 Hz in line mode, 22 Hz to 22 kHz bandwidth. Procedure: Input a 60 Hz +18 dBu balanced signal. Monitor the associated AUX output with a 22 Hz to 22 kHz bandwidth and set the reference. Change the input to common mode (same frequency and amplitude) Verify the associated AUX output is attenuated at least 40 dB below reference with a 22 Hz to 22 kHz bandwidth.

4.6 Test Procedures
4.6.1 LOAD PRESET 32
Note: Preset 32 is the factory default test preset. This preset sets the audio paths straight through (no gain, filters, or processing) to their respective AUX outputs. Main outputs A and B are driven from inputs 1 and 2 respectively.

Procedure: Send the select preset 32 command: Send: DA DT CT B2 7F 09 20 CS; Select preset 32

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4.6.6 HEAD ROOM / INPUT CLIP LEVEL
Spec: < 1 % THD+N, with a +19.9 dBu input signal. Initial Conditions: Input signal: 1 KHz, +19.9 dBu. Procedure: Verify each main and AUX output meets spec.

4.6.7 INPUT POTENTIOMETER
Spec: ą 2 dB at the 12, and +20 dB settings. Initial Conditions: Input signal: 1 kHz, 0 dBu in to all inputs. Procedure: Verify each input potentiomenter by perfoming the following: Set all potentiometers full counter clockwise. Verify each AUX output is 13 ą2 dBu. Set potentiometer full clockwise. Verify each AUX output is +20.5 ą2 dBu. Return potentiometer to the zero setting.

4.6.8 PHANTOM SUPPLY
Spec: 25.75 ą1VDC unloaded, between each signal pins (+, ) and chassis ground. Initial Conditions: Remove all input signals and impedences. Set all inputs to phantom mode. Procedure: For each input, Verify the DC voltage on the "+" and "" pins referenced to chassis ground pin on all audio inputs.

Send: DA DT CT C0 50 0A CS; Get Control Port Digital Input 2 Return String: DA DT AK CT C0 50 0C IN2 CS Send: DA DT CT 80 51 0A CS; Get Control Port Digital Input 3 Return String: DA DT AK CT 80 51 0C IN3 CS Send: DA DT CT C0 51 0A CS; Get Control Port Digital Input 4 Return String: DA DT AK CT C0 51 0C IN4 CS Send: DA DT CT 80 52 0A CS; Get Control Port Digital Input 5 Return String: DA DT AK CT 80 52 0C IN5 CS Send: DA DT CT C0 52 0A CS; Get Control Port Digital Input 6 Return String: DA DT AK CT C0 52 0C IN6 CS Send: DA DT CT 80 53 0A CS; Get Control Port Digital Input 7 Return String: DA DT AK CT 80 53 0C IN7 CS Send: DA DT CT C0 53 0A CS; Get Control Port Digital Input 8 Return String: DA DT AK CT C0 53 0C IN8 CS Inject a TTL high on the even numbered control port logic inputs (IN2, IN4, IN6, and IN8) and leave the odd numbered inputs open. Use the above commands to read the control port inputs and verify the even numbered inputs return $01 and the odd inputs return $00.

4.6.9 CONTROL PORT OUTPUT VOLTAGE PINS
Spec: Pins at rated voltage ą10%. Procedure: . Verify voltage between pins 9 and 10 of the control port is 5 ą0.25VDC. Verify voltage between pins 29 and 28 of the control port is 10 ą0.5VDC.

4.6.11 CONTROL PORT LOGIC OUTPUTS
Spec: Control Port Logical Outputs individually switch between On and Off. Procedure: Use the following commands to set the odd control port logical outputs and the even outputs off: Send: DA DT CT 80 58 09 01 CS; Set Control Port Digital Output 1 On. Send: DA DT CT C0 58 09 00 CS; Set Control Port Digital Output 2 Off. Send: DA DT CT 80 59 09 01 CS; Set Control Port Digital Output 3 On. Send: DA DT CT C0 59 09 00 CS; Set Control Port Digital Output 4 Off. Send: DA DT CT 80 5A 09 01 CS; Set Control Port Digital Output 5 On. Send: DA DT CT C0 5A 09 00 CS; Set Control Port Digital Output 6 Off. Send: DA DT CT 80 5B 09 01 CS; Set Control Port Digital Output 7 On. Send: DA DT CT C0 5B 09 00 CS; Set Control Port Digi-

4.6.10 CONTROL PORT LOGIC INPUTS
Spec: TTL level inputs are detected on the control port inputs. Procedure: Inject a TTL high on the odd numbered control port logic inputs (IN1, IN3, IN5, and IN7) and leave the even numbered inputs open. Use the following commands to read the control port inputs and verify the odd numbered inputs return $01 and the even inputs return $00: Send: DA DT CT 80 50 0A CS; Get Control Port Digital Input 1 Return String: DA DT AK CT 80 50 0C IN1 CS

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tal Output 8 Off. Send: DA DT CT 80 5C 09 01 CS; Set Control Port Digital Output 9 On. Send: DA DT CT C0 5C 09 00 CS; Set Control Port Digital Output 10 Off. Send: DA DT CT 80 5D 09 01 CS; Set Control Port Digital Output 11 On. Send: DA DT CT C0 5D 09 00 CS; Set Control Port Digital Output 12 Off. Send: DA DT CT 80 5E 09 01 CS; Set Control Port Digital Output 13 On Send: DA DT CT C0 5E 09 00 CS; Set Control Port Digital Output 14 Off. Send: DA DT CT 80 5F 09 01 CS; Set Control Port Digital Output 15 On. Send: DA DT CT C0 5F 09 00 CS; Set Control Port Digital Output 16 Off. Verify the odd control port outputs are on (> 3 volts) and the even control port outputs are off (<1 volts). Use the following commands to set the even control port logical outputs on and the odd outputs off: Send: DA DT CT 80 58 09 00 CS; Set Control Port Digital Output 1 Off. Send: DA DT CT C0 58 09 01 CS; Set Control Port Digital Output 2 On. Send: DA DT CT 80 59 09 00 CS; Set Control Port Digital Output 3 Off. Send: DA DT CT C0 59 09 01 CS; Set Control Port Digital Output 4 On. Send: DA DT CT 80 5A 09 00 CS; Set Control Port Digital Output 5 Off. Send: DA DT CT C0 5A 09 01 CS; Set Control Port Digital Output 6 On. Send: DA DT CT 80 5B 09 00 CS; Set Control Port Digital Output 7 Off. Send: DA DT CT C0 5B 09 01 CS; Set Control Port Digital Output 8 On. Send: DA DT CT 80 5C 09 00 CS; Set Control Port Digital Output 9 Off. Send: DA DT CT C0 5C 09 01 CS; Set Control Port Digital Output 10 On. Send: DA DT CT 80 5D 09 00 CS; Set Control Port Digital Output 11 Off. Send: DA DT CT C0 5D 09 01 CS; Set Control Port Digital Output 12 On. Send: DA DT CT 80 5E 09 00 CS; Set Control Port Digital Output 13 Off Send: DA DT CT C0 5E 09 01 CS; Set Control Port Digital Output 14 On.

Send: DA DT CT 80 5F 09 00 CS; Set Control Port Digital Output 15 Off. Send: DA DT CT C0 5F 09 01 CS; Set Control Port Digital Output 16 On. Verify the even control port outputs are on (> 3 volts) and the odd control port outputs are off (<1 volts). Use the following commands to set the even control port logical outputs off: Send: DA DT CT C0 58 09 00 CS; Set Control Port Digital Output 2 Off. Send: DA DT CT C0 59 09 00 CS; Set Control Port Digital Output 4 Off. Send: DA DT CT C0 5A 09 00 CS; Set Control Port Digital Output 6 Off. Send: DA DT CT C0 5B 09 00 CS; Set Control Port Digital Output 8 Off. Send: DA DT CT C0 5C 09 00 CS; Set Control Port Digital Output 10 Off. Send: DA DT CT C0 5D 09 00 CS; Set Control Port Digital Output 12 Off. Send: DA DT CT C0 5E 09 00 CS; Set Control Port Digital Output 14 Off. Send: DA DT CT C0 5F 09 00 CS; Set Control Port Digital Output 16 Off.

4.6.12 CONTROL PORT ANALOG INPUTS
Spec: Each input measures 0, 5, and 10 VDC within 10%. Procedure: Inject 10 VDC into the odd Control Port Analog Inputs. Inject 5 VDC into the even Control Port Analog Inputs. Use the following commands to verify the odd analog inputs are between $FF and $E6: DA DT CT 81 54 0A CS; Get Control Port Analog Input 9 Return String: DA DT AK CT 81 54 0C IN9 CS Send: DA DT CT 81 55 0A CS; Get Control Port Analog Input 11 Return String: DA DT AK CT 81 55 0C IN11 CS Send: DA DT CT 81 56 0A CS; Get Control Port Analog Input 13 Return String: DA DT AK CT 81 56 0C IN13 CS Send: DA DT CT 81 57 0A CS; Get Control Port Analog Input 15 Return String: DA DT AK CT 81 57 0C IN15 CS 5.13.4. Use the following commands to verify the even analog inputs are between $98 and $66: Send: DA DT CT C1 54 0A CS; Get Control Port Analog Input 10 Return String: DA DT AK CT C1 54 0C IN10 CS

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Send: DA DT CT C1 55 0A CS; Get Control Port Analog Input 12 Return String: DA DT AK CT C1 55 0C IN12 CS Send: DA DT CT C1 56 0A CS; Get Control Port Analog Input 14 Return String: DA DT AK CT C1 56 0C IN14 CS Send: DA DT CT C1 57 0A CS; Get Control Port Analog Input 16 Return String: DA DT AK CT C1 57 0C IN16 CS Open drive to all Control Port Analog Inputs. Use the following commands to verify all the analog inputs are between $19 and $00: Send: DA DT CT 81 54 0A CS; Get Control Port Analog Input 9 Return String: DA DT AK CT 81 54 0C IN9 CS Send: DA DT CT C1 54 0A CS; Get Control Port Analog Input 10 Return String: DA DT AK CT C1 54 0C IN10 CS Send: DA DT CT 81 55 0A CS; Get Control Port Analog Input 11 Return String: DA DT AK CT 81 55 0C IN11 CS Send: DA DT CT C1 55 0A CS; Get Control Port Analog Input 12 Return String: DA DT AK CT C1 55 0C IN12 CS Send: DA DT CT 81 56 0A CS; Get Control Port Analog Input 13 Return String: DA DT AK CT 81 56 0C IN13 CS Send: DA DT CT C1 56 0A CS; Get Control Port Analog Input 14 Return String: DA DT AK CT C1 56 0C IN14 CS Send: DA DT CT 81 57 0A CS; Get Control Port Analog Input 15 Return String: DA DT AK CT 81 57 0C IN15 CS Send: DA DT CT C1 57 0A CS; Get Control Port Analog Input 16 Return String: DA DT AK CT C1 57 0C IN16 CS

4.6.14 PUSHBUTTON TEST
Spec: Pushbuttons operational. Procedure: Use one of the following two methods to test the three front panel pushbuttons: Method 1 (Manual Verification) Hold in the "SEL" button and verify the IQ-USM 810 display cycles between the three display modes (preset, address, and baud rate). Use the "SEL" button to select the preset mode Press the "" button and verify the preset display increases its number. Press the "" button and verify the preset display decreases its number. Method 2 (Auto Verification) Use the following IQ command to continually poll the switch status object: Send: DA DT CT C1 05 0A CS; Return button status Return String: DA DT AK CT C1 05 0C BTN CS Press the "SEL" button and very the object returns $01. Press the "" button and verify the object returns $02. Press the "" button and verify the object returns $04.

4.6.15 REAL TIME CLOCK
Spec: The RTC can be set, can be read, keeps time, and power backup is operational.
Note: The real time clock Ucode object uses a four-byte time code. The code is the number of seconds from 12:00AM on January 1, 1970. The data bytes are returned least significant first.

4.6.13 DISPLAY TEST
Spec: All LEDs and LED segments individually light. Procedure: Start the display test mode: Send: DA DT CT 80 06 09 03 CS; Select test display mode. Verify display lights all LEDs according to the test pattern. (See Section 4.9 for test pattern) Stop the display test mode: Send: DA DT CT 80 06 09 02 CS; Select test display mode.

Example: For 3:34:14 PM on July 21,1999: 1999-1970 = 29 years = 914,544,000 seconds 29 years / 4 = 8 leap year days= 691,200 seconds July 1 = (31+28+31+30+31+30)= 181 days = 15,638,400 seconds 21st = 21 days = 1,814,400 seconds PM = 12 hours = 43,200 seconds 3:34:14 = 12,854 seconds Time from 12:00 AM Jan. 1,1970= 932,744,054 seconds
932,744,054 converted to hex = $37988B76 $37988B76 broken into bytes, LSB first = $76 $8B $98 $37.
Note: The real time clock is powered from a 1 mF capacitor (C25) when the unit is unpowered. This capacitor must be charged above 2.2 volts for the real time clock to operate without unit power. Normal charging time is 14 minutes. To fast charge the capacitor short TP7 and TP8 for at least 4.2 minutes. Remove jumper prior to a power cycle to prevent discharging the capacitor.

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Procedure: Set the clock to the current time with the clock write command. Send: DA DT CT 80 03 09 CK4 CK3 CK2 CK1 CS; Set real time clock Where CK1, CK2, CK3, and CK4 are the four bytes of the time code. 5.16.2. Allow the IQ-USM810 to operate for > 100 seconds.
Note: other tests may be performed during this time.

Verify IQ messages pass through the unit under test: Suggested test string: 01 02 03 04 FE FF Return string: 01 02 03 04 Reapply power to IQ-USM 810.

4.6.18 IQ BUS HUB / DAISY CONNECTIONS
Spec: Both types on IQ Bus connections are functional.
Note: This product has two types of IQ bus connections. The Daisy type connects the input in one port of the dual RJ-45 and the output in the other. The Hub type connects both input and output to one RJ-45 port.

Remove TP7-TP8 jumper if in use. Perform a power cycle on the IQ-USM810.
Note; this may be the same power cycle used for the IQ Bus Dropout Relay Operation test.

Read the clock and compare its time with the current time. Send: DA DT CT 80 03 0A CS Return String: DA DT AK CT 80 03 0C CK4 CK3 CK2 CK1 CS Where CK1, CK2, CK3, and CK4 are the four bytes of the time code. The two times must be within one second.

For this test, perform IQ communication via the Crown bus. Procedure: For each type of bus connection (Daisy, Hub), perform at least one of the above tests that require a test on the IQ response.

4.6.19 SHIPPING STATE RESTORATION
Spec: The IQ-USM 810 is returned to the factory defaults.
Note: This section may be skipped when testing a service unit if it is known that the customer wishes to retain the mixers settings and presets. Note: The following steps must be performed as part of the final power down sequences to ensure the IQ-USM 810 has been returned to factory defaults and presets. If the IQ-USM 810 is re-powered before packing, the following procedure should be repeated.

4.6.16 IQ BUS MASTER CONTROL
Spec: Hardware can force the IQ Bus high. (Open the loop) For this test, perform IQ communication via the Crown bus. Procedure: Send the Master IQ Bus command: Send: DA DT CT C0 05 09 01 CS; Master IQ bus (Open loop) Verify no echo responses on subsequent IQ commands: Suggested test string: 01 02 03 04 FE FF Send the normal IQ Bus command... Send: DA DT CT C0 05 09 00 CS; Unmaster IQ bus (Close loop) Verify echo responses on subsequent IQ commands: Suggested test string: 01 02 03 04 FE FF Return string: 01 02 03 04

Procedure: Send the select preset 0 command: Send: DA DT CT B2 7F 09 00 CS; Select preset 0 Send the load preset command: Send: DA DT CT B4 7F 09 01 CS; Load preset
Note: The load preset command must be sent within approximately 2 seconds of the select preset command.

Send the select preset 32 command: Send: DA DT CT B2 7F 09 20 CS; Select preset 32 Send the load preset command: Send: DA DT CT B4 7F 09 01 CS; Load preset
Note: The load preset command must be sent within approximately 2 seconds of the select preset command. Note: Preset 0 and 32 may also be selected using the front panel controls.

4.6.17 IQ BUS DROPOUT RELAY OPERATION
Spec: IQ Bus remains connected when power is removed. For this test, perform IQ communication via the Crown bus. Procedure: Power down IQ-USM 810.

1) Use the "" and "" keys to select preset 0. (Display shows P00.) 2) Press "SEL" switch. 3) Use the "" and "" keys to select preset 32. (Display shows P32.) 4) Press "SEL" switch.

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4.6.20 CHASSIS GROUND
Spec: Ground conductor of the power inlet is connected to chassis ground.
Note: This test to be completed after the complete product assembly.

4.7 Typical Measurements
Output Noise 20 Hz to 20 KHz bandwidth, line mode: 77 dBu Frequency Response 20 Hz to 20 KHz, referenced to 1 KHz, line mode: 0.27 dB. Harmonic Distortion THD+N, at 1 KHz, 20 Hz to 20 KHz bandwidth, line mode, 0 dBu input: 0.013 %. Common Mode Rejection at 60 Hz, line mode: 66.5 dB. Head Room / Input Clip Level highest input level before 1 % TDH+N, Line mode: .131 % TDH+N @ +20 dBu. Input Potentiometer at 1 KHz, 0 dBu input: Potentiometer at 12 setting: 12.85 dB at +20 setting: +20.43 dB Phantom Supply between each signal pin ("+ and "") and ground of each input: 25.77 VDC Control Port Output Voltage Pins 5 volt supply (between pins 9 and 10): 4.92 VDC 10 volt supply (between pins 29 and 28): 10.26 VDC

Procedure: Verify power inlet less than 1 W between connector ground and chassis. Recommended chassis test points: RS232 Connector shell or screw locks, Multi-Function Control Port shell of screw locks or Crown bus connector shield.

4.4.21 HI-POT
Spec: Power Supply withstands Hi-Pot spikes. Procedure: Verify unit allows no breakdown leakage current with a 1-second, 1.2-kV Hi-Pot from AC mains (Hot and Neutral) to earth ground.

4.8 Test/Debug Objects
Object Number Dec Hex/ASN1 704 $2C0 $C0 $05 Description / Command string format Bus Master: Allows manual control of the bus master function. (Normally an internal function of the Ucode protocol). With this object set, no IQ bus, communication passes through the IQ-USM 810 Crown bus port. Send: DA DT CT C0 05 09 01 CS; to master the IQ Bus, open the loop Response: None Send: DA DT CT C0 05 00 CS; to unmaster the IQ Bus, close the loop Response: DA DT AK CT 00 CS; standard ACK Display Test Mode: Cycles each section of the display through a known sequence allowing the operator to verify that all segments and indicators are functional. See Section 4.7 for known sequence. Send: DA DT CT 80 06 09 01 CS; To force the preset LED on Response: DA DT AK CT 00 CS; standard ACK Send: DA DT CT 80 06 09 00 CS; To set the preset LED in normal mode Response: DA DT AK CT 00 CS; standard ACK Pushbutton Test: Reads a single byte that is bit mapped to indicate a pushbutton depression (bit 0 = "SEL" depressed, bit 1 ="" depressed, bit 2 = "" depressed): Send: DA DT CT C1 05 0A CS, To get data Response: DA DT AK CT C1 05 0C BTN CS

768

$300 $80 $06

705

$2C1 $C1 $05

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4.9 Display Test Patterns
Figure 4.1 shows display test patterns for the IQ-USM 810. For each display section, the sequence starts at the top and cycles to the bottom, and then repeats. LED Display Enable/Data/Interface Input Gate Status

Figure 4.1 Display Test Patterns

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Š2000 Crown International, Inc.

130447-1 Rev. A

IQ-USM 810 Service Manual

4.10 Error Codes
Figure 4.2 shows error codes for the IQ-USM 810.

E01 E02 E03 E04 E05 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25

UART failed system controller power-on self test RAM failed system controller power-on self test Application code in flash failed crc test Flash verify error Unrecoverable firmware error Sharc 0 interface hardware error (timeout, etc.) Sharc 1 interface hardware error (timeout, etc.) Sharc 2 interface hardware error (timeout, etc.) Sharc 3 interface hardware error (timeout, etc.) Sharc 0 failed SRAM test Sharc 1 failed SRAM test Sharc 2 failed SRAM test Sharc 3 failed SRAM test Sharc 0 failed SDRAM test Sharc 1 failed SDRAM test Sharc 2 failed SDRAM test Sharc 3 failed SDRAM test Sharc 0 software watchdog timeout Sharc 1 software watchdog timeout Sharc 2 software watchdog timeout Sharc 3 software watchdog timeout Figure 4.2 IQ-USM 810 Error Codes

4.11 Troubleshooting FAQs
The following FAQs are provided to answer a few questions that may arise in the course of servicing the IQUSM 810. Q. What does the display indicate during power up? A. When the IQ-USM 810 initially powers up, it displays the following: dSP...810...SH0...SH1...SH2...SH3...Pxx. This is the boot sequence for the internal processors. Initially, the System Controller processor boots, then it sequentially boots the four DSP processors (SH0-3). After the System Controller processor successfully boots all four DSP processors, audio processing is allowed to begin. Q. When I power up the IQ-USM 810, it continues to boot. What's up? A. If the System Controller processor encounters an error
Š2000 Crown International, Inc.

during the boot process, it terminates the process at that point, displays an error code on the front panel, then reboots. See Section 4.10 for a list of error codes. Q. What is the most common error? A. Hopefully, no error is common. When "E22" is displayed as the error code, it is most likely due to a loss of digital audio clocking from the Input board. The short 26-pin ribbon cable carries digital audio and clocking from the Input board to the SHARC board. Check for creation of Master Clock (12.288 MHz), Serial Clock (3.032 MHz), and Frame Clock (48 kHz) by the Input board. Q. How do I reboot the IQ-