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For U.S.A., Canada & Europe model
SERVICE MANUAL
MODEL
DN-S5000
TABLE TOP SINGLE CD PLAYER
Some illustrations using in this service manual are slightly different from the actual set .
16-11, YUSHIMA 3-CHOME, BUNKYOU-KU,TOKYO 113-0034 JAPAN Telephone: 03 (3837) 5321
X0161V.02 MO/CDM 0302
DN-S5000
2
DISASSEMBLY
(Follow the procedure below in reverse order when reassembling) 1. SLIP DISC, SLIP MAT
(1)
.
Remove a screw 69 and pull out Slip Disc and Slip Mat. 69 Washer Slip Disc Slip Mat Slip Sheet Anti-static Sheet
2. PLATTER
(1) (2)
.
Remove Belt from Motor Pully. Remove 3 screws 60 and pull out Platter. 60 Belt 60 Platter
Motor Pully
2
DN-S5000 3. DRIVE UNIT
(1) (2) (3)
.
3
Remove 4 screws 71 and pull out Drive Unit. Disconnect Flat cable and Connector. Detach Drive Unit.
Drive Unit
71 71
Connector Flat cable Drive Unit
Note: Do not pull out aslant to prevent Flat cable damage. Do not fail to pull AC cord from wall outlet before disconnect the Flat cable and Connector. If AC cord is remained plugged into wall outlet, power is kept supplied in the unit, which may cause danger.
4. COVER UNIT
(1) (2) (3)
.
Remove 5 screws 70 and pull out Cover Unit. Disconnect Connectors. Detach Cover unit. Cover unit CX042 70 70
Connector
CX101
CX041
70
Connector CX031 Note: Do not fail to pull AC cord from wall outlet before disconnect Connectors. If AC cord is remained plugged into wall outlet, power is kept supplied in the unit, which may cause danger.
3
DN-S5000 5. SENSOR AND SCALE UNITS OF PLATTER
(1) (2) (3) Remove 2 screws 64 and pull out Sensor Cover and Sensor unit. Remove a E Ring. Pull out Scale unit. 64 64 Sensor Cover Sensor unit E Ring Scale unit
4
6. SENSOR AND SCALE UNITS OF SLIP DISC
(1) (2)
.
Remove 2 screws 64 and pull out Sensor Cover and Sensor unit. Remove a screw 60 and pull out Scale unit. Scale unit 60 64 64 Sensor Cover
Sensor unit
7. POWER PWB
(1)
.
Remove 5 screw 51 and pull out Power PWB. 51 Power PWB 51
4
DN-S5000 8. DSP PWB UNIT
(1)
.
5
Remove 9 screws 52 and pull out DSP PWB unit 52
DSP PWB unit
52 52
9. DRIVE COVER
(1)
.
Remove 4 screws 12 and pull out Drive cover. 19 Drive cover 19
19 19
10. DRIVE
(1) (2) (3)
.
Move Drive Rack in arrow direction through the Hole on the bottom chassis.
Loader frame comes out.
Pull up Loader panel while pulling it towards front. Remove 4 screws 6 and pull out Drive. Drive
4
6 6 4
5
DN-S5000
6
BLOCK DIAGRAM 1
2
3
4
5
6
7
8
DN-S5000
-HB,F1,F2 GND,+5,+9
A
LEDdriver
128Mb SDRAM ROM DRIVE ATAPI INTERFACE 128Mb SDRAM
D16 ~ 31
TFS0 TCK0 TXD0A TXD0B
33M LRCK BCLK MAIN1 MON1
main out
BU2090
AMP10 8CH D/A PCM1608
mon out
ADRESS
ADSP21065L
PANEL µcom
LEDdriver
DSP
SHOCK PROOF
TXD1B
AMP11
BU2090
DIT SM5902
384fs
MAIN DOUT
main digital out
TMP86CM47U ROM32k RAM1k
RAM control ATAPI interface
TFS1 TCK1 TXD1A
LED out Key scan VR in
B
BUS select DMA
16Bit Bus
D0 ~ D15
MON DOUT CONTROL DIT SM5902
moni digital out
FLAG
D0
DISC
CPU DSP ~ BUS interface
34.0M
FW PULSE
5v
PANEL DISC
TURN TABLE
~
5.0V -HB,F1,F2 SWITCHING POWER SUPPLY ±9.0V
9V
SYSTEM
URN TABLE
DIR
TMP86CM47U
CPU
micon 4M FRASH memory
D0 ~ D16 ADRESS
RAM10K
SERIAL 1 SERIAL 2 SERIAL 3
MN102H730F
UART UART UART
5v
X'EFFECT IN
TURN TABLE
SENSOR
ATAP Interface CPU
D15
DISC
RV PULSE
SENSOR
HB
FLT Driver
C
FLT
DRIVER 3.3-5V
X'EFFECT OUT FADER1 FADER2
5.0V
5.0V Ragurater
3.3V memo 4M(8M) FRASH memory
ML9207 adress
D/A
CONTROL motor driver Motor
D
E
6
DN-S5000
7
CONFIRMING THE SERVO
Required Measuring Implement
Reference disc (TCD784 or CO-74176)
1. What is Service Program
Service program is a special program intended for confirming servo functions etc.
2. Contents of Service Program
Switch on the power while pushing the PITCH BEND + button and CUE button at the same time. After actuating the servo program, select an aiming process number with the SELECT knob, A1 button, A2 button, or A3 button. Press the SELECT knob to execute the selected process, the process number is then displayed on the track indicator of the display. To exit from the service program, just switch off the power.
Process No. (TRACK Indication) Function (Character-display) Check Version with JOG dial. 1. System µcom version No.: "Sys_XXXX " 01 µcom Version check (Version No.) 2. DSP soft version No.: "Dsp_XXXX " 3. ATAPI µcom version No.: "Atapi_XXXX " 4. PANEL µcom version No.: "Panel_XXXX " 5. ROM drive mecha. µcom version No.: "Drive_XXXX " 02 OPEN/CLOSE (Open Close) Drive Diagnostic (Drive_Diag) Drive Data Read (Data Read) Performs open/close each time when the SELECT knob is pushed. ROM drive performs operation check when the SELECT knob is pushed, and indicates the operational result. If the disc holder open, it starts the operation check after closing. It indicates "Normal_End" if it ends normal. In case of error, ROM drive error code is displayed in the character's lower portion as "E****". Starts continuous playback at its maximum reading speed from the beginning of disc when the SELECT knob is pushed. It halts reading and stops if the knob is pushed again. Turn the PLATTER to display the logging error codes in the occurred order. ("Error Data" is displayed.) 05 Error Code Check (Error Data) 10 error logs are memorized at maximum. Kinds of Error Code, displayed Error Code Table (Appears only at Heat Run and Chucking Test function) Pressing SELECT knob enters to data erase mode. ("Err Clear?" is displayed.) If the SELECT knob is pushed again, the memorized error data are cleared. Total time span of servo function that counted by the hour is displayed. ("Total Time" is displayed.) The display time is less than 65535 hours. Note: No time is counted if powered down within 59 minutes. Pressing SELECT knob enters to data erase mode. ("Time Clear?" is displayed.) If the SELECT knob is pushed again, the memorized time data are cleared. Starts automatic servo adjustment when the SELECT knob is pushed, and after completing the adjustment, sort of the used disc is indicated. Data is selectable with the PLATTER. 1. Disc check, CD/CD-RW 2. Focus gain data Automatic 07 Servo Adjustment call 3. Focus balance data 4. Focus offset data 5. Tracking gain data 6. Tracking balance data 7. Tracking offset data 8. PreAMP Tracking Sensor Gain 9. DSP Tracking Sensor Gain 10. PI offset
Contents
03
04
SELECT knob
06
Total Running Time (Total_Time)
7
DN-S5000
Adjustment Item 1 2 3 4 5 6 Focus Gain Focus Balance Focus Offset Tracking Gain Tracking Balance Tracking Offset * Reference data. Adjustment Value indication at character portions. 35 ~ 120 -20 ~ +20 -20 ~ +20 35 ~ 120 -20 ~ +20 -20 ~ +20
8
3. TEST MODE
Process No. (TRACK Indication) Function (Character-display) Contents Starting with the PLAY/PAUSE button, it repeats open/close of the tray and playback. All tracks are played back if the track count is less than 20. Only the first and last tracks are played back if the tracks are more than 21. When any errors, it stops and indicates error code (see Error Code Table). Starting with the PLAY/PAUSE button, it repeats open/close of the tray, servo on, and TOC read. The display shows the number of the tray operation. When any errors, it stops and indicates error code (see Error Code Table). It starts system check when the PLAY/PAUSE button is pushed, and indicates the status by performing plain operational check in the system . 1. Communication judge between the system µcom and DSP 2. DSP SDRAM write/read operation check 3. Communication judge between the system µcom and ATAPI µcom A3 button 4. Communication judge between the ATAPI µcom and ROM drive 5. ROM drive operation check 6. D/A register write/read operation check 7. DIT register write/read operation check After finishing the check, it indicates the result on the character display lower portion. When the 1. ~ 7. items are OK, their item numbers are indicated. But if there is a NG item, its item number is not indicated. Judges whether PLATTER can rotate at the specified rotating speed. A4 button
A1 button
-
Heat Run (H/R1_Normal)
A2 button
-
Chucking Test (H/R2_Tray)
-
System check (Sys._Check)
-
The message "Platter_OK" is displayed on the character display if the rotating speed meets the specification. Otherwise, "Platter_NG" is displayed.
4. Error Code Table (Appears only at Heat Run and Chucking Test function)
Error Code E1 00 E1 01 E1 03 E1 04 E1 05 E1 06 E2 02 E3 00 E4 00 E4 01 E5 00 Automatic Adjustment Error Unable to detect disc Unable to adjust tracking offset Unable to adjust focus fine gain Unable to actuate focus Unable to actuate tracking Unable to adjust tracking fine gain Servo down during automatic adjustment Unable to read TOC Unable to close the disc holder in the regular time Unable to open the disc holder in the regular time Slide error Contents
8
DN-S5000
Detailed error can be displayed by PLATTER when error occurs.
Error Indication TR Displays the track No. in which error occurred. MIN SEC FRAM "H * * * * CHARACTER E ***"
Error code
9
Displays the time at which error occurred.
Operation count
5. System µcom and DSP Version Upgrade
System µcom and DSP can be upgraded in the following manner. Version Upgrade Method (1) Record the version upgrade software on a CD-R or CD-RW disc, only as one file with the format ISO9660 Mode-1. The file name of the supplied version upgrade software should be used as is and this disc needs to finalize. (2) After loading the disc made in above step 1, turn off the power. Then, turn on the power while pressing the MODE button and PITCH BEND button. The version upgrade starts with reading data of the disc. (3) When you start version upgrade operation, messages "Version_Up" and "System&DSP" are displayed on the character display. Recovery positions are turned on one by one from the left end according as the upgrade operation proceeds. When this operation is completed, all recovery positions are turned on. In case of some error or the power is turned off during the version upgrade, it may be impossible to operate at all thereafter. Changing of IC502 on GU-3482 is necessary in this case, and software writing to IC502 should be done beforehand. (4) When the upgrade is completed, the disk is ejected and operation returns to the normal mode. (5) File name of the upgrade software indicates version numbers.
File name T5. * * * * * * . BIN
System µcom DSP version version
6. ROM Drive (FG-5000) µcom Version Upgrade
Drive (FG-5000) µcom can be upgraded in the following manner. Version Upgrade Method (1) Record the version upgrade software on a CD-R or CD-RW disc, only as one file with the format ISO9660 Mode-1. The file name of the supplied version upgrade software should be used as is and this disc needs to finalize. (2) After turning on the power, load the disc made in above step 1 into the mecha. you want to upgrade the version. (3) "Drive" and "Version UP?" are indicated in the character display. Press the CD EJECT button and remove the disc when not upgrade the version. (4) Press the PLAY/PAUSE to start the version upgrade. "Now Loading" is indicated. (5) When the version upgrade is finished, "Complete" is indicated and the disc EJECT. (6) Turn off the power once and turn on again after take out the disc. The version upgrade ends in 20~30 seconds normally. If the power turned off underway or the version upgrade ends abnormally, the drive may become malfunction. In such a case, version upgrade with PC will be needed. (7) File name of the upgrade software indicates version number.
File name FG5K * * * * . BIN
Version number
9
DN-S5000
10
SEMICONDUCTORS
IC's
MN102H730F (IC501)
96 65
97
64
TOP VIEW
128
33
1
32
MN102H730F Terminal Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name CS0_ CS1_ D00 D01 D02 D03 VDD VSS D04 D05 D06 D07 D08 D09 D10 PD0,DMAACK1_ PD1,DMAREQ1_ D11 D12 D13 D14 D15 WORD VDD MODE Symbol CS0_ CS1_ DQ0 DQ1 DQ2 DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 RESERVE RESERVE DQ11 DQ12 DQ13 DQ14 DQ15 WORD VDD MODE I/O O O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I -- I DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext Pu Pu -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ini -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L L -- -- -- -- -- -- -- L Res -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L Function Ext. memory chip select 0 (Flash ROM CS) Ext. memory chip select 1 (Flash ROM for memo) Ext. memory data in/output 0, DSP interface 0 Ext. memory data in/output 1, DSP interface 1 Ext. memory data in/output 2, DSP interface 2 Ext. memory data in/output 3, DSP interface 3 Power (+3.3V) GND Ext. memory data in/output 4, DSP interface 4 Ext. memory data in/output 5, DSP interface 5 Ext. memory data in/output 6, DSP interface 6 Ext. memory data in/output 7, DSP interface 7 Ext. memory data in/output 8, DSP interface 8 Ext. memory data in/output 9, DSP interface 9 Ext. memory data in/output 10, DSP interface 10
Ext. memory data in/output 11, DSP interface 11 Ext. memory data in/output 12, DSP interface 12 Ext. memory data in/output 13, DSP interface 13 Ext. memory data in/output 14, DSP interface 14 Ext. memory data in/output 15, DSP interface 15 Data bus width select (H: 16bit), GND fixed Power (+3.3V) Processor mode, GND fixed
10
DN-S5000
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Pin Name PC3 XI XO VDD OSCI OSCO VSS P57,BOSC PC5,NMI RST_ PC0 P76 P60,IRQ0 P61,IRQ1 P62,IRQ2,TM10IOA P63,IRQ3,TM10IOA P64,IRQ4 P65,IRQ5,TM12IOA P66,IRQ6 P67,IRQ7 P70,TM13IOB P71 PD2,DMAACK0_ PD3,TM3IO VDD P77 P72,TM14IOB P73 P74 P75,TM12IOB PA0,SBI0 PA1,SBO0 PA2,SBT0 PA3,SBI1 PA4,SBO1 PA5 PB0,SBI2 PB1,SBO2 PB2 PB3,SBI3 PB4,SBO3 PB5,SBT3 VDD VSS AVSS Vref P80 P81 P82 P83 P84 P85 P86 P87 PD4 PD5 P90 P91 P92 P93 Vref+ AVDD Symbol MUTE XI XO VDD OSCI OSCO VSS TEST NMI RST_ YMCLK MDO DTIMA DTIMB TABLE CLK4M ATANS_ DISCPA DISCDIR DISCINT DISCA YMDATA NRES_ DISCPA_ VDD ZSENCE2 DISCPB YMLD1_ YMLD2_ CLK4M RXD1 TXD1 MCMD_ X'RXDOUT X'TXDOUT ZSENCE1 X'RXD IN X'TXD IN APRES_ ATDATA MDATA MCLK VDD VSS AVSS Vref DFLG2 DFLG1 DR_/W1 DACK_ DBSY_ DFLG0 DREQ_ FPLAY1 FCUE1 FPLAY2 FCUE2 RESERVE PNLRST APOWER Vref+ AVDD I/O O I O -- I O -- I I I O O I I I I I I I I I O O I -- I I O O I I O O I O I I O O I O O -- -- -- -- I/O I/O O I I I/O O I I I I O -- O -- -- DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext Pu -- -- -- -- -- -- Pu -- -- -- Pd Pu Pu (Pu) -- (Pu) (Pu) (Pu) (Pu) -- -- Pd -- -- -- -- -- -- -- (Pu) Pu Pu (Pd) Pu -- (Pd) Pu Pd (Pu) -- -- -- -- -- -- Pu Pu -- Pu Pu Pu Pu (Pu) (Pu) (Pu) (Pu) -- Pd Pd -- -- Ini H -- -- -- -- -- -- H -- -- H -- H H H -- -- H H H -- H L -- -- -- -- H H -- -- H H -- H -- -- H L -- H H -- -- -- -- -- -- H H H -- H H H H H L L L -- -- Res H -- -- -- -- -- -- -- -- -- -- L H H H -- H H H H -- -- L -- -- -- -- -- -- -- H H H H H -- H H L H -- -- -- -- -- -- H H -- H H H H H H H H -- L L -- -- Function Mute signal (H: Mute) Oscillation input Oscillation output Power (+3.3V) Oscillation input, 34.0MHz Oscillation output GND P.W.B. check mode IN Connect to Power µcom reset Clock for SM5902(DOUT)/PCM1608(D/A) data PCM1608(D/A) input data Main playback clock input Monitor playback clock input Clock pulse input for platter Clock pulse input for platter ATAPI µcom serial interface Clock pulse input for scratch disc Direction pulse input for scratch disc Start pulse input for scratch disc SCRATCH for DISC pulse A count input SM5902(DOUT)/PCM1608(D/A) output data SM5902(DOUT)/PCM1608(D/A) reset signal Clock invert pulse input for scratch disc Power (+3.3V) SM5902 µcom interface status for MONITOR SCRATCH for DISC pulse B count input SM5902(DOUT) chip select for MAIN SM5902(DOUT) chip select for MONITOR Clock pulse input for disc Data receive from PANEL Data send to PANEL (PU µcom specify) ATAPI µcom serial interface (PU µcom specify) Data receive from X'EFFECT OUT Data send to X'EFFECT OUT SM5902 µcom interface status for MAIN Data receive from X'EFFECT IN Data send to X'EFFECT IN ATAPI µcom reset signal ATAPI µcom serial receive signal ATAPI µcom serial send signal ATAPI µcom serial send/receive clock Power (+3.3V) GND Analog ref. GND for A/D conversion, GND Analog ref. V for A/D conversion, GND DSP gener al flag 2 DSP gener al flag 1 DSP interf ace send/receive select signal DSP interf ace ACK DSP interf ace busy signal DSP gener al flag 0 DSP interf ace request signal Main fader start PLAY input Main fader start CUE input Monitor fader start PLAY input Monitor fader start CUE input Panel µcom reset signal (L:Reset) Analog output voltage ON/OFF (L:OFF) Analog ref. V for A/D conversion, +3.3V Power (+3.3V)
11
11
DN-S5000
Pin No. 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name P94 P95 P96,DAC2 P97,DAC3 BREQ_ BRACK_ WEL_ P51 RE_ CS2_ VDD VSS P54, BSTRE P55, WR_ CS3_ A00 A01 A02 A03 A04 A05 A06 A07 A08 PD6 PD7,TM7IO A09 A10 A11 A12 A13 VDD PC4 A14 A15 A16 A17 A18 A19 A20 A21 Symbol MCNT0 MCNT1 MCNTDA RESERVE BREQ_ BRACK_ WE_ RESERVE RE_ CS2_ VDD VSS ML RESERVE CS3_ A00 A01 A02 A03 A04 A05 A06 A07 A08 RESERVE DISCPB_ A09 A10 A11 A12 A13 VDD RESERVE A14 A15 A16 A17 A18 A19 A20 A21 I/O O O O O I O O O O O -- -- O O O O O O O O O O O O O I O O O O O -- O O O O O O O O O DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext Pu Pu Pu -- (Pu) Pu Pu -- Pu Pu -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pu Pu Pu Pu Pu Ini L L L H H H -- H -- -- -- -- H H -- -- -- -- -- -- -- -- -- -- L -- -- -- -- -- -- -- L -- -- -- -- -- -- -- -- Res L L L -- H H H -- H H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function Motor control signal 0 Motor control signal 1 Motor rotation speed control signal A/D 0 Bus request signal Bus request accept signal Ext. memory write enable (Lower 8bit) Ext. memory read enable Ext. memory chip select 2 (DSP1 interface) Power (+3.3V) GND PCM1608 (D/A) chip select Not used Ext. memory address bus 0 Ext. memory address bus 1 Ext. memory address bus 2 Ext. memory address bus 3 Ext. memory address bus 4 Ext. memory address bus 5 Ext. memory address bus 6 Ext. memory address bus 7 Ext. memory address bus 8
12
Ext. memory address bus 9 Ext. memory address bus 10 Ext. memory address bus 11 Ext. memory address bus 12 Ext. memory address bus 13 Power (+3.3V) Ext. memory address bus 14 Ext. memory address bus 15 Ext. memory address bus 16 Ext. memory address bus 17 Ext. memory address bus 18 Ext. memory address bus 19 Ext. memory address bus 20 Ext. memory address bus 21
12
DN-S5000 ADSP-21065L (IC401)
208 157
13
1
156
TOP VIEW
52
105
53
104
ADSP-21065L Terminal Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Port Name VDD RFS0 GND RCLK0 DR0A DR0B TFS0 TCLK0 VDD GND DT0A DTOB RFS1 GND RCLK1 DR1A DR1B TFS1 TCLK1 VDD VDD DT1A DT1B PWM_EVENT1 GND PWM_EVENT0 BR1_ BR2_ VDD CLKIN XTAL_ VDD Symbol (IC301) VDD YLRCK GND YBCK ADDATA YLRCK YBCK VDD GND MOUT1 DOUT1 LRCK1 GND BCK1 SAMP2 LRCK2 BCK2 VDD VDD SOUT1 SAMP1 GND Symbol (IC401) VDD YLRCK GND YBCK ADDATA YLRCK YBCK VDD GND MOUT2 DOUT2 LRCK2 GND BCK2 SAMP1 LRCK1 BCK1 VDD VDD SOUT2 SAMP2 GND I/O -- I -- I I I I I -- -- O O I -- I I I I/O I/O -- -- O O I/O -- I/O I I -- I O -- DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext -- IPu -- -- IPu IPu IPu -- -- -- IPu IPu IPu -- -- IPu IPu IPu -- -- -- IPu IPu Pd -- Pd Pu Pu -- -- -- -- Ini -- -- -- -- -- -- -- -- -- -- -- -- -- -- L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Res -- H -- -- H H H -- -- -- H H H -- -- H H H -- -- -- H H L -- L H H -- -- -- -- Function Power (+3.3V) Receive frame sync (LRCK) signal (Serial port IN 0) GND Receive frame sync (BCK) signal (Serial port IN 0) Data receive A (serial port IN 0) Data receive B (serial port IN 0) Send frame sync (LRCK) signal (Serial port OUT 0) Send frame sync (BCK) signal (Serial port OUT 0) Power (+3.3V) GND Data send A (Serial port OUT 0) Data send B (Serial port OUT 0) Receive frame sync (LRCK) signal (Serial port IN 1) GND Receive frame sync (BCK) signal (Serial port IN 1) Data receive A (serial port IN 1) Data receive B (serial port IN 1) Send frame sync (LRCK) signal (Serial port OUT 1) Send frame sync (BCK) signal (Serial port OUT 1) Power (+3.3V) Power (+3.3V) Data send A (Serial port OUT 1) Data send B (Serial port OUT 1) PWM1 output GND PWM0 output Multi-processing bus request 1 Multi-processing bus request 1 Power (+3.3V) Clock input X'tal oscillator pin Power (+3.3V)
VDD
VDD
VDD
VDD
13
DN-S5000
Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Port Name GND SDCLK1 GND VDD SDCLK0 DMAR1_ DMAR2_ HBR_ GND RAS_ CAS_ SDWE_ VDD DQM SDCKE SDA10 GND DMAG1_ DMAG2_ HBG_ BMSTR VDD CS_ SBTS_ GND WR_ RD_ GND VDD GND REDY SW_ CPA_ VDD VDD GND ACK MS0_ MS1_ GND GND MS2_ MS3_ FLAG11 VDD FLAG10 FLAG9 FLAG8 GND DATA0 DATA1 DATA2 VDD DATA3 DATA4 DATA5 GND DATA6 DATA7 DATA8 VDD GND Symbol (IC301) GND GND VDD Symbol (IC401) GND GND VDD I/O -- O -- -- I/O I I I -- I/O I/O I/O -- O I/O O -- O O O O -- I I -- I/O I/O -- -- -- O I/O I/O -- -- -- I/O I/O I/O -- -- I/O I/O O -- I/O I I -- I/O I/O I/O -- I/O I/O I/O -- I/O I/O I/O -- -- DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext -- Pd -- -- -- Pu Pu Pu -- Pu Pu Pu -- -- -- Pd -- -- -- -- -- -- -- Pu -- -- -- -- -- -- -- -- -- -- -- -- -- Pu -- -- -- -- -- Pu -- Pu -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ini -- -- -- -- -- H H -- -- H H H -- -- H L -- H H H H -- L H -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Res -- L -- -- -- H H H -- H H H -- -- -- L -- -- -- -- -- -- L H -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- H -- H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function GND SDRAM clock enable 1 GND Power (+3.3V) SDRAM clock enable 0 DMA request 1 DMA request 2 Host bus request (BOOT) GND SDRAM row access strobe SDRAM column access strobe SDRAM write enable Power (+3.3V) SDRAM data mask SDRAM clock enable SDRAM A10 GND DMA ground 1 DMA ground 2 Host bus ground (BOOT) Bus master output (H out) Power (+3.3V) Chip select (BOOT) Extend bus three state GND Memory write strobe Memory read strobe GND Power (+3.3V) GND Host bus ACK Sync type write select Core priority access Power (+3.3V) Power (+3.3V) GND Memory ACK Memory select 0 Memory select 1 GND GND Memory select 2 Memory select 3 General flag 11 (In DMA flag L: DMA) Power (+3.3V) General flag 10 (In SAMPLER copy flag) General flag 9 (JOG turning direction detect signal B) General flag 8 (JOG turning direction detect signal A) GND Ext. bus data 0 Ext. bus data 1 Ext. bus data 2 Power (+3.3V) Ext. bus data 3 Ext. bus data 4 Ext. bus data 5 GND Ext. bus data 6 Ext. bus data 7 Ext. bus data 8 Power (+3.3V) GND
14
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
GND VDD GND
GND VDD GND
VDD VDD GND
VDD VDD GND
GND GND
GND GND
DMABSY1 VDD SAMPCOP JOGB1 JOGA1 GND
DMABSY2 VDD SAMPCOPY JOGB2 JOGA2 GND
VDD
VDD
GND
GND
VDD GND
VDD GND
14
DN-S5000
Pin No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Port Name VDD DATA9 DATA10 DATA11 GND DATA12 DATA13 NC NC DATA14 VDD GND DATA15 DATA16 DATA17 VDD DATA18 DATA19 DATA20 GND NC DATA21 DATA22 DATA23 GND VDD DATA24 DATA25 DATA26 VDD GND DATA27 DATA28 DATA29 GND VDD VDD DATA30 DATA31 FLAG7 GND FLAG6 FLAG5 FLAG4 GND VDD VDD NC ID1 ID0 EMU_ TD0 TRST_ TDI TMS GND TCK BSEL BMS_ GND GND VDD Symbol (IC301) VDD Symbol (IC401) VDD I/O -- I/O I/O I/O -- I/O I/O -- -- I/O -- -- I/O I/O I/O -- I/O I/O I/O -- -- I/O I/O I/O -- -- I/O I/O I/O -- -- I/O I/O I/O -- -- -- I/O I/O I/O -- I/O O O -- -- -- -- I I O O I I I -- I I I -- -- -- DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pu -- Pu -- -- -- -- -- -- -- -- -- -- IPu Pd IPu -- Pu -- -- -- -- -- Ini -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L L -- -- -- -- -- -- -- H H -- -- -- Res -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- H -- -- -- -- -- -- L L -- -- H L H -- H H H -- -- -- Function Power (+3.3V) Ext. bus data 9 Ext. bus data 10 Ext. bus data 11 GND Ext. bus data 12 Ext. bus data 13 NC NC Ext. bus data 14 Power (+3.3V) GND Ext. bus data 15 Ext. bus data 16 Ext. bus data 17 Power (+3.3V) Ext. bus data 18 Ext. bus data 19 Ext. bus data 20 GND NC Ext. bus data 21 Ext. bus data 22 Ext. bus data 23 GND Power (+3.3V) Ext. bus data 24 Ext. bus data 25 Ext. bus data 26 Power (+3.3V) GND Ext. bus data 27 Ext. bus data 28 Ext. bus data 29 GND Power (+3.3V) Power (+3.3V) Ext. bus data 30 Ext. bus data 31 General flag 7 (RESERVE) GND General flag 6 (RESERVE) General flag 5 (Pulse output for generating monitor play time) General flag 4 (Pulse output for generating main play time) GND Power (+3.3V) Power (+3.3V) NC Multi-processing ID1 (Single processor: 0) Multi-processing ID2 (Single processor: 0) Emulation status Test data output (JTAG) Test reset (JTAG) Test data input (JTAG) Test mode select (JTAG) GND Test clock (JTAG) EPROM boot select (Boot by EPROM: 1) Boot memory select (Host processor boot: 1) GND GND Power (+3.3V)
15
GND
GND
VDD GND
VDD GND
VDD
VDD
GND
GND
GND VDD
GND VDD
VDD GND
VDD GND
GND VDD VDD
GND VDD VDD
DFLG12 GND DFLG11 DTIMB1 DTIMA1 GND VDD VDD
DFLG22 GND DFLG21 DTIMB2 DTIMA2 GND VDD VDD
EMU1_ TD01 TRST1_ TDI1 TMS1 GND TCK1 BMS1_ GND GND VDD
EMU2_ TD02 TRST2_ TDI2 TMS2 GND TCK2 BMS2_ GND GND VDD
15
DN-S5000
Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Port Name RESET_ VDD GND ADDR23 ADDR22 ADDR21 VDD ADDR20 ADDR19 ADDR18 GND GND ADDR17 ADDR16 ADDR15 VDD ADDR14 ADDR13 ADDR12 VDD GND ADDR11 ADDR10 ADDR9 GND VDD ADDR8 ADDR7 ADDR6 GND GND ADDR5 ADDR4 ADDR3 VDD VDD ADDR2 ADDR1 ADDR0 GND FLAG0 FLAG1 FLAG2 VDD FLAG3 NC NC GND IRQ0_ IRQ1_ IRQ2_ NC Symbol (IC301) DRES_ VDD GND Symbol (IC401) DRES_ VDD GND I/O I -- -- I/O I/O I/O -- I/O I/O I/O -- -- I/O I/O I/O -- I/O I/O I/O -- -- I/O I/O I/O -- -- I/O I/O I/O -- -- I/O I/O I/O -- -- I/O I/O I/O -- I/O I/O I/O -- I/O -- -- -- I I I -- DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pu -- -- -- Pu Pu -- -- Ini H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Res L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- H L -- -- Function DSP reset signal Power (+3.3V) GND Ext. bus address 23 Ext. bus address 22 Ext. bus address 21 Power (+3.3V) Ext. bus address 20 Ext. bus address 19 Ext. bus address 18 GND GND Ext. bus address 17 Ext. bus address 16 Ext. bus address 15 Power (+3.3V) Ext. bus address 14 Ext. bus address 13 Ext. bus address 12 Power (+3.3V) GND Ext. bus address 11 Ext. bus address 10 (SDRAM: Connects SDA10) Ext. bus address 9 GND Power (+3.3V) Ext. bus address 8 Ext. bus address 7 Ext. bus address 6 GND GND Ext. bus address 5 Ext. bus address 4 Ext. bus address 3 Power (+3.3V) Power (+3.3V) Ext. bus address 2 Ext. bus address 1 Ext. bus address 0 GND General flag 0 (Command read write select) General flag 1 General flag 2 Power (+3.3V) General flag 3 (RESERVE) -- -- GND Interrupt request input 0 (SYS mcom interface) Interrupt request input 1 (SYS mcom interface) Interrupt request input 2 (JOG turning speed detect signal) NC
16
VDD
VDD
GND GND
GND GND
VDD
VDD
VDD GND
VDD GND
GND VDD
GND VDD
GND GND
GND GND
VDD VDD
VDD VDD
GND DR_/W1 DACK1_ DBSY1 VDD DFLG10
GND DR_/W2 DACK2_ DBSY2 VDD DFLG20
GND DREQ1 DREQ1_ JOGINT1
GND DREQ2 DREQ2_ JOGINT2
16
DN-S5000 TMP86CM47U(IC151)
17
33 34
23 22
TOP VIEW
44 12
1
TMP86CM47U Terminal Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name VSS XIN XOUT TEST VDD P21 P22 RESET_ P20 (LED) P00 (INT0) P01 P02, (RXD) P03, (TXD) P04 (SO) P05 P06 (SCK) P07 P17 P16 P15 P14 P13 P12 P11 (INT1) P10 P30 (AIN0) P31 (AIN1) P32 (AIN2) P33 (AIN3) P34 (AIN4) P35 (AIN5) P36 P37 VAREF AVDD AVSS P40 (LED) P41 (LED) P42 (LED) P43 (LED) P44 (LED) P45 (LED) P46 (LED) P47 (LED) Symbol VSS XIN XOUT TEST VDD LED AT LECLK1 RST_ LED4 TRSB BEND_ RXD TXD FLDA FLCS_ FLCP_ LECLK2 KIN5 KIN4 KIN3 KIN2 KIN1 KIN0 TRSA FLRES_ PITCH SCRSEL SCRDIR SEARCH SCAN KINAD PLAY CUE VAREF AVDD AVSS KOUT0 KOUT1 KOUT2 KOUT3 LED0 LED1 LED2 LED3 I/O -- I O I -- O O I O I O I O O O O O I I I I I I I O I I I I I I I I I I I O O I/O I/O O O O O DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext -- -- -- -- -- Pu Pu -- -- Pu Pu Pu Pu Pu Pu Pu Pu Pu Pu Pu Pu Pu Pu Pu Pd -- Pu Pu Pu Pu Pu Pu Pu -- -- -- Pu Pu Pu Pu -- -- -- -- Ini -- -- -- -- -- L H -- H -- H -- H H H H L -- -- -- -- -- -- -- L -- -- -- -- -- -- -- -- -- -- -- H H H H H H H H Res -- -- -- -- -- H H -- -- H -- H H H H H H H H H H H H H L -- H H H H H H H -- -- -- H H H H -- -- -- --
11
Function GND (0V) Oscillation input 16.0MHz Oscillation output Fixed to L Power (+5.0V) BU2090 data (1&2) Clock signal 1 for BU2090 data output µcom reset LED4 ON/OFF (L: ON) Track select encorder B input BEND button Data receive from system µcom Data send to system µcom ML9207 data signal ML9207 latch signal Clock signal for ML9207 data output Clock signal 2 for BU2090 data output Key scan input 5 Key scan input 4 Key scan input 3 Key scan input 2 Key scan input 1 Key scan input 0 Track select encorder A input ML9207 reset signal Pitch VR signal A/D SCRATCH source select key input A/D SCRATCH DIR select key input SEARCH VR A/D input O SCAN VR A/D input O key A/D input PLAY/PAUSE key input CUE key input Power (+5.0V), Analog ref.V for A/D conversion Power (+5.0V), Power for A/D conversion circuit only GND (0V), Analog GND for A/D conversion Key scan output 0/LED line select 0 (L: select) Key scan output 1/LED line select 1 (L: select) Key scan output 2 (Except scaning: IN) Key scan output 3 (Except scaning: IN) LED ON/OFF 0 (L: ON) LED ON/OFF 1 LED ON/OFF 2 LED ON/OFF 3
17
DN-S5000 SM5902AF (IC651, 652)
18
33 34
23 22
TOP VIEW
44 12
SM5902AF Terminal Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol VDD2 UC1 UC2 UC3 UC4 UC5 DIT NTEST CLK Vss YSRDATA YLRCK YSCK ZSCK ZLRCK ZSRDATA YFLAG YFCLK YBLKCK NRESET ZSENSE VDD1 YDMUTE YMLD YMDATA YMCLK A10 NCAS D2 D3 D0 D1 NWE NRAS A9 A8 A7 A6 A5 A4 A0 A1 A2 A3 I/O
1
Function
11
Setting H L
-- IP/O IP/O IP/O IP/O IP/O O IP I --
I I I O O O I I I I O -- I I I I O O I/O I/O I/O I/O O O O O O O O O O O O O
VDD power supply terminal. Microcomputer interface extended I/O 1. Not Used (OPEN) Microcomputer interface extended I/O 2. Not Used (OPEN) Microcomputer interface extended I/O 3. Not Used (OPEN) Microcomputer interface extended I/O 4. Not Used (OPEN) Microcomputer interface extended I/O 5. Not Used (OPEN) Digital audio interface terminal. Test terminal. 16.9344 MHz clock input. Ground terminal. Audio serial input data. Audio serial input LR clock. Audio serial input bit clock. Audio serial output bit clock. Audio serial output LR clock. Audio serial output data. RAM overflow flag for signal processing IC. X'tal system frame clock. Sub-code block clock signal. System reset terminal. Microcomputer interface status output. VDD power supply terminal. Forcible mute terminal. Microcomputer interface latch clock. Microcomputer interface serial data. Microcomputer interface shift clock. DRAM address 10. DRAM CAS control. DRAM data input/output 2. DRAM data input/output 3. DRAM data input/output 0. DRAM data input/output 1. DRAM WE control. DRAM RAS control. DRAM address 9. DRAM address 8. DRAM address 7. DRAM address 6. DRAM address 5. DRAM address 4. DRAM address 0. DRAM address 1. DRAM address 2. DRAM address 3.
Test
Lch
Rch
Lch
Rch Over
Reset
Mute
18
DN-S5000 PCM1608Y (IC705)
ML MC MDI MDO ZERO8 DATA4 ZERO7 NC VCC1 AGND1 VCC2 AGND2
19
36 35 34 33 32 31 30 29 28 27 26 25
RST SCKI SCKO BCK LRCK TEST VDD DGND DATA1 DATA2 DATA3 ZEROA
37 38 39 40 41 42 43 44 45 46 47 48
TOP VIEW
24 23 22 21 20 19 18 17 16 15 14 13
VCC3 AGND3 VCC4 AGND4 VOUT8 AGND6 VCC5 AGND5 VOUT7 VCOM VOUT1 VOUT2
1 2 3 4 5 6 7 8 9 10 11 12
ZERO1/GPO1 ZERO2/GPO2 ZERO3/GPO3 ZERO4/GPO4 ZERO5/GPO5 ZERO6/GPO6 NC NC VOUT6 VOUT5 VOUT4 VOUT3
BCK LRCK DATA1 (1, 2) DATA2 (3, 4) DATA3 (5, 6) DATA4 (7, 8) 4x/8x Oversampling Digital Filter with Function Controller Function Control I/F Enhanced Multi-Level Delta-Sigma Modulator Serial Input I/F
DAC
Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter
VOUT1
DAC
VOUT2
DAC
VOUT3
DAC
VOUT4 VCOM VOUT5
DAC
TEST RST ML MC MDI MDO
DAC
VOUT6
DAC
VOUT7
DAC
VOUT8
System Clock System Clock Manager
SCKI
Zero Detect
Power Supply
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
ZEROA
ZERO7
ZERO8
PCM1608Y Terminal Function
Pin No. 1 2 3 4 5 6 7 8 9 10 Pin Name ZERO1/GPO1 ZERO2/GPO2 ZERO3/GPO3 ZERO4/GPO4 ZERO5/GPO5 ZERO6/GPO6 NC NC VOUT6 VOUT5 I/O O O O O O O -- -- O O Function Zero Data Flag for VOUT1. Can also be used as GPO pin Zero Data Flag for VOUT2. Can also be used as GPO pin Zero Data Flag for VOUT3. Can also be used as GPO pin Zero Data Flag for VOUT4. Can also be used as GPO pin Zero Data Flag for VOUT5. Can also be used as GPO pin Zero Data Flag for VOUT6. Can also be used as GPO pin No Connection No Connection Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz
19
AGND1-8
SCKO
DGND
VDD
VCC1-5
DN-S5000
Pin No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name VOUT4 VOUT3 VOUT2 VOUT1 VCOM VOUT7 AGND5 VCC5 AGND6 VOUT8 AGND4 VCC4 AGND3 VCC3 AGND2 VCC2 AGND1 VCC1 NC ZERO7 DATA4 ZERO8 MDO MDI MC ML RST SCKI SCKO BCK LRCK TEST VDD DGND DATA1 DATA2 DATA3 ZEROA I/O O O O O O O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O l l l l l O l l -- -- -- l l l O Function Voltage Output of Audio Signal Corresponding to Rch on DATA2. Up to 96kHz Voltage Output of Audio Signal Corresponding to Rch on DATA2. Up to 96kHz Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND Voltage Output for Audio Signal Corresponding to Rch on DATA4. Up to 192kHz Analog Ground Analog Power Supply, +5V Analog Ground Voltage Output for Audio Signal Corresponding to Rch on DATA4. Up to 192kHz Analog Ground Analog Power Supply, +5V Analog Ground Analog Power Supply, +5V Analog Ground Analog Power Supply, +5V Analog Ground Analog Power Supply, +5V No Connection Zero Data Flag for VOUT7 Serial Audio Data Input VOUT7 and VOUT8 (2) Zero Data Flag for VOUT7 Serial Audio Data Output for Serial Port (3) Serial Audio Data Input for Serial Port (1) Shift Clock for Serial Control Port (1) Latch Enable for Serial Control Port (1) System Reset, Active LOW (1) System Clock Input frequency is 128,192,256,384,512,or 768fs. (2) Buffered Clock Output frequency is 128,192,256,384,512,or 768fs. (2) Shift Clock Input for Serial Audio Data. Clock must be 32,48,or,64fs. (2) Left and Right Clock Input. This clock is equal to the sampling rate, fs. (2) Test Pin. This pin should be connected to DGND. (1) Digital Power Supply, +3.3V Digital Ground Serial Audio Data Input VOUT1 and VOUT2 (2) Serial Audio Data Input VOUT3 and VOUT4 (2) Serial Audio Data Input VOUT5 and VOUT6 (2) Zero Data Flag. Logical "AND" of ZERO1 through ZERO6
20
Note: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.
20
DN-S5000 ML9207-01GP (IC101)
AD2 AD1 VDISP2 NC VFL2 P4 P3 P2 P1 VDD DA CP CS RESET OSC1 OSC0 GND VFL1 COM24 COM23
21
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AD3 AD4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3
TOP VIEW
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 VDISP1 COM1 COM2
ML9207-01GP Terminal Function
Pin No. 3~37 39~62 1, 2, 79, 80 72~75 71 38, 78 64 63, 76 70 69 68 67 65 66 77 Symbol SEG1~35 COM1~24 AD1~4 P1~4 VDD VDISP1~2 GND VFL1~2 DA CP CS RESET OSCO OSC1 NC I/O O O O O Function FL display anode electrode drive output pin FL display grid electrode drive output pin FL display anode electrode drive output pin General port output pin VDD-GND: Power for logic VDISP-VFL: Power for FL display drive Same power source should be used for VDD and VDISP Serial data input pin (positive logic). Shift clock input pin Chip select input pin Reset input pin, L: All functions are initialized Pin for self-oscillation, target oscillation frequency 4.0MHz Not used
--
I I I I I O --
21
DN-S5000 TMP86CM47U (IC102)
22
33 34
23 22
TOP VIEW
44 12
1
TMP86CM47U Terminal Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name VSS XIN XOUT TEST VDD P21(LED) P22(LED) RESET_ P20(LED) P00(INT0) P01 P02(RXD) P03(TXD) P04(SO) P05 P06(SCK_) P07 P17 P16 P15(INT3) P14 P13 P12(INT2) P11(INT1) P10 P30(AIN0) P31(AIN1) P32 P33 P34 P35 P36 P37 VAREF AVDD AVSS P40(LED) P41(LED) P42(LED) P43(LED) P44(LED) P45(LED) P46(LED) P47(LED) Symbol VSS XIN XOUT TEST VDD LEDAT LECLK RST_ LED8 TRSB KIN7 RXD TXD FLDA FLCS_ FLCP_ KIN6 FLRES_ KIN5 JOGD KIN4 KIN3 JOGC TRSA KIN2 PIT PITC KIN1 KIN0 KOUT0 KOUT1 KOUT2 KOUT3 VAREF AVDD AVSS LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 I/O -- I O I -- O O I O I I I O O O O I O I I I I I I I I I I I O O I/O I/O I I I O O O O O O O O DET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ed -- -- Ed Ed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Ext -- -- -- -- -- Pu Pu -- -- Pu Pu Pu Pu Pu Pu Pu Pu Pd Pu Pu Pu Pu Pu Pu Pu -- -- Pu Pu Pu Pu Pu Pu -- -- -- -- -- -- -- -- -- -- -- Ini -- -- -- -- -- L L -- H -- -- -- H H H H -- L -- -- -- -- -- -- -- -- -- -- -- H H H H -- -- -- H H H H H H H H Res -- -- -- -- -- H H -- -- H H H H H H H H L H H H H H H H -- -- H H H H H H -- -- -- -- -- -- -- -- -- -- --
11
Function GND(0V) Oscillation input 16.0MHz Oscillation output Fixed to L Power (+5.0V) BU2090 data Clock signal for BU2090 data output µcom reset LED ON/OFF8 (L: ON) Track select encoder B input Key scan input 7 Data receive from main unit Data send to main unit ML9207 data signal ML9207 latch signal Clock signal for ML9207 data output Key scan input 6 ML9207 reset signal Key scan input 5 JOG encoder D interrupt input Key scan input 4 Key scan input 3 JOG encoder C interrupt input Track select encoder A interrupt input Key scan input 2 Pitch VR signal Pitch VR center value signal Key scan input 1 Key scan input 0 Key scan output 0/LED line select 0 (L: Select) Key scan output 1/LED line select 1 (L: Select) Key scan output 2 (Other than scan, IN) Key scan output 3 (Other than scan, IN) Power (+5.0V), Analog ref. V for A/D conversion Power (+5.0V), For A/D conversion circuit only GND(0V), Analog GND for A/D conversion LED ON/OFF0 (L: ON) LED ON/OFF1 LED ON/OFF2 LED ON/OFF3 LED ON/OFF4 LED ON/OFF5 LED ON/OFF6 LED ON/OFF7
* Pd or Pu detected in input port when power on, Pd=CD1, Pu=CD2
22
DN-S5000 M5705 (IC501)
XSAWRCVCO XSVREFO XSPDOFTR2 XSVR_PLL XSFTROPI XSFDO AVSS_PL XSPLLFTR2 AVDD5_PL XSFDIREF XSPDIREF GND XTSLRF XTPLCK VDD XRA(3) XRA(2) XRA(1) XRA(0) XRA(4) XRA(5) XRA(6) GND XRA(7) XRA(10) XRA(11) VDD XRA(8) XRA(9) XROEJ VDD XRCASJ XRRASJ XRSDCLK XRWEJ XRD(7) XRD(8) XRD(6) GND XRD(9) XRD(5) XRD(10) XRD(4) XRD(11)
23
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
AVSS-DS XSRFIN XSIPIN AVDD5-DS XSDSSLV XSRSLINT VDD XSAWRC XSRFGC XSEFGC XSFOCUS XSTRACK XSSLEG AVDD5-DA XSMOTOR AVSS-DA XSRFRPLP XSTELP XSVREF2 XSRFRP XSTEXI AVSS-AD XSTEI XSFEI XSAEI AVDD5-AD XSSBAD GND XSDFCT XSCSJ XSCLK XSDATA XSLDC XSFGIN XSSPDON XSFLAG(3) XSFLAG(2) XSFLAG(1) XSFLAG(0) XMP1_7 XMP1_6 GND NC XMP1_4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
XRD(3) XRD(12) GND XRD(2) XRD(13) XRD(1) XRD(14) XRD(0) XRD(15) XHD(7) XHD(8) XHD(6) XHD(9) XHD(5) XHD(10) XHD(4) XHD(11) VDD XHD(3) XHD(12) XHD(2) XHD(13) GND XHD(1) XHD(14) XHD(0) XHD(15) XHDRQ XHIOWJ XHIORJ XHIORDY XHDACKJ XHINT XHCS16J XHA(1) XHPDIAGJ XHA(0) XHA(2) XHCS1J XHCS3J XHDASPJ XMA(15) XMA(14) XMA(13)
XMP1_3 XMFSCSJ XMP1_2 XGPIO(2) XMP1_1 XMRSTJ XGPO(1) XGPO(0) XCRSTJ XMPSENJ VDD XMALE XMP1_0 VDD XOSC1 XOSC2 GND XMD(0) XMD(1) XMD(2) XMD(3) XMD(4) XMD(5) XMD(6) XMD(7) XMCSJ XMRDJ XMWRJ XMINT1J XMA(11) XMA(10) VDD XMA(9) XMA(8) XMA(7) XMA(6) XMA(5) XMA(4) XMA(3) XMA(2) XMA(1) XMA(0) XMA(12) GND
4M DRAM
M5705
ATAPI & MPEG I/F
M
Data Separator DVD-DSP RAM Arbiter
PC MPEG DEC.
C3 ECC EDC Digital Servo
Motor Driver
CD-DSP Target Search
MCU
ROM
M5705 Terminal Function
Pin No. 2 3 5 6 8 9 10 11 12 13 15 17 18 19 20 21 23 24 25 Pin Name XSRFIN XSIPIN XSDSSLV XSRSLINT XSAWRC XSRFGC XSEFGC XSFOCUS XSTRACK XSSLEG XSMOTOR XSRFRPLP XSTELP XSVREF2 XSRFRP XSTEXI XSTEI XSFEI XSCEI Type I/A I/A O/A I/A O/A O/A O/A O/A O/A O/A O/A I/A I/A I/A I/A I/A I/A I/A I/A Description Analog RF signal input after passing through the equalizer Inverting input pin of data slicer Slice level output pin Reference current setting pin for analog data slicer Output for enlarge VCO range. Analog output from DAC buffer RF gain control output E,F gain control output Output voltage level for focusing buffer IC Output voltage level for tracking buffer IC Output voltage level for sledge buffer IC Output voltage level for spindle motor buffer IC High bandwidth low pass filter input for RFRP High bandwidth low pass filter input for TE 2.1V reference voltage input RF ripple/envelope signal input Tracking zero crossing input signal Tracking error input signal Focus error input signal 1. Center error input signal 2. Photo Interrupt input
23
DN-S5000
Pin No. 27 166 167 169 171 172 173 174 175 176 29 30 31 32 33 34 35 36, 37, 38, 39 48, 51, 52 40 41 43 44 45 47 49 57 46 54 56 70 71 72 73 74, 75, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91 62, 63, 64, 65, 66, 67, 68, 69 163 164 59 60 53 94 93 103 104 105 101 99 50 100 Pin Name XSSBAD XSPDIREF XSFDIREF XSPLLFTR2 XSFDO XSFTROPI XSVR_PLL XSPDOFTR2 XSVREFO XSAWRCVCO XSDFCT XSCSJ XSCLK XSDATA XSLDC XSFGIN XSSPDON XSFLAG[3:0] XGPIO[2:0] XMP1_7 XMP1_6 XMP1_5 XMP1_4 XMP1_3 XMP1_2 XMP1_1 XMP1_0 XMFSCSJ XMPSENJ XMALE XMCSJ XMRDJ XMWRJ XMINT1J XMA[15:0] XMD[7:0] XTPLCK XTSLRF XOSC1 XOSC2 XCRSTJ XHCS1J XHCS3J XHIORJ XHIOWJ XHDRQ XHDACKJ XHCS16J XHRSTJ XHINT Type I/A I/A I/A I/A O/A I/A I/A I/A O/A I/A I O O I/O O I O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I I I I I O I O I O Description Sub-beam addition signal input Phase detector reference current generator. Connect a resistor between this pin and ground to set reference current Frequency detector reference current generator. Connect a resistor between this pin and ground to set reference current Data PLL loop filter pin#2 Output node of frequency detector charge pump circuit Input node of loop filter OP circuit PLL reference voltage input Phase detector filter pin#1 Reference voltage output Auto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode Detect detection signal input Chip select signal for accessing control registers Clock output for accessing control registers Registers data input/output pin Laser diode on/off control output for both CD/DVD Motor Hall sensor input Spindle motor on output These pins are used to monitor some status of servo control block 1. These pins are used as general purpose I/O bus 2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6. Internal microcontroller programmable I/O port 1.7. Internal microcontroller programmable I/O port 1.6. This pin is now changed to be NC. Internal microcontroller programmable I/O port 1.4. Internal microcontroller programmable I/O port 1.3. Internal microcontroller programmable I/O port 1.2. Internal microcontroller programmable I/O port 1.1. Internal microcontroller programmable I/O port 1.0. This pin is default used as the A16 (microcontroller address line 16) Output chip select connected to external flash ROM chip enable pin Output program store enable connected to external ROM PSENJ pin. This signal is used as address latch signal in address/data mux mode 1. This signal must be asserted for all microcontroller accesses to the register of this chip 2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1 1. This signal is used as the Read Strobe signal 2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0 This signal is used as the Wire Strobe signal 1. This signal is an interrupt line to the microcontroller 2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7 These pins are used as address bus These pins are used as data bus for the 16-bit processor mode, or the address/data mux bus for the 8-bit processor mode. PLCK test pin SLRF test pin Crystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz Crystal output Chip Reset. As asserted low input generates a component reset that stops all operations within the chip and deasserts all output signals. All input/output signals are set to input. This pin is used to select the command block task file registers This pin is used to select the control block task file registers Asserted by the host during a host I/O read operation Asserted by the host during a host I/O write operation 1. DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer between the host and the controller. This pin is tri-stated when DMA transfers are not enabled. 2. MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected. 1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge signal during DMA data transfers. 2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected 1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data bus. This pin is open-drain tri-state output. 2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected. Host Reset. The reset of ATA bus 1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to indicate to the host that the controller needs attention. 2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
24
24
DN-S5000
Pin No. 97 92 102 95, 96, 98 Pin Name XHPDIAGJ XHDASPJ XHIORDY XHA[2:0] Type I/O I/O I/O I Description This pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain output. This pin is used for Master/Slave drive communication and/or for driving an LED 1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller is not ready to respond. This pin will be tri-stated when a read or write is not in progress. 2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected Host address lines. The host address lines A[2:0] are used to access the various host control, status, and data registers 1. Host data bus. This bus is used to transfer data and status between the host and the controller. 2. MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected. 3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of bit3-0 and VCD I/F is as follow HD0--CD-DATA HD1--CD-LRCK HD2--CD-BCK HD3--CD-C2PO This signal is the clock output for SDRAM This signal is used as the memory output enable for external DRAM buffers. After RSTJ is asserted, this signal will be low This signal is asserted low when a buffer memory write operation is active This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this signal will be high This signal is used as column address output to external DRAM. After RSTJ is asserted, this signal will be high 1. RAM address lines. These are bits11-0 for addressing the buffer memory. 2. Hardware setting. The bits6-0 are used as hardware setting for some functions. RA[9] : FLASH size is 64K/128K 1: FLASH size is 64K 0: FLASH size is 128K RA[8] : External CPU is 8032/H8 1: 8032 0: H8 RA[7] : Microcontroller programmable I/O port 1 pin control 1: By internal microcontroller 0: By registers to decide input/output RA[6] : System test pin output 1: Normal operation 0: System test pin output RA[5] : For testing purpose, donít need to set RA[4] : IDE master/slave 1: Slave 0: Master RA[3] : For testing purpose, donít need to set RA[2] : For testing purpose, donít need to set RA[1-0] : MCU Mode selection 11: Normal Mode (internal uP internal address latch) , 10: Outside uP Mode (ICE Mode) 01: Test mode for internal uP testing 00: Internal uP mode with external address latch
25
106, 107, 108, 109, 111, 112, 113, 114, 116, 117, 118, 119, XHD[15.0] 120, 121, 122, 123 143 147 142 144 145 XRSDCLK XROEJ XRWEJ XRRASJ XRCASJ
I/O
O O O O O
148, 149, 151, 152, 153, 155, 156, 157, 158, XRA[11:0] 159, 160, 161
O
124, 125, 126, 127, 128, 129, 131, 132, 134, 135, 136, 137, 138, 139, 140, 141 4 14 26 168 7, 55, 58, 76, 115, 146, 150, 162 1 16 22 170 28, 42, 61, 88, 110, 130, 138, 154, 165
XRD[15:0]
I/O
These signals are the 8-bit parallel data lines to/from the buffer memory.
AVDD5_DS AVDD5_DA AVDD5_AD AVDD5_PL VDD AVSS_DS AVSS_DA AVSS_AD AVSS_PL GND
Analog Power +5V for Data Slicer part Analog Power +5V for DAC part Analog Power +5V for ADC part Analog Power +5V for Data PLL part Power +3.3V for digital core logic and pad Analog Ground for Data Slicer part Analog Ground for DAC part Analog Ground for ADC part Analog Ground for Data PLL part Digital Ground core logic and pad.
25
DN-S5000 SP3721A (IC502)
CDRDDC
26
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVDRFP DVDRFN PD1 PD2 A2 B2 C2 D2 CP 1 2 3 4 5 6 7 8 9 48 SDEN 47 SDATA 46 SCLK 45 LCP 44 LCN 43 CE 42 FE 41 TE 40 MEI 39 MEV 38 TPH 37 DFT 36 PI 35 MIN 34 MEVO 33 MLPF 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TOP VIEW
CN 10 D 11 C 12 B 13 A 14 F 15 E 16
VIP
VCI
VCI2
VNB
CDTE
VPB
VIIRR
VIB
VC
SP3721A Terminal Function
Pin No. 1, 2 63 59, 60 53, 54 32 49 11~14 5~8 15~16 3~4 40 35 21 23 25 61, 62 51, 52 57 64 42 41 Pin Name DVDREP DVDREN , CDRF AIP AIN , DIP DIN , FDCHG# HOLD1 D, C, B, A A2, B2, C2, D2 F, E PD1, PD2 MEI MIN DVDPD CDPD LDON# ATON/ATOP FNN, FNP SIGO CDRFDC FE TE Type I I I I I I I I I I I I I I I O O O O O O Description RF Signal Inputs. Differential RF signal attenuator input pins RF Signal Inputs. Single-ended RF signal attenuator input pin AGC Amplifier Inputs. Differential AGC amplifier input pins Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended output buffer and full wave rectifier Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches. A low level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for the MIRR bottom hold circuit. (open high) Hold Control. A TLL compatible control pin which, when pulled high, disables the RF AGC charge pump and holds the RF AGC amplifier gain at its present value. (open high) Photo Detector Interface Inputs. Inputs from the main beam Photo detector matrix outputs Photo Detector Interface Inputs. AC coupled inputs for the DPD from the main beam Photo detector matrix outputs CD tracking Error Inputs. Inputs from the CD photo detector error outputs. CD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs Mirror Envelope Inputs. The SIGO envelope input pin RF signal Input for Mirror. AC coupled inputs for the mirror detection circuit from the pull-in signal output. (PI) APC Input. DVD APC input pin from the monitor photo diode APC Input. CD APC input pin from the monitor photo diode APC Output On/Off. APC output control pin. A low level activates the LD output. (open high) Differential Attenuator Output. Attenuator outputs Differential Normal Output. Filter normal outputs Single Ended Normal Output. Single-ended RF output CD RF Signal Output. Single ended CD RF summing output Focusing Error Signal Output. Focus error output reference to VCI Tracking Error Signal Output. Tracking error output reference to VCI
26
FDCHG#
NC
DVDPD
DVDLD
LDON#
CDPD
CDLD
HOLD1
CDRF
ATON
ATOP
SIGO
VNA
FNN
FNP
BYP
VPA
DIN
AIN
DIP
AIP
RX
DN-S5000
Pin No. 43 34 37 29 36 22 24 56 9 10 45 44 30 31 39 17 38 26 27 18 55 33 19 48 47 46 58 28 50 20 Pin Name CE NEVO DFT MIRR PI DVDLD CDLD BYP CP CN LCP LCN MP MB MEV CDTE TPH VC VCI VCI2 RX MLPF NC SDEN SDATA SCLK VPA VPB VNA VNB Type O O O O O O O I/O I/O I/O -- -- -- -- -- -- -- -- -- -- -- -- -- I I/O I Description Center Error Signal Output. Center error output reference to VCI SIGO Bottom Envelope Output. Bottom envelope for mirror detection Defect Output. Pseudo CMOS output. When a defect is detected, the DFT output goes high. Also the servo AGC output can be monitored at this pin, when CAR bits 7-4 are `0011' Mirror Detect Output. Mirror Detect comparator output. Pseudo CMOS output Pull-in Signal Output. The summing signal output of A, B, C, D or PD1, PD2 for mirror detection. Reference to VCI APC output. DVD APC output pin to control the laser power APC output. CD APC output pin to control the laser power The RF AGC integration capacitor CBYP is connected between BYP and VPA , Differential Phase tracking LPF pin. An external capacitance is connected between this pin and the CN pin Differential Phase tracking LPF pin. An external capacitance is connected between this pin and the CP pin Center Error LPF pin. An external capacitance is connected between this pin and the LCN pin Center Error LPF pin. An external capacitance is connected between this pin and the LCP pin MIRR signal Peak hold pin. An external capacitance is connected to between this pin and VPB MIRR signal Bottom hold pin. An external capacitance is connected to between this pin and VPB Sigo Bottom Envelope pin. An external capacitance is connected to between this pin and VPB CD Tracking. E-F Opamp output for feedback PI Top Hold pin. An external capacitance is connected to between this pin and VPB Reference Voltage output. This pin provides the internal DC bias reference voltage (+2.5V lix). Output Impedance is less than 50ohms Reference Voltage input. DC bias voltage input for the servo input reference Reference Voltage input. DC bias voltage input for the servo input reference Reference Resistor Input. An external 8.2kohm, 1% resistor is connected from this pin to ground to establish a precise PTAT (proportional to absolute temperature) reference current for the filter MIRR signal LPF pin. An external capacitance is connected between this pin and VPB No Connect Serial Data Enable. Serial Enable CMOS input. A high level input enable the serial port (Not to be left open) Serial Data. Serial data bi-directional CMOS pin. NRZ programming data for the internal registers is applied to this input ( Not to be left open) Serial Clock. Serial Clock CMOS input. The clock applied to this pin is synchronized with the data applied to SDATA (Not to be left open) Power. Power supply pin for the RF block and serial port Power. Power supply pin for the servo block Ground. Ground pin for the RF block and serial port Ground. Ground pin for the servo bolck
27
27
DN-S5000 128M SDRAM (IC402, 403) Pin Assignment
Pin No. 22, 23~26, 29~35 20, 21 Pin Name Function A0~A11 Address Bank Select Data Input/Output Description Multiplexed pins for row and column address. Row address: A0~A11. Column address: A0~A8. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input.
28
1
54
BS0, BS1 2, 4, 5, 7, 8, DQ0~ 10,11, 13, 42, DQ15 44,45, 47, 48, 50, 51, 53 19 CS# RAS# CAS# WE# UDQM/ LDQM CLK CKE Vcc Vss VccQ VssQ NC
18
TOP VIEW
17 16 15, 39
38 37 1, 14, 27 28, 41, 54 3, 9, 43, 49 6, 12, 46, 52 36, 40
27
28
Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Row Address Strobe Command input. When sampled at the rising edge of the clock, RAS#, CAS# and WE# define the operation to be executed. Column Address Strobe Referred to RAS# Write Enable Referred to RAS# input/output mask The output buffer is placed at Hi-A (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. Clock Inputs System clock used to sample inputs on the rising edge of clock. Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power (+3.3V) Power for input buffers and logic circuit inside DRAM. Ground Ground for input buffers and logic circuit inside DRAM. Power (+3.3V) for I/O buffer Separated power from Vcc, used for output buffers to improve noise. Ground for I/O buffer Separated ground from Vss, used for output buffers to improve noise. No Connection No Connection
Chip Select
W29EE011P (IC507)
A12 A15 A16 NC VDD WE NC
4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE DQ7
VDD VSS CE OE WE CONTROL OUTPUT BUFFER DQ0 : DQ7
Terminal Function
Name A0 - A16 DQ0 - DQ7 CE OE WE VDD GND NC Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection
TOP VIEW
14 15 16 17 18 19 20
DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6
A0 . . . . . . . A16
DECODER
CORE ARRAY
28
DN-S5000 BD6670FM (IC510)
EXOR
H1+ Hall comp FG3
29
BD6670FM Terminal Function
Pin Pin No. Name
28
PWM Comp FG
Function
Hall input Amp 1 positive input Hall input Amp 1 negative input Hall input Amp 2 positive input Hall input Amp 2 negative input Hall input Amp 3 positive input Hall input Amp 3 negative input Gain switch pin GND Capacitor pin 1 for charge pump Capacitor pin 2 for charge pump Capacitor connection pin for charge pump Capacitor connection pin for phase compensation Short Brake Pin Power supply for signal division Power supply for driver Torque control standard voltage input terminal Torque control voltage input terminal Power Save in Resistor connection pin for current sense Output3 for motor Resistor connection pin for current sense Output2 for motor Resistor connection pin for current sense Output1 for motor Power supply for driver Hall bias pin FG output pin FG3 output pin
1
H1-
27
VH
2
H2+ Hall Amo
3
H2-
Hall bias
26
VM
25 TSD
A1
4
H3+
24
RNF1
5
H3-
6
GSW
U-Pre Driver Driver Gain control OSC Matrix
23
A2
22
7
GND
8
CP1
L-Pre Driver
RNF1
21
A3
20 Charge Pump PS
Current Sense AMP Torque AMP RNF2
9
CP2
19
PS
10
VG
18
EC
11
CNF
17
ECR
12
SB
16
Matrix VM
13
Vcc
15
CL
14 D CK Q QB
REVERSE DETECT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
H1+ H1H2+ H2H3+ H3GSW GND CP1 CP2 VG CNF SB VCC VM ECR EC PS RNF2 A3 RNF1 A2 RNF1 A1 VM VH FG FG3
BA5954FP (IC509)
28 27 26 10k 7.5k STAND BY THERMAL SHUT DOWN 20k x2 7.5k DET.AMP . 25 24 23 22 PreGND 10k 21 PVcc2 15k LOADING DRIVER ACTUATOR DRIVER PVcc1 PVcc2 Vcc SLED DRIVER 25k Vcc 2 3 4 5 6 7 8 PVcc1 PGND 9 10 11 12 13 14 ACTUATOR DRIVER 20 19 PGND 18 17 16 15
BU2090F (IC103, 201)
VSS 1 DATA 2 CLOCK 3 Q0 4 Q1 5 Q2 6 Q3 7 Q4 8 Output Buffer (Open Drain) Control Circuit 12-bit Shift Register Latch 16 VDD 15 Q11 14 Q10 13 Q9 12 Q8 11 Q7 10 Q6 9 Q5
DET.AMP . x2 7.5k 20k 7.5k 10k 1 10k
BA5954FP Terminal Function
Pin Pin No. Name Function Pin Pin No. Name Function
1 VINFC Focus driver input 2 CFCerr1 Cap. connection pin for error amp filter 3 CFCerr2 Cap. connection pin for error amp filter 4 VINSL+ Op. amp input (+) for sled driver 5 VINSL- Op. amp input (-) for sled driver 6 VOSL Op. amp output for sled driver 7 VNFFC Focus driver feedback pin 8 Vcc Pre Vcc, power Vcc for sled driver 9 PVcc1 Power Vcc for loading driver 10 PGND Power GND 11 VOSL- Output (-) of sled driver 12 VOSL+ Output (+) of sled driver 13 VOFC- Output (-) of focus driver 14 VOFC+ Output (+) of focus driver
15 VOTK+ Output (+) of tracking driver 16 VOTK- Output (-) of tracking driver 17 VOLD+ Output (+) of loading driver 18 VOLD- Output (-) of loading driver 19 PGND Power GND 20 VNFTK Tracking driver feedback pin 21 PVcc2 Power Vcc for actuator driver 22 PreGND Pre GND 23 VINLD Loading driver input 24 CTKerr2 Cap. connection pin for error amp filter 25 CTKerr1 Cap. connection pin for error amp filter 26 VINTK Tracking driver input 27 BIAS Bias input 28 STBY Standby pin
29
DN-S5000 TA7291F(IC512)
30
TA7291F Terminal Function
P 7 8 4 1 5 6 2 10 PIN No. S 2 6 8 5 9 1 7 3 F 11 15 5 1 7 9 4 13 SYMBOL Vcc Vs Vref GND IN1 IN2 OUT1 OUT2 FUNCTION DESCRIPTION Supply voltage terminal for Logic Supply voltage terminal for Motor driver Supply voltage terminal for control GND terminal Input terminal Input terminal Output terminal Output terminal
TRANSISTORS
DTA114EK DTC114EK DTA114EK
PNP Type
C
DTC114EK
NPN Type
C
B TOP VIEW E C
B
R1 R1 R2 E R2
R1 B R1 R2 E R2 DTA114EK 10kohm 10kohm DTC114EK 10kohm 10kohm
DIODES
FMB-G14
FRONT VIEW
AW04 RN1Z RN2Z RN3Z
30
DN-S5000
31
FL DISPLAY
24-ST-09GN (FL101)
82 51
1
44
Pin Connection
8 8 8 8 8 8 8 8 7 6 5 4 3 2 P Connection N N N N N N 2 PPPPPP 0
Pin No.
8 1 P 1 9
8 0 P 1 8 9 P 2 2
7 9 P 1 7 1 0 P 2 3
7 8 P 1 6 1 1 P 2 4
7 7 P 1 5 1 2 P 2 5
7 6 P 1 4 1 3 P 2 6
7 5 P 1 3 1 4 P 2 7
7 4 P 1 2 1 5 P 2 8
7 3 P 1 1 1 6 P 2 9
7 2 P 1 0 1 7 P 3 0
7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1 2 2 PPPPPPPPP 0 9 8 7 6 5 4 3 2 1 3 4N 9 8 7 6 5 4 3 2 1 GGGGGGGGGGGGP 1 8 P 3 1 1 9 P 3 2 2 0 P 3 3 2 1 P 3 4 2 2 P 3 5 2 3 P 3 6 2 4 P 3 7 2 5 P 3 8 2 6 P 3 9 2 2 2 3 3 3 3 3 3 3 3 3 3 7 8 9 0 1 2 3 4 5 6 7 8 9 2 2 2 1 1 1 1 1 1 1 1 1 2 1 0 9 8 7 6 5 4 3 2 1N GGGGGGGGGGGGP
4 4 4 4 4 9 8 7 6 5 NNNNN PPPPP 4 4 4 4 4 0 1 2 3 4 NF F F F P+ + + +
1 2 3 4