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6ZG-1
English
SERVICE MANUAL
CD MECHANISM BASIC CD MECHANISM : 3ZG-2 E1 TYPE YSDFNSHCM VOS1NDSM YVOS1NDM YSDNSHM SDFNSHM
S/M Code No. 09-994-326-2N2
TABLE OF CONTENTS
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING ................................................ 3 Precaution to replace Optical block......................................................................................................... 3 DISASSEMBLY INSTRUCTIONS ........................................................................................................ 4-6 ELECTRICAL MAIN PARTS LIST ....................................................................................................... 7-9 TRANSISTOR ILLUSTRATION ............................................................................................................ 10 BLOCK DIAGRAM-1 (YSDFNSHCM, YSDNSHM, SDFNSHM) ..................................................... 11, 12 BLOCK DIAGRAM-2 (VOS1NDSM, YVOS1NDM) ......................................................................... 13, 14 WIRING-1 (YSDFNSHCM, YSDNSHM, SDFNSHM) ...................................................................... 15, 16 SCHEMATIC DIAGRAM-1 (YSDFNSHCM, YSDNSHM, SDFNSHM) ............................................ 17, 18 WIRING-2 (VOS1NDSM, YVOS1NDM) ........................................................................................... 19-22 SCHEMATIC DIAGRAM-2 (VOS1NDSM, YVOS1NDM 1/2) .......................................................... 23, 24 SCHEMATIC DIAGRAM-3 (VOS1NDSM, YVOS1NDM 2/2) .......................................................... 25, 26 WIRING-3 .............................................................................................................................................. 27 WAVE FORM ................................................................................................................................... 28-31 IC DESCRIPTION ............................................................................................................................ 32-48 IC BLOCK DIAGRAM ....................................................................................................................... 49-51 TEST MODE ................................................................................................................................... 52, 53 MECHANICAL EXPLODED VIEW 1/1 .................................................................................................. 54 MECHANICAL PARTS LIST 1/1 ........................................................................................................... 55 CD MECHANISM EXPLODED VIEW 1/1 ............................................................................................. 56 CD MECHANISM PARTS LIST 1/1 ...................................................................................................... 56 REFERENCE NAME LIST .................................................................................................................... 57
2
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING
This set employs laser. Therefore, be sure to follow carefully the instructions below when servicing.
CAUTION
Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.
WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER EXIT WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE FROM A DISTANCE OF MORE THAN 30cm FROM THE SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL PICK-UP BLOCK. Caution: Invisible laser radiation when open and interlocks defeated avoid exposure to beam. Advarsel:Usynling laserståling ved åbning, når sikkerhedsafbrydere er ude af funktion. Undgå udsættelse for stråling.
ATTENTION
L'utilisation de commandes, réglages ou procédures autres que ceux spécifiés peut entraîner une dangereuse exposition aux radiations.
ADVARSEL!
Usynlig laserståling ved åbning, når sikkerhedsafbrydereer ude af funktion. Undgå udsættelse for stråling. This Compact Disc player is classified as a CLASS 1 LASER product. The CLASS 1 LASER PRODUCT label is located on the rear exterior.
VAROITUS!
Laiteen Käyttäminen muulla kuin tässä käyttöohjeessa mainitulla tavalla saattaa altistaa käyt-täjän turvallisuusluokan 1 ylittävälle näkymättömälle lasersäteilylle.
VARNING!
Om apparaten används på annat sätt än vad som specificeras i denna bruksanvising, kan användaren utsättas för osynling laserstrålning, som överskrider gränsen för laserklass 1.
CLASS 1 KLASSE 1 LUOKAN 1 KLASS 1
LASER PRODUCT LASER PRODUKT LASER LAITE LASER APPARAT
Precaution to replace Optical block (KSS-213B)
Body or clothes electrostatic potential could ruin laser diode in the optical block. Be sure ground body and workbench, and use care the clothes do not touch the diode. 1) After the connection, remove solder shown in the right figure.
3
DISASSEMBLY INSTRUCTIONS
1. How to replace PICK UP.
1) Open the TRAY. Push the stopper to arrow direction and release half of the SHAFT SLED. Turn GEAR MAIN CAM to the counterclockwise (arrow "a") direction, and lift up CD mechanism. (Fig-1) Remove SHAFT SLED. CD mechanism in down position, replace PICK UP. Lift up CD mechanism (Fig-1), and Reassemble the SHAFT SLED. PICKUP
2) 3) 4) 5)
SHAFT SLED STOPPER a GEAR MAIN CAM Fig-1
2. How to remove the 5CD CHANGER BLOCK (Fig-2)
1) 2) Remove the two FFC of the CD circuit board, and remove the five SCREWS. Lift 5 CD CHANGER BLOCK from behind, and remove it. (5CD CHANGER BLOCK can be removed even if PANEL TRAY is not removed.)
5CD CHANGER BLOCK FFC SCREW LIFT UP
FFC Fig-2
4
3. The disassemble and reassemble the TRAY
3-1. Disassembling procedure.
1) Push the PLATE GEAR'S Boss at the bottom part of CHAS MECHA strongly to the outside (arrow "b" direction). (Fig-3) (Confirm that TRAY appears a little in the front.) Draw TRAY to the open position. Remove FFC, and push the two LEVERS at both side of the CHAS MECH to remove TRAY. (Fig-4) TRAY
b BOSS
2) 3)
5CD CHANGER BLOCK
FFC
LEVER
Fig-3
LEVER
Fig-4
3-2. Reassembling procedure.
1) Confirm that LEVER TRAY is at the most right position and check for the CD Mechanism to be in the down position. (Fig-5) Push in the TRAY along the rail of the CHAS MECHA. 3) After TRAY is half closed and FFC is put in, it can enter by force until the end of TRAY closed. (Fig-6)
2)
FFC TRAY
LEVER TRY Fig-5 Fig-6 5
4. How to reassemble the TURN TABLE. (Fig-7)
1) Push LEVER TT in the direction of "C", and put in the TURN TABLE 5CD. (Fig-7) After reassembly, one of the TURN TABLE DISC TRAY (can be either one of the five disc trays) must be aligned with TURN TABLE 5CD. (Fig-8) That is, having no gap difference between the TURN TABLE 5CD and the TRAY 5CD. When reassembling the TURN TABLE 5CD, it is acceptable facing any CD number (1-5).
*
ALIGN
C
LEVER TT
TRAY 5CD
Fig-7
TURN TABLE 5CD
Fig-8
6
ELECTRICAL MAIN PARTS LIST
REF. NO IC
PART NO.
KANRI NO.
DESCRIPTION
REF. NO C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C150 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C212 C213 C213 C214 C214 C215 C216 C217 C218 C219 C220 C221 C222 C223 C228 C230 C231 C401 C402 C501 C502 C503 C504 C505 C506 C507
87-A20-547-010 87-A20-919-040 87-A20-917-010 87-A20-546-010 87-A20-592-040 87-A20-602-040 87-A20-925-040 87-A20-905-040 87-070-305-010 87-001-982-010 87-A20-918-040 87-A20-653-010 87-017-825-010 86-ZG1-658-010 87-A20-895-010 87-A20-921-040 87-A20-249-040 87-A20-962-040 87-A20-957-040 86-ZG1-655-040 87-A21-099-040
C-IC,CXA1992AR C-IC,BA5915FP C-IC,CXD2540Q-1/2 C-IC,CXD2589Q C-IC,M51943 AML C-IC,M5291FP C-IC,BA05FP C-IC,BA033FP IC,BA6897S IC,TA7291S C-IC,SM5878AM C-IC,RL5C293 IC,GP1F32T C-IC,CXP84548-112Q C-IC,CXD1856R C-IC,SN74LVU04APW C-IC,BU2874FV C-IC,MSM54V16258B/BSL C-IC,SN74LV245APW C-IC,MSM531031B-72GS-KR1 C-IC,HD74HC393FP
KANRI DESCRIPTION NO. 87-010-263-040 CAP,E 100-10 87-010-178-080 CHIP CAP 1000P 87-010-550-040 CAP,E 100-6.3 GAS 87-010-182-080 C-CAP,S 2200P-50 B 87-010-198-080 CAP, CHIP 0.022 87-016-081-080 87-016-081-080 87-016-081-080 87-010-497-040 87-016-081-080 87-010-197-080 87-010-402-040 87-010-382-040 87-010-213-080 87-010-263-040 87-010-197-080 87-010-369-080 87-010-197-080 87-010-369-080 87-010-197-080 87-010-494-040 87-010-154-080 87-010-154-080 87-010-154-080 87-010-596-080 87-010-596-080 87-012-140-080 87-010-596-080 87-010-198-080 87-016-081-080 87-010-550-040 87-010-550-040 87-012-158-080 87-010-145-080 87-010-596-080 87-010-188-080 87-012-156-080 87-018-134-080 87-010-400-040 87-010-197-080 87-010-318-080 87-012-154-080 87-012-154-080 87-010-176-080 87-010-176-080 87-010-401-040 87-010-382-040 87-010-401-040 87-010-382-040 87-010-318-080 87-010-318-080 87-010-380-040 87-010-197-080 87-010-196-080 87-010-370-040 87-010-197-080 87-010-186-080 87-016-081-080 87-018-209-080 87-010-197-080 87-018-209-080 87-010-403-080 87-010-403-040 87-016-459-040 87-010-197-080 87-010-263-040 87-010-196-080 87-010-196-080 87-010-196-080 87-010-196-080 C-CAP,S 0.1-16 RK C-CAP,S 0.1-16 RK C-CAP,S 0.1-16 RK CAP,E 4.7-35 GAS C-CAP,S 0.1-16 RK CAP, CHIP 0.01 DM CAP,E 2.2-50 CAP,E 22-25 SME C-CAP,S 0.015-50 B CAP,E 100-10 CAP, CHIP 0.01 DM C-CAP,S 0.033-25 K B CAP, CHIP 0.01 DM C-CAP,S 0.033-25 K B CAP, CHIP 0.01 DM CAP,E 1-50 GAS CAP CHIP 10P CAP CHIP 10P CAP CHIP 10P CAP, S 0.047-16 CAP, S 0.047-16 CAP 470P CAP, S 0.047-16 CAP, CHIP 0.022 C-CAP,S 0.1-16 RK CAP,E 100-6.3 GAS CAP,E 100-6.3 GAS C-CAP,S 390P-50 CH C-CAP,S 1P-50 CH CAP, S 0.047-16 CAP,CHIP 6800P C-CAP,S 220P-50 CH CAPACITOR,TC-U 0.01-16 CAP,E 0.47-50 CAP, CHIP 0.01 DM C-CAP,S C-CAP,S C-CAP,S C-CAP,S C-CAP,S 47P-50 CH 150P-50 CH 150P-50 CH 680P-50 SL 680P-50 SL
PART NO.
TRANSISTOR 89-406-555-080 89-111-625-080 87-026-463-080 87-026-237-080 87-A30-117-010 87-026-231-080 89-421-722-380 89-320-011-080 87-026-223-080 89-110-155-080 87-026-580-080 89-327-125-080 87-026-470-080 87-026-210-080 TR,2SD655 (0.5W) TR,2SA1162 (0.15W) TR,2SA933S (0.3W) CHIP-TR,DTC124XK TR,2SA1357 CHIP-TRANSISTER,DTA124XK TR,2SD2172V/W TR,2SC2001 (15W) TR,DTC143TK TR,2SA1015(0.4W) C-TR,DTA123JK CHIP TR,2SC2712GR TR,HN1C03F (0.3W) CHIP-TR,DTC144EK
CAP,E 1-50 SME CAP,E 22-25 SME CAP,E 1-50 SME CAP,E 22-25 SME C-CAP,S 47P-50 CH C-CAP,S 47P-50 CH CAP,E 47-16 SME CAP, CHIP 0.01 DM CHIP CAPACITOR,0.1-25 CAP,E 330-6.3 SME CAP, CHIP 0.01 DM CAP,CHIP 4700P C-CAP,S 0.1-16 RK CAP, CER 0.1-50V CAP, CHIP 0.01 DM CAP, CER 0.1-50V CAP, ELECT 3.3-50V CAP,E 3.3-50 SME CAP,E 470-10 SMG CAP, CHIP 0.01 DM CAP,E 100-10 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25
DIODE 87-020-027-080 87-020-465-080 87-A40-180-040 87-018-199-080 CHIP-DIODE 1SS184 DIODE,1SS133 (110MA) C-DIODE,SB07-015C CAP, CER 3300P
5CD C.B 86-ZG1-605-010 86-ZG1-667-010 87-010-196-080 87-010-260-080 87-010-197-080 CABLE,FFC 16P F-CABLE,8P 1.25 175MM BLACK CHIP CAPACITOR,0.1-25 CAP, ELECT 47-25V CAP, CHIP 0.01 DM
C1 C2 C4
7
REF. NO C508 C509 C510 C601 C602 C603 C701 C702 C703 C705 C901 C902 C991 C992 C993 C994 CN3 CN7 CON1 CON2 CON3 CON5 CON6 JR9 JR28 JW8 JW42 JW47 JW48 JW72 L101 L201 LED901 M601 R101 R102 R103 R104 R105 R106 R420 SW601 SW602 SW603 X201
KANRI DESCRIPTION NO. 87-016-459-040 CAP,E 470-10 SMG 87-010-196-080 CHIP CAPACITOR,0.1-25 87-010-196-080 CHIP CAPACITOR,0.1-25 87-010-197-080 CAP, CHIP 0.01 DM 87-016-251-040 CAP,E 220-16 SMG 87-010-196-080 87-010-322-080 87-010-318-080 87-010-318-080 87-010-178-080 87-010-260-040 87-010-196-080 87-010-196-080 87-010-196-080 87-010-196-080 87-010-196-080 86-ZG1-609-010 86-ZG1-606-010 87-A60-424-010 87-009-034-010 87-A60-133-010 87-A60-154-010 87-A60-162-010 83-XM1-617-080 83-XM1-617-080 87-018-115-080 87-003-223-010 87-003-223-010 87-026-689-080 87-003-223-010 87-003-102-080 87-003-102-080 87-A40-123-010 87-045-305-010 87-022-363-080 87-022-363-080 87-022-363-080 87-022-363-080 87-022-365-080 87-022-365-080 87-029-060-080 87-036-109-010 87-036-109-010 87-036-109-010 87-A70-046-010 CHIP CAPACITOR,0.1-25 C-CAP,S 100P-50 CH C-CAP,S 47P-50 CH C-CAP,S 47P-50 CH CHIP CAP 1000P CAP,E 47-25 SME CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CONN ASSY,6P CONN ASSY 2P CONN,16P V TOC-B CONN,6P PH V CONN,8P V FE CONN,6P H FE CONN,14P H FE C-COIL,BK2125HM601 C-COIL,BK2125HM601 CAP, CER 47P-50V FERRITE BEAD BLO2RN2 FERRITE BEAD BLO2RN2 PROTECTOR,1A 60V 491 FERRITE BEAD BLO2RN2 COIL, 10UH COIL, 10UH LED,SLZ-8128A-01-B MOTOR, RF-500TB DC-5V (2MA) C-RES,S 68K-1/10W F C-RES,S C-RES,S C-RES,S C-RES,S C-RES,S 68K-1/10W F 68K-1/10W F 68K-1/10W F 100K-1/10W F 100K-1/10W F
PART NO.
REF. NO C121 C123 C125 C126 C127 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C149 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C300 C301 C302 C303 C304 C305 C306 C307 C308 C309 C310 C311 C312 C401 C402 C411 C601 C602 C603 C706 C707 C708 C709 C801 C802 C803 C804 C805 C806 C807 C808 C809 C810 C811 C812 C813 C814
KANRI DESCRIPTION NO. 87-010-596-080 CAP, S 0.047-16 87-016-669-080 C-CAP,S 0.1-25 K B 87-010-198-080 CAP, CHIP 0.022 87-016-669-080 C-CAP,S 0.1-25 K B 87-010-263-040 CAP,E 100-10 87-010-263-040 87-010-263-040 87-010-178-080 87-010-263-040 87-010-196-080 87-010-196-080 87-010-196-080 87-010-196-080 87-010-182-080 87-010-197-080 87-010-384-040 87-010-196-080 87-010-196-080 87-010-197-080 87-010-196-080 87-010-196-080 87-010-213-080 87-010-263-040 87-010-197-080 87-016-251-040 87-010-196-080 87-010-184-080 87-016-669-080 87-010-992-080 87-012-156-080 87-016-526-080 87-010-197-080 87-010-182-080 87-010-197-080 87-016-251-040 87-012-140-080 87-010-178-080 87-010-384-040 87-010-384-040 87-016-251-040 87-010-196-080 87-010-263-040 87-010-196-080 87-010-263-040 87-010-196-080 87-010-178-080 87-010-403-040 87-010-403-040 87-018-214-080 87-010-197-080 87-016-251-040 87-010-196-080 87-010-184-080 87-010-184-080 87-010-184-080 87-010-184-080 87-010-197-080 87-010-197-080 87-010-384-040 87-010-196-080 87-010-196-080 87-010-196-080 87-010-313-080 87-010-313-080 87-010-178-080 87-010-178-080 87-010-178-080 87-010-178-080 87-010-405-040 87-010-405-040 CAP,E 100-10 CAP,E 100-10 CHIP CAP 1000P CAP,E 100-10 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 C-CAP,S 2200P-50 B CAP, CHIP 0.01 DM CAP,E 100-25 SME CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CAP, CHIP 0.01 DM CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 C-CAP,S 0.015-50 B CAP,E 100-10 CAP, CHIP 0.01 DM CAP,E 220-16 SMG CHIP CAPACITOR,0.1-25 CHIP CAPACITOR 3300P(K) C-CAP,S 0.1-25 K B C-CAP,S 0.047-25 B C-CAP,S 220P-50 CH C-CAP,S 0.47-16 BK CAP, CHIP 0.01 DM C-CAP,S 2200P-50 B CAP, CHIP 0.01 DM CAP,E 220-16 SMG CAP 470P CHIP CAP 1000P CAP,E 100-25 SME CAP,E 100-25 SME CAP,E 220-16 SMG CHIP CAPACITOR,0.1-25 CAP,E 100-10 CHIP CAPACITOR,0.1-25 CAP,E 100-10 CHIP CAPACITOR,0.1-25 CHIP CAP 1000P CAP,E 3.3-50 SME CAP,E 3.3-50 SME CAP TC U 0.1-50F CAP, CHIP 0.01 DM CAP,E 220-16 SMG CHIP CAPACITOR,0.1-25 CHIP CAPACITOR 3300P(K) CHIP CAPACITOR 3300P(K) CHIP CAPACITOR 3300P(K) CHIP CAPACITOR 3300P(K) CAP, CHIP 0.01 DM CAP, CHIP 0.01 DM CAP,E 100-25 SME CHIP CAPACITOR,0.1-25 CHIP CHIP CAP, CAP, CHIP CAPACITOR,0.1-25 CAPACITOR,0.1-25 CHIP 18P CHIP 18P CAP 1000P
PART NO.
RES,FUSE 33-1/4 W PUSH SWITCH PUSH SWITCH PUSH SWITCH VIB,XTAL 16.934MHZ
VCD C.B
C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120
CHIP CAP 1000P CHIP CAP 1000P CHIP CAP 1000P CAP,E 10-50 CAP,E 10-50
8
REF. NO C815 C816 C851 C852 C853 C854 C855 C856 C857 C858 C859 C860 C861 C862 C863 C864 C865 C866 C891 C892 C893 C901 C903 C904 C905 C906 C931 C932 C933 C943 C944 C945 C946 C947 C948 C949 C952 C953 C954 C955 C956 C957 C958 C959 C960 C961 C962 C963 C991 C992 CN3 CN3 CN6 CN7 CN7 CN101 CN102 CN301 CN302 CN851
KANRI DESCRIPTION NO. 87-010-318-080 C-CAP,S 47P-50 CH 87-010-318-080 C-CAP,S 47P-50 CH 87-010-197-080 CAP, CHIP 0.01 DM 87-010-197-080 CAP, CHIP 0.01 DM 87-010-196-080 CHIP CAPACITOR,0.1-25 87-010-196-080 87-010-197-080 87-012-140-080 87-012-140-080 87-010-322-080 87-016-459-040 87-010-405-040 87-010-197-080 87-010-405-040 87-010-197-080 87-010-197-080 87-010-197-080 87-010-197-080 87-010-405-040 87-010-197-080 87-010-322-080 87-010-197-080 87-010-197-080 87-010-196-080 87-010-196-080 87-010-405-040 87-010-805-080 87-010-197-080 87-010-322-080 87-010-405-040 87-010-805-080 87-010-154-080 87-010-154-080 87-010-316-080 87-010-316-080 87-010-805-080 87-010-805-080 87-010-196-080 87-010-196-080 87-010-196-080 87-010-805-080 87-010-805-080 87-010-805-080 87-010-805-080 87-010-805-080 87-010-805-080 87-010-805-080 87-010-196-080 87-010-322-080 87-010-322-080 86-ZG1-609-010 87-A60-133-010 87-A60-160-010 86-ZG1-606-010 86-ZG1-606-010 87-A60-424-010 87-009-034-010 87-A60-154-010 86-ZG1-620-010 87-A60-109-010 CHIP CAPACITOR,0.1-25 CAP, CHIP 0.01 DM CAP 470P CAP 470P C-CAP,S 100P-50 CH CAP,E 470-10 SMG CAP,E 10-50 CAP, CHIP 0.01 DM CAP,E 10-50 CAP, CHIP 0.01 DM CAP, CHIP 0.01 CAP, CHIP 0.01 CAP, CHIP 0.01 CAP,E 10-50 CAP, CHIP 0.01 DM DM DM DM
PART NO.
REF. NO J851 L101 L102 L151 L301 L302 L851 L852 L853 L891 L901 L941 M601 R130 R131 R132 R133 R134 R135 SW601 SW602 SW603 X801 X901 X902 X903 X904 T-T C.B C411 CON8 LED411 M401 PS401 Q411 S401 LED C.B LED701 LED702 LED703
KANRI DESCRIPTION NO. 87-009-502-010 JACK,PIN 1P Y EARTH 87-005-196-080 COIL,10UH 87-005-196-080 COIL,10UH 87-005-204-080 COIL,47UH 87-A50-095-010 COIL,68UH RCR875D 87-005-469-080 87-005-196-080 87-005-466-080 87-005-196-080 87-005-196-080 87-005-196-080 87-005-196-080 87-045-305-010 87-022-364-080 87-022-364-080 87-022-364-080 87-022-364-080 87-022-364-080 87-022-364-080 87-036-109-010 87-036-109-010 87-036-109-010 87-030-270-080 87-030-264-080 87-A70-145-080 87-A70-152-080 87-A70-084-080 COIL 4.7UH FLR50 COIL,10UH COIL,2.7UH J FLR50 COIL,10UH COIL,10UH COIL,10UH COIL,10UH MOTOR, RF-500TB DC-5V (2MA) C-RES,S 82K-1/10W F C-RES,S 82K-1/10W F C-RES,S 82K-1/10W C-RES,S 82K-1/10W C-RES,S 82K-1/10W C-RES,S 82K-1/10W PUSH SWITCH F F F F
PART NO.
· Regarding connectors, they are not stocked as they are not the initial order items. The connectors are available after they are supplied from connector manufacturers upon the order is received.
CHIP RESISTOR PART CODE
Chip Resistor Part Coding
8 8
A
Resistor Code Value of resistor Chip resistor
Dimensions (mm)
Figure
Wattage 1/16W 1/16W 1/10W 1/8W
Type 1005 1608 2125 3216
Tolerance 5% 5% 5% 5%
Symbol CJ CJ CJ CJ
Form
L W
L 1.0
t
W 0.5 0.8 1.25 1.6
t 0.35 0.45 0.45 0.55
:A Resistor Code : A
104 108 118 128
C-CAP,S 100P-50 CH CAP, CHIP 0.01 DM CAP, CHIP 0.01 DM CHIP CAPACITOR,0.1-25 CHIP CAPACITOR,0.1-25 CAP,E 10-50 CAP, S 1-16 CAP, CHIP 0.01 DM C-CAP,S 100P-50 CH CAP,E 10-50 CAP, S 1-16 CAP CHIP 10P CAP CHIP 10P C-CAP,S 33P-50 CH C-CAP,S 33P-50 CH CAP, CAP, CHIP CHIP CHIP CAP, CAP, CAP, CAP, CAP, S 1-16 S 1-16 CAPACITOR,0.1-25 CAPACITOR,0.1-25 CAPACITOR,0.1-25 S S S S S 1-16 1-16 1-16 1-16 1-16
PUSH SWITCH PUSH SWITCH VIB,XTAL 16.9344MHZ CERA LOCK(MU)12.0MHZ VIB,CER 33.86MHZ CSTMXWOH3 VIB,CER 45.00MHZ CSAMXZ040 VIB,XTAL 13.5MHZ-50P
1.6 2 3.2
87-018-214-080 87-A60-156-010 87-070-288-010 87-A90-036-010 87-A90-156-010 87-A30-031-010 87-036-109-010
CAP TC U 0.1-50F CONN,8P H FE LED,GL380 MOT ASSY,RF-300CA-11 SNSR,SG-240 P-TR,PT380F PUSH SWITCH
TRANSISTOR ILLUSTRATION
C1 C
87-017-733-080 87-017-733-080 87-017-733-080 LED,SEL1250SMTP5 RED LED,SEL1250SMTP5 RED LED,SEL1250SMTP5 RED
B1 E1
ECB
VIDEO SW C.B
ECB 2SA1015 2SC2001 2SD655 2SD2172
B E 2SA1162 2SC2712 DTA123JK DTA124XK DTC123JK DTC124XK DTC143TK DTC144EK
ECB 2SA1357
E1 B2 C2 HN1C03F
CAP, S 1-16 CAP, S 1-16 CHIP CAPACITOR,0.1-25 C-CAP,S 100P-50 CH C-CAP,S 100P-50 CH CONN ASSY,6P CONN,8P V FE CONN,12P H FE CONN ASSY 2P CONN ASSY 2P CONN,16P V TOC-B CONN,6P PH V CONN,6P H FE CONN ASSY,2P VIDEO-SW CONN,2P V S2M-2W
2SA933
S851 DRIVE C.B CN3 M20 M21 SW1 87-009-349-010 87-045-358-010 87-045-356-010 87-A90-042-010 CONN,6P H WHT PH MOT,RF-310TA 43 MOT,RF-310TA 30 SW,LEAF MSW-17310MVPO 87-A90-238-010 SW,SL 1-1-3 9L
9
10
SCHEMATIC DIAGRAM-1 (YSDFNSHCM, YSDNSHM, SDFNSHM)
17
18
WIRING-3
1 2 3 4 5 6 7
WAVE FORM
1
SYSTEM CLOCK f=16.9344MHz
VOLT/DIV: 2V TIME/DIV: 0.1µS
4
VC
TRACKING
TIME/DIV: 1mS
A 4.4V 0 B
5
VOLT/DIV: 500mV TIME/DIV: 0.5µS
FOCUS SEARCH
2
RF
VC 1.3±0.2V C VC
3
D
FOCUS
VOLT/DIV: 200mV TIME/DIV: 2mS
E
F
G
H
I
J
K 27 28
6
IC905 Pin
106
(XTL20)
VOLT/DIV: 2V TIME/DIV: 10nS
0
IC851 Pin = (FLDOUT)
VOLT/DIV: 2V TIME/DIV: 10mS
7
IC905 Pin 2 (XTL00)
VOLT/DIV: 2V TIME/DIV: 10nS
!
IC851 Pin + (OSDCLK)
VOLT/DIV: 2V TIME/DIV: 50nS
8
IC906 Pin 6
VOLT/DIV: 2V TIME/DIV: 20nS
@
IC801 Pin 3 (CKO)
VOLT/DIV: 2V TIME/DIV: 20nS
9
IC901 Pin / (EXTAL)
VOLT/DIV: 2V TIME/DIV: 20nS
#
IC952 Pin ! (B8)
VOLT/DIV: 2V TIME/DIV: 1mS
29
$
IC952 Pin 9 (A8)
VOLT/DIV: 2V TIME/DIV: 1mS
IC851 Pin 61 (PAL60) PAL DISC PAL
VOLT/DIV: 200mV TIME/DIV: 10µS
%
IC931 Pin % (VBLK)
VOLT/DIV: 2V TIME/DIV: 20µS
IC851 Pin 61 (PAL60) NTSC DISC PAL AUTO
VOLT/DIV: 200mV TIME/DIV: 10µS
^
IC931 Pin * (VB)
VOLT/DIV: 2V TIME/DIV: 20µS
*
_______________
IC851 Pin & (H SYNC) NTSC
VOLT/DIV: 2V TIME/DIV: 50µS
&
_______________
IC851 Pin 61 (PAL60) NTSC DISC NTSC
VOLT/DIV: 200mV TIME/DIV: 10µS
IC851 Pin & (H SYNC) PAL AUTO
VOLT/DIV: 2V TIME/DIV: 50µS
30
_______________
______________
IC851 Pin & (H SYNC) PAL
VOLT/DIV: 2V TIME/DIV: 50µS
IC851 Pin * (V SYNC) PAL
VOLT/DIV: 2V TIME/DIV: 10mS
(
______________
IC851 Pin * (V SYNC) NTSC
VOLT/DIV: 2V TIME/DIV: 10mS
)
CN6 Pin ! (O-DISH, SENS)
VOLT/DIV: 2V TIME/DIV: 200mS
______________
IC851 Pin * (V SYNC) PAL AUTO
VOLT/DIV: 2V TIME/DIV: 10mS
31
IC DESCRIPTION IC, CXD2589Q
Pin No. 1, 20, 45, 60 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19, 46, 61, 80 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name VSS LMUT RMUT SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO XLTO CLKO SPOA SPOB XLON FOK VDD MDP PWMI TEST TESI VPCO VCKI V16M VCTL PCO FILO FILI AVSS CLTV AVDD RF BIAS ASYI ASYO LRCK LRCKI PCMD PCMDI I/O -- O O I O O I I I I I O O O I I O I -- O I I I O I O I O O I -- I -- I I I O O I O I GND. Lch-"0" detect flag. Rch-"0" detect flag. Clock input for SQSO read out. SubQ 80 bit serial output. SENS signal output to CPU. Serial data input from CPU. Latch input from CPU, Latch serial data at fall down. Clock input to serial data transfer from CPU. SENS input from SSP. Numbers of track jump are counted and input. Serial data output to SSP. Serial-data latch output to SSP. Latch at fall down. Clock output for serial data transfer to SSP. Microcomputer expansion interface. (Input A) Microcomputer expansion interface. (Input B) Microcomputer expansion interface. (Output) Focus OK input terminal. Used for SENS output and servo-auto sequencer. Power supply. (+5V) Servo control for spindle motor. External control input for spindle motor. TEST terminal. (Connected to GND) TEST terminal. (Connected to GND) Charge pump output for extensive EFM PLL. VCO2 oscillator input for extensive EFM PLL. VCO2 oscillator output for extensive EFM PLL. VCO2 control voltage input for extensive EFM PLL. Charge pump output for master PLL. Filter (slave = digital PLL) output for master PLL. Filter input for master PLL. Analog GND. VCO control voltage input for master. Analog power. (+5V) EFM signal input. Constant current input to asymmetry circuit. Comparison voltage input to asymmetry circuit. EFM full-swing output. (L=VSS, H=VDD) D/A interface, LR clock output f=FS. LR clock input. D/A interface, serial data output. (2's COMP, MSB first) D/A interface, serial data input. (2's COMP, MSB first) Description
32
Pin No. 43 44 47 48 49 50 51 52 53 54 55 56 57 58 59 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Note) · · · · · · · ·
Pin Name BCK BCKI XUGF XPCK GFS C2PO XTSL C4M DOUT EMPH EMPHI WFCK SCOR SESO EXCK SYSM AVSS AVDD AOUT1 AINI LOUT1 AVSS XVDD XTAI XTAO XVSS AVSS LOUT2 AIN2 AOUT2 AVDD AVSS XRST
I/O O I O O O O I O O O I O O O I I -- -- O I O -- -- I O -- -- O I O -- -- I D/A interface bit clock output. D/A interface bit clock input.
Description
XUGF output, MNT1 or RPCK output by switching command. XPLCK output, MNT0 output by switching command. GFS output, MNT3 or XRAOF output by switching command. C2PO output, GTOP output by switching command. X'tal select input terminal, X'tal: 16.9344MHz = "L" 33.8688MHz = "H". 4.2336MHz output, Output 1/4 divided frequency of VCKI at CAV-W mode. Digital Out connector output signal. "H" when the playback disc has emphasis. "L" when it does not. De-emphasis ON/OFF, "H" when ON, "L" when OFF. WFCK output. H output when the subcode sync S0 or S1 is detected. Serial output for SubP-W. SBSO read out clock input. Mute input terminal, Active the "H" setting. Analogue GND. Analogue power supply. (+5V) Lch/analogue output terminal. Lch/OP AMP input terminal. Lch/LINE output terminal. Analogue GND. Power supply for master clock. Input terminal for crystal oscillator circuit. Input external master clock from this terminal. Output terminal for crystal oscillator circuit. GND terminal for master clock. Analogue GND. Rch/LINE output terminal. Rch/OP AMP input terminal. Rch/analogue output terminal. Analogue power supply. (+5V) Analogue GND. Reset system at "L" setting.
PCMD is the two's complement output with MSB first. GTOP monitors the protection status of the Frame Sync. (H: Sync protection window opened). XUGF is the Frame Sync negative pulse which is obtained from the EFM signal. This is the signal before the sync protection. XPLCK is the inverted signal of the EFM PLL clock. The PLL works so that the fall-down edge and the changed point of the EFM signal agree. GFS is the signal that goes "H" when the Frame Sync and the internally inserted timing agree. RFCK is the signal having 136 micro-seconds (during normal speed) that is generated to have the same accuracy as X'tal. C2PO is the signal indicating the error status of the data. XRAOF is the signal that is generated when the 16k RAM goes outside the jitter margin ±4F.
33
IC, CXA1992AR
Pin No. 1 2 3 4 Pin Name FEO FEI FDFCT FGD I/O O I I I Description Output terminal for focus error amplifier. Internally connected to window comparator input for bias condition. Input terminal for focus error. Capacitor connection terminal for time constant used when there is defect. This pin is connected to GND via capacitor when high frequency gain of the focus servo is attenuated. 5 6 7 8 FLB FE_O FEM SRCH I O I I This is a pin where the time constant is externally connected to raise the low frequency gain of the focus servo. Focus drive output. Focus amplifier inverted input pin. This is a pin where the time constant is externally connected to generate the focus search waveform. 9 TGU I This is a pin where the selection time constant is externally connected to set the tracking servo the high frequency gain. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TG2 FSET TA_M TA_O SL_P SL_M SL_O ISET Vcc LOCK CLK XLT DATA XRST C_OUT SENS1 SENS2 FOK CC2 CC1 CB CP I I I O I I O I I I I I I I O O O O I O I I This is a pin where the selection time constant is externally connected to set the tracking high frequency gain. Pin for setting peak of the phase compensator of the focus tracking. Tracking amplifier inverted input pin. Tracking drive output. Sled amplifier non-inverted input pin. Sled amplifier inverted input pin. Sled drive output. The current which determines height of the focus search, track jump and sled kick is input with external resistance connected. Power supply. "L" setting starts sled disorder-prevention circuit. (Not pull-up resistance) Clock input for serial data transfer from CPU. (No pull-up resistance) Latch input from CPU. (No pull-up resistance) Serial data input from CPU. (No pull-up resistance) Reset system at "L" setting. (No pull-up resistance) Signal output for track number counting. FZC, DFCT1, TZC, BALH, TGH, FOH, or ATSC is output depending on the command from CPU. DFCT2, MIRR, BALL, TGL or FOL is output depending on the command from CPU. Output terminal for focus OK comparator. Input pin where the DEFECT bottom hold output is capacitance coupled. DEFECT bottom-hold output terminal. Internally connected to interruption comparator input. Connection terminal for DEFECT bottom-hold capacitor. Connection terminal for MIRR hold-capacitor. Anti-reverse input terminal for MIRR comparator.
34
Pin No. 32 33
Pin Name RF_I RF_O
I/O I O
Description Input terminal by capacity combination of RF summing amplifier. Output terminal of RF summing amplifier. Checkpoint of Eye pattern. Anti-reverse input terminal for RF summing amplifier.
34
RF_M
I
The gain of RF amplifier is decided by the connection resistance between RF_M and RFO terminals.
35 36 37
RFTC LD PD
I O I
This is a pin where the selection time constant is externally connected to control the RF level. APC amplifier output terminal. APC amplifier input terminal. RFI-V amplifier inverted input pin.
38, 39
PD1, PD2
I
These pins are connected to the A+C and B+C pins of the optical pickup, receiving by currents input.
40
FEBIAS
I/O
Bias adjustment pin of the focus error amplifier. F and EIV amplifier inverted input pins.
41, 42
F, E
I
These pins are connected to the F and E of the optical pickup, receiving by current input.
43 44 45 46 47 48 49 50 51 52
EI VEE TEO LPFI TEI ATSC TZC TDFCT VC FZC
-- -- O I I I I I O I
Gain adjustment pin of the I-V amplifier E. (When not in use of BAL automatic adjustment) GND connection pin. Output terminal for tacking-error amplifier. Output E-F signal. BAL adjustment comparator input pin. (Input through LPF from TEO) Input terminal for tracking error. Window-comparator input terminal for detecting ATSC. Input terminal for tracking-zero cross comparator. Capacitor connection pin for the time constant used when there is defect. Output terminal for DC voltage reduced to half of VCC+VEE. Input terminal for focus-zero cross comparator.
35
IC, CXD2540Q
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin Name FOK FSW MON MDP MDS LOCK NC VCOO VCOI TEST PDO VSS PWMI V16M VCTL VPCO VCKI FILO FILI PCO AVSS CLTV AVDD RF BIAS ASYI ASYO ASYE NC PSSL WDCK LRCK VDD DA16 DA15 DA14 DA13 DA12 I/O I O O O O O -- O I I O -- I O I O I O I O -- I -- I I I O I -- I O O -- O O O O O High, when sampled value of GFS at 460Hz is high. Low, when sampled value of GFS at 460Hz is low by 8 times successively. Not used. Analog EFM PLL oscillation circuit output. Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz. TEST pin. Analog EFM PLL charge pump output. GND. Spindle motor external control input. VCO2 oscillation output for the wide-band EFM PLL. VCO2 control voltage input for the wide-band EFM PLL. Wide-band EFM PLL charge pump output. VCO2 oscillation input for the wide-band EFM PLL. Multiplier PLL (slave=digital PLL) filter output. Multiplier PLL filter input. Multiplier PLL charge pump output. Analog GND. Multiplier VCO1 control voltage input. Analog power supply (5V). EFM signal input. Constant current input of the asymmetry circuit. Asymmetry comparator voltage input. EFM full-swing output. Low: asymmetry circuit off; high: asymmetry circuit on. Not used. Audio data output mode switching input. Low: serial output; high: parallel output. D/A interface for 48-bit slot. Word clock f=2Fs. D/A interface for 48-bit slot. LR clock f=Fs. Power supply (5V). DA16 (MSB) output when PSSL=1. 48-bit slot serial data (two's complement, MSB first) when PSSL=0. DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0. DA14 output when PSSL=1. 64-bit slot serial data (two's complement, LSB first) when PSSL=0. DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0. DA12 output when PSSL=1. 64-bit slot LR clock when PSSL=0. Description Focus OK input. Used for SENS output and the servo auto sequencer. Spindle motor output filter switching output. Spindle motor on/off control output. Spindle motor servo control.
36
Pin No. 39 40 41 42 43 44 45 46 47 48 49 50
Pin Name DA11 DA10 DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 APTR
I/O O O O O O O O O O O O O
Description DA11 output when PSSL=1. GTOP output when PSSL=0. DA10 output when PSSL=1. XUGF output when PSSL=0. DA09 output when PSSL=1. XPLCK output when PSSL=0. DA08 output when PSSL=1. GFS output when PSSL=0. DA07 output when PSSL=1. RFCK output when PSSL=0. DA06 output when PSSL=1. C2PO output when PSSL=0. DA05 output when PSSL=1. XRAOF output when PSSL=0. DA04 output when PSSL=1. MNT3 output when PSSL=0. DA03 output when PSSL=1. MNT2 output when PSSL=0. DA02 output when PSSL=1. MNT1 output when PSSL=0. DA01 output when PSSL=1. MNT0 output when PSSL=0. Aperture compensation control output. This pin outputs a high signal when the right channel is used.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
APTL VSS XTAI XTAO XTSL FSTT FSOF C16M MD2 DOUT EMPH WFCK SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT VDD CLOK SEIN CNIN
O -- I O I O O O I O O I O O I O I I -- I O O -- O I I
Aperture compensation control output. This pin outputs a high signal when the left channel is used. GND. Crystal oscillation circuit input. Crystal oscillation circuit output. Crystal selector input. 2/3 frequency divider output for Pins 53 and 54. 1/4 frequency divider output for Pins 53 and 54. 16.9344MHz output. (V16M output in CLV-W and CAV-W modes) Digital-out on/off control. High: on; low: off Digital-out output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. WFCK (write frame clock) output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. Sub Q 80-bit and PCM peak, level metter and internal status outputs. SQSO readout clock input. High: mute; low: release SENS output to CPU. System reset. Reset when low. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Power supply (5V). Serial data transfer clock input from CPU. SENS input from SSP. Track jump count signal input.
37
Pin No. 77 78 79 80
Pin Name DATO XLTO CLKO MIRR
I/O O O O I Serial data output to SSP.
Description
Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP. Mirror signal input. Used when the number of tracks is 128 or more for the 2N-track jump and M track move of the auto sequencer.
Notes) · The 64-bit slot is an LSB first, two's complement output, and the 48-bit slot is an MSB first, two's complement output. · GTOP is used to monitor the frame sync protection status. (High: sync protection window open.) · XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection. · XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. · GFS goes high when the frame sync and the insertion protection timing match. · RFCK is derived from the crystal accuracy, and has a cycle of 136µ. · C2PO represents the data error status. · XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
38
IC, SM5878M
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name MUTE DEEM CKO DVSS BCKI DI DVDD LRCI TSTN TO1 AVDDL LO AVSS RO AVDDR MUTEO XVDD XTI XTO XVSS DS RSTN MODE ATCK I/O I I O -- I I -- I I O -- O -- O -- O -- I O -- I I I I Description MODE = H: Soft mute ON/OFF terminal. (Mute at H). MODE = L: Attenuator level DOWN/UP terminal. (DOWN at H). De-emphasis ON/OFF terminal. (De-emphasis ON at H). Oscillator clock output. (16.9344 MHz). Digital VSS terminal. Bit clock input terminal. Serial data input terminal. Digital VDD terminal. Sample rate clock (fs) input terminal. (H = L ch/L = R ch). Test input. ("H" or open during normal operation) Test output 1. (Normally low level output). Analog VDD terminal. (For L ch). Left channel analog output terminal. Analog VSS terminal. Right channel analog output terminal. Analog VDD terminal. (For R ch). Infinity zero detection output. X'tal system VDD terminal. X'tal oscillator terminal. (Or external clock input terminal of 16.9344 MHz). X'tal oscillator terminal. X'tal system VSS terminal. Double-speed/normal playback selection. (Double-speed at H). Reset terminal. (Reset at L). Soft mute/Attenuator mode selection. (Soft mute at H). Attenuator level setup clock (Ignored when MODE = H).
39
IC, CXD1856R
Pin No. 1 Pin Name VSS I/O -- GND. Video decoder master clock. Input the clock signal to the XTL0I or connect an 2, 3 XTL0O, XTL0I O/I external oscillator between XTL0I and XTL 0O. The recommend frequency is 27 MHz, 28.3636 MHz (NTSC 8fs) or 65.4686 MHz (PAL 8fs). 4 VDD -- Power supply. This is the register address input terminal when the host interface is in the parallel 5, 6, 119, 120 HA0-HA3 I mode. HA0 is the serial data input terminal in the serial mode. HA1 to HA3 must be fixed to the "L" level during the serial mode. This is the register data input/output terminal when the host interface is in the parallel 7-13, 16 HD0-HD7 I/O mode. HA0 is the serial data output terminal in the serial mode. HD1 to HD7 must be fixed the "L" level during the serial mode. 14 15 17-21, 23, 24, 32, 33 22 25 MA0-MA8 O VDD VSS -- -- Power supply. GND. DRAM address signal output terminal. The DRAM address signal output terminal must be connected to the DRAM address terminal in the way that the terminal numbers match each other. VSS CKEY -- O GND. Chroma key signal terminal. This terminal goes to "L" while outputting the color that is specified as the key color. Set this terminal to OPEN when it is not used. Video data identification signal terminal. This terminal goes to "H" outputting the 26 DTVLD O picture of the frame memory. This terminal goes to "L" while outputting the border color or during blanking. Set this terminal to OPEN when it is not used. 27-29 30 31 34 PIN27-PIN29 PIN30 VSS XRAS -- -- -- O Not used. GND. GND.
_______
Description
Low address strobe signal output terminal. Connect this terminal to the DRAM RAS signal terminal.
______
35
XMWE
O
DRAM write enable signal output terminal. Connect this terminal to the DRAM WE signal terminal. Use this terminal when 8-Mbit DRAM is connected. Connect this terminal to the
_______
DRAM CAS signal terminal of the upper words (256K to 512K-1) side when the 36 XCAS2/MA9 O DRAM system consists of the two DRAMs * 256 * 16 bits (upper bite and lower bite are common). Connect this terminal to the MA9 terminal (common to the two DRAMs) when DRAM system consists of the two DRAMs * 512 Kw * 8 bits. This is the DRAM column address strobe signal output. Connect this terminal to the
_______
DRAM CAS signal terminal of the lower words (0 to 256 K-1) side when DRAM 37 XCAS0 O system consists of the two DRAMs * 256 Kw * 16 bits (upper bite and lower bite are
_______
common). Connect this terminal commonly to the DRAM CAS signal terminal in all connections other than the above described connection. 38-43, 4655 44 VDD -- MD0-MD15 I/O DRAM data signal input/output terminal. These terminals must be connected to the DRAM data terminals in the way that the terminal numbers match each other. Power supply.
40
Pin No. 45 56
Pin Name VSS OSDEN
I/O -- I GND.
Description
OSD enable signal terminal. Polarity to enable the OSD can be changed by setting the register. OSD data input terminal. The color that is registered in the color table and specified
57-59
OSDB, OSDG, OSDR
I
by the three inputs (3 bits), is output when the signal that is input to the OSDEN terminal is in the enable state.
60 61
VDD VSS
-- --
Power supply. GND. Video output enable signal terminal. When this terminal is set to "L", the picture data
62
XVOE
I
output and the DCLK output are enabled. When this terminal is set to "H", they are disabled (high impedance). In order to make the output enable, the setting of the output control register must also be set to the enable state.
63-70 71-73, 76-80 81-88 74 75
R/Cr0-R/Cr7 G/Y0-G/Y2, G/Y3-G/ Y7 B/Cb0-B/Cb7 VDD VSS
O O O -- -- Power supply. GND. Dot clock (DCLK) signal terminal. The DCLK frequency is normally 13.5 MHz. The Picture data output terminal. Output data formats (RGB, YCbCr) and correspondence between terminals and output data can be changed by the register setting.
89
DCLK
I/O
DCLK signal can be input from this terminal or can be output from this terminal after dividing-frequency of the clock input.
90 91
VDD VSS
-- --
Power supply. GND. Horizontal sync signal terminal. When the internal sync generator is used, the
92
HSYNC
I/O
horizontal sync signal that is obtained by frequency-dividing the dot clock (DCLK) is output. When the internal sync generator is not used, the external horizontal sync is input to this terminal. Vertical sync signal terminal. When the internal sync generator is used, the vertical
93
VSYNC
I/O
sync signal that is obtained by frequency-dividing the dot clock (DCLK) is output. When the internal sync generator is not used, the external vertical sync is input to this terminal. This terminal is used for the two signals of the field identification signal (FID) and the horizontal sync phase reference signal (FHREF). Use of this terminal is determined by the register setting. When set to FID, this terminal is used as output terminal when the internal sync generator is used, and is used as input terminal when the internal sync
94
FID/FHREF
I/O
generator is not used. "H" correspond to the odd fields. When this terminal is set to FHREF, the horizontal sync phase reference signal that is obtained by frequencydividing XTL0, is output. When XTL0 is 8 fsc, the signal that corresponds to H. SYNC cycle is generated that can be used for phase comparison with the H. SYNC signal.
41
Pin No.
Pin Name
I/O
Description This terminal is used for the two signals of the composite blanking signal (CBLNK) and the fsc signal. Use of this terminal is determined by the register setting. When
95
CBLNK/FSC
I/O
set to CBLNK, this terminal is used as output terminal when the internal sync generator is used, and is used as input terminal when the internal sync generator is not used. When set to fsc, the signal that is obtained by dividing-frequency of XTL0 is output. The dividing ratio of either 1/8 or 1/16 can be selected.
96
CSYNC
O I
Composite sync signal terminal. The composite sync signal is generated by frequencydividing the DCLK signal. This terminal cannot accept any inputs.
97
XSGRST
Sync signal generator reset signal input. The internal generator is initialized by setting this terminal to "L".
98 99 100 101 102 103 104 105
CLK0O DOUT DATO LRCO BCKO FSXI VDD VSS
O O O O O I -- --
The clock signal that is obtained by frequency-dividing XTL0 is output from this terminal. Dividing ratio of either 1, 1/2, 1/4 or 1/8 can be selected. Audio digital output terminal. Audio serial data output terminal to DAC. L/R clock output terminal to DAC. Bit clock output terminal to DAC. Clock input for audio interface. Input the 256fs (11.2896 MHz), 384fs (16.9344 MHz), 512fs (22.5792 MHz) or (33.8688 MHz) etc., to this terminal. Power supply. GND. Master clock terminal of the CD-ROM decoder and audio decoder. Either input the
106, 107
XTL2O, XTL2I
O/I
clock signal to XTL2I or connect an external oscillator between XTL2I and XTL2O. Recommended frequency is 45 MHz. This clock serves for internal circuit only, and is not synchronized with the input and output signals.
108 109
VDD C2PO
-- I
Power supply. This is the terminal to input the C2 pointer from CD-DSP. It indicates that the DATI input has an error.
110 111 112 113 114
LRCI DATI BCKI DOIN XHCS
I I I I I
This is the terminal to input the LR clock from CD-DSP. It indicates if it is L channel or R channel. This is the terminal to input the serial data from CD-DSP. This is the terminal to input the bit clock from CD-DSP. This is the clock to strobe the DATI input. This is the terminal to input the digital data from CD-DSP. This is the terminal of the chip select input signal during register access. This is the terminal to output the wait signal during register access. This terminal outputs the unique wait signal that is generated or not generated by the register, during
115
XHDT
I/O
DRAM access when the host interface is in the parallel mode. The pull up resistor is required since this terminal operates in the open drain configuration. Use the pull up resistor in the serial mode operation too.
____
116
HRW
I
This terminal receives the R/W input signal when the host interface is in the parallel mode. This terminal receives the serial clock input during the serial mode.
42
Pin No. 117
Pin Name XHIRQ
I/O O
Description This is the interrupt request signal output terminal. The pull up resistor is required since this terminal operates in the open drain configuration.
118
XRST
I
This is the hardware reset signal input terminal. All operations are initialized when this terminal is set to "L".
43
IC, RL5C293
Pin No. 1 2, 19, 39, 59 3 Pin Name VCOIN GND PALMODE I/O I/O -- I Description Charge pump output/VCO input terminal (Connect an external capacitor for loop filter, to this terminal). Digital ground. Video mode selection control terminal (LVTTL level). NTSC mode when PALMODE = 0. PAL mode when PALMODE = 1. Video sync mode selection control terminal (LVTTL level). Internal sync mode when MASTERB = 0. External sync mode when MASTERB = 1. However, when CDGMODE = 1, mode is fixed to the external sync mode regardless of MASTERB 4 MASTERB I status so that the MASTERB terminal functions the switch selecting either 262 (NTSC) or 312 (PAL) scanning line when MASTER B = 1, or 263 (NTSC or 313 (PAL) scanning line when MASTER B = 0, in the non-interlaced scanning. (See page 10) (This terminal has the pull-up function). 5 RESETB I Reset input terminal (LVTTL level). Enter the reset state when this terminal is set to "L". The data B input terminal (LVTTL level). Data input range is from 16 to 235, or from 6-13 B7-B0 I 0 to 255 (as controlled by the DICNT terminal) When FORM = 0, connect this terminal to ground. 14 TESTI0 I Test input terminal Enters the test mode when TESTI0 = 1. Connect this terminal to ground or set it open. Pixel clock input terminal (LVTTL level). When inputting the pixel clock, select the input pixel clock frequency that is appropriate for the respective modes. (See page 7.) 15 PXCLK I Frequency accuracy of the subcarrier signal of the video signal depends on that of this clock signal. Therefore, determine the frequency accuracy of the pixel clock according to the required accuracy of the subcarrier signal. 16, 30, 63 VCC -- Digital block power supply (+3.3 V or +5 V). Horizontal sync signal input/output terminal (LVTTL level). This terminal functions as the input terminal during the external sync mode, and as the output terminal during 17 HSYNCB I/O the internal sync mode. During the external sync mode, the input sync signal is sampled by PXCLK and only the fall-down edge is detected. The standard cycle of HSYNCB is 858 clock (VCD_NTSC) or 864 clock (VCD_PAL). (For CDG mode, see page 9.) This terminal functions as the output terminal during the internal sync mode. Vertical sync signal input/output terminal (LVTTL level). This terminal functions as the input terminal during the external sync mode, and as the output terminal during the internal sync mode. During the external sync mode, the input sync signal is sampled 18 VSYNCB I/O by PXCLK and the fall-down edge is detected. When the fall-down edges of HSYNCB and VSYNCB agree, the timing is judged to be the start of the ODD field. When they do not agree, the timing is judged to be the start of the EVEN field. This terminal functions as the output terminal during the internal sync mode. Input format selection terminal (LVTTL level). When FORM = 0, the input format is 20 FORM I CCIR-601YCbCr (4 : 2 : 2) . When FORM = 1, the input format is RGB input. (This terminal has the pull-up function).
44
Pin No.
Pin Name
I/O
Description Internal trap filter control terminal (LVTTL level). Trap filter display is disabled when
21
TRAPFEN
I
TRAPFEN = 0. Trap filter is enabled when TRAPFEN = 1. (This terminal has the pullup function). The G data or Y data input terminal (LVTTL level). The data input range is from 16 to
22-29
G7-G0
I
235 or from 0 to 255 in the case of the G data (as controlled by the DICNT terminal), and the data input range is from 16 to 235 in the case of the Y data. The R data or CbCr data input terminal (LVTTL level). The data input range is from
31-38
R7-R0
I
16 to 235 or from 0 to 255 in the case of the R data (as controlled by the DICNT terminal), and the data input range is from 16 to 240 in the case of the CbCr data.
40
CLKOUT
O
Clock output terminal Clock output of the doubled frequency of PXCLK when CLKMODE = 0. Clock output of 1/2 the frequency of PXCLK when CLKMODE = 1. Field indication signal output terminal Outputs "H" when the field is the ODD field.
41
FLDOUT
O
Outputs "L" when the field is the EVEN field. Polarity of the terminal becomes invalid during the external sync mode. Clock output terminal for OSD_IC The clock signal having 1/2 the frequency of the
42
OSDCLK
O
input PXCLK frequency is output when CLKMODE = 0. The clock signal having 1/4 the frequency of the input PXCLK frequency is output when CLKMODE = 1. (See page 6.) The video data input control terminal (LVTTL level). Set this terminal to DICNT = 0 normally. When DICNT = 1 is set, the data input range of RGB can be expanded to
43
DICNT
I
the range of 0 to 255 on the condition that FORM = 0. When FORM = 1, the Cb data can be input starting from the odd cycle. (See page 8.) (This terminal has the pull-up function).
44 45 46, 47, 50 48 49
SLEEP AVCC NC VIDEO IREF
I -- -- O --
The SLEEP mode control terminal (LVTTL level). Normal operation mode is selected when SLEEP = 0. The SLEEP mode is selected when SLEEP = 1. Analog block power supply (+5 V). Be sure to set this terminal to open. Analog video output terminal (This terminal is driven in 37.5 ). An external resistor is connected to this terminal, that sets the full scale output current value.
51 52, 53
COMP AGND
-- --
An external de-coupling capacitor is connected to this terminal, that is used for phase compensation. Analog ground. CDG_PAL4FSC mode selection control terminal. (LVTTL level). Status of this
54
PAL4FSC
I
PAL4FSC terminal is made valid only when PALMODE = 1 and CDGMODE = 1. The mode is the CDG_PAL908fH mode when PAL4FSC = 0. The mode is the CDG_PAL4FSC mode when PAL4FSC = 1. The input terminal to specify the OSD color. (LVTTL level). This input signal
55-57
OSD2-OSD0
I
sampled by PKCLK and is encoded instead of the data supplied from the RGB input terminal when VSW = 1. When the OSD function is not used, connect this terminal to ground.
45
Pin No.
Pin Name
I/O
Description The OSD background video control terminal. (LVTTL level). This input signal
58
VSW
I
sampled by PXCLK and displays the data that is supplied from the RGB input terminal when VSW = 0, and displays the data that is supplied from the OSCD 0-2 input terminal when VSW = 1. The CDG mode selection control terminal. (LVTTL level). The VCD mode is
60
CDGMODE
I
selected when CDGMODE = 0. The CDG mode is selected when CDGMODE = 1. (See page 9.) (This terminal has the pull-up function). The PAL60 mode selection control terminal. (LVTTL level). Set this terminal to
61
PAL60
I
PAL60 = 0 normally. The PAL60 mode is selected when PALMODE = 1 and PAL60 = 1 at the same time. The setting of PALMODE = 0 and PAL60 = 1 is reserved. (See page 9.) (This terminal has the pull-up function). The pixel rate frequency input selection terminal. (LVTTL level). The pixel rate
62
CLKMODE
I
frequency is input to the PXCLK terminal when CLKMODE = 0. The double pixel rate frequency is input to the PXCLK terminal when CLKMODE = 0. (See page 7.) (This terminal has the pull-up function).
64
PLLGND
--
PLL ground.
46
IC, CXP84548-112Q
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pin Name CLV-W HSTSTP VCD XRST XHRST HA0 HA1 HA2 HA3 HXCE HRW BUS HCLK HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 PH0 PICT HRST VRST PALMD PAL60 XHDT XHCS XRST EXTAL XTAL VSS PE6 PE7 AVSS AVREF OSDDT OSDXCS OSDCLK TRSRVO I/O I O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O I O I I O I/O O O -- -- O O O I Fixed to CLV-W: 1, CLV-N. Cause of STOP. 1: STOP by the stop request from the host. DISC type. 1: When no in the VCD DISC SSP/DSP reset output. Reset at "L". CXD1856 reset output. Reset at "L". Title back: Connected to CXD1856 HA0. Title back: Connected to CXD1856 HA1. Title back: Connected to CXD1856 HA2. Title back: Connected to CXD1856 HA3. Connected to title back ROM XCE. Connected to bus select DIR, CXD1586 HRW. Connected to bus select XG. Clock for address count. Title back bus data 0. Title back bus data 1. Title back bus data 2. Title back bus data 3. Title back bus data 4. Title back bus data 5. Title back bus data 6. Title back bus data 7. Not used. Title back bank select. (Connected to A16). Address counter RST output. RL5C293 reset output. Reset at "L". PAL mode output. NTSC: L, PAL: "H". PAL mode output. H: PAL60 (used together with PALMD: H) Connected to CXD1856 XHDH. Connected to CXD1856 XHCS. Reset input. External 12 MHz ceramic oscillator is connected to this terminal. External 12 MHz ceramic oscillator is connected to this terminal. Connected to ground. Not used. Not used. GND. 3.3 V power supply. OSD serial, data output. OSD serial, CS output. OSD serial, clock output. Tracking servo ON/OFF. 1: ON, 0: OFF. Description
47
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pin Name HALT LSW EMPH VMODE O-BUSY I-BUSY CLOCK COMMAND STATUS SQCK SQSO PB7/SO1 FOK GFS SENS2 SENS MD2 RBPLS VSYNC SCOR HIRQ CNIN CLOK P15 DATA XLAT AMUTE DMUTE VMUTE DEEM VDD NC PG4 PG5 PG6 PG7 SH AUTO DISP
I/O I I I I O I I I O O I O I I I I O O I I I I O O O O O O O O -- -- O O O O I I I
Description HALT input. 1: HALT detected (A/D conversion value is 80 H or higher). Pick up inside switch input. "L" when INSIDE is detected. Emphasis input. ON only (CD-DA) at "H". NTSC/PAL AUTO/PAL selection. (Analog input). Busy input to host microprocessor. Busy output from host microprocessor. Host microprocessor, clock input. Host microprocessor, data input. Host microprocessor, data output. Clock output for reading SQSO. Inputs such as SUBQ, PCM, DATA, level data, status and others. Not used. FOK input. GFS input. SENS 2 input. DSP SENS input. DSP DIGITAL OUT MUTE output. ON at "H". Tracking balance fraction data output. (A+B)/2. V. SYNC input. Subcode sync input. "H" during S0,S1 input. Connected to CXP1856 HIRQ. C input. Clock output to CD DSP. Not used. Data output to CD DSP. XLAT output to CD DSP. LINE OUT MUTE output. Mute at "H". DSP mute output. Mute at "H". RL5C293 sleep output. Normally "L" / Sleep at "H". Deemphasis output. Deemphasis ON at "H". 3.3 V power supply. Not used. Not used. Not used. Not used. Not used. Pick that is equipped with shutter. 1: With shutter. Auto adjustment YES/NO. 1: Auto adjustment YES. Auto adjustment value indication. 1: Indicated.
48
IC BLOCK DIAGRAM IC, TA7291S
STOP
BRAKE
: HI IMPEDANCE NOTE : INPUT "H" ACTIVE
PROTECTOR CIRCUIT (TSD)
IC, BA6897
49
IC, SN74LS245APW
IC, M5291FP
IC, BA5915
6.65K
6.65K
6.65K
6.65K
CH1 MUTE
T.S.D: Thermal shut-down Resistors are in units of .
50
IC, BU2874AFV
CYCLE DETECTOR CIRCUIT
HORIZONTAL TIMING COUNTER
BLUE-BACK VERTICAL TIMING COUNTER
VERTICAL TIMING COUNTER
COLOR / BURST PHASE SIGNAL GENERATOR
BLUE-BACK
HORIZONTAL
TIMING COUNTER
OSD
BLUE-BACK VIDEO OUTPUT SYNTHESIZER
OSD
V. SYNC SEPARATOR CIRCUIT
VIDEO SIGNAL ANALOG SWITCH CLAMP CIRCUIT
DIVIDER
1 / 448
CHARACTER HIGH-LIGHT DATA
RAM WRITE ADDRESS COUNTER
DATA SELECTOR
OSD, CHARACTER, BACKGROUND OUTPUT CONTROL
RAM
1BIT*288 WORDS
CHARACTER RAM
6BITS*288WORDS
COMPOSITE SYNC SEPARATOR CIRCUIT
CHARACTER GENERATOR ROM 12*18 BITS 256 WORDS
51
TEST MODE
< How to Enter the Test Mode >
While pressing the PROGRAM key, insert the AC power cord to AC wall outlet. Pressing the [E] key decreases the track number to -1. Pressing the [F] key increases the track number to +1. Pressing OPEN/CLOSE key opens or closes the tray. The machine enters the [Sled mode].
< When the Machine Has Entered the Test Mode >
The system is initialized and the main power is turned on. During the test mode, the main power of the CD block is turned on always. The test mode starts with the [Sled mode].
< How to Exit the Test Mode >
Remove the AC power cord from power outlet, or turn off the system power. The focus bias, tracking balance and the tracking gain adjustment values can be displayed, modified, set and released in the Play mode only of the following Test mode. When the PRGM button is pressed during Play, the adjustment value of the focus bias is displayed. After that, you can enter the followings: · FOCUS - BIAS [Display]: Pressing the RANDOM key during disc play, the focus bias setting value is displayed. [Adjustment]: Every pressing of the fi key decrements the adjustment value by 1 step. Every pressing of the fl key increments the adjustment value by 1 step. [Set]: The adjustment value is set by pressing the PLAY key after adjustment. Playback a disc after setting. [Release]: The set value can be released by pressing the STOP key. · TRACKING - BALANCE [Display]: Pressing the REPEAT key during disc play, the tracking balance setting value is displayed. [Adjustment]: The same procedure as in the FOCUS BIAS. [Set]: The same procedure as in the FOCUS - BIAS. [Release]: The same procedure as in the FOCUS - BIAS. · TRACKING - GAIN [Display]: Pressing the DISPLAY key during disc play, the tracking balance setting value is displayed. [Adjustment]: The same procedure as in the FOCUS BIAS. [Set]: The same procedure as in the FOCUS - BIAS. [Release]: The same procedure as in the FOCUS - BIAS.
< Types of Test Mode >
[Sled mode]
All displays of the FL tubes light. The optical pickup can be moved by pressing [E] or [F] key. Pressing the [9] key establishes the [Focus mode]. Pressing the [2] key establishes the [Play mode]. Pressing the [E] key moves the sled to outer circumference. Pressing the [F] key moves the sled to inner circumference. Pressing OPEN/CLOSE key opens or closes the tray.
[Focus mode]
Lighting of all displays of the FL tubes are turned off and returns to normal display. The focus search is performed in the focus mode regardless whether disc is inserted or not, or focus OK or NG. (Numbers of times of focus search is unlimited. Auto sequence is not used.) Focus servo is not locked in even the focus is obtained. Pressing the [2] key establishes the [Play mode]. Pressing the [E] key decreases the track number to -1. Pressing the [F] key increases the track number to +1. Pressing OPEN/CLOSE key opens or closes the tray. The machine enters the [Sled mode].
[Play mode]
Lighting of all displays of the FL tubes are turned off and returns to normal display. The focus search (numbers of search is unlimited) is performed. When focus comes to in-focus, the focus servo is locked in and the machines enters the normal play mode. During [Play mode], GFS and sound skipping are not monitored. When focus becomes out-of-focus, another attempt is made to search for focus. The tracking servo and the sled servo can be turned on and off by pressing the [2] key. Pressing the [9] key establishes the [Sled mode]. The [ || ] display can be turned on and off by pressing the [2] key . While the [ || ] display is turned off: CLV-A Tracking servo: on Sled servo: on While the [ || ] display is turned on: CLV-A Tracking servo: off Sled servo: off
Display method
8 8 8-8 8: 8 8
· FOCUS - BIAS
F 8-8 8 8 L-8 8 G A-8 8
·
TRACKING - BALANCE
·
TRACKING - GAIN
52
1. How to Activate CD Test Mode Insert the AC plug while pressing the function CD button. FL display tubes will show the "start mode" display (repeating the indications "TEST" and "00 00 00" alternately), and the test mode will be activated.
2. How to Cancel CD Test Mode Either one of the following operations will cancel the CD test mode. · Press the function button. · Press the power switch button. (except CD function button) · Disconnect the AC plug
3. Description of the CD Test Mode Functions When test mode is activated, the following mode functions from No. 1 to No. 4 can be used by pressing the operation keys. [Values of Focus Balance, Tracking Balance and Tracking Gain] The displayed contents show the actual value after flashing three times. Mode/No. Start mode No.1 Search mode Operation Activation 9 key FL display Start mode display Operation Test mode is activated. CD block power is ON. Laser diode turns always ON. Continual focus search (The pickup lens repeats the fullswing up-down motion.) * Avoid continual searches that last for more than 10 minutes. · · · · Contents · Automatic adjustment value
"CD "
No.2 Play mode No.3 Sled mode
1 2 key
Normal display
fi key fl
Start mode display
No.4
· APC circuit check · Laser current measurement (Laser current control. Across a resistor connected between emitter and GND.) FOCUS SERVO · Check focus search waveform · Check focus error waveform (FOK/FZC are not monitored in the search mode) * NOTE 1 FOCUS SERVO/TRACKING SERVO · Normal playback CLV SERVO/SLED SERVO Check DRF · Pickup moves to the outermost track SLED SERVO · Pickup moves to the innermost track Check SLED mechanism operation * NOTE 2 (During playback, machine operates normally.)
* NOTE 1: There are cases when the tracking servo cannot be locked owing to the protection circuit being operated when heat builds up in the driver IC if the focus search is operated continually for more than 10 minutes. In these cases the power supply should be switched off for 10 minutes until heat has been reduced and then re-started. * NOTE 2: When pressing the fi or fl keys, take care to avoid damage to the gears. Because the sled motor is activated when the fi or fl keys are pressed, even when the pick-up is at the outermost or innermost track. * NOTE 3: The machine cannot enter the traverse mode even though the PAUSE button is pressed during PLAY. It enters the normal PAUSE state. 4. Operation Outline The operation of each mode is carried out in the direction of the arrows from the start mode as indicated in the following illustration.
No. 2 Search mode
1 2
No. 3 Play mode
9 9
2 No. 1 Start mode (All FLs light up.)
fi fl 1 2
9
No. 4 Sled mode If the DISC DIRECT PLAY button is pressed, the machine performs the same operation as the PLAY button is pressed as shown. If the tray is opened by pressing OPEN/CLOSE button during Play mode or Traverse mode, the machine returns to the Start mode.
53
1. How to Activate CD Test Mode Insert the AC plug while pressing the function CD button. FL display tubes will show the "start mode" display (repeating the indications "TEST" and "00 00 00" alternately), and the test mode will be activated.
2. How to Cancel CD Test Mode Either one of the following operations will cancel the CD test mode. · Press the function button. · Press the power switch