Text preview for : Schematic Diagram.pdf part of SAMSUNG Q320 Repair Manual
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THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4 3 2
1
D
D
MIAMI-EXT
CPU :Intel Penryn Chip Set :Intel Cantiga & ICH9M Remarks : Montevina Platform Model Name PBA Name PCB Code Dev. Step Revision T.R. Date MIAMI-EXT MAIN BA41-xxxxxA PR 1.0 2009.2.10 : : : : : :
C
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
B
Design
CHECK
APPROVAL
g un al ms nti Sa de nfi Co
DRAW DATE TITLE
C
B
A
SE LEE
CHECK DEV. STEP
A
9/19/2008 SE LEE ADV1
MIAMI-EXT
SAMSUNG Owner : SEC Mobile R & D
4
MAIN
ELECTRONICS
Signature :
3
X
2
APPROVAL
REV
ES CHO
MODULE CODE LAST EDIT
rev 1.0
COVER
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
1
OF
61
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8-1
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
3
2
1
FAN
Clocking
PG 19
Mobile Processor
Penryn-6M FSB 1067
478pin PG 20,21,22 L2 Cache : 6/3MB FSB 800/1067 MT/S
CPU DC/DC
IMVP-6
D
PG 18 (TBD) PG 19
CK-505
Charging Circuit
Smart Battery Module ON BOARD
Termination PG 28,29
DC/DC
CPU Thermistor
D
VCCP / DC-DC
PG 69 Channel A (Standard) DDR II 667/800
HDMI Ext. PEG
PEG x16
PG 57 PG 57 CRT PG 56 LCD
LCD
N10M-GE1
CRT
C
- - This Document can not be used without Samsung's authorization -
PG 52,53 ANT
USB 0,2,6
8. Block Diagram and Schematic
PG 61
Bluetooth
PG 63
Camera
High Definition Audio
PG 43
HDAUDIO
AMP
PG 42
Aud.
Audio ALC272
RJ11 PG 54
B
PG 45
MDC Modem
LPC
HP MIC-IN
2P 2P
PG 43
PG 35
SPI ROM
PG 50 PG 51
SATA HDD SATA ODD
SPKR
R
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
MCH-M Cantiga-PM
Dual channel
DDR II PG 28 SODIMM 0
External Graphics
PM45
Channel B (Reverse)
DDR II 667/800
DDR II PG 29 SODIMM 1
DDR II Power
PG 72
1329 FCBGA
PG 23 -27
Direct Media Interface x4, 1.5V
CLINK
C
USB 0,2,6
PCIE x1
Lane 4
8057
RJ45 PG 47 USB 5 Lane 1
PCIE x1
52P
OPTION
USB 8
ICH9-M
ANT USB 1 PG 12
Mini Card 1
676 BGA
PCIE x1
Lane 2
52P
HD Audio
USB 3
Mini Card 2
PG 30 - 34
PG 13
HD Audio
12P
PCIE x1
Lane 3
USB 7
Express Card
HD Audio
PG 14
PG 54
B
SPI USB 4
3 IN 1
SD(SDHC)
PG 15
AU6336
MMC
PG 15
PG 15
SATA 0
SATA 1
3.3V LPC, 33MHz
MICOM
Touch PAD
PG 62
PG 49
H8S-2110B TMKBC (TBD)
SPKR L
KBD
PG 60
80 Port
A
PG 55
LED
PG 64
DRAW DATE TITLE
A
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0 undefined
MAIN
ELECTRONICS
BLOCK DIAGRAM
PART NO.
BA41-#####A
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SAMSUNG PROPRIETARY
4
3
2
1
D
THERMAL SENSOR & FAN CONTROL
D
C726
10000nF-X5R 6.3V 100nF 10V 100nF 10V
C
KBC3_PWRGD
FAN5_VDD FAN3_FDBACK#
- - This Document can not be used without Samsung's authorization -
SHDN_SEL MODE 0 HIGH Z CH3(DIODE MODE) N/A (SHDN# NOT USED) CH1(INTEL MODE) R1
CPU3_THRMTRIP# P3.3V_AUX
8. Block Diagram and Schematic
1
B
TRIP_SET pin voltage = (T-75)/21 3.3 * [R2/(R1+R2)] = (T-75)/21
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
P5.0V P3.3V_AUX P3.3V P3.3V_AUX
10K 1% 10K 1% 10K 1%
nostuff
49.9 1%
10K 1%
R655
Check if PU is doubled to Micom Side.
C725
C728
R671 R672 R650
1 24 27 14 16
U511 EMC2102
VDD_3V VDD_5V_1 VDD_5V_2
SMDATA SMCLK
22 23
R651
10000nF-X5R 6.3V
C727
KBC3_THERM_SMDATA KBC3_THERM_SMCLK
C
POWER_OK RESET# ALERT# SYS_SHDN# 19 12
THM3_ALERT# THM3_STP#
10 25 26 28
FAN_MODE FAN_1 FAN_2 TACH
DN1 DP1
2 3
DN2 DP2
4 5
0.47nF 50V
C700
CPU2_THERMDC
13
THERMTRIP#
R654
0
nostuff
9 11
SHDN_SEL TRIP_SET
DN3 DP3
6 7
2.2nF
C701
CPU2_THERMDA GFX3_THERMDN
For Intel 45nm(From penryn)
50V
GFX3_THERMDP
10mil width and 10mil spacing.
2
R653
200K 1%
8 15 21
NC_1 NC_2 NC_3
CLK_SEL CLK_IN
17 18
C699
GND THRM_PAD
20 29
2.2nF 50V
1
3
MMBT3904 Q525
1209-001718
Opposite side of CPU.
R2
R652
51.1K 1%
SMBUS Address 7Ah
93 degree C
R635
20K 1%
For Nvidia NP9M/P(Nvidia Feedback) It could be changed by 3rd vendor recommand value.
B
P3.3V
R14 FAN5_VDD
Line Width = 20 mil
10K 1%
J2 HDR-4P-1R-SMD P1.05V FAN3_FDBACK#
R676
2K 1%
10000nF-X5R 6.3V
C8
5 6
1 2 3 4 MNT1 MNT2
CPU3_THRMTRIP#
3711-000456
A
CPU1_THRMTRIP#
nostuff nostuff
3 1 2
Q524 MMBT3904
DESIGN DATE TITLE
A
SE LEE 9/19/2008
GFX3_THERM#
R673
0
CHECK
DEV. STEP
MIAMI-EXT
SE LEE ADV1
SAMSUNG
nostuff
APPROVAL REV
THERMAL SENSOR
ES CHO
MODULE CODE LAST EDIT
ELECTRONICS
rev 1.0
THERMAL SENSOR EMC2102
PART NO.
BA41-#####A
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SAMSUNG PROPRIETARY
4 3
2
1
D
P1.05V
D
PENRYN
CPU1_A#(16:3) 3 4 5 6 7 8 9 10 11 12 13 14 15 16
J3-1
56
C
CPU1_ADSTB0# CPU1_A#(35:17) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# 0 ADDR GROUP BR0# F1 DEFER# DRDY# DBSY# CONTROL IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM# G6 E4 C1 F3 F4 G3 G2 H4 D20 B3 H5 F21 E1 ADS# BNR# BPRI#
CPU1_INIT#
1/4 H1 E2 G5
CPU1_ADS# CPU1_BNR# CPU1_BPRI#
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
CPU1_ADSTB1#
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# 1 ADDR GROUP A20M# FERR# IGNNE# ICH STPCLK# LINT0 LINT1 SMI# REQ0# REQ1# REQ2# REQ3# REQ4#
0143854500|bga_479p_sock
B
MT16 RMNT-38-50-1P
MT17 MT18 RMNT-38-50-1P RMNT-38-50-1P
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
J3-2 PENRYN
CPU1_D#(15:0) CPU1_BREQ#
R734
DATA GRP 0
DATA GRP 2
CPU1_DEFER# CPU1_DRDY# CPU1_DBSY#
CPU1_LOCK#
CPU1_CPURST# CPU1_RS0# CPU1_RS1# CPU1_RS2# CPU1_TRDY#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CPU1_DSTBN0# CPU1_DSTBP0# CPU1_DBI0# CPU1_D#(31:16)
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
2/4
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
CPU1_D#(47:32)
C
CPU1_HIT# CPU1_HITM#
A6 A5 C4
CPU1_A20M# CPU1_FERR# CPU1_IGNNE#
DATA GRP 1
K3 H2 K2 J3 L1
0 1 2 3 4
CPU1_STPCLK# CPU1_INTR CPU1_NMI CPU1_SMI# CPU1_REQ#(4:0)
DATA GRP 3
D5 C6 B4 A3
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CPU1_DSTBN1# CPU1_DSTBP1# CPU1_DBI1#
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3#
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
CPU1_DSTBN2# CPU1_DSTBP2# CPU1_DBI2# CPU1_D#(63:48)
CPU1_DSTBN3# CPU1_DSTBP3# CPU1_DBI3#
0143854500|bga_479p_sock
B
MT19 RMNT-38-50-1P
A
DRAW DATE TITLE
A
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0 undefined
CPU
ELECTRONICS
PENRYN (1/3)
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
9 4 3 2
OF
61
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
1
8-4
Q320
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
3
2
1
D
H CLK
CLK0_HCLK0 CLK0_HCLK0#
BCLK0 BCLK1 SLP# DPSLP# DPRSTP# DPWR# PWRGOOD PSI# VID_6 VID_5 VID_4 VID_3 VID_2 VID_1 VID_0 VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7 VCCP_8 VCCP_9 VCCP_10 VCCP_11 VCCP_12 VCCP_13 VCCP_14 VCCP_15 VCCP_16 K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21 VCCA_1 VCCA_2
A22 A21 D7 B5 E5 D24 D6 AE6
10nF 25V
J3-3 PENRYN 3/4
P1.5V
B26 C26
CPU Core Voltage Table
C844
10000nF 6.3V
D
IMVP-6
C845
Active Mode
VID(6:0) Voltage
Active/Deeper Sleep Dual Mode Region
VID(6:0) Voltage 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.5000 V 1.4875 V 1.4750 V 1.4625 V 1.4500 V 1.4375 V 1.4250 V 1.4125 V 1.4000 V 1.3875 V 1.3750 V 1.3625 V 1.3500 V 1.3375 V 1.3250 V 1.3125 V 1.3000 V 1.2875 V 1.2750 V 1.2625 V 1.2500 V 1.2375 V 1.2250 V 1.2125 V 1.2000 V 1.1875 V 1.1750 V 1.1625 V 1.1500 V 1.1375 V 1.1250 V 1.1125 V 1.1000 V 1.0875 V 1.0750 V 1.0625 V 1.0500 V 1.0375 V 1.0250 V 1.0125 V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.0000 V 0.9875 V 0.9750 V 0.9625 V 0.9500 V 0.9375 V 0.9250 V 0.9125 V 0.9000 V 0.8875 V 0.8750 V 0.8625 V 0.8500 V 0.8375 V 0.8250 V 0.8125 V 0.8000 V 0.7875 V 0.7750 V 0.7625 V 0.7500 V 0.7375 V 0.7250 V 0.7125 V 0.7000 V 0.6875 V 0.6750 V 0.6625 V 0.6500 V 0.6375 V 0.6250 V 0.6125 V 0.6000 V 0.5875 V 0.5750 V 0.5625 V 0.5500 V 0.5375 V 0.5250 V 0.5125 V 0.5000 V
Deeper Sleep/Extended Deeper Sleep Dual Mode Region
CPU1_SLP# CPU1_DPSLP# CPU1_DPRSTP# CPU1_DPWR# CPU1_PWRGDCPU CPU1_PSI# CPU1_VID(6:0) P1.05V R733
56 5%
2.5V AD 6 5 4 3 2 1 0
AE2 AF3 AE3 AF4 AE5 AF5 AD6
P1.05V R251
1K 1% AD26 GTLREF COMP3 COMP2 COMP1 COMP0 VCCSENSE VSSSENSE TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7
0143854500|bga_479p_sock
CPU1_BSEL2 CPU1_BSEL1 CPU1_BSEL0
BSEL2 BSEL1 BSEL0 TCK TDI TDO TMS TRST# DBR# AC5 AA6 AB3 AB5 AB6 C20
XDP/ITP SIGNALS
C
C21 B23 B22
CPU2_THERMDA CPU2_THERMDC CPU1_THRMTRIP#
PREQ# PRDY# BPM3# BPM2# BPM1# BPM0# AC1 AC2 AC4 AD1 AD3 AD4
THERMAL
D21 A24 B25 C7 PROCHOT# THRMDA THRMDC THERMTRIP#
R658
2K 1%
R675 R674 R682 R681
54.9 27.4 54.9 27.4 1% 1% 1% 1% Y1 AA1 U26 R26 AF7 AE7 C23 D25 C24 AF26 AF1 A26 C3 RSVD RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 M4 N5 T2 V3 B2 D2 D22 D3 F6
- - This Document can not be used without Samsung's authorization -
CPU1_VCCSENSE CPU1_VSSSENSE
8. Block Diagram and Schematic
B
P1.05V
near the CPU
BSEL
CPU1_TDI CPU1_TMS FSB 1067 MHz FSB 800 MHz CPU1_TCK CPU1_TRST#
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
P1.05V EC512 220uF C784
100nF 10V
VID(6:0)
Voltage
C783
100nF 10V
C729
100nF 10V
C730
100nF 10V
C731
100nF 10V
100nF 10V
C785
CPU1_TCK CPU1_TDI
CPU1_TMS CPU1_TRST# ITP3_DBRESET#
Active DPRSLPVR 0 1 DPRSTP* 0 or 1 PSI2*
Deeper Slp DPRSLPVR 1 0 DPRSTP* 0 or 1 PSI2*
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0.4875 V 0.4750 V 0.4625 V 0.4500 V 0.4375 V 0.4250 V 0.4125 V 0.4000 V 0.3875 V 0.3750 V 0.3625 V 0.3500 V 0.3375 V 0.3250 V 0.3125 V 0.3000 V 0.2875 V 0.2750 V 0.2625 V 0.2500 V 0.2375 V 0.2250 V 0.2125 V 0.2000 V 0.1875 V 0.1750 V 0.1625 V 0.1500 V 0.1375 V 0.1250 V 0.1125 V 0.1000 V 0.0875 V 0.0750 V 0.0625 V 0.0500 V 0.0375 V 0.0250 V 0.0125 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V
C
nostuff nostuff
R735 R701
1K 1K
1% 1%
*"1111111" : 0V power good asserted.
54.9 1%
*Yonah Processor (2.33 GHz / 800 MHz : TBD) GTLREF : Keep the Voltage divider within 0.5" of the first GTLREF0 pin with Zo=55ohm trace. Minimize coupling of any switching signals to this net.
R679
R680
54.9
COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm) trace shorter than 1/2" to their respective Banias socket pins. Pull-down
BSEL0, BSEL1, BSEL2 BSEL0, BSEL2
54.9 1% 54.9
GND test points within 100mil of the VCC/VSSsense at the end of the line. Route the VCC/VSSsense as a Zo=55ohm traces with equal length. Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away (preferred 50mil) from any other signal. And GND via 100mil away from each of the VCC/VSS test point vias.
A
R678 R677
A
DRAW DATE TITLE
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0 undefined
CPU
ELECTRONICS
PENRYN (2/3)
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
10 4 3 2
OF
61
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
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Q320
8-5
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
3
2
1
VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141
K23 K26 K4 L21 L24 L3 L6 M2 M22 M25 M5 N1 N23 N26 N4 P21 P24 P3 P6 R2 R22
D
D
C
CPU1_VCCSENSE
R657
100 1%
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
CPU1_VSSSENSE
R656
100
Due to Prodizer
B
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
CPU_CORE
1% A10 A12 A13 A15 A17 A18 A20 A7 A9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AA7 AA9 AB10 AB12 AB14 AB15 AB17 AB18 AB20 AB7 AB9 AC10 AC12 AC13 AC15 AC17 AC18 AC7 AC9 AD10 AD12 AD14 AD15 AD17 AD18 AD7 AD9 AE10 AE12 AE13 AE15 AE17 AE18 AE20
6.3V 6.3V 22000nF-X5R
Y6 Y3 Y24 Y21 W4 W26 W23 W1 V5 V25 V22 V2 U6 U3 U24 U21 T4 T26 T23 T1 R5 R25
VSS_163 VSS_162 VSS_161 VSS_160 VSS_159 VSS_158 VSS_157 VSS_156 VSS_155 VSS_154 VSS_153 VSS_152 VSS_151 VSS_150 VSS_149 VSS_148 VSS_147 VSS_146 VSS_145 VSS_144 VSS_143 VSS_142
A11 A14 A16 A19 A2 A23 A25 A4 A8 AA11 AA14 AA16 AA19 AA2 AA22 AA25 AA5 AA8 AB1 AB11 AB13 AB16 AB19 AB26 AB4 AB8 AC11 AC14 AC16 AC19 AC21 AC24 AC3 AC6 AC8 AD11 AD13 AD16 AD19 AD2 AD22 AB23 AD25 AD5 AD8 AE1 AE11 AE14 AE16 AE19 AE23 AE26 AE4 AE8 AF11 AF13 AF16 AF19 AF2 AF21
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60
CPU_CORE
CPU_CORE
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 AE9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 AF9 B10 B12 B14 B15 B17 B18 B20 B7 B9 C10 C12 C13 C15 C17 C18 C9 D10 D12 D14 D15 D17 D18 D9 E10 E12 E13 E15 E17 E18 E20 E7 E9 F10 F12 F14 F15 F17 F18 F20 F7 F9
J3-4
PENRYN
4/4
22000nF-X5R
VSS_120 VSS_119 VSS_118 VSS_117 VSS_116 VSS_115 VSS_114 VSS_113 VSS_112 VSS_111 VSS_110 VSS_109 VSS_108 VSS_107 VSS_106 VSS_105 VSS_104 VSS_103 VSS_102 VSS_101 VSS_100 VSS_99 VSS_98 VSS_97 VSS_96 VSS_95 VSS_94 VSS_93 VSS_92 VSS_91 VSS_90 VSS_89 VSS_88 VSS_87 VSS_86 VSS_85 VSS_84 VSS_83 VSS_82 VSS_81 VSS_80 VSS_79 VSS_78 VSS_77 VSS_76 VSS_75 VSS_74 VSS_73 VSS_72 VSS_71 VSS_70 VSS_69 VSS_68 VSS_67 VSS_66 VSS_65 VSS_64 VSS_63 VSS_62 VSS_61 20%
K1 J5 J25 J22 J2 H6 H3 H24 H21 G4 G26 G23 G1 F8 F5 F25 F22 F2 F19 F16 F13 F11 E8 E6 E3 E24 E21 E19 E16 E14 E11 D8 D4 D26 D23 D19 D16 D13 D11 D1 C8 C5 C25 C22 C2 C19 C16 C14 C11 B8 B6 B24 B21 B19 B16 B13 B11 AF8 AF6 AF25
C
20%
C702
C703
B
0143854500|bga_479p_sock
A
DRAW DATE TITLE
A
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0 undefined
CPU
ELECTRONICS
PENRYN (3/3)
PART NO.
BA41-#####A
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THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
3
2
1
CK505M
P3.3V BLM18PG181SN1 nostuff P1.5V P3.3V B23 BLM18PG181SN1 BLM18PG181SN1 B16 B22 VDD_SRC_IO
10000nF-X5R 10000nF-X5R 10000nF-X5R 10000nF-X5R 10V 10V 10V 10V 10V 10V
D
FSA FSB HOST CLK 266 MHz 333 MHz 200 MHz 400 MHz 133 MHz 100 MHz 166 MHz RSVD
VDD_CPU_IO VDD_PLL3_IO VDD_IO
6.3V 6.3V 6.3V 6.3V
100nF 100nF 100nF 100nF 100nF 100nF
FSC 0 1 0 1 0 1 0 1
C144 C143 C97 C80 C96 C78 C145 C99 C77 C81
D
BSEL0 BSEL1 BSEL2
C141
C79
C95
C76
C98
C94
P3.3V
1%
1%
1%
C
10K 10K 10K
U6 SLG8SP513 nostuff
C142
C93
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
R59
R74
R55
CLK3_FM48 CLK3_USB48 CPU1_BSEL0 CPU1_BSEL1 CPU1_BSEL2 R79
10K 33 1% 1%
R60 R58
33 33 2.2K 1% 1%
R61
- - This Document can not be used without Samsung's authorization -
CLK3_ICH14
R80
8. Block Diagram and Schematic
CHP3_CPUSTP# CHP3_PCISTP# CLK3_PWRGD CLK3_PCLKICH CLK3_DBGLPC R81 R76 R78 R75
22.6
R116
0 22.6 1% 1%
R56
CLK3_PCLKMICOM
22.6 475 475
1% 1% 1%
B
MCH3_CLKREQ# CHP3_SATACLKREQ# SMB3_CLK SMB3_DATA
0.012nF
0.012nF
THERM_GND
14.31818MHz C90 C139
0.018nF
50V
nostuff
50V
50V
0.5pF
0.01nF
50V
Change SMB3 CLK/DATA TO SMB3_CLK/DATA_M in AMT system
10K
10K
10K
Y1
1 2
0.018nF 50V
CLK REQ CLK REQ A CLK REQ B
DEVICE SATA GMCH MINI CARD EXP3_CLKREQ# Pin 20/21
SRC PORT SRC2 SRC4 SRC6 SRC8 Pin 24/25 Place 14.318MHz within 500mils of CK-505
TME : OVER CLOCKING ENABLE
A
CLK REQ E CLK REQ F SEL_LCDCLK* LOW HIGH
This part is 64pin QFN package.
DRAW DATE TITLE
65
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
4700nF-X5R
10V 10V 10V 100nF 100nF
VDD_REF
VDD_48
VDD_PCI
VDD_PLL3 VDD_SRC VDD_CPU
10V 10V
100nF
100nF
100nF
100nF
4700nF-X5R
10V
10V
10V
C
19 33 43 52 56 27 VDD_IO VDD_SRC_IO1 VDD_SRC_IO2 VDD_SRC_IO3 VDD_CPU_IO VDD_PLL3_IO VDD_REF VDD_48 VDD_PCI VDD_PLL3 4 16 9 23
nostuff
55
NC
VDD_SRC VDD_CPU
46 62
17 64 5
USB_FS_A FSB_TESTMODE REF_FS_C_TEST_SEL
CPU0 CPU0#
61 60
CLK0_HCLK0 CLK0_HCLK0#
44 45 CPU1_MCH CPU1_MCH# 58 57
CPUSTOP# PCISTOP#
CLK0_HCLK1 CLK0_HCLK1#
63 SRC11_CLKREQH# SRC11#_CLKREQG# 40 39
CLKPWRGD_PWRDN#
ITM3_CLKREQ# LOM3_CLKREQ#
14 PCIF_5_ITP_EN SRC10 SRC10# 41 42
CLK1_MINIPCIE2 CLK1_MINIPCIE2#
13 PCI_4_SEL_LCDCLK# 12 SRC9 SRC9# 37 38
PCI_3
CLK1_PCIELOM CLK1_PCIELOM#
11 PCI_2 SRC8_ITP SRC8#_ITP# 54 53
CLK1_EXPCARD CLK1_EXPCARD#
10 PCI_1_CLKREQ_B# 8 SRC7_CLKREQF# SRC7#_CLKREQE# 51 50
PCI_0_CLKREQ_A#
EXP3_CLKREQ# MIN3_CLKREQ#
7 6 SCL SDA SRC6 SRC6# 48 47
B
CLK1_MINIPCIE CLK1_MINIPCIE#
3 2 XTAL_IN XTAL_OUT SRC4 SRC4# 34 35
nostuff
CLK1_MCH3GPLL CLK1_MCH3GPLL#
18 59 22 15 26 1 30 36 49 VSS_48 VSS_CPU VSS_IO VSS_PCI VSS_PLL3 VSS_REF VSS_SRC1 VSS_SRC2 VSS_SRC3
C91
C75
C92
SRC3_CLKREQC# SRC3#_CLKREQD#
31 32
1%
1%
1%
CLK1_PCIEICH CLK1_PCIEICH#
SRC2 SRC2# 28 29
CLK1_SATA CLK1_SATA# R77 R73 R57
LCDCLK_27M LCDCLK#_27M_SS 24 25
R62 R63
0 0
CLK3_GFX_27M CLK3_GFX_27M_SS
SRC0_DOT96 SRC0#_DOT96# 20 21
CLK1_PEG CLK1_PEG#
1205-003156
A
SE LEE
CHECK DEV. STEP
9/19/2008
MIAMI-EXT
DOT_96/DOT_96# SRC_0/SRC_0# PEG_CLK/PEG_CLK# 27M & 27M_SS
APPROVAL
SAMSUNG
SE LEE
REV
ADV1 ES CHO
MODULE CODE LAST EDIT
MAIN_CLOCK_CIRCUIT
rev 1.0 undefined
ELECTRONICS
CK_CLOCK_505M
PART NO.
BA41-#####A
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2.5V AD
20% 6.3V
SAMSUNG PROPRIETARY
P1.05V EC513 C714 220uF 22000nF-X5R C739
220nF 10V
4
3
2
P1.05V
1
C736
220nF 10V 100nF 10V
C711 C29
470nF 16V
C28
2200nF 10V
4700nF-X5R 4700nF-X5R 10V 10V
C27
C26
EC5 220uF
2.5V AD
AA28 AA33 AA34 AB34 AC26 AC28 AC33 AC34 AE26 AE33 AF23 AF25 AF28 AF33 AG24 AG25 AG26 AG33 AG34 AH23 AH25 AH28 AJ23 AJ26 AJ33 AK33 AM33 T32 U33 U34 V33 V34 W33 Y33 Y34
T10 T11 T12 T13 T2 T5 T6 T7 T8 T9 U1 U10 U11 U12 U13 U2 U3 U5 U6 U7 U8 U9 V1 V2 V3
D
CPU1_D#(63:0)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
CPU1_A#(35:3)
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25
P1.05V R704
221 1%
MCH1_HXSWING
100nF 10V
R705
100 1%
C787
C
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
P1.05V R736
1K 1%
MCH1_HVREF
R737
2K 1%
B
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 HOST DATA BUS
VCC CORE
VTT
CPU1_CPURST#
1nF 50V
CPU1_SLP# C1028
0.1nF 50V
C12 E11
C1029 MCH1_HXSWING MCH1_HVREF
For ESD
R702
C5 E3 24.9 1%
1608
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44
B11 A11
16V 16V 16V
C847 C735 C786
CFG#
A
CFG(5) CFG(6) CFG(7) CFG(9) CFG(10) CFG(16) CFG(19) CFG(20)
Current Setting (def. : default Option) High Low DMIx2 DMIx4 (def.) iTPM Host Interface Enable iTPM Host Interface Disable (def.) ME Crypto no confidentiality ME Crypto confidentiality (def.) PEG Reversal (def.) Normal PCIE Loop Back Disable(def) PCIE Loop Back Enable Dynamic ODT Disabled Dynamic ODT Enabled (def.) DMI Lane Normal (def.) DMI Lane Reversal SDVO or PCIE X1 SDVO and PCIE X1 Simultaneously Only(def.)
AA29 AA30 AA32 AB30 AC29 AC30 AC32 AE29 AE30 AE32 AF30 AG29 AG30 AG32 AH29 AH30 AH32 AJ29 AJ32 AK23 AK24 AK25 AK26 AK28 AK29 AK30 AK32 AL26 AL28 AL29 AL30 AL32 AM30 AM32 U30 U32 V29 V30 W29 W30 W32 Y29 Y30 Y32
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
*POCAFEB-12 Only (Remove in MP Model)
470nF 470nF 470nF
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
A8 AB2 L1
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
U2-1 EB88CTPM 1 OF 5
HOST ADDRESS BUS
0904-002376
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
D
C
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ#
H12 B16 G17 A9 F11 G12
CPU1_ADS# CPU1_ADSTB0# CPU1_ADSTB1# CPU1_BNR# CPU1_BPRI# CPU1_BREQ#
H_DEFER# H_DBSY# H_DPWR# H_DRDY#
E9 B10 J11 F9
CPU1_DEFER# CPU1_DBSY# CPU1_DPWR# CPU1_DRDY#
H_HIT# H_HITM# H_LOCK# H_TRDY# HOST CONTROL
H9 E12 H11 C9
CPU1_HIT# CPU1_HITM# CPU1_LOCK# CPU1_TRDY#
HPLL_CLK HPLL_CLK#
AH7 AH6
CLK0_HCLK1 CLK0_HCLK1#
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
J8 L3 Y13 Y1
CPU1_DBI0# CPU1_DBI1# CPU1_DBI2# CPU1_DBI3#
B
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
L10 M7 AA5 AE6
CPU1_DSTBN0# CPU1_DSTBN1# CPU1_DSTBN2# CPU1_DSTBN3#
H_CPURST# H_CPUSLP#
CFG
NC
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_SWING H_RCOMP
L9 M8 AA6 AE5
H_DVREF H_AVREF
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 VTTLF VTTLF_1 VTTLF_2 VTTLF_3
B15 K13 F13 B13 B14
0 1 2 3 4
CPU1_DSTBP0# CPU1_DSTBP1# CPU1_DSTBP2# CPU1_DSTBP3# CPU1_REQ#(4:0)
H_RS#_0 H_RS#_1 H_RS#_2
B6 F12 C8
CPU1_RS0# CPU1_RS1# CPU1_RS2#
CPU1_BSEL0 CPU1_BSEL1 CPU1_BSEL2
P1.05V R706
2.2K
A
DRAW DATE TITLE
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0 undefined
MCH_CANTIGA_PM_DDR3
ELECTRONICS
CANTIGA (1/5)
PART NO.
BA41-#####A
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OF
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Q320
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
A
C
D
B
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
4
M29 G32 L32 M32 M33 B42 G38 F37 K37 A41 H38 G37 J37 H47 E46 G40 A40 E29 G29 E28 G28 J28 B28 A28 B30 B29 C29 HDA_BCLK HDA_SYNC HDA_RST# HDA_SDI HDA_SDO HDA C40 C41 H48 D45 F40 B40 C44 B43 E37 E38 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL H24 F25 H25 K25 C31 E32 H32 J32 A37 B37 LVDSB_CLK LVDSB_CLK# K33 J33 J29 L29 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSA_CLK LVDSA_CLK# LVDS LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 L_VDD_EN L_BKLT_EN L_BKLT_CTRL L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA TV_RTN TVA_DAC TVB_DAC TVC_DAC TV TV_DCONSEL_0 TV_DCONSEL_1 CRT_TVO_IREF CRT_IRTN CRT_BLUE CRT_GREEN CRT_RED VGA CRT_HSYNC CRT_VSYNC CRT_DDC_CLK CRT_DDC_DATA A43 A44 A46 A47 A5 A6 B4 B45 B47 B48 BC1 BC48 BD1 BD48 BE2 BE47 BF1 BF3 BF46 BF48 BG1 BG2 BG4 BG45 BG47 BG48 BH2 BH3 BH43 BH44 BH46 BH47 BH5 BH6 C3 C46 C48 D2 D47 E1 E48 F1 F48 AH10 AH12 AH13 AH9 AK34 AL34 AM35 AN35 AY21 B2 B31 BF18 BF23 BG23 BH18 K12 M1 M36 N36 R33 T24 T33 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22
PEG1_RXN(15:0)
RSVD11 RSVD10 RSVD13 RSVD12
RSVD
AE16 AE17 AE19 AF16 AF17 AF19 AG16 AG17 AG19 AH16 AH17 AH19 AJ16 AJ19 AK16 AK17 AK19 AK20 AK21 AL16 AL19 AL21 AM16 AM17 AM19 AM20 AM21 U16 U19 U20 U21 V16 V17 V19 V21 V23 V24 V25 V26 V28 W16 W17 W19 W20 W21 W23 W24 W25 W26 W28 Y16 Y17 Y19
VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
AA15 AA20 AA21 AA23 AA24 AA25 AB15 AB20 AB23 AB25 AC20 AC21 AC23 AC24 AE15 AE20 AE21 AE23 AE24 AE25 AF15 AF20 AG15 AG21 AH15 AH20 AJ15 AJ21 AL15 AM14 AM15 AN14 T14 T16 T17 U14 U15 V15 Y15 Y21 Y24 Y26
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 C60 M46 C57 M47 C55 M40 C53 M42 C42 R48 C52 N38 C46 T40 C51 U37 C45 U40 C36 Y40 C32 AA46 C34 AA37 C30 AA40 C37 AD43 C39 AC46 C722 J42 C59 L46 C58 M48 C56 M39 C54 M43 C43 R47 C50 N37 C47 T39 C49 U36 C44 U39 C48 Y39 C31 Y46 C35 AA36 C33 AA39 C38 AD42 C40 AD46 C723
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
NC PCIE GFX GFX VCC
3
3 2
DRAW MODULE CODE APPROVAL CHECK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2 OF 5
0904-002376
EB88CTPM
U2-2
GFX VCC NCTF
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PEG1_RXP(15:0)
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7
AA16 AA19 AB16 AB17 AB19 AC16 AC17
GFX VCC NCTF
2
PEG1_TXN(15:0)
undefined
LAST EDIT
PCIE GFX
ES CHO
REV
SE LEE
DEV. STEP
SE LEE
DATE
MISC
PM
ME
CLK
DMI
PEG1_TXP(15:0)
DPLL_REF_SSCLK DPLL_REF_SSCLK#
SDVO_CTRLCLK SDVO_CTRLDATA
DDPC_CTRLCLK DDPC_CTRLDATA
DPLL_REF_CLK DPLL_REF_CLK#
9/19/2008
THERMTRIP# PM_EXT_TS#_0 PM_EXT_TS#_1
PM_SYNC# PM_DPRSTP# DPRSLPVR
rev 1.0 October 24, 2008 20:01:49 PM
PEG_COMPI PEG_COMPO
ADV1
GFX_VR_EN
ICH_SYNC# TSATN#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
CL_CLK CL_DATA CL_PWROK CL_RST#
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
PEG_CLK PEG_CLK#
CLKREQ#
CL_VREF
PWROK RSTIN#
P3.3V
TITLE
R687 R686 R709
MCH_CANTIGA_PM_DDR3
E41 F41
B38 A38
AD35 AE44 AF46 AH43
AE35 AE43 AE46 AH42
AE40 AE38 AE48 AH40
AE41 AE37 AE47 AH39
B33 B32 G33 F33 E33
H36 B12
K36
G36 E36
N28 M28
T20 N33 P32
AT40 AT11
R29 B7 R32
AH34
AH37 AH36 AN36 AJ35
F43 E43
C34
T37 T36
CANTIGA (2/5)
MIAMI-EXT
100
R703
R710
1608
10K 10K 10K
5%
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
R660
MCH3_ICHSYNC# P1.05V
MCH3_CLKREQ#
CHP3_CL_CLK_0 CHP3_CL_DATA_0 KBC3_PWRGD CHP3_CL_RST_0#
CLK1_MCH3GPLL CLK1_MCH3GPLL#
DMI1_RXP_0 DMI1_RXP_1 DMI1_RXP_2 DMI1_RXP_3
DMI1_RXN_0 DMI1_RXN_1 DMI1_RXN_2 DMI1_RXN_3
DMI1_TXP_0 DMI1_TXP_1 DMI1_TXP_2 DMI1_TXP_3
DMI1_TXN_0 DMI1_TXN_1 DMI1_TXN_2 DMI1_TXN_3
R689
56
0
CHP3_PM_SYNC# CPU1_DPRSTP# CHP3_DPRSLPVR
1
1
CPU1_THRMTRIP# MCH3_EXTTS0# MCH3_EXTTS1#
KBC3_PWRGD PLT3_RST#
49.9 1%
PAGE
MCH3_EXTTS0# MCH3_EXTTS1# MCH3_CLKREQ#
PART NO.
SAMSUNG
P1.05V_PEG
10V
C715 100nF
14
OF
P1.05V
500 ohm for Cantiga
ELECTRONICS
499 1%
1K 1%
R662
R688
BA41-#####A
61
A
B
C
D
Q320
8-9
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG. MEM1_ADQ(63:0)
SAMSUNG PROPRIETARY
4 3
2
1
PLACE EACH CAP NEAR AV42 PIN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
MEM1_VREF
C719 R637
SM_REXT SM_VREF SM_DRAMRST# SM_PWROK SB_CAS# SB_RAS# SB_WE# BF17 AV42 BC36 AR36 BG16 AU17 BF14 SB_CS#_0 SB_CS#_1 AV16 AR13 499 1%
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
100nF 10V
100nF 10V
C718
nostuff nostuff
0 1 2
MEM1_ADM(7:0)
0 1 2 3 4 5 6 7
SA_BS_0 SA_BS_1 SA_BS_2 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SYSTEM MEMORY A SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_CAS# SA_RAS# SA_WE#
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
D
MEM1_ABS(2:0)
BD21 BG18 AT25 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7
D
MEM1_VREF
MEM1_ADQS#(7:0)
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 BA21 1 BC24 2 BG24 3 BH24 4 BG25 5 BA24 6 BD24 7 BG27 8 BF25 9 AW24 10 BC21 11 BG26 12 BH26 13 BH17 14 AY25
MEM1_ADQS(7:0)
C
MEM1_AMA(14:0)
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
MEM1_ACAS# MEM1_ARAS# MEM1_AWE# MEM1_CS0# MEM1_CS1#
BA17 AY16 BD17 AY17 BC28 AY28 AP24 AR24 AT21 AR21 BG22 BH21 BF28 BH28
BD20 BB20 AY20
SA_CS#_0 SA_CS#_1 SA_ODT_0 SA_ODT_1 SA_CKE_0 SA_CKE_1 SA_CK_0 SA_CK#_0 SA_CK_1 SA_CK#_1 SM_RCOMP SM_RCOMP# SM_RCOMP_V_OH SM_RCOMP_V_OL
B
P1.8V_AUX R640
80.6 1%
MEM1_ODT0 MEM1_ODT1 MEM1_CKE0 MEM1_CKE1 CLK1_MCLK0 CLK1_MCLK0# CLK1_MCLK1 CLK1_MCLK1#
R639
80.6 1%
P1.8V_AUX Route as short as possible
1K 1%
R641
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
U2-3 EB88CTPM 3 OF 5
0904-002376
SYSTEM MEMORY A
MEM1_BCAS# MEM1_BRAS# MEM1_BWE#
DDR 3 : Connect to VR. DDR 2 : Connect to GND
MEM1_CS2# MEM1_CS3#
SB_ODT_0 SB_ODT_1 BF15 AY13
MEM1_ODT2 MEM1_ODT3
SB_CKE_0 SB_CKE_1 AY36 BB36
MEM1_CKE2 MEM1_CKE3
SB_CK_0 SB_CK#_0 SB_CK_1 SB_CK#_1 AV24 AU24 AU20 AV20
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
0 1 2 3 4 5 6 7
CLK1_MCLK2 CLK1_MCLK2# CLK1_MCLK3 CLK1_MCLK3# MEM1_BDM(7:0)
C
SYSTEM MEMORY B
SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
0 1 2 3 4 5 6 7
MEM1_BDQS#(7:0)
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6
0 1 2 3 4 5 6 7
MEM1_BDQS(7:0)
SYSTEM MEMORY B
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
MEM1_BMA(14:0)
B
SB_BS_0 SB_BS_1 SB_BS_2
BC16 BB17 BB33
0 1 2
MEM1_BBS(2:0)
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
MEM1_BDQ(63:0) C684 R643
3.01K 1%
10nF 25V
C682
A
2200nF 10V
A
Teenah R642
1K 1%
SM_RCOMP : 20 ohm to VSS SM_RCOMP# : 20 ohm to P1.8V_AUX C686
10nF 25V
DRAW
DATE
TITLE
SE LEE
9/19/2008
C665
2200nF 10V
Cantiga
SM_RCOMP : 80 ohm to P1.5V_AUX SM_RCOMP# : 80 ohm to VSS
CHECK
DEV. STEP
MIAMI-EXT
SE LEE
APPROVAL REV
SAMSUNG
ADV1 ES CHO
MODULE CODE LAST EDIT
MCH_CANTIGA_PM_DDR3
rev 1.0
ELECTRONICS
CANTIGA (3/5)
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
15 4 3 2
OF
61
8-10
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
1
Q320
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG. P1.8V_AUX EC507 220uF
2.5V AD
22000nF-X5R 20% 6.3V 100nF 10V 100nF 10V
SAMSUNG PROPRIETARY
4
3
2
1
NC FOR DDR2 BD?? C687
22000nF-X5R 20% 6.3V
C683 C685 C688
D
BD16 BB24 BB21 BA36 AW16 AW13 AT13
D
BH32 BH31 BH29 BG32 BG31 BG30 BG29 BF32 BF31 BF29 BD32 BD29 BC32 BC29 BB32 BB29 BA32 BA29 AY32 AY29 AW32 AW29 AV32 AV29 AU32 AU29 AT32 AT29 AR32 AR29 AP33 AP32 AP29 AN33 AN32
P1.05V C846
10000nF 6.3V 1000nF 6.3V
P3.3V
P1.05V
nostuff
C788
VCC_SM_NC_7 VCC_SM_NC_6 VCC_SM_NC_5 VCC_SM_NC_4 VCC_SM_NC_3 VCC_SM_NC_2 VCC_SM_NC_1
VCC_SM_35 VCC_SM_34 VCC_SM_33 VCC_SM_32 VCC_SM_31 VCC_SM_30 VCC_SM_29 VCC_SM_28 VCC_SM_27 VCC_SM_26 VCC_SM_25 VCC_SM_24 VCC_SM_23 VCC_SM_22 VCC_SM_21 VCC_SM_20 VCC_SM_19 VCC_SM_18 VCC_SM_17 VCC_SM_16 VCC_SM_15 VCC_SM_14 VCC_SM_13 VCC_SM_12 VCC_SM_11 VCC_SM_10 VCC_SM_9 VCC_SM_8 VCC_SM_7 VCC_SM_6 VCC_SM_5 VCC_SM_4 VCC_SM_3 VCC_SM_2 VCC_SM_1
VCC AXG
P1.05V_PEG
VCC_SM
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
VCC HAD
A21 B21 B22
VCC_HV
C721
VCC AXG
100nF 10V
AF48 AG47 AH47 AH48 VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
C
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
B27 A26
A25 CRT / TV POWER VCCA_DAC_BG
A24 B24
- - This Document can not be used without Samsung's authorization -
VCCA_TV_DAC_1 VCCA_TV_DAC_2
P1.5V
M25
8. Block Diagram and Schematic
VCCD_TVDAC VCCD_QDAC VCCA_LVDS
C789
100nF 10V
C790
10nF 25V
R708
0 J48
L28
AXG SENSE
B
K47
L37 M38 VCCD_LVDS_1 VCCD_LVDS_2 VCC_TX_LVDS
C681 C716 C679 C720 C709 C717 C706
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
VCC_HDA A32 VCC_HV_1 VCC_HV_2 VCC_HV_3 A35 B35 C35
R738 C791 100nF
12.1 1%
10V
3
1
2
BAT54A D520
2A routing
P1.05V_PEG
SHORT6 C740
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 U46 U47 U48 V47 V48
INSTPAR P1.05V
C742
4700nF-X5R 20% 6.3V 10V
22000nF-X5R
EC510 220uF
2.5V AD
SHORT5
PEG POWER
INSTPAR
U2-4 EB88CTPM 4 OF 5
P1.05V P1.5V
Cantiga : 1.5V
VCCA_PEG_BG AD48
C
C25 100nF
0904-002376
R23 C741 100nF
1
B4 BLM18PG181SN1
AA48
10V
VCCA_PEG_PLL
10V
10000nF 6.3V
C24
AA47
VCCD_PEG_PLL
PLL POWER
VCCA_DPLLA
F47
VCCA_DPLLB
L48
VCCA_HPLL
AD1
C733
VCCA_MPLL
AE1
4700nF-X5R 10V LVDS POWER
C734 P1.05V
100nF 10V
VCCD_HPLL
AF1
BLM18PG181SN1
VCC_SM_LF VCC_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK VCCA_SM VCC_AXG_SENSE AJ14
R661
0
C705
VCCA_SM_CK_NCTF_8 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_1
VSS_AXG_SENSE
AH14
0
100nF 10V
R683 R684 C704
1
100nF 10V
R659
1
B513
B
P1.05V C732
VCCA_SM_CK_5 VCCA_SM_CK_4 VCCA_SM_CK_3 VCCA_SM_CK_2 VCCA_SM_CK_1 VCC_SM_CK_4 VCC_SM_CK_3 VCC_SM_CK_2 VCC_SM_CK_1 VCC_SM_LF_7 VCC_SM_LF_6 VCC_SM_LF_5 VCC_SM_LF_4 VCC_SM_LF_3 VCC_SM_LF_2 VCC_SM_LF_1 VCCA_SM_9 VCCA_SM_8 VCCA_SM_7 VCCA_SM_6 VCCA_SM_5 VCCA_SM_4 VCCA_SM_3 VCCA_SM_2 VCCA_SM_1
22000nF-X5R 20% 6.3V
BB13 BA37 AY5 AV44 AV21 AM40 AM10
BH20 BG20 BF21 BF20
100nF 1000nF 220nF 1000nF 220nF 470nF 100nF
10V 6.3V 10V 6.3V 10V 16V 10V
AM28 AM26 AM25 AM24 AM23 AL25 AL24 AL23
AT16 AR20 AR17 AR16 AP20 AP17 AP16 AN20 AN17
AP28 AP25 AN28 AN25 AN24
nostuff
P1.05V
C707
P1.8V_AUX
A
B510 BLM18PG181SN1 R638
1
22000nF-X5R 22000nF-X5R 1000nF 4700nF-X5R 20% 20% 6.3V 10V 6.3V 6.3V
C708
C710
C712
EC509 220uF
2.5V AD
P1.05V C737 C664
10000nF 6.3V 10V
DRAW DATE TITLE
A
C713 C680 100nF
100nF 10V
2200nF 10V
C738
22000nF-X5R 20% 6.3V
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE ADV1
MIAMI-EXT
nostuff
APPROVAL REV
SAMSUNG
ES CHO
MODULE CODE LAST EDIT
MCH_CANTIGA_PM_DDR3
rev 1.0
ELECTRONICS
CANTIGA (4/5)
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
16 4 3 2
OF
61
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
1
Q320
8-11
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4 3
2
1
C
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
B
VSSA_DAC_BG
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16
VSSA_LVDS
VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5
A3 A48 BH1 BH48 C1
AA17 AB29 AB32 AC19 AF29 AF32 AJ17 AJ30 AL17 AL20 AM29 U17 U23 U26 V20 V32
AJ6 BG21 BG28 BG33 BG36 BG40 BG42 BG6 BH23 BH25 BH38 BH8 C11 C14 C17 C20 C26 C28 C32 C37 C38 C43 C6 E13 E16 E24 E25 E40 E8 F20 F24 F28 F29 F3 F32 F36
B25
J47
VSS_349 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240
A12 A15 A18 A20 A23 A29 A31 A34 AA1 AA10 AA12 AA14 AA26 AA35 AA38 AA41 AA44 AA7 AB21 AB24 AB26 AB28 AB33 AB47 AC15 AC2 AC25 AD12 AD2 AD38 AD41 AD44 AD47 AD5 AD9 AE10 AE13 AE2 AE28 AE34 AE36 AE39 AE42 AE7 AF2 AF21 AF24 AF26 AF34 AF47 AG20 AG23 AG28 AH11 AH2 AH21 AH24 AH26 AH33 AH35 AH38 AH41 AH44 AH5 AH8 AJ10 AJ13 AJ2 AJ20 AJ24 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS F38 F44 F46 F5 G11 G13 G16 G21 G24 G25 G41 G47 G9 H1 H17 H28 H29 H33 H37 H40 H46 H5 J12 J21 J24 J25 J36 J38 J43 J5 J7 K16 K2 K20 K24 K28 K29 K32 L12 L13 L24 L25 L33 L36 L39 L42 L47 L5 L8 M10 M17 M2 M21 M41 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS VSS TV & LVDS VSS VSS SCB VSS NCTF
0904-002376
VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135
AJ25 AJ28 AJ34 AJ37 AJ39 AJ42 AJ47 AJ7 AK15 AL3 AL33 AL48 AM1 AM12 AM34 AM36 AM39 AM41 AM43 AM46 AM6 AM9 AN11 AN13 AN16 AN21 AN29 AN37 AN40 AN42 AN47 AN7 AN9 AP2 AP21 AR2 AR25 AR28 AR33 AR46 AR48 AT10 AT12 AT17 AT20 AT24 AT28 AT37 AT39 AT42 AT6 AT8 AU16 AU2 AU21 AU36 AU38 AU41 AU43 AU48 AU7 AV10 AV12 AV25 AV28
D
D
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
U2-5 EB88CTPM 5 OF 5
VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 M44 M6 N11 N13 N16 N20 N25 N29 N32 N39 N42 N47 N7 P1 P28 P3 P33 P36 P46 R17 R21 R24 R3 R46 T29 T35 T38 T41 T44 T47 U24 U25 U28 U29 U35 U38 U41 U44 V46 W15 W34 Y11 Y2 Y20 Y23 Y25 Y28 Y35 Y38 Y41 Y44 Y47 Y5 Y8 VSS VSS VSS
DRAW DATE TITLE
VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205
AV3 AV33 AV40 AV43 AV46 AV6 AV8 AW17 AW2 AW20 AW21 AW37 AW47 AY11 AY24 AY42 AY46 AY7 B23 B26 B34 B36 B39 B41 B8 B9 BA13 BA16 BA2 BA20 BA28 BA33 BA38 BA46 BA5 BB11 BB25 BB37 BB40 BB47 BB8 BC13 BC17 BC20 BC3 BC33 BC38 BC43 BC9 BD11 BD25 BD28 BD36 BD41 BD46 BD6 BE4 BF12 BF24 BF26 BF34 BF37 BF44 BF9 BG10 BG13 BG14 BG15 BG17 BG19
C
B
A
SE LEE
CHECK DEV. STEP
A
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0
MCH_CANTIGA_PM_DDR3
ELECTRONICS
CANTIGA (5/5)
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
17 4 3 2
OF
61
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
8-12
1
Q320
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
3
2
1
DDR SO-DIMM #0
MEM1_AMA(14:0)
0 1
P0.9V
D
MEM1_ADQ(63:0)
D
R928
56
R929
2
56
MEM1_AMA(14:0)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
C
MEM1_ABS(0) MEM1_ABS(1)
BA0 BA1 S0* S1* CK0 CK0* CK1 CK1* CKE0 CKE1 CAS* RAS* WE* SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
0 1 2 3 4 5 6 7
MEM1_ABS(2)
107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15 A16_BA2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 DQS*0 DQS*1 DQS*2 DQS*3 DQS*4 DQS*5 DQS*6 DQS*7
3709-001550
1/2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
DDR2-1 DDR2-SODIMM-200P-RVS
ME POWER RAIL UNDER ME ENABLE
R927
3 4
56
R926
56
MEM1_CS0# MEM1_CS1# CLK1_MCLK0 CLK1_MCLK0# CLK1_MCLK1 CLK1_MCLK1# MEM1_CKE0 MEM1_CKE1 MEM1_ACAS# MEM1_ARAS# MEM1_AWE# 10K 1% R588 10K 1% R587 SMB3_CLK SMB3_DATA MEM1_ODT0 MEM1_ODT1 MEM1_ADM(7:0)
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
B
MEM1_ADQS(7:0)
MEM1_ADQS#(7:0)
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
P1.8V_AUX
R925
5
56
R924
6
56
R923
7
56
DDR2-2 DDR2-SODIMM-200P-RVS
112 111 117 96 95 118 81 82 87 103 88 104
R922
56
2/2
8
R921
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
9
56
R920
10
56
R919
11
56
P3.3V
R918
12
56
R917
13
56
C636
100nF 10V
2200nF 10V
C635
R916
14
56
C
R915
199 VDDSPD
56
MCH3_EXTTS0#
83 120 50 69 163
NC1 NC2 NC3 NC4 NCTEST
MEM1_CS0#
R914 MEM1_CS1#
56
R913 MEM1_CKE0
56
R912
1 VREF
56
MEM1_VREF
MEM1_CKE1
R911 C657
100nF 10V
56
C658
2200nF
10V
201 202
GND0 GND1
MEM1_ODT0
R910 MEM1_ODT1
56
R909
47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
56
MEM1_ABS(0)
R908 MEM1_ABS(1)
56
R907 MEM1_ABS(2)
56
R617 MEM1_ACAS#
56
R906 MEM1_ARAS#
56
R905 MEM1_AWE#
56
R904
56
B
3709-001550
Place one cap close to every 2 pull-up resistors terminated to P0.9V
P0.9V
Place one cap close to every 2 pull-up resistors terminated to P0.9V
C644 C647 C617 C616 C608 C653 C651 C610 C649 C646 C605 C612 C655 nostuff
ME POWER RAIL UNDER ME ENABLE
10V 10V 10V 10V 10V 10V 10V 10V
nostuff
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF nostuff
nostuff
10V
10V
10V
10V
10V
nostuff nostuff
A
P1.8V_AUX EC506 220uF
2.5V AD
Place near SO-DIMM0
A
C652 C614
2200nF 10V
2200nF 10V
C566
2200nF 10V
C654
2200nF 10V
C641
2200nF 10V
C650
100nF 10V
C648
100nF 10V
C645
100nF 10V
C643
100nF 10V
DRAW
DATE
TITLE
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0
SODIMM_DDR2
ELECTRONICS
SODIMM_DDR2 #1
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
18 4 3 2
OF
61
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
1
Q320
8-13
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
3
2
1
DDR SO-DIMM #1
ME POWER RAIL UNDER ME ENABLE
D
MEM1_BDQ(63:0) MEM1_BMA(14:0)
0 1
P0.9V R955 R954
2
D
56
DDR1-1 DDR2-SODIMM-200P-RVS
P1.8V_AUX
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
56
R953
56
MEM1_BMA(14:0)
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15 A16_BA2 107 106 BA0 BA1 S0* S1* CK0 CK0* CK1 CK1* CKE0 CKE1 CAS* RAS* WE* SA0 SA1 SCL SDA ODT0 ODT1 10 26 52 67 130 147 170 185
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1/2
MEM1_BBS(2)
C
MEM1_BBS(0) MEM1_BBS(1) MEM1_CS2# MEM1_CS3# CLK1_MCLK2 CLK1_MCLK2# CLK1_MCLK3 CLK1_MCLK3# MEM1_CKE2 MEM1_CKE3 P3.3V
1% 1% 198 200 197 195 114 119 30 32 164 166 79 80 113 108 109 110 115
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
MEM1_BCAS# MEM1_BRAS# MEM1_BWE# 10K R565 10K R564 SMB3_CLK SMB3_DATA MEM1_ODT2 MEM1_ODT3 MEM1_BDM(7:0)
B
MEM1_BDQS(7:0)
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 13 31 51 70 131 148 169 188 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
MEM1_BDQS#(7:0)
0 1 2 3 4 5 6 7
11 29 49 68 129 146 167 186
DQS*0 DQS*1 DQS*2 DQS*3 DQS*4 DQS*5 DQS*6 DQS*7
3709-001568
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
P3.3V C603
100nF 10V
DDR1-2 DDR2-SODIMM-200P-RVS
3
R952
56
C602
2200nF 10V
112 111 117 96 95 118 81 82 87 103 88 104
2/2
4
R951
56 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
5
R950
56
6
R949
56
7
R948
56
8
R947
56
9
R946
56
10
R945
56 199
11
R944
56 VDDSPD 83 120 50 69 163
12
R943
56 NC1 NC2 NC3 NC4 NCTEST
13
R942
56
C
MCH3_EXTTS1#
14
R941
56
MEM1_VREF
1
VREF
MEM1_CS2#
R940
56
C623
100nF 10V
C624
2200nF 10V
201 202
GND0 GND1
MEM1_CS3#
R939
56 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
MEM1_CKE2
R589
56
MEM1_CKE3
R938
56
MEM1_ODT2
R937
56
MEM1_ODT3
R936
56
MEM1_BBS(0)
R935
56
MEM1_BBS(1)
R934
56
MEM1_BBS(2)
R933
56
MEM1_BCAS#
R932
56
MEM1_BRAS#
R931
56
3709-001568
MEM1_BWE#
R930
56
B
BA70-00601A
BA70-00601A
BA70-00601A
CONTACT-PLATE-EMI
CONTACT-PLATE-EMI
CONTACT-PLATE-EMI
CONTACT-PLATE-EMI
BA70-00601A
EMI504
EMI500
EMI502
EMI501
EMI
EMI
EMI
EMI
P0.9V
Place one cap close to every 2 pull-up resistors terminated to P0.9V
C615 C619 C567 C565 C613 C609 C563 C564 C570 C604 C569 C607 C620 nostuff nostuff nostuff nostuff 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF nostuff 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V nostuff P1.8V_AUX Place near SO-DIMM1
A
EC501 220uF
2.5V AD
A
C571 C621
2200nF 10V
2200nF 10V
C572
2200nF 10V
C568
2200nF 10V
C642
2200nF 10V
C611 C618 C606 C622
100nF 10V 100nF 10V 100nF 10V 100nF 10V
DRAW
DATE
TITLE
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0
SODIMM_DDR2
ELECTRONICS
SODIMM_DDR2 #2
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
19 4 3 2
OF
61
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
8-14
1
Q320
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG. Internal VR Strap INTVRMEN Pull up VccSus1_05, VccSus1_5, VccCL1_5 VccLAN1_05, VccCL1_05 C895
0.007nF
SAMSUNG PROPRIETARY
4 3 2
1
Y501 32.768KHz
D
P3.3V_MICOM
2 1
D
R800
10M
P3.3V
PRTC_BAT R88
1M
19-B3 9-D4
KBC3_CPURST#
3
4
R873
10K
1%
D524 BAT54C C108
1000nF-X5R
CHP3_INTRUDER#
0.007nF
C893
2801-003856
KBC3_A20G
R155
10K 1%
2
R87
20K
1%
19-B4 9-D4
CHP3_RTCRST# R824 CHP3_RTCRST# CHP3_ME_RTCRST# CHP3_INTRUDER#
R89
20K
19-C2 9-D4
1%
RTC LPC
0
R90 CHP3_ME_RTCRST#
300K 1%
J5 HDR-2P-1R
C
nostuff nostuff nostuff For RTC Reset 3711-002162
1 2 MNT1 MNT2 3 4
10000nF 6.3V
R86
1K 1000nF-X5R 6.3V 1000nF-X5R 6.3V
C110
C109
C910
LAN / GLAN
RTC Battery Holder CR203 : 4301-000108
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
HDA3_AUD_BCLK HDA3_HDMI_BCLK HDA3_AUD_SYNC HDA3_HDMI_SYNC HDA3_HDMI_RST# HDA3_AUD_RST#
B
CHP3_SATALED#
SATA Cap. Place ment : Distance b/w the ICH9-M & cap on the "P" signal should be identical distance b/w the ICH9-M & cap on the "N" signal same pair.
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
3
PRTC_BAT
C23 C24
U517-1 NH82801IBM 1/5
1
RTCX1 RTCX2
9-D4 9-D4 9-D4
19-B4 19-C2 19-B3
A25 F20 C22
RTCRST# SRTCRST# INTRUDER#
FWH0_LAD0 FWH1_LAD1 FWH2_LAD2 FWH3_LAD3
K5 K4 L6 K2
0 1 2 3
LPC3_LAD(3:0)
FWH4_LFRAME#
K3
LPC3_LFRAME#
B22 A22 INTVRMEN LAN100_SLP LDRQ0# LDRQ1#_GPIO23 J3 J1
P1.05V C1031
E25 GLAN_CLK A20GATE A20M# N7 AJ27
For ESD
0.1nF 50V
C13
LAN_RTCSYNC
KBC3_A20G CPU1_A20M#
F14 G13 D14 LAN_RXD0 LAN_RXD1 LAN_RXD2 DPRSTP# DPSLP# AJ25 AE23
R96
56
C
R97
FERR#
AJ26
56
CPU1_DPRSTP# CPU1_DPSLP#
D13 D12 E13 AD22
CPU1_FERR#
LAN_TXD0 LAN_TXD1 LAN_TXD2 CPUPWRGD AF25
CPU1_PWRGDCPU
B10 CPU
P1.5V
IGNNE#
CPU1_IGNNE#
GLAN_DOCK#_GPIO56 B28 B27 INIT# INTR RCIN# AE22 AG25 L3
C1032
GLAN_COMPI GLAN_COMPO
R163 R164 R189 R191 R135 R160
22.6 22.6 22.6 22.6 22.6 22.6
1% 1% 1% 1% 1% 1%
R64
24.9 1%
CPU1_INIT# CPU1_INTR KBC3_CPURST# 1608
AF6 AH4 HDA_BIT_CLK HDA_SYNC NMI SMI# AF23 AF24
0.1nF 50V
For ESD
P1.05V
CPU1_NMI CPU1_SMI#
AE7 HDA_RST# STPCLK# AH27 AG26
CPU1_STPCLK# HDA3_AUD_SDI0
AF4 AG4 AH3 AE5 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 THRMTRIP# AG27
R98 R102
54.9 1% IHDA
56
CPU1_THRMTRIP#
P3.3V
HDA3_HDMI_SDI2
PECI
Place 56 ohm resistor within 2" of ICH9M HDA3_AUD_SDO HDA3_HDMI_SDO R186 R188
22.6 22.6 1% 1% AG5 HDA_SDOUT
Place PU resistor within 2" of 56ohm res. R157 C196 AG7
SATA4RXN SATA4RXP SATA4TXN SATA4TXP AH11 AJ11 AG12 AF12
25V 25V 25V 25V 10nF 10nF 10nF 10nF
10K 1%
For ESD
0.022nF AE8 50V
HDA_DOCK_EN#_GPIO33 HDA_DOCK_RS#_GPIO34
AG8
C159 C160 C161 C162
SATALED#
SAT1_RXN4 SAT1_RXP4 SAT1_TXN4 SAT1_TXP4
SATA SATA
B
C166 C170
10nF 10nF
SAT1_RXN0 SAT1_RXP0 SAT1_TXN0 SAT1_TXP0
25V 25V
C164 C165
10nF 25V 10nF 25V
AJ16 AH16 AF17 AG17
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
AH9 AJ9 AE10 AF10
SAT1_RXN1 SAT1_RXP1 SAT1_TXN1 SAT1_TXP1
C169 C168 C167 C171
10nF 10nF 10nF 10nF
25V 25V 25V 25V
AH13 AJ13 AG14 AF14
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
SATA_CLKN SATA_CLKP
AH18 AJ18
CLK1_SATA# CLK1_SATA
SATARBIAS# SATARBIAS AJ7 AH7
0904-002378
R161
24.9 1%
A
DRAW DATE TITLE
A
SE LEE
CHECK DEV. STEP
9/19/2008 SE LEE
APPROVAL REV
MIAMI-EXT
ADV1 ES CHO
MODULE CODE LAST EDIT
SAMSUNG
rev 1.0
ICH_9M_B
ELECTRONICS
ICH9-M (1/5)
PART NO.
BA41-#####A
October 24, 2008 20:01:49 PM
PAGE
20 4 3 2
OF
61
D:/users/mobile16/mentor/miami/1024_adv1order/miami_ext_081025
1
Q320
8-15
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
3
2
1
D
C
- - This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
P3.3V
R154
10K 10K
CHP3_SERIRQ
R872
PCI3_CLKRUN#
LPC option ; These are used with LPC
B
P3.3V_AUX
nostuff
PLT3_RST_ORG#
1 2
5
+ 3
U516 7SZ08
4
R840
100K 1%
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
C_BE0# C_BE1# C_BE2# C_BE3# D8 B4 D6 A5 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# D3 E3 R1 C6 E4 C2 J4 A4 F5 D7 10K PLTRST# PCICLK PME# C14 D4 R2
P3.3V
D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3
U517-2 NH82801IBM 2/5
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI REQ0# GNT0# REQ1#_GPI050 GNT1#_GPIO51 REQ2#_GPIO52 GNT2#_GPIO53 REQ3#_GPIO54 GNT3#_GPIO55
D
P3.3V
F1 G4 B6 A7 F13 F12 E6 F6
10K
R863
1K 1%
R865
R860 R849 R862 R859 R867 R851 R864 R858
10K 10K 10K 10K 10K 10K 10K
C
PLT3_RST_ORG# CLK3_PCLKICH
R868 R861 R866 R857
10K 10K 10K 10K
J5 E1 J6 C4
PIRQA# PIRQB# PIRQC# PIRQD#
Interrupt I/F
PIRQE#_GPIO2 PIRQF#_GPIO3 PIRQG#_GPIO4 PIRQH#_GPIO5
H4 K6 F2 G2
R1004
0
FFS3_INT PEX1_MINIRXN1 PEX1_MINIRXP1 PEX1_MINITXN1 PEX1_MINITXP1 C121 C120
100nF 100nF
10V 10V
N29 N28 P27 P26
PERN1 PERP1 PETN1 PETP1
PCI - Express
PERN5 PERP5 PETN5 PETP5
E29 E28 F27 F26
nostuff
P3.3V
PEX1_MINIRXN2 PEX1_MINIRXP2 PEX1_MINITXN2 PEX1_MINITXP2
C119 C117
100nF 100nF
10V 10V
L29 L28 M27 M26
PERN2 PERP2 PETN2 PETP2
PERN6_GLAN_RXN PERP6_GLAN_RXP PETN6_GLAN_TXN PETP6_GLAN_TXP
C29 C28 D27 D26
R777
PEX1_EXPCARDRXN3 PEX1_EXPCARDRXP3 PEX1_EXPCARDTXN3 PEX1_EXPCARDTXP3
C116 C115
100nF10V 100nF10V
J29 J28 K27 K26
1K 1%
P3.3V
PERN3 PERP3 PETN3 PETP3
nostuff
iTPM Disable
SPI SPI_CLK SPI_CS0# SPI_CS1#_GPIO58_CLGPIO6 SPI_MOSI SPI_MISO D23 D24 F23 D25 E23
PEX1_GLAN_RXN4 PEX1_GLAN_RXP4 PEX1_GLAN_TXN4 PEX1_GLAN_TXP4
100nF 100nF
C83 C82
G29 G28 10V H27 10V H26
R778 R801
12.1 12.1 PERN4 PERP4 PETN4 PETP4
1% 1%
SPI3_CLK SPI3_CS0# R776
R94
10K
B
12.1 1%
SPI3_MOSI SPI3_MISO
0904-002378
AC caps : PCIE need to be within 250mils of the driver Resistor for Test : Place S