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204pin DDR3 SDRAM SODIMM
DDR3 SDRAM Unbuffered SODIMMs Based on 1Gb B-die
HMT164S6BFR6C HMT112S6BFR6C HMT125S6BFR8C
*Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 1.0 / Jul. 2010 1
Revision History
Revision No. 0.1 0.2 0.3 0.4 0.5 1.0 History Initial Release Modified Speed grade. Corrected typo on package ball feature. Added IDD Specification Updated IDD Specification Corrected typo JEDEC Update. Add supported CL5 Draft Date Oct. 2008 Dec. 2008 Feb. 2009 Apr. 2009 Sep. 2009 Jul. 2010 Remark
Rev. 1.0 / Jul. 2010
2
Description
Hynix Unbuffered Small Outline DDR3 SDRAM DIMMs (Unbuffered Small Outline Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM devices. These Unbuffered DDR3 SDRAM SODIMMs are intended for use as main memory when installed in systems such as mobile personal computers.
Features
· VDD=1.5V +/- 0.075V · VDDQ=1.5V +/- 0.075V · VDDSPD=3.0V to 3.6V · Functionality and operations comply with the DDR3 SDRAM datasheet · 8 internal banks · Data transfer rates: PC3-10600, PC3-8500, or PC3-6400 · Bi-directional Differential Data Strobe · 8 bit pre-fetch · Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4 · On Die Termination (ODT) supported · RoHS compliant
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number HMT164S6BFR6C-G7/H9 HMT112S6BFR6C-G7/H9 HMT125S6BFR8C-G7/H9 Density 512MB 1GB 2GB Organization 64Mx64 128Mx64 256Mx64 Component Composition 64Mx16(H5TQ1G63BFR)*4 64Mx16(H5TQ1G63BFR)*8 128Mx8(H5TQ1G83BFR)*16 # of ranks 1 2 2
Rev. 1.0 / Jul. 2010
3
Key Parameters
MT/s DDR3-1066 DDR3-1333 Grade -G7 -H9 tCK (ns) 1.875 1.5 CAS Latency (tCK) 7 9 tRCD (ns) 13.125 13.5 tRP (ns) 13.125 13.5 tRAS (ns) 37.5 36 tRC (ns) 50.625 49.5 CL-tRCD-tRP 7-7-7 9-9-9
Speed Grade
Frequency [MHz] Grade CL5 -G7 -H9 667 667 CL6 800 800 CL7 1066 1066 CL8 1066 1066 1333 1333 CL9 CL10 Remark
Address Table
512MB(1Rx16) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A12 A0-A9 BA0-BA2 2KB 1GB(2Rx16) 8K/64ms A0-A12 A0-A9 BA0-BA2 2KB 2GB(1Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB
Rev. 1.0 / Jul. 2010
4
Pin Descriptions
Pin Name CK[1:0] CK[1:0] CKE[1:0] RAS CAS WE S[1:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Description Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses On Die Termination Inputs Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Num ber 2 2 2 1 1 1 2 14 1 1 3 2 1 1 2 VREFDQ VREFCA VTT VDDSPD NC Input/Output Reference Termination Voltage SPD Power Reserved for future use 1 1 2 1 2 Total: 204 Pin Name DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] EVENT TEST RESET VDD VSS Description Data Input/Output Data Masks Data strobes Data strobes, negative line Temperature event pin Logic Analyzer specific test pin (No connect on SODIMM) Reset Pin Core and I/O Power Ground Num ber 64 8 8 8 1 1 1 18 52
Rev. 1.0 / Jul. 2010
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Input/Output Functional Descriptions
Symbol
CK0/CK0 CK1/CK1
Type
Polarity
Function
IN
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is Cross Point driven from the clock inputs and output timing for read operations is synchronized to the input clock. Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register. When sampled at the cross point of the rising edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM. Reference voltage for SSTL15 inputs. -- Selects which SDRAM internal bank of eight is activated. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read of Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A12(BC) is samples during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop: LOW, burst chopped). Data Input/Output pins. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. Power supplies for core, I/O, Serial Presence Detect, and ground for the module. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. Cross Point In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. -- These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.
CKE[1:0]
IN
S[1:0]
IN
Active Low
ODT[1:0] RAS, CAS, WE VREFDQ VREFCA BA[2:0]
IN IN Supply IN
Active High Active Low
A[9:0], A10/AP, A11, A12/BC A[15:13]
IN
--
DQ[63:0] DM[7:0] VDD, VDDSPD VSS
I/O IN
-- Active High
Supply
DQS[7:0], DQS[7:0]
I/O
SA[1:0]
IN
Rev. 1.0 / Jul. 2010
6
Symbol
SDA
Type
I/O
Polarity
--
Function
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
SCL
IN OUT (open drain) Supply IN
--
EVENT
This signal indicates that a thermal event has been detected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the Active Low EVENT pin on TS/SPD part. No pull-up resister is provided on DIMM. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. Used by memory bus analysis tools (unused (NC) on memory DIMMs)
VDDSPD RESET TEST
Rev. 1.0 / Jul. 2010
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Pin Assignments
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Front Side VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 Back Side VSS DQ4 DQ5 VSS DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 Pin # 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 Front Side DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD Pin # 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 Back Side VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A152 A142 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1 Pin # 105 Front Side VDD Pin # 106 108 110 112 114 116 118 120 122 124 Back Side VDD BA1 RAS VDD S0 ODT0 VDD ODT1 NC VDD Pin # 157 159 161 163 165 167 169 171 173 175 Front Side DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 Pin # 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 Back Side DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS EVENT SDA SCL VTT
107 A10/AP 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 BA0 VDD WE CAS VDD A132 S1 VDD TEST VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS
126 VREFCA 177 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS 179 181 183 185 187 189 191 193 195 197
83 A12/BC 85 87 89 91 93 95 97 99 101 103 A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0
199 VDDSPD 200 201 203 SA1 VTT 202 204
NC = No Connect; RFU = Reserved Future Use 1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules. 2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
Rev. 1.0 / Jul. 2010
8
Functional Block Diagram
512MB, 64Mx64 Module(1Rank of x16)
A[O:N]/BA[O:N]
SCL SA0 SA1
A[O:N]/BA[O:N]
DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8:15]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
240ohm +/-1%
SCL A0 Temp Sensor (with SPD) A1 A2 EVENT EVENT SCL A0 A1 A2
S0 RAS
ODT0
CK0 CKE0
CAS
CK0
WE
SDA The SPD may be integrated with the Temp Sensor or may be a separate component
D0
ODT CK CKE
SCL SA0 SA1
(SPD) WP
SDA
RAS
CAS
WE
CS
CK
A[O:N]/BA[O:N]
DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
240ohm +/-1%
Vtt VDDSPD VREFCA VREFDQ
Vtt
SPD/TS D0D3 D0D3 D0D3 D0D3, SPD, Temp sensor D0D3 D0D3 Terminated at near card edge NC NC Temp Sensor D0-D3
D1
ODT
VDD VSS CK0 CK0 CK1 CK1 ODT1 S1 EVENT RESET
RAS
CAS
CS
CS
ODT
RAS
CAS
CKE
CK
A[O:N]/BA[O:N]
DQS4 DQS4 DM4 DQ [32:39] DQS5 DQS5 DM5 DQ [40:47]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
D2
WE
CK
CK CKE ZQ
WE
CK
240ohm +/-1%
D0
D1
D2
D3
A[O:N]/BA[O:N]
DQS6 DQS6 DM6 DQ [48:55] DQS7 DQS7 DM7 DQ [56:63]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
240ohm +/-1%
D3
ODT
RAS
CAS
CS
CKE
WE CK
CK
NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown
Rank 0
Address and Control Lines
Vtt
Vtt
VDD
Rev. 1.0 / Jul. 2010
Vtt
9
1GB, 128Mx64 Module(2Rank of x16)
ODT0 A[O:N]/BA[O:N]
ODT1
CK0 CKE0
CK1 CKE1
SCL SA0 SA1
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8:15]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
240ohm +/-1%
D0
ODT CK CKE
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
240ohm +/-1%
SCL A0 Temp Sensor (with SPD) A1 A2 EVENT EVENT SCL A0 A1 A2
CAS
CK0
RAS
S0
CK1
WE
S1
SDA The SPD may be integrated with the Temp Sensor or may be a separate component
D4
ODT CK CKE
SCL SA0 SA1
(SPD) WP
SDA
CAS
RAS
RAS
CAS
WE
CK
WE
CS
CS
CK
Vtt DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] 240ohm +/-1% LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] 240ohm +/-1% VDDSPD VREFCA VREFDQ VDD
A[O:N]/BA[O:N]
Vtt
SPD/TS D0D7 D0D7 D0D7 D0D7, SPD, Temp sensor D0D3 D0D7 D0D3 D0D7 Temp Sensor D0-D7
ZQ
ZQ
A[O:N]/BA[O:N]
D1
ODT
D5
ODT CK CKE
VSS CK0 CK1 CK0 CK1 EVENT RESET
RAS
CAS
CK CKE
RAS
CAS
WE
WE
CK
CS
CS
CK
A[O:N]/BA[O:N]
ODT
RAS
CAS
CKE
CK
CS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
DQS6 DQS6 DM6 DQ [48:55] DQS7 DQS7 DM7 DQ [56:63]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
ZQ
D0
D1
D2
D3
D3
ODT
D7
ODT CK CKE
NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown
Rank 0 Rank 1
Address and Control Lines
RAS
CAS
CKE
RAS
CAS
WE CK
WE
CK
Vtt Vtt VDD VDD Vtt
Rev. 1.0 / Jul. 2010
CS
CS
CK
Vtt
240ohm +/-1%
CS
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
240ohm +/-1%
ODT
RAS
CAS
CK
CK CKE
WE
A[O:N]/BA[O:N]
DQS4 DQS4 DM4 DQ [32:39] DQS5 DQS5 DM5 DQ [40:47]
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
240ohm +/-1%
D2
LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15]
ZQ
240ohm +/-1%
D6
D4
D5
D6
D7
WE
CK
V1
V2
V3
V4
Vtt
V1
V2
V3
V4
10
2GB, 256Mx64 Module(2Rank of x8)
A[O:N]/BA[O:N]
Cterm
ODT0 CK0 CKE0
VDD Vtt
Cterm
VDD Vtt
CKE1 ODT1
Vtt
CK1
RAS
CAS
CK1
S1
DQS3 DQS3 DM3 DQ[24:31]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
S0
CK0
WE
D11
A[O:N]/BA[O:N]
LDQS LDQS LDM DQ [0:7]
ZQ
240ohm +/-1%
D3
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
D4
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
D12
A[O:N]/BA[O:N]
DQS4 DQS4 DM4 DQ[32:39]
ODT
ODT
ODT
CS
CS
CS
DQS1 DQS1 DM1 DQ[8:15]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
D1
A[O:N]/BA[O:N]
LDQS LDQS LDM DQ [0:7]
ZQ
240ohm +/-1%
D9
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
CS
D14
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
ODT
CAS
CAS
CAS
RAS
RAS
RAS
RAS
CK CKE
CK CKE
CK CKE
CAS
CK CKE
WE
WE
WE
CK
CK
CK
WE
CK
D6
A[O:N]/BA[O:N]
DQS6 DQS6 DM6 DQ[48:55]
ODT
ODT
ODT
RAS
RAS
CS
CS
DQS0 DQS0 DM0 DQ[0:7]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
CS
D0
A[O:N]/BA[O:N]
LDQS LDQS LDM DQ [0:7]
ZQ
240ohm +/-1%
D8
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
CS
D15
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
ODT
CAS
RAS
RAS
CK CKE
CAS
CAS
CK CKE
CAS
CK CKE
CK CKE
WE
WE
WE
CK
WE
CK
CK
CK
D7
A[O:N]/BA[O:N]
DQS7 DQS7 DM7 DQ[56:43]
ODT
ODT
CAS
CAS
ODT
CS
DQS2 DQS2 DM2 DQ[6:23]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
D2
A[O:N]/BA[O:N]
LDQS LDQS LDM DQ [0:7]
ZQ
240ohm +/-1%
D10
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
CS
D13
A[O:N]/BA[O:N]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1% DQS5 DQS5 DM5 DQ[40:47]
D5
A[O:N]/BA[O:N]
ODT
ODT
ODT
RAS
RAS
CK CKE
CK CKE
CS
CS
The SPD may be integrated with the Temp Sensor or may be a separate component
SCL SA0 SA1 SCL A0 A1 A2
D9
CS
CS
Vtt
ODT
CAS
RAS
RAS
CK CKE
CAS
CAS
CAS
CK CKE
WE
WE
WE
CK
WE
CK
CK
CK
ODT
RAS
RAS
CK CKE
CK CKE
CAS
RAS
RAS
CK CKE
CAS
CK CKE
WE
WE
WE
CK
WE
CK
CK
CK
CS
CS
Vtt
SPD/TS D0D15 D0D15 D0D15 D0D15, SPD, Temp sensor D0D7 D8D15 D0D7 D8D15 D0-D7 D8-D15 D0D7 D8D15 D0D7 D8D15 Temp Sensor D0-D15
V2
D3
V1
V9
D12
V8
VDDSPD
D6
(SPD) WP
VREFCA VREFDQ VDD VSS CK0 CK1 CK0 CK1
SDA
V3
D8
V7 V4 V5
D10 D5
V6
D7
SCL SA0 SA1
SCL A0 Temp Sensor (with SPD) A1 A2 EVENT EVENT
SDA
D0
V4
D2
V5
D13
V6 V7
CKE0
D15
CKE1 S0 S1 ODT0 ODT1 EVENT RESET
NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown
V3
V1
V2
D11
Vtt
V1 V9 V8
D4
Rank 0 Rank 1
D1
D14
Rev. 1.0 / Jul. 2010
11
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol VDD VDDQ Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V
o
Notes 1, 1, 1 1, 2
VIN, VOUT Voltage on any pin relative to Vss TSTG Notes: Storage Temperature
C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol TOPER Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Hynix DDR3 SDRAMs support Auto Self-Refresh and Extended Temperature Range and please refer to Hynix component datasheet and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range. Parameter Normal Operating Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units
oC oC
Notes 1,2 1,3
Rev. 1.0 / Jul. 2010
12
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Symbol VDD VDDQ Supply Voltage Supply Voltage for Output Parameter Rating Min. 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575 Units V V Notes 1,2 1,2
Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and ADDress
DDR3-800/1066/1333 Symbol VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VRefCA(DC) Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low AC Input logic high AC input logic low Reference Voltage for ADD, CMD inputs Vref + 0.100 VSS Vref + 0.175 Note2 Vref + 0.150 Note2 0.49 * VDD Max VDD Vref - 0.100 Note2 Vref - 0.175 Note2 Vref - 0.150 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 Unit Notes
Notes: 1. For input only pins except RESET, Vref = VrefCA (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 26. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV.
Rev. 1.0 / Jul. 2010
13
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in " DDR3 Device Operation") as well as derating tables in Table 44 of "DDR3 Device Operation" depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
DDR3-800/1066 Symbol VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VRefDQ(DC) Parameter Min DC input logic high Vref + 0.100 DC input logic low VSS AC input logic high Vref + 0.175 AC input logic low Note2 AC Input logic high Vref + 0.150 AC input logic low Note2 Reference Voltage for DQ, 0.49 * VDD DM inputs Max VDD Vref - 0.100 Note2 Vref - 0.175 Note2 Vref - 0.150 0.51 * VDD Min Vref + 0.100 VSS Vref + 0.150 Note2 0.49 * VDD Max VDD Vref - 0.100 Note2 Vref - 0.150 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 DDR3-1333 Unit Notes
Notes: 1. Vref = VrefDQ (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 26. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV.
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Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 21. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
voltage
VDD
VRef ac-noise VRef(DC)
VRef(t) VRef(DC)max VDD/2 VRef(DC)min
VSS
time
Illustration of VRef(DC) tolerance and VRef ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef(DC), as defined in figure above. This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
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AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC VIL.DIFF.AC.MIN Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
VIL.DIFF.MIN
0 half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and "time above ac-level" tDVAC
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Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3-800, 1066, 1333 Symbol VIHdiff VILdiff VIHdiff (ac) VILdiff (ac) Notes: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL (ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 26. Parameter Min Differential input high Differential input logic low Differential input high ac Differential input low ac + 0.200 Note 3 2 x (VIH (ac) - Vref) Note 3 Max Note 3 - 0.200 Note 3 2 x (VIL (ac) - Vref) V V V V 1 1 2 2 Unit Notes
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 tDVAC [ps] @ |VIH/Ldiff (ac)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max tDVAC [ps] @ |VIH/Ldiff (ac)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max -
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Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g., if VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK.
VDD or VDDQ
VSEHmin VSEH
VDD/2 or VDDQ/2 CK or DQS VSELmax
VSS or VSSQ
VSEL time
Single-ended requirements for differential signals. Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
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Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3-800, 1066, 1333 Symbol VSEH VSEL Notes: 1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs. 2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 26. Parameter Min Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Max Note 3 Note 3 (VDD / 2) = 0.175 (VDD / 2) = 0.175 V V V V 1,2 1,2 1,2 1,2 Unit Notes
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in the table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS
VDD CK, DQS
VIX VDD/2 VIX VIX
CK, DQS VSS
Vix Definition
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Cross point voltage for differential input signals (CK, DQS)
DDR3-800, 1066, 1333 Symbol VIX VIX Parameter Min Differential Input Cross Point Voltage relative to VDD/2 for CK, CK Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS -150 -175 -150 Max 150 175 150 mV mV mV 1 Unit Notes
Notes: 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK is larger than 3 V/ns. 2. Refer to the table "Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU" on page 19 for VSEL and VSEH standard values.
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 "Address / Command Setup, Hold and Derating" on page 137 in "DDR3 Device Operation" for single-ended slew rate definitions for address and command signals. See 7.6 "Data Setup, Hold and Slew Rate Derating" on page 144 in "DDR3 Device Operation" for singleended slew rate definition for data signals.
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Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and figure below.
Differential Input Slew Rate Definition
Measured Description Min
Max
Defined by
Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Notes:
VILdiffmax VIHdiffmin
VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Delta TRdiff vIHdiffmin
0
vILdiffmax Delta TFdiff
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
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AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) DDR3-800, 1066, 1333 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ Unit V V V V V 1 1 Notes
Notes: 1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ / 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3-800, 1066, 1333 + 0.2 x VDDQ - 0.2 x VDDQ Unit V V Notes 1 1
Notes: 1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ/2 at each of the differential outputs.
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Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.
Single-ended Output slew Rate Definition
Measured Description From Single-ended output slew rate for rising edge Single-ended output slew rate for falling edge VOL(AC) VOH(AC) To VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTRse [VOH(AC)-VOL(AC)] / DeltaTFse Defined by
Notes: 1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse Single Ended Output Voltage(l.e.DQ)
vOH(AC)
V
vOl(AC)
Delta TFse
Single Ended Output Slew Rate Definition
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3-800 Parameter Single-ended Output Slew Rate Symbol SRQse Min 2.5 Max 5 DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5
Units
V/ns
Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting
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Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and Figure below.
Differential Output Slew Rate Definition
Measured Description From Differential output slew rate for rising edge Differential output slew rate for falling edge VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff Defined by
Notes: 1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Voltage(i.e. DQS-DQS)
Delta TRdiff vOHdiff(AC)
O
vOLdiff(AC) Delta TFdiff
Differential Output Slew Rate Definition
Differential Output slew Rate Definition
Differential Output Slew Rate
DDR3-800 Parameter Differential Output Slew Rate Symbol SRQdiff Min 5 Max 10 DDR3-1066 Min 5 Max 10 DDR3-1333 Min 5 Max 10
Units
V/ns
Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting
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Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK, CK
DUT
DQ DQS DQS
25 Ohm VTT = VDDQ/2
Reference Load for AC Timing and Output Slew Rate
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Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) DDR3800 0.4 0.4 0.67 0.67 DDR31066 0.4 0.4 0.5 0.5 DDR31333 0.4 0.4 0.4 0.4 Units V V V-ns V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT) See figure below for each parameter definition
M axim um A m plitude O vershoot A rea
V olts (V)
VDD V SS
U ndershoot Area M axim um A m plitud e Tim e (ns) Add ress and Control O vershoot and U ndershoot D efinition
Address and Control Overshoot and Undershoot Definition
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Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) DDR3800 0.4 0.4 0.25 0.25 DDR31066 0.4 0.4 0.19 0.19 DDR31333 0.4 0.4 0.15 0.15 Units V V V-ns V-ns
(CK, CK, DQ, DQS, DQS, DM) See figure below for each parameter definition
M a x im u m A m p litu d e O v e rs h o o t A re a
V o lts (V )
VDDQ VSSQ
U n d e rs h o o t A re a M a x im u m A m p litu d e T im e (n s ) C lo c k , D a ta S tro b e a n d M a s k O v e rs h o o t a n d U n d e rs h o o t D e fin itio n
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
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Refresh parameters by device density
Refresh parameters by device density
Parameter REF command ACT or REF command time Average periodic refresh interval RTT_Nom Setting tRFC tREFI 0 C TCASE 85 C 85 C TCASE 95 C 512Mb 90 7.8 3.9 1Gb 110 7.8 3.9 2Gb 160 7.8 3.9 4Gb 300 7.8 3.9 8Gb 350 7.8 3.9 Units ns us us
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Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 31.
Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Supported CL Settings Supported CWL Settings Symbol min 15 15 15 52.5 37.5 3.0 2.5 5, 6 5 DDR3-800E 6-6-6 max 20 -- -- -- 9 * tREFI 3.3 3.3 ns ns ns ns ns ns ns 1, 2, 3, 4, 9 1, 2, 3 9 Unit Notes
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG)
nCK nCK
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DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 31.
Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CL = 7 CL = 8 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 min 13.125 13.125 13.125 50.625 37.5 3.0 Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 5, 6, 7, 8 5, 6 < 2.5 < 2.5 3.3 DDR3-1066F 7-7-7 max 20 -- -- -- 9 * tREFI 3.3 ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3, 4, 6, 9 4 1, 2, 3, 6 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 9 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
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DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 31.
Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5, 6 CWL = 7 CWL = 5, 6 CL = 10 CWL = 7 min 13.5 (13.125)8 13.5 (13.125)8 13.5 (13.125)8 49.5 (49.125)8 36 3.0 Reserved 2.5 Reserved Reserved Reserved 1.875 (Optional)
5
DDR3-1333H 9-9-9 max 20 -- -- -- 9 * tREFI 3.3 3.3 ns ns ns ns ns ns ns ns ns ns ns < 2.5 Reserved Reserved 1.875 Reserved Reserved 1.5 Reserved 1.5 (Optional) 5, 6, 8, (7), 9, (10) 5, 6, 7 <1.875 <1.875 < 2.5 ns ns ns ns ns ns ns ns ns ns 1, 2, 3, 4, 7, 9 4 1, 2, 3, 7 1, 2, 3, 4, 7 4 4 1, 2, 3, 4, 7 1, 2, 3, 4 4 1, 2, 3, 7 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 5 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
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Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next `Supported CL', where tCK(AVG) = 3.0 ns should only be used for CL = 5 calculation. 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. `Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to Hynix DIMM data sheet and/or the DIMM SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Hynix DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K. 9. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.
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Environmental Parameters
Symbol
TOPR HOPR TSTG HSTG PBAR
Parameter
Operating temperature Operating humidity (relative) Storage temperature Storage humidity (without condensation) Barometric Pressure (operating & storage)
Rating
0 to 65 10 to 90 -50 to +100 5 to 95 105 to 69
Units
oC
Notes
1, 3 1 1 1 1, 2
%
o
C
% K Pascal
Note: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. Up to 9850 ft. 3. The designer must meet the case temperature specifications for individual module components.
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Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
512MB: HMT164S6BFR6C
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
1GB: HMT112S6BFR6C
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
2GB: HMT125S6BFR8C
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
Note: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
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IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. · IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
·
For IDD and IDDQ measurements, the following definitions apply: · · · · · · · "0" and "LOW" is defined as VIN <= VILAC(max). "1" and "HIGH" is defined as VIN >= VIHAC(max). "MID_LEVEL" is defined as inputs are VREF = VDD/2. Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1. Basic IDD and IDDQ Measurement Conditions are described in Table 2. Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10. IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
·
· Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
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IDD
IDDQ (optional)
VDD
RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ
VDDQ
DDR3 SDRAM
DQS, DQS DQ, DM, TDQS, TDQS
RTT = 25 Ohm VDDQ/2
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above
Application specific memory channel environment
IDDQ Test Load
Channel IO Power Simulation
IDDQ Simulation
IDDQ Simulation
Correction Channel IO Power Number Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement
Rev. 1.0 / Jul. 2010
36
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol DDR3-1066 7-7-7 1.875 7 7 27 20 7 1KB page size 2KB page size 1KB page size 2KB page size 20 27 4 6 48 59 86 160 187 DDR3-1333 9-9-9 1.5 9 9 33 24 9 20 30 4 5 60 74 107 200 234 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
tCK
CL
nRCD nRC nRAS nRP nFAW nRRD
nRFC -512Mb nRFC-1 Gb nRFC- 2 Gb nRFC- 4 Gb nRFC- 8 Gb
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and Description
IDD0
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
IDD1
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 1.0 / Jul. 2010
37
Symbol Precharge Standby Current
Description
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6; Pattern Details: see Table 6. Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P0 Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit
IDD2P1
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD3N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Rev. 1.0 / Jul. 2010
38
Symbol Operating Burst Read Current
Description
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
IDD4R
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
IDD4W
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
IDD5B
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede); IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Rev. 1.0 / Jul. 2010
39
Symbol Auto Self-Refresh Current
Description
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6TC
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a,f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
IDD7
10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.0 / Jul. 2010
40
Table 3 - IDD0 Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1,2 3,4 ... nRAS ... 1*nRC+0 1*nRC+1, 2
ACT D, D D, D PRE ACT D, D D, D PRE
CS
Datab)
0 1 1 0 0 1 1 0
0 0 1 0 0 0 1 0
1 0 1 1 1 0 1 1
1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 F F F F
-
repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3, 4 ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat pattern 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Rev. 1.0 / Jul. 2010
41
Table 4 - IDD1 Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2
ACT D, D D, D RD PRE ACT D, D D, D RD PRE
CS
Datab)
0 1 1 0 0 0 1 1 0 0
0 0 1 1 0 0 0 1 1 0
1 0 1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1 1 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 F F F F F
00000000 00110011 -
repeat pattern 1...4 until nRCD - 1, truncate if necessary repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MIDLEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 1.0 / Jul. 2010
42
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2 3
D D D D
CS
Datab)
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2 3
D D D D
CS
Datab)
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Rev. 1.0 / Jul. 2010
43
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2,3 4 5
RD D D,D RD D D,D
CS
Datab)
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
1 0 1 1 0 1
0 0 0 0 0 0
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
00000000 00110011 -
Static High
toggling
6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
0
0
1 2,3 4 5 6,7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
1 2 3 4 5 6 7
WR D D,D WR D D,D repeat repeat repeat repeat repeat repeat repeat
0 1 1 0 1 1 0 1 1 0 1 1 Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop
0, 0, 0, 0, 0, 0, 0,
0 0 1 0 0 1 but but but but but but but
0 0 1 0 0 1 BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0]
WE
CS
Datab) 00000000 00110011 -
1 1 1 1 1 1 = = = = = = =
Static High
toggling
0 0 0 0 0 0 1 2 3 4 5 6 7
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Jul. 2010
44
Table 9 - IDD5B Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0 1
0
1.2 3,4 5...8
REF D, D D, D
CS
Datab)
0 1 1
0 0 1
0 0 1
1 0 1
0 0 0
0 0 0
0 00 00
0 0 0
0 0 0
0 0 F
-
repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Static High
toggling
9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC-1
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Rev. 1.0 / Jul. 2010
45
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
0 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
0
1 2 3 4 5 6 7 8 Static High toggling 9
0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2
10
11 12 13 14 15 16 17 18 19
2*nFAW+2*nRRD 2*nFAW+3*nRRD 2*nFAW+4*nRRD 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 3*nFAW+4*nRRD
ACT 0 0 1 1 0 0 00 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 D 1 0 0 0 0 0 00 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F RDA 0 1 0 1 0 1 00 1 0 F D 1 0 0 0 0 1 00 0 0 F repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F Assert and repeat above D Command until 2* nFAW - 1, if necessary ACT 0 0 1 1 0 0 00 0 0 F RDA 0 1 0 1 0 0 00 1 0 F D 1 0 0 0 0 0 00 0 0 F Repeat above D Command until 2* nFAW + nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 0 RDA 0 1 0 1 0 1 00 1 0 0 D 1 0 0 0 0 1 00 0 0 0 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary
WE
CS
Datab)
00000000 00110011 -
-
0 0 0 0 0 0 0
00110011 00000000 -
0
-
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Jul. 2010
46
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec. The actual measurements may vary according to DQ loading cap.
512MB, 64M x 64 SO-DIMM: HMT164S6BFR6C
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 1066 400 500 200 200 40 140 200 280 140 780 780 720 40 48 48 840 DDR3 1333 420 520 220 220 40 140 220 300 160 860 860 720 40 48 48 1040 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
1GB, 128M x 64 SO-DIMM: HMT112S6BFR6C
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
Rev. 1.0 / Jul. 2010
DDR3 1066 600 700 400 400 80 280 400 560 280 980 980 920 80 96 96 1040
DDR3 1333 640 740 440 440 80 280 440 600 320 1080 1080 940 80 96 96 1260
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
note
47
2GB, 256M x 64 SO-DIMM: HMT125S6BFR8C
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 1066 1000 1080 800 800 160 400 800 960 480 1360 1360 1760 160 192 192 1680 DDR3 1333 1080 1200 880 880 160 480 880 1040 480 1520 1520 1800 160 192 192 2040 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 1.0 / Jul. 2010
48
Module Dimensions
64Mx64 - HMT164S6BFR6C
Front
67.60mm
Side
3.80mm max
2.0
4.00 0.10
SPD
20.0mm 6.00
Detail-A
30.0mm
pin 1 2.15 2 X 1.80 0.10 21.00 1.65 0.10 3.00 39.00
pin 203
1.00 0.08 mm
Back
Detail of Contacts A
4.00 0.10
0.3 0.15
0.45 0.03 0.60 1.00 0.05
0.3~1.0
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 1.0 / Jul. 2010 49
2.55
128Mx64 - HMT112S6BFR6C
Front
67.60mm
Side
3.80mm max
2.0
4.00 0.10
SPD
20.0mm 6.00
Detail-A
30.0mm
pin 1 2.15 2 X 1.80 0.10 21.00 1.65 0.10 3.00 39.00
pin 203
1.00 0.08 mm
Back
Detail of Contacts A
4.00 0.10
0.3 0.15
0.45 0.03 0.60 1.00 0.05
0.3~1.0
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 1.0 / Jul. 2010 50
2.55
256Mx64 - HMT125S6BFR8C
Front
67.60mm
Side
3.80mm max
2.0
4.00 0.10
SPD
20.0mm 6.00
Detail-A
30.0mm
pin 1 2.15 2 X 1.80 0.10 21.00 1.65 0.10 3.00 39.00
pin 203
1.00 0.08 mm
Back
Detail of Contacts A
4.00 0.10
0.3 0.15
0.45 0.03 0.60 1.00 0.05
0.3~1.0
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 1.0 / Jul. 2010 51
2.55
`H' Part Number
Last updated: Nov. 2008
H M P X XX X X X X X X X - XX XX
1 2 3 4 5 6 7 8 9 10 11 12 13 1415 1617
HYNIX MEMORY
FBDIMM
1)
MODULE OPTIONS
Other DIMM's L0 : Low Profile Dx Ex Nx : IDT AMB : NEC AMB : Intel AMB
PRODUCT FAMILY
M : DRAM MODULE
MODULE SPEED(tCL-tRCD-tRP) PRODUCT MODE
P : DDR2 SDRAM G7 S6 S5 Y5 Y4 C4 E3 : : : : : : : DDR2-1066 7-7-7 DDR2-800 6-6-6 DDR2-800 5-5-5 DDR2-667 5-5-5 DDR2-667 4-4-4 DDR2-533 4-4-4 DDR2-4