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PIC16F87X Data Sheet
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
2001 Microchip Technology Inc.
DS30292C
"All rights reserved. Copyright © 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights."
Trademarks The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR and SelectMode are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS30292C - page ii
2001 Microchip Technology Inc.
PIC16F87X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
· PIC16F873 · PIC16F874 · PIC16F876 · PIC16F877
Pin Diagram
PDIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 40 39 38 37 36 35 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
Microcontroller Core Features:
· High performance RISC CPU · Only 35 single word instructions to learn · All single cycle instructions except for program branches which are two cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM Data Memory · Pinout compatible to the PIC16C73B/74B/76/77 · Interrupt capability (up to 14 sources) · Eight level deep hardware stack · Direct, indirect and relative addressing modes · Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Programmable code protection · Power saving SLEEP mode · Selectable oscillator options · Low power, high speed CMOS FLASH/EEPROM technology · Fully static design · In-Circuit Serial Programming (ICSP) via two pins · Single 5V In-Circuit Serial Programming capability · In-Circuit Debugging via two pins · Processor read/write access to program memory · Wide operating voltage range: 2.0V to 5.5V · High Sink/Source Current: 25 mA · Commercial, Industrial and Extended temperature ranges · Low-power consumption: - < 0.6 mA typical @ 3V, 4 MHz - 20 µA typical @ 3V, 32 kHz - < 1 µA typical standby current
PIC16F877/874
7 8 9 10 11 12 13 14 15 16 17 18 19 20
34 33 32 31 30 29 28 27 26 25 24 23 22 21
Peripheral Features:
· Timer0: 8-bit timer/counter with 8-bit prescaler · Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit · 10-bit multi-channel Analog-to-Digital converter · Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slave) · Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection · Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) · Brown-out detection circuitry for Brown-out Reset (BOR)
2001 Microchip Technology Inc.
DS30292C-page 1
PIC16F87X
Pin Diagrams
PDIP, SOIC
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP NC RB7/PGD RB6/PGC RB5 RB4 NC 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 9
PIC16F876/873
PLCC
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
QFP
44 43 42 41 40 39 38 37 36 35 34
NC NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM
1 2 3 4 5 6 7 8 9 10 11
PIC16F877 PIC16F874
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS RA4/T0CKI
DS30292C-page 2
RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
18 19 20 21 22 23 24 25 26 27 282
RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC
7 8 9 10 11 12 13 14 15 16 17
PIC16F877 PIC16F874
RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
2001 Microchip Technology Inc.
PIC16F87X
Key Features PICmicroTM Mid-Range Reference Manual (DS33023) Operating Frequency RESETS (and Delays) FLASH Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Instruction Set PIC16F873 DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 128 13 Ports A,B,C 3 2 MSSP, USART -- 5 input channels 35 instructions PIC16F874 DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 128 14 Ports A,B,C,D,E 3 2 MSSP, USART PSP 8 input channels 35 instructions PIC16F876 DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 256 13 Ports A,B,C 3 2 MSSP, USART -- 5 input channels 35 instructions PIC16F877 DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 256 14 Ports A,B,C,D,E 3 2 MSSP, USART PSP 8 input channels 35 instructions
2001 Microchip Technology Inc.
DS30292C-page 3
PIC16F87X
Table of Contents
1.0 Device Overview ................................................................................................................................................... 5 2.0 Memory Organization.......................................................................................................................................... 11 3.0 I/O Ports .............................................................................................................................................................. 29 4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 41 5.0 Timer0 Module .................................................................................................................................................... 47 6.0 Timer1 Module .................................................................................................................................................... 51 7.0 Timer2 Module .................................................................................................................................................... 55 8.0 Capture/Compare/PWM Modules ....................................................................................................................... 57 9.0 Master Synchronous Serial Port (MSSP) Module ............................................................................................... 65 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................ 95 11.0 Analog-to-Digital Converter (A/D) Module......................................................................................................... 111 12.0 Special Features of the CPU............................................................................................................................. 119 13.0 Instruction Set Summary................................................................................................................................... 135 14.0 Development Support ....................................................................................................................................... 143 15.0 Electrical Characteristics................................................................................................................................... 149 16.0 DC and AC Characteristics Graphs and Tables................................................................................................ 177 17.0 Packaging Information ...................................................................................................................................... 189 Appendix A: Revision History .................................................................................................................................... 197 Appendix B: Device Differences ................................................................................................................................ 197 Appendix C: Conversion Considerations ................................................................................................................... 198 Index .......................................................................................................................................................................... 199 On-Line Support ......................................................................................................................................................... 207 Reader Response ...................................................................................................................................................... 208 PIC16F87X Product Identification System ................................................................................................................. 209
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS30292C-page 4
2001 Microchip Technology Inc.
PIC16F87X
1.0 DEVICE OVERVIEW
This document contains device specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data sheet. The PIC16F876/873 devices come in 28-pin packages and the PIC16F877/874 devices come in 40-pin packages. The Parallel Slave Port is not implemented on the 28-pin devices. The following device block diagrams are sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1:
Device PIC16F873 PIC16F876
PIC16F873 AND PIC16F876 BLOCK DIAGRAM
Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes
13 Program Counter FLASH Program Memory
Data EEPROM 128 Bytes 256 Bytes
Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC
8 Level Stack (13-bit)
RAM File Registers RAM Addr(1)
Program Bus
14 Instruction reg Direct Addr 7
9
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low Voltage Programming 8
MUX
ALU
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1,2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2001 Microchip Technology Inc.
DS30292C-page 5
PIC16F87X
FIGURE 1-2:
Device PIC16F874 PIC16F877
PIC16F874 AND PIC16F877 BLOCK DIAGRAM
Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes
13 FLASH Program Memory 8 Level Stack (13-bit) Program Counter
Data EEPROM 128 Bytes 256 Bytes
Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC
RAM File Registers RAM Addr(1)
Program Bus
14 Instruction reg Direct Addr 7
9
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8
MUX
ALU
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE
W reg
Parallel Slave Port
MCLR
VDD, VSS
RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1,2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
DS30292C-page 6
2001 Microchip Technology Inc.
PIC16F87X
TABLE 1-1:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F873 AND PIC16F876 PINOUT DESCRIPTION
DIP Pin# 9 10 SOIC Pin# 9 10 I/O/P Type I O Buffer Type Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2 or negative analog reference voltage. RA3 can also be analog input3 or positive analog reference voltage. RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP
1
1
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD
21 22 23 24 25 26 27 28
21 22 23 24 25 26 27 28
I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2)
RB0 can also be the external interrupt pin.
RB3 can also be the low voltage programming input. Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. P = power ST = Schmitt Trigger input
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT VSS VDD Legend: I = input
11 12 13 14 15 16 17 18 8, 19 20
11 12 13 14 15 16 17 18 8, 19 20
I/O I/O I/O I/O I/O I/O I/O I/O P P
ST ST ST ST ST ST ST ST -- --
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc.
DS30292C-page 7
PIC16F87X
TABLE 1-2:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION
DIP Pin# 13 14 PLCC Pin# 14 15 QFP Pin# 30 31 I/O/P Type I O Buffer Type ST/CMOS(4) -- Description Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2 or negative analog reference voltage. RA3 can also be analog input3 or positive analog reference voltage. RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP
1
2
18
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
3 4 5 6 7 8
19 20 21 22 23 24
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD Legend: I = input
33 34 35 36 37 38 39 40
36 37 38 39 41 42 43 44
8 9 10 11 14 15 16 17
I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2)
RB0 can also be the external interrupt pin.
RB3 can also be the low voltage programming input. Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. P = power ST = Schmitt Trigger input
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30292C-page 8
2001 Microchip Technology Inc.
PIC16F87X
TABLE 1-2:
Pin Name
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED)
DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
15 16 17 18 23 24 25 26
16 18 19 20 25 26 27 29
32 35 36 37 42 43 44 1
I/O I/O I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST ST ST
RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VSS VDD NC Legend: I = input
19 20 21 22 27 28 29 30 8 9 10 12,31 11,32 --
21 22 23 24 30 31 32 33 9 10 11 13,34 12,35 1,17,28, 40
38 39 40 41 2 3 4 5 25 26 27 6,29 7,28 12,13, 33,34
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P
ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) PORTE is a bi-directional I/O port. ST/TTL(3) ST/TTL(3) ST/TTL(3) -- -- -- RE0 can also be read control for the parallel slave port, or analog input5. RE1 can also be write control for the parallel slave port, or analog input6. RE2 can also be select control for the parallel slave port, or analog input7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected. P = power ST = Schmitt Trigger input
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc.
DS30292C-page 9
PIC16F87X
NOTES:
DS30292C-page 10
2001 Microchip Technology Inc.
PIC16F87X
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
There are three memory blocks in each of the PIC16F87X MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is detailed in Section 4.0. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory, and the PIC16F873/874 devices have 4K x 14. Accessing a location above the physically implemented address will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h.
FIGURE 2-1:
PIC16F877/876 PROGRAM MEMORY MAP AND STACK
PC<12:0>
FIGURE 2-2:
PIC16F874/873 PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
Stack Level 1 Stack Level 2
Stack Level 8
Stack Level 8
RESET Vector
0000h
RESET Vector
0000h
Interrupt Vector
0004h 0005h
Interrupt Vector
0004h 0005h
Page 0
07FFh 0800h
On-Chip Program Memory
Page 0
07FFh 0800h
Page 1 On-Chip Program Memory Page 2
17FFh 1800h 0FFFh 1000h
Page 1
0FFFh 1000h
Page 3
1FFFh 1FFFh
2001 Microchip Technology Inc.
DS30292C-page 11
PIC16F87X
2.2 Data Memory Organization
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Note: EEPROM Data Memory description can be found in Section 4.0 of this data sheet.
RP1:RP0 00 01 10 11
Bank 0 1 2 3
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register (FSR).
DS30292C-page 12
2001 Microchip Technology Inc.
PIC16F87X
FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON EEDATA EEADR EEDATH EEADRH
PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2)
SSPCON2 PR2 SSPADD SSPSTAT
TXSTA SPBRG
General Purpose Register 16 Bytes
General Purpose Register 16 Bytes
ADRESL ADCON1
General Purpose Register 96 Bytes
EFh F0h FFh
16Fh 170h 17Fh
General Purpose Register 80 Bytes accesses 70h - 7Fh Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on the PIC16F876. 2: These registers are reserved, maintain these registers clear.
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PIC16F87X
FIGURE 2-4: PIC16F874/873 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 96 Bytes File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 10Dh 10Eh EEDATH 10Fh EEADRH 110h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2)
SSPCON2 PR2 SSPADD SSPSTAT
TXSTA SPBRG
ADRESL ADCON1
120h
1A0h
General Purpose Register 96 Bytes
accesses 20h-7Fh 16Fh 170h FFh 17Fh Bank 2
accesses A0h - FFh 1EFh 1F0h 1FFh Bank 3
7Fh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on the PIC16F873. 2: These registers are reserved, maintain these registers clear.
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PIC16F87X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section.
TABLE 2-1:
Address Bank 0 00h(3) 01h 02h(3) 03h(3) 04h(3) 05h 06h 07h 08h(4) 09h(4) 0Ah(1,3) 0Bh(3) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP -- RP1 -- RP0 TO PD Z DC C Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(3) -- -- -- PEIE ADIF (5) -- -- T0IE RCIF -- -- INTE TXIF EEIF -- RBIE SSPIF BCLIF RE2 T0IF CCP1IF -- RE1 INTF TMR2IF -- RE0 RBIF TMR1IF CCP2IF Write Buffer for the upper 5 bits of the Program Counter
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx xxxx xxxx ---- -xxx ---0 0000 0000 000x 0000 0000 -r-0 0--0 xxxx xxxx xxxx xxxx
27 47 26 18 27 29 31 33 35 36 26 20 22 24 52 52 51 55 55 70, 73 67 57 57 58 96 99 101 57 57 58 116 111
Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register -- -- WCOL -- T1CKPS1 T1CKPS0 TOUTPS1 CKP T1OSCEN TOUTPS0 SSPM3 T1SYNC TMR2ON SSPM2 TMR1CS TMR1ON Timer2 Module Register TOUTPS3 TOUTPS2 SSPOV SSPEN Synchronous Serial Port Receive Buffer/Transmit Register SSPM1 SSPM0 Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
--00 0000 0000 0000
T2CKPS1 T2CKPS0 -000 0000
xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx
CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- ADCS1 -- ADCS0 CCP2X CHS2 CCP2Y CHS1 CCP2M3 CHS0 CCP2M2 GO/DONE CCP2M1 -- CCP2M0 ADON A/D Result Register High Byte
--00 0000 xxxx xxxx 0000 00-0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as `0'. PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
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TABLE 2-1:
Address Bank 1 80h(3) 81h 82h(3) 83h(3) 84h(3) 85h 86h 87h 88h(4) 89h(4) 8Ah(1,3) 8Bh(3) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON -- -- SSPCON2 PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- -- -- -- ADRESL ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP -- INTEDG RP1 -- T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(2) -- -- OBF -- PEIE ADIE (5) -- IBOV -- T0IE RCIE -- -- PSPMODE INTE TXIE EEIE -- -- RBIE SSPIE BCLIE -- PORTE Data Direction Bits T0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE CCP2IE BOR Write Buffer for the upper 5 bits of the Program Counter
0000 0000 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 ---0 0000 0000 000x 0000 0000 -r-0 0--0 ---- --qq
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
27 19 26 18 27 29 31 33 35 37 26 20 21 23 25 -- -- 68 55 73, 74 66 -- -- -- 95 97 -- -- -- -- 116 112
Unimplemented Unimplemented GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register Low Byte ADFM -- -- -- PCFG3 PCFG2 PCFG1 PCFG0
-- --
0000 0000 1111 1111 0000 0000 0000 0000
-- -- --
0000 -010 0000 0000
-- -- -- --
xxxx xxxx 0--- 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as `0'. PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
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TABLE 2-1:
Address Bank 2 100h(3) 101h 102h(3) 103h(3) 104h(3) 105h 106h 107h 108h 109h 10Ah(1,3) 10Bh(3) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(3) 181h 182h(3) 183h(3) 184h(3) 185h 186h 187h 188h 189h 18Ah(1,3) 18Bh(3) 18Ch 18Dh 18Eh 18Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_REG PCL STATUS FSR -- TRISB -- -- -- PCLATH INTCON EECON1 EECON2 -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE EEPGD -- PEIE -- -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE WRERR T0IF WREN INTF WR RBIF RD
0000 0000 1111 1111 0000 0000 0001 1xxx xxxx xxxx
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
INDF TMR0 PCL STATUS FSR -- PORTB -- -- -- PCLATH INTCON EEDATA EEADR EEDATH EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
27 47 26 18 27 -- 31 -- -- -- 26 20 41 41 41 41 27 19 26 18 27 -- 31 -- -- -- 26 20 41, 42 41 -- --
--
xxxx xxxx
-- -- --
---0 0000 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
EEPROM Data Register Low Byte EEPROM Address Register Low Byte -- -- -- -- EEPROM Data Register High Byte -- EEPROM Address Register High Byte
--
1111 1111
-- -- --
---0 0000 0000 000x x--- x000 ---- ---0000 0000 0000 0000
EEPROM Control Register2 (not a physical register) Reserved maintain clear Reserved maintain clear
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as `0'. PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
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PIC16F87X
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high, or low order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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2.2.2.2 OPTION_REG Register
Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device
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2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
REGISTER 2-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.4 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the individual enable bits for the peripheral interrupts.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 PSPIE(1) bit 7 R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.5 PIR1 Register
Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 PSPIF(1) bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: · SPI - A transmission/reception has taken place. · I2C Slave - A transmission/reception has taken place. · I2C Master - A transmission/reception has taken place. - The initiated START condition was completed by the SSP module. - The initiated STOP condition was completed by the SSP module. - The initiated Restart condition was completed by the SSP module. - The initiated Acknowledge condition was completed by the SSP module. - A START condition occurred while the SSP module was idle (Multi-Master system). - A STOP condition occurred while the SSP module was idle (Multi-Master system). 0 = No SSP interrupt condition has occurred. CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PSPIF is reserved on PIC16F873/876 devices; always maintain this bit clear. Legend: R = Readable bit - n = Value at POR
W = Writable bit '1' = Bit is set
U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS 8Dh)
U-0 -- bit 7 R/W-0 Reserved U-0 -- R/W-0 EEIE R/W-0 BCLIE U-0 -- U-0 -- R/W-0 CCP2IE bit 0
bit 7 bit 6 bit 5 bit 4
Unimplemented: Read as '0' Reserved: Always maintain this bit clear Unimplemented: Read as '0' EEIE: EEPROM Write Operation Interrupt Enable 1 = Enable EE Write Interrupt 0 = Disable EE Write Interrupt BCLIE: Bus Collision Interrupt Enable 1 = Enable Bus Collision Interrupt 0 = Disable Bus Collision Interrupt Unimplemented: Read as '0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3
bit 2-1 bit 0
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2.2.2.7 PIR2 Register
.
The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt.
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS 0Dh)
U-0 -- bit 7 R/W-0 Reserved U-0 -- R/W-0 EEIF R/W-0 BCLIF U-0 -- U-0 -- R/W-0 CCP2IF bit 0
bit 7 bit 6 bit 5 bit 4
Unimplemented: Read as '0' Reserved: Always maintain this bit clear Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP, when configured for I2C Master mode 0 = No bus collision has occurred Unimplemented: Read as '0' CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3
bit 2-1 bit 0
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2.2.2.8 PCON Register
Note: The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT), and an external MCLR Reset. BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a "don't care" and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration word).
REGISTER 2-8:
PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-1 BOR bit 0
bit 7-2 bit 1
Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 0
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2.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
2.4
Program Memory Paging
FIGURE 2-5:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0
GOTO,CALL
All PIC16F87X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the return instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.
2.3.1
COMPUTED GOTO
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, "Implementing a Table Read" (AN556).
EXAMPLE 2-1:
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETURN
2.3.2
STACK
;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh)
The PIC16F87X family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
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PIC16F87X
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-6.
EXAMPLE 2-2:
MOVLW MOVWF CLRF INCF BTFSS GOTO :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 FSR register 0
RP1:RP0
6
From Opcode
Bank Select
Location Select 00 00h 01 80h 10 100h 11 180h
Bank Select
Location Select
Data Memory(1)
7Fh Bank 0
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
Note 1: For register file map detail, see Figure 2-3.
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NOTES:
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3.0 I/O PORTS
FIGURE 3-1:
Data Bus Data Latch D Q VDD CK Q P I/O pin(1)
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
WR Port
3.1
PORTA and the TRISA Register
WR TRIS
TRIS Latch D Q N
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
CK
Q
VSS Analog Input Mode
RD TRIS
TTL Input Buffer Q D
EN
RD Port
To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-2:
Data Bus WR Port
BLOCK DIAGRAM OF RA4/T0CKI PIN
Data Latch D Q Q N TRIS Latch D Q Q VSS Schmitt Trigger Input Buffer
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
CK
I/O pin(1)
EXAMPLE 3-1:
BCF BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank0 Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6>are always read as '0'.
WR TRIS
STATUS, RP0 STATUS, RP1 PORTA
CK
RD TRIS
BSF MOVLW MOVWF MOVLW
STATUS, RP0 0x06 ADCON1 0xCF
Q
D EN EN
MOVWF
TRISA
RD Port
TMR0 Clock Input Note 1: I/O pin has protection diodes to VSS only.
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TABLE 3-1:
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 Buffer TTL TTL TTL TTL ST TTL Input/output or analog input. Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF. Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port or analog input. Function
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
Address 05h 85h 9Fh
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- Bit 6 -- -- -- Bit 5 RA5 -- Bit 4 RA4 -- Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on: Value on all POR, other BOR RESETS
--0x 0000 --11 1111 --0u 0000 --11 1111 --0- 0000
Name PORTA TRISA
PORTA Data Direction Register
ADCON1 ADFM
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note:
When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG3:PCFG0 = 0100,0101, 011x, 1101, 1110, 1111.
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3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Three pins of PORTB are multiplexed with the Low Voltage Programming function: RB3/PGM, RB6/PGC and RB7/PGD. The alternate functions of these pins are described in the Special Features Section. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Po