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INTEGRATED CIRCUITS
DATA SHEET
TDA4680 Video processor with automatic cut-off and white level control
Product specification Supersedes data of April 1993 File under Integrated Circuits, IC02 1996 Oct 25
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
FEATURES · Operates from an 8 V DC supply · Black level clamping of the colour difference, luminance and RGB input signals with coupling-capacitor DC level storage · Two fully-controlled, analog RGB inputs, selected either by fast switch signals or via I2C-bus · Saturation, contrast and brightness adjustment via I2C-bus · Same RGB output black levels for Y/CD and RGB input signals · Timing pulse generation from either a 2 or 3-level sandcastle pulse for clamping, horizontal and vertical synchronization, cut-off and white level timing pulses · Automatic cut-off control with picture tube leakage current compensation · Software-based automatic white level control or fixed white levels via I2C-bus · Cut-off and white level measurement pulses in the last 4 lines of the vertical blanking interval (I2C-bus selection for PAL, SECAM, or NTSC, PAL-M) · Increased RGB signal bandwidths for progressive scan and 100 Hz operation (selected via I2C-bus) · Two switch-on delays to prevent discolouration before steady-state operation · Average beam current and peak drive limiting · PAL/SECAM or NTSC matrix selection via I2C-bus · Three adjustable reference voltage levels (via I2C-bus) for automatic cut-off and white level control · Emitter-follower RGB output stages to drive the video output stages · Hue control output for the TDA4555, TDA4650/T, TDA4655/T or TDA4657. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA4680 TDA4680WP DIP28 PLCC28 DESCRIPTION plastic dual in-line package; 28 leads (600 mil) plastic leaded chip carrier; 28 leads GENERAL DESCRIPTION
TDA4680
The TDA4680 is a monolithic integrated circuit with a colour difference interface for video processing in TV receivers. Its primary function is to process the luminance and colour difference signals from multistandard colour decoders, TDA4555, TDA4650/T, TDA4655/T or TDA4657, Colour Transient Improvement (CTI) IC, TDA4565, Picture Signal Improvement (PSI) IC, TDA4670, or from a feature module. The required input signals are: · Luminance and negative colour difference signals · 2 or 3-level sandcastle pulse for internal timing pulse generation · I2C-bus data and clock signals for microcontroller control. Two sets of analog RGB colour signals can also be inserted, e.g. one from a peritelevision connector and the other from an on-screen display generator; both inputs are fully-controlled internally. The TDA4680 includes full I2C-bus control of all parameters and functions with automatic cut-off and white level control of the picture tube cathode currents. It provides RGB output signals for the video output stages. There is a very similar IC TDA4681 available. The only differences are in the NTSC matrix.
VERSION SOT117-1 SOT261-2
1996 Oct 25
2
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
QUICK REFERENCE DATA SYMBOL VP IP V8(p-p) V6(p-p) V7(p-p) V14 supply voltage (pin 5) supply current (pin 5) luminance input (peak-to-peak value) -(B - Y) input (peak-to-peak value) -(R - Y) input (peak-to-peak value) 3-level sandcastle pulse H+V H BK 2-level sandcastle pulse H+V BK Vi(p-p) Vo(b-w) Tamb RGB input signals at pins 2, 3, 4, 10, 11 and 12 (peak-to-peak value) RGB outputs at pins 24, 22 and 20 (black-to-white value) operating ambient temperature - - - - 0 2.5 4.5 0.7 2.0 - - - - 2.5 4.5 8.0 PARAMETER - - - - MIN. 7.2 TYP. 8.0 85 0.45 1.33 1.05
TDA4680
MAX. 8.8 - - - - - - - - - - - 70
UNIT V mA V V V V V V V V V V °C
1996 Oct 25
3
handbook, full pagewidth
1996 Oct 25
hue control voltage
PONRES, CB0 and CB1, CG0 and CG1, CR0 and CR1 RAR A75 to A70, A85 to A80, A95 to A90 A45 to A40, A55 to A50, A65 to A60 AA5 to AA0 A05 to A00, A15 to A10, A25 to A20, A35 to A30
BLOCK DIAGRAM
Philips Semiconductors
26
SDA
27 3 x 6-BIT REFERENCE REGISTERS, D/A CONVERTER white level 19 control cut-off control
RC RW
leakage, cut-off and white level current input
I2C-bus 6-BIT D/A CONVERTER
3 x 2-BIT WHITE LEVEL REGISTERS AND PONRES
SCL
28
I2C-BUS TRANSCEIVER
BREN
TDA4680
18
1ST AND 2ND SWITCH-ON DELAYS WHITE LEVEL AND CUT-OFF COMPARATORS
sandcastle pulse SANDCASTLE BK PULSE H+V DETECTOR (H) TIMING GENERATOR 16 17
14
SC5 DELOF
leakage storage
BCOF, FSBL, FSWL, WPEN, VBW2, VBW1, VBW0
peak drive limiting storage 15 average beam current
SATOF
2 x 8-BIT CONTROL REGISTERS timing pulses
Video processor with automatic cut-off and white level control
4
Y-MATRIX 4 x 6-BIT D/A CONVERTERS 3 x 6-BIT D/A CONVERTERS R FAST SIGNAL SOURCE SWITCH, BLANKING 1 G B B G SATURATION AND CONTRAST ADJUST R R WHITE POINT ADJUST G B R BRIGHTNESS ADJUST, G BLANKING 2, MEASUREMENT B PULSES SUPPLY 5 9 B VP = 8 V
PEAK DRIVE AND AVERAGE BEAM CURRENT LIMITING
FSW1
13
NMEN
FSDIS2, FSON2, FSDIS1, FSON1
R1
10
G1
11
BCOF
B1
12
Y
8
R
24 22 20
R G B RGB outputs
-(R - Y)
7
-(B - Y)
6
PAL/SECAM, NTSC MATRIX
G
B
CUT-OFF ADJUST, OUTPUT STAGES
FSW2
1
R2
2
G2
3
B2
4
21
23 G
25 R
MED693
I2C-bus data and control signals
cut-off storage
Product specification
TDA4680
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
PINNING SYMBOL PIN FSW2 R2 G2 B2 VP -(B - Y) -(R - Y) Y GND R1 G1 B1 FSW1 SC BCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 red input 2 green input 2 blue input 2 supply voltage colour difference input -(B - Y) colour difference input -(R - Y) luminance input ground red input 1 green input 1 blue input 1 fast switch 1 input sandcastle pulse input average beam current limiting input CL WI CI BO CB GO CG RO CR HUE SDA SCL 17 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION fast switch 2 input SYMBOL PIN CPDL 16
TDA4680
DESCRIPTION storage capacitor for peak drive limiting storage capacitor for leakage current white level measurement input cut-off measurement input blue output blue cut-off storage capacitor green output green cut-off storage capacitor red output red cut-off storage capacitor hue control output I2C-bus serial data input/output I2C-bus serial clock input
3 G2
R2 2 G2 3 B2 4 VP 5 -(B - Y) 6 -(R - Y) 7
27 SDA 26 HUE 25 CR 24 RO 23 CG VP 5 -(B - Y) 6 -(R - Y) 7 Y 8
2 R2
4 B2
FSW2 1
28 SCL
26 HUE
27 SDA
28 SCL
handbook, halfpage
1 FSW2
25 CR 24 RO 23 CG
TDA4680
Y 8 GND 9 R1 10 G1 11 B1 12 FSW1 13 SC 14
MED694
22 GO GND 9 21 CB 20 BO 19 CI 18 WI 17 CL 16 CPDL 15 BCL R1 10 G1 11
TDA4680WP
22 GO 21 CB 20 BO 19 CI
B1 12
FSW1 13
SC 14
BCL 15
CPDL 16
CL 17
WI 18
MED695
Fig.2 Pin configuration for DIP-version.
Fig.3 Pin configuration for PLCC-version.
1996 Oct 25
5
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
I2C-BUS Control The I2C-bus transmitter/receiver provides the data bytes to select and adjust the following functions and parameters: · Brightness adjust · Saturation adjust · Contrast adjust · Hue control voltage · RGB gain adjust · RGB reference voltage levels · Peak drive limiting · Selection of the vertical blanking interval and measurement lines for cut-off and white level control according to transmission standard · Selects either 3-level or 2-level (5 V) sandcastle pulse · Enables/disables input clamping pulse delay · Enables/disables white level control · Enables cut-off control; enables output clamping · Enables/disables full screen white level · Enables/disables full screen black level · Selects either PAL/SECAM or NTSC matrix · Enables saturation adjust; enables nominal saturation · Enables/disables synchronization of the execution of I2C-bus commands with the vertical blanking interval · Reads the result of the comparison of the nominal and actual RGB signal levels for automatic white level control. I2C-bustransmitter/receiver and data transfer I2C-BUS SPECIFICATION The I2C-bus is a bidirectional, two-wire, serial data bus for intercommunication between ICs in a system. The microcontroller transmits/receives data from the I2C-bus transceiver in the TDA4680 over the serial data line SDA (pin 27) synchronized by the serial clock line SCL (pin 28). Both lines are normally connected to a positive voltage supply through pull-up resistors. Data is transferred when the SCL line is LOW. When SCL is HIGH the serial data line SDA must be stable. A HIGH-to-LOW transition of the SDA line when SCL is HIGH is defined as a START bit. A LOW-to-HIGH transition of the SDA line when SCL is HIGH is defined as a STOP bit. Each transmission must start with a START bit and end with a STOP bit. The bus is busy after a START bit and is only free again after a STOP bit has been transmitted. 1996 Oct 25 6
TDA4680
I2C-BUS RECEIVER (MICROCONTROLLER WRITE MODE) Each transmission to/from the I2C-bus transceiver consists of at least three bytes following the START bit. Each byte is acknowledged by an acknowledge bit immediately following each byte. The first byte is the Module Address (MAD) byte, also called slave address byte. This consists of the module address, 1000100 for the TDA4680, plus the R/W bit (see Fig.4). When the TDA4680 is a slave receiver (R/W = 0) the module address byte is 10001000 (88H). When the TDA4680 is a slave transmitter (R/W = 1) the module address byte is 10001001 (89H). The length of a data transmission is unrestricted, but the module address and the correct sub-address must be transmitted before the data byte(s). The order of data transmission is shown in Figs 5 and 6. Without auto-increment (BREN = 0 or 1) the module address (MAD) byte is followed by a Sub-Address (SAD) byte and one data byte only (see Fig.5).
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
TDA4680
handbook, full pagewidth
MSB 1 0 0 0 1 0
LSB 0 X R/W
MED696
ACK
module address
Fig.4 The module address byte.
handbook, full pagewidth
STA
MAD SAD
STO
MED697
START condition
data byte
STOP condition
Fig.5 Data transmission without auto-increment (BREN = 0 or 1).
handbook, full pagewidth
STA START condition
MAD SAD
STO
MED698
data byte data bytes
STOP condition
Fig.6 Data transmission with auto-increment (BREN = 0).
1996 Oct 25
7
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
AUTO-INCREMENT The auto-increment format enables quick slave receiver initialization by one transmission, when the I2C-bus control bit BREN = 0 (see control register bits of Table 1). If BREN = 1 auto-increment is not possible. If the auto-increment format is selected, the MAD byte is followed by a SAD byte and by the data bytes of consecutive sub-addresses (Fig.6). All sub-addresses from 00H to 0FH are automatically incremented, the sub-address counter wraps round from 0FH to 00H. Reserved sub-addresses 0BH, 0EH and 0FH are treated as legal but have no effect. Sub-addresses outside the range 00H and 0FH are not acknowledged by the device and neither auto-increment nor any other internal operation takes place (for versions V1 to V5 sub-addresses outside the range 00H and 0FH are acknowledged but neither auto-increment nor any other internal operation takes place). Sub-addresses are stored in the TDA4680 to address the following parameters and functions (see Table 1): · Brightness adjust · Saturation adjust · Contrast adjust · Hue control voltage · RGB gain adjust · RGB reference voltage levels · Peak drive limiting adjust · Control register functions. The data bytes D7 to D0 (see Table 1) provide the data of the parameters and functions for video processing. CONTROL REGISTER 1 VBWx (Vertical Blanking Window): x = 0, 1 or 2. VBWx selects the vertical blanking interval and positions the measurement lines for cut-off and white level control. The actual lines in the vertical blanking interval after the start of the vertical pulses selected as measurement lines for cut-off and white level control are shown in Table 2. The standards marked with (*) are for progressive line scan at double line frequency (2fL), i.e. approximately 31 kHz. NMEN (NTSC Matrix Enable): 0 = PAL/SECAM matrix 1 = NTSC matrix. 1996 Oct 25 8 WPEN (White Pulse Enable): 0 = white measuring pulse disabled 1 = white measuring pulse enabled. BREN (Buffer Register Enable):
TDA4680
0 = new data is executed as soon as it is received 1 = data is stored in buffer registers and is transferred to the data registers during the next vertical blanking interval. The I2C-bus transceiver does not accept any new data until this data is transferred into the data registers. DELOF (Delay Off) delays the leading edge of clamping pulses: 0 = delay enabled 1 = delay disabled. SC5 (SandCastle 5 V): 0 = 3-level sandcastle pulse 1 = 2-level (5 V) sandcastle pulse. CONTROL REGISTER 2 FSON2 (Fast Switch 2 ON) FSDIS2 (Fast Switch 2 Disable) FSON1 (Fast Switch 1 ON) FSDIS1 (Fast Switch 1 Disable) The RGB input signals are selected by FSON2 and FSON1 or FSW2 and FSW1: · FSON2 has priority over FSON1 · FSW2 has priority over FSW1 · FSDIS1 and FSDIS2 disable FSW1 and FSW2 (see Table 3). BCOF (Black level Control Off): 0 = automatic cut-off control enabled 1 = automatic cut-off control disabled; RGB outputs are clamped to fixed DC levels. FSBL (Full Screen Black Level): 0 = normal mode 1 = full screen black level (cut-off measurement level during full field). FSWL (Full Screen White Level): 0 = normal mode 1 = full screen white level (white measurement level during full field).
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
SATOF (Saturation control Off): 0 = saturation control enabled 1 = saturation control disabled, nominal saturation enabled. I2C-BUS TRANSMITTER (MICROCONTROLLER READ MODE) As an I2C-bus transmitter, R/W = 1, the TDA4680 sends a data byte from the status register to the microcontroller. The data byte consists of following bits: PONRES, CB1, CB0, CG1, CG0, CR1, CR0 and 0, where PONRES is the most significant bit. PONRES (Power On Reset) monitors the state of TDA4680's supply voltage: 0 = normal operation 1 = supply voltage has dropped below approximately 6.0 V (usually occurs when the TV receiver is switched on or the supply voltage was interrupted). When PONRES changes state from a logic LOW to a logic HIGH all data and function bits are set to logic LOW. Table 1 Sub-address (SAD) and data bytes; note 1 FUNCTION Brightness Saturation Contrast Hue control voltage Red gain Green gain Blue gain Red level reference Green level reference Blue level reference Peak drive limit Reserved Control register 1 Control register 2 Reserved Reserved Note 1. X = don't care. SAD (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F MSB D7 0 0 0 0 0 0 0 0 0 0 0 X SC5 SATOF X X D6 0 0 0 0 0 0 0 0 0 0 0 X DELOF FSWL X X D5 A05 A15 A25 A35 A45 A55 A65 A75 A85 A95 AA5 X BREN FSBL X X D4 A04 A14 A24 A34 A44 A54 A64 A74 A84 A94 AA4 X WPEN BCOF X X D3 A03 A13 A23 A33 A43 A53 A63 A73 A83 A93 AA3 X NMEN X X D2 A02 A12 A22 A32 A42 A52 A62 A72 A82 A92 AA2 X VBW2 X X
TDA4680
2-BIT WHITE LEVEL ERROR SIGNAL (see Table 4) CB1, CB0 = 2-bit white level of the blue channel. CG1, CG0 = 2-bit white level of the green channel. CR1, CR0 = 2-bit white level of the red channel.
LSB D1 A01 A11 A21 A31 A41 A51 A61 A71 A81 A91 AA1 X VBW1 X X D0 A00 A10 A20 A30 A40 A50 A60 A70 A80 A90 AA0 X VBW0 X X
FSDIS2 FSON2 FSDIS1 FSON1
1996 Oct 25
9
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
Table 2 VBW2 0 0 0 1 1 1 Notes Cut-off and white level measurement lines; notes 1 to 3 VBW1 0 0 1 0 0 1 VBW0 0 1 0 0 1 0 R 19 16 22 38, 39 32, 33 44, 45 G 20 17 23 40, 41 34, 35 46, 47 B 21 18 24 42, 43 36, 37 48, 49 WHITE 22 19 25 44, 45 38, 39 50, 51
TDA4680
STANDARD PAL/SECAM NTSC/PAL M PAL/SECAM (EB) PAL*/SECAM* NTSC*/PAL M* PAL*/SECAM* (EB)
1. The line numbers given are those of the horizontal pulse counts after the start of the vertical component of the sandcastle pulse. 2. * line frequency of approximately 31 kHz. 3. (EB) is extended blanking. Table 3 Signal input selection by the fast source switches; notes 1 to 4 ANALOG SWITCH SIGNALS FSW2 (PIN 1) L L H L L L L L H Notes 1. H: logical HIGH implies that the voltage >0.9 V. 2. L: logical LOW implies that the voltage <0.4 V. 3. X = don't care. 4. ON indicates the selected input signal. L L H H H X L H L L H X H X L H X X L H L H X X X X X FSW1 (PIN 13) L H X X X X X L H X X X ON ON ON ON ON ON ON ON ON ON ON RGB2 INPUT SELECTED RGB1 Y/CD ON
I2C-BUS CONTROL BITS FSON2 FSDIS2 FSON1 FSDIS1 L L L L
1996 Oct 25
10
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
Table 4 CX1 0 1 1 0 2-bit white level error signals; bits CX1 and CX0 CX0 0 0 1 1 INTERPRETATION RAR (Reset-After-Read): no new measurements since last read actual (measured) white level less than the tolerance range actual (measured) white level within the tolerance range actual (measured) white level greater than the tolerance range
TDA4680
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Vi supply voltage (pin 5) input voltage (pins 1 to 8, 10 to 13, 16, 21, 23 and 25) input voltage (pins 14, 15, 18 and 19) input voltage (pins 27 and 28) Iav IM I18 I26 Tstg Tamb Ptot average current (pins 20, 22 and 24) peak current (pins 20, 22 and 24) input current output current storage temperature operating ambient temperature total power dissipation SOT117-1 SOT261-2 - - 1.2 1.0 W W PARAMETER - -0.1 -0.7 -0.1 +4 +4 0 +0.5 -20 0 MIN. MAX. 8.8 +VP VP + 0.7 +8.8 -10 -20 2 -8 +150 70 V V V V mA mA mA mA °C °C UNIT
1996 Oct 25
11
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
TDA4680
CHARACTERISTICS All voltages are measured in test circuit of Fig.10 with respect to GND (pin 9); VP = 8.0 V; Tamb = 25 °C; nominal signal amplitudes (black-to-white) at output pins 24, 22 and 20; nominal settings of brightness, contrast, saturation and white level control; without beam current or peak drive limiting; unless otherwise specified. SYMBOL Supply (pin 5) VP IP V6(p-p) V7(p-p) V6,7 I6,7 R6,7 Vi(p-p) V8(bias) I8 R8 supply voltage supply current -(B - Y) input (peak-to-peak value) -(R - Y) signal (peak-to-peak value) internal DC bias voltage input current AC input resistance 7.2 - - - - - 100 10 - - - 100 10 - - - 100 10 - - - 100 10 8.0 85 8.8 110 - - - 0.15 - - - - 0.15 - - - - 0.15 - - - - 0.15 - - V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Colour difference inputs [-(B - Y): pin 6; -(R - Y): pin 7] notes 1 and 2 notes 1 and 2 at black level clamping during line scan at black level clamping Luminance/sync (VBS; Y: pin 8) luminance input voltage at pin 8 (peak-to-peak value) internal DC bias voltage input current AC input resistance note 2 at black level clamping during line scan at black level clamping RGB input 1 (R1: pin 10; G1: pin 11; B1: pin 12) Vi(p-p) input voltage at pins 10, 11 and 12 (peak-to-peak value) input current AC input resistance note 2 at black level clamping during line scan at black level clamping R10/11/12 RGB input 2 (R2: pin 2, G2: pin 3, B2: pin 4) Vi(p-p) V2/3/4 I2/3/4 R2/3/4 input voltage at pins 2, 3 and 4 (peak-to-peak value) internal DC bias voltage input current AC input resistance note 2 at black level clamping during line scan at black level clamping 0.7 5.4 - - - V V µA µA M 0.7 5.4 - - - V V µA µA M 0.45 3.1 - - - V V µA µA M 1.33 1.05 3.1 - - - V V V µA µA M
V10/11/12(bias) internal DC bias voltage I10/11/12
1996 Oct 25
12
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA4680
MAX.
UNIT
Fast signal switch FSW1 (pin 13) to select Y, CD or R1, G1, B1 inputs (control bits: see Table 3) V13 R13 t voltage to select Y and CD voltage range to select R1, G1, B1 internal resistance to ground difference between transit times for signal switching and signal insertion - 0.9 - - - - 4.0 - 0.4 5.0 - 10 V V k ns
Fast signal switch FSW2 (pin 1) to select Y, CD/R1, G1, B1 or R2, G2, B2 inputs (control bits: see Table 3) V1 R1 t voltage to select Y, CD/R1, G1, B1 voltage to select R2, G2, B2 internal resistance to ground difference between transit times for signal switching and signal insertion - 0.9 - - - - 4.0 - 0.4 5.0 - 10 V V k ns
Saturation adjust [acts on internal RGB signals under I2C-bus control; sub-address 01H (bit resolution 1.5% of maximum saturation); data byte 3FH for maximum saturation, data byte 23H for nominal saturation and data byte 00H for minimum saturation] ds saturation below maximum at 23H at 00H; f = 100 kHz - - 5 50 - - dB dB
Contrast adjust [acts on internal RGB signals under I2C-bus control; sub-address 02H (bit resolution 1.5% of maximum contrast); data byte 3FH for maximum contrast, data byte 2CH for nominal contrast and data byte 00H for minimum contrast] dc contrast below maximum at 2CH at 00H - - 3 22 - - dB dB
Brightness adjust [acts on internal RGB signals under I2C-bus control; sub-address 00H (bit resolution 1.5% of brightness range); data byte 3FH for maximum brightness, data byte 27H for nominal brightness and data byte 00H for minimum brightness] dbr black level shift of nominal signal amplitude referred to cut-off measurement level at 3FH at 00H - - 30 -50 - - % %
White potentiometers [under I2C-bus control; sub-addresses 04H (red), 05H (green) and 06H (blue); data byte 3FH for maximum gain; data byte 22H for nominal gain and data byte 00H for minimum gain]; note 3 Gv relative to nominal gain increase of AC gain decrease of AC gain at 3FH at 00H - - 60 60 - - % %
1996 Oct 25
13
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA4680
MAX.
UNIT
RGB outputs (pins 24, 22 and 20; positive going output signals and no peak drive limitation; sub-address 0AH = 3FH); note 4 Vo(b-w) nominal output signals (black-to-white value) maximum output signals (black-to-white value) Vo Vo V24,22,20 Iint Ro d spread between RGB output signals output voltages voltage of cut-off measurement line internal current sources output resistance output clamping (BCOF = 1) - 3.2 - 6.8 2.3 - - - - - 2.0 - - - 2.5 5.0 65 - - - - - 10 0.8 2.7 - 110 V V % V V mA
Frequency response frequency response of Y path (from pin 8 to pins 24, 22, 20) frequency response of CD path (from pins 7 to 24 and 6 to 20) frequency response of RGB1 path (from pins 10 to 24, 11 to 22 and 12 to 20) f = 10 MHz f = 8 MHz f = 10 MHz 3 3 3 dB dB dB
f = 10 MHz frequency response of RGB2 path (from pins 2 to 24, 3 to 22 and 4 to 20) Sandcastle pulse detector (pin 14) CONTROL BIT SC5 = 0; 3-LEVEL; notes 5 and 6 V14 sandcastle pulse voltage for horizontal and vertical blanking pulses for horizontal pulses (line count) for burst key pulses CONTROL BIT SC5 = 1; 2-LEVEL; note 5 V14 sandcastle pulse voltage for horizontal and vertical blanking pulses for burst key pulses
-
-
3
dB
2.0 4.0 6.3
2.5 4.5 -
3.0 5.0
V V
VP + 0.7 V
2.0 4.0
2.5 4.5
3.0
V
VP + 0.7 V
1996 Oct 25
14
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
SYMBOL GENERAL I14 td tBK input current leading edge delay of the clamping pulse required burst key pulse time V14 < 0.5 V control bit DELOF = 0 control bit DELOF = 1 control bit DELOF = 0; normally used with fL control bit DELOF = 1; normally used with 2fL npulse required horizontal or burst key pulses e.g. at interlace scan during vertical blanking interval (VBW2 = 0) e.g. at progressive line scan (VBW2 = 1) Average beam current limiting (pin 15); note 7 Vc(15) Vc(15) Vbr(15) Vbr(15) contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage voltage difference for full brightness reduction - - - - 4.0 -2.0 2.5 -1.6 -100 - - 3 1.5 4 8 - 1.5 0 - - - - PARAMETER CONDITIONS MIN. TYP.
TDA4680
MAX. - - - - - 29 57
UNIT µA µs µs µs µs - -
- - - -
V V V V
Peak drive limiting voltage [pin 16; internal peak drive limiting level (Vpdl) acts on RGB outputs under I2C-bus control; sub-address 0AH]; note 8 V20/22/24 I16 V16 Vc(16) Vc(16) Vbr(16) Vbr(16) RGB output voltages charge current discharge current internal voltage limitation contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage voltage difference for full brightness reduction during peak white at 00H at 3FH - 6.5 - - 4.5 - - - - - - -1 5 - 4.0 -2.0 2.5 -1.6 3.0 - - - - - - - - V V µA mA V V V V V
1996 Oct 25
15
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
SYMBOL PARAMETER CONDITIONS MIN. - - 150 only during warming up switch-on delay 1 switch-on delay 1 during leakage measurement period - - - - - - - 0.5 TYP.
TDA4680
MAX.
UNIT
Automatic cut-off and white level control (pins 19 and 18); notes 9 to 11; see Fig.8 V19 I19 permissible voltage (also during scanning period) output current input current additional input current V24,22,20 V19(th) Vref warming up amplitude (under I2C-bus control; sub-address 0AH) voltage threshold for picture tube cathode warming up internally controlled voltage VP - 1.4 V -140 - - µA µA mA V V V
Vpdl - 0.7 - 5.0 3.0 - -
DATA BYTE 07H FOR RED REFERENCE LEVEL, DATA BYTE 08H FOR GREEN REFERENCE LEVEL AND DATA BYTE 09H FOR BLUE
REFERENCE LEVEL
V19
difference between VMEAS (cut-off or 3FH (maximum VMEAS) white level measurement voltage) and 20H (nominal VMEAS) Vref 00H (minimum VMEAS) input current internal resistance white level register (measured value within tolerance range) to Vref; I18 800 µA
1.5 - - -
- 1.0 - - 100 250
- - 0.5 800 - -
V V V µA mV
I18 R18 V19
white level measurement - white level measurement -
Storage of cut-off control voltage/output clamping voltage (pins 25, 23 and 21) I21/23/25 charge and discharge currents input currents of storage inputs Storage of leakage information (pin 17) I17 charge and discharge currents leakage current V17 voltage for reset to switch-on below during leakage measurement period outside time LM - - - 0.4 - - - 0.1 3.0 mA µA V during cut-off measurement lines outside measurement time - - 0.3 - - 0.1 mA µA
Hue control (under I2C-bus control; sub-address 03H; data byte 3FH for maximum voltage; data byte 20H for nominal voltage and data byte 00H for minimum voltage); note 12 V26 output voltage at 3FH at 20H at 00H Iint current of the internal current source at pin 26 4.8 - - 500 - 3.0 - - - - 1.0 - V V V µA
1996 Oct 25
16
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA4680
MAX.
UNIT
I2C-bus transceiver clock SCL (pin 28) fSCL VIL VIH IIL IIH tL tH tr tf input frequency range LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current clock pulse LOW clock pulse HIGH rise time fall time V28 = 0.4 V 0 - 3.0 -10 - 4.7 4.0 - - - 3.0 V27 = 0.4 V V27 = 0.4 V -10 - 3.0 - - 0.25 - - - - - - - - - - - - - - - - - 100 1.5 6.0 - 10 - - 1.0 0.3 kHz V V µA µA µs µs µs µs
I2C-bus transceiver data input/output SDA (pin 27) VIL VIH IIL IIH IOL tr tf tSU;DAT LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current LOW level output current rise time fall time data set-up time 1.5 6.0 - 10 - 1.0 0.3 - V V µA µA mA µs µs µs
Notes to the characteristics 1. The values of the -(B - Y) and -(R - Y) colour difference input signals are for a 75% colour-bar signal. 2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 . 3. The white potentiometers affect the amplitudes of the RGB output signals including the white measurement pulses. 4. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources. 5. Sandcastle pulses are compared with internal threshold voltages independent of VP. The threshold voltages separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14 exceeds the defined internal threshold voltage. The internal threshold voltages (control bit SC5 = 0) are: 1.5 V for horizontal and vertical blanking pulses 3.5 V for horizontal pulses 6.0 V for the burst key pulse. The internal threshold voltages (control bit SC5 = 1) are: 1.5 V for horizontal and vertical blanking pulses 3.5 V for the burst key pulse. 6. A sandcastle pulse with a maximum voltage equal to (VP + 0.7 V) is obtained by limiting a 12 V sandcastle pulse. 7. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness. 8. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness. The maximum RGB outputs are determined via the I2C-bus under sub-address 0AH. When an RGB output exceeds the maximum voltage, peak drive limiting is delayed by one horizontal line.
1996 Oct 25
17
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
TDA4680
9. The vertical blanking interval is defined by a vertical pulse which contains 4 (8) or more horizontal pulses; it begins with the start of the vertical pulse and ends with the end of the white measuring line. If the vertical pulse is longer than the selected vertical blanking window the blanking period ends with the end of the complete line after the end of the vertical pulse. The counter cycle time is 31 (63) horizontal pulses. If the vertical pulse contains more than 29 (57) horizontal pulses, the black level storage capacitors will be discharged while all signals are blanked. During leakage current measurement, the RGB channels are blanked to ultra-black level. During cut-off measurement one channel is set to the measurement pulse level, the other channels are blanked to ultra-black. Since the brightness adjust shifts the colour signal relative to the black level, the brightness adjust is disabled during the vertical blanking interval (see Figs 7 and 8). 10. During picture cathode warming up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 5.0 V, the monitor pulse is switched off and cut-off and white level control are activated (second switch-on delay). As soon as cut-off control stabilizes, RGB output blanking is removed. 11. Range of cut-off measurement level at the RGB outputs is 1 to 5 V. The recommended value is 3 V. 12. The hue control output at pin 26 is an emitter follower with current source. Table 5 Demodulator axes and amplification factors PARAMETER (B - Y)* demodulator axis (R - Y)* demodulator axis (R - Y)* amplification factor (B - Y)* amplification factor Table 6 PAL/SECAM and NTSC matrix; notes 1 and 2 MATRIX PAL/SECAM NTSC Notes 1. PAL/SECAM signals are matrixed by the equation: VG - Y = -0.51VR - Y - 0.19VB - Y NTSC signals are matrixed by the equations (hue phase shift of -5 degrees): VR - Y* = 1.57VR - Y - 0.41VB - Y; VG - Y* = -0.43VR - Y - 0.11VB - Y; VB - Y* = VB - Y In the matrix equations: VR - Y and VB - Y are conventional PAL demodulation axes and amplitudes at the output of the NTSC demodulator. VG - Y*, VR - Y* and VB - Y* are the NTSC-modified colour difference signals; this is equivalent to the demodulator axes and amplification factors shown in Table 5. VG - Y* = -0.27VR - Y* - 0.22VB - Y*. 2. The vertical blanking interval is selected via the I2C-bus (see Table 2 and Fig.8). Vertical blanking is determined by the vertical component of the sandcastle pulse; this vertical component has priority when it is longer than the vertical blanking interval of the transmission standard. NMEN 0 1 NTSC 0° 115° 1.97 2.03 PAL 0° 90° 1.14 2.03
1996 Oct 25
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Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
TDA4680
handbook, full pagewidth
MED701
(1)
white measurement level for green signal
(2)
cut-off measurement level for green signal
ultra-black level (1) Maximum brightness. (2) Nominal brightness.
Fig.7 Cut-off and white level measurement pulses.
621 622 623 624 625 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
vertical flyback 850 µs
V component of the sandcastle pulse
PAL, SECAM
LM (leakage current measurement time) vertical blanking interval, 22 complete lines
MR MG MB WR WG WB
V component of the sandcastle pulse
NTSC, PAL M
LM vertical blanking interval, 19 complete lines
MR MG MB WR WG WB
cut-off and white level measurement pulses
V component of the sandcastle pulse PAL, SECAM (with increased vertical blanking interval)
LM
vertical blanking interval, 25 complete lines
handbook, full pagewidth
MR MG MB WR WG WB
MED702
Fig.8 Leakage current, cut-off and white level current measurement timing diagram.
1996 Oct 25
19
handbook, full pagewidth
1996 Oct 25
25 24 23 22 21 20 19 18 17 16 15
MR WM MG MB reference HE LM
Philips Semiconductors
INTERNAL PIN CONFIGURATION
28
27
26
TDA4680
CL
CL
CL
CL
CL
CL
CL
CL
CL
Video processor with automatic cut-off and white level control
20
+ 4 5 6 7 8 9 10 11 zener diode protection for pins 27 and 28 (version V6)
1
2
3
12
13
14
MED699
+
ESD protection diode on all pins except pins 5, 9, 27 and 28
Product specification
TDA4680
Fig.9 Internal circuits.
1996 Oct 25
SCL SDA FSW2 1 28 27 26 25 24 23 22 Go 6 Ro Go Bo CI 10 82 k CON2 BZX79 C6V2
MED700
hue
handbook, full pagewidth
Philips Semiconductors
FSW2 10 nF 2 3 4 5 6 7 CG 5 220 nF Ro 4 GND CR 3 220 nF HUE 2 +12 V 1 200 V 10 nF 10 nF 75 75 10 nF 10 nF 10 nF 47 nF Y 8 9 10 11 12 13 14 15 BCL 16 CPDL 1 µF 17 CL 300 nF 18 WI 1 nF 2.2 k(2) 19 CI 9 20 Bo 8 21 GND 10 nF 10 nF 10 nF FSW1 SC 75 1N4148 1N4148 75 B1 G1 R1 -(R - Y) -(B - Y) VP B2 G2 R2 SDA 100
SCL 100
R2
G2
B2
75
75
TEST AND APPLICATION INFORMATION
-(B - Y)
-(R - Y)
TDA4680
CB 7 220 nF
Y
R1
Video processor with automatic cut-off and white level control
21
1N4148 1N4148 10 k 22 µF 3.9 k BR1(1) 3.9 k
G1
B1
FSW1
4.7 k
SC
75
75
22 µH
VP = 8 V
220 µF
beam current
(1) Insert link BR1 if average beam current is not required. (2) Value depends on video output current stages and picture tube.
Product specification
TDA4680
Fig.10 Test and application circuit.
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
PACKAGE OUTLINES
handbook, plastic dual in-line package; 28 leads (600 mil) DIP28: full pagewidth
TDA4680
SOT117-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 28 15 MH w M (e 1)
pin 1 index E
1
14
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.020 0.014 c 0.32 0.23 0.013 0.009 D (1) 36.0 35.0 1.41 1.34 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 1.7 0.067
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT117-1 REFERENCES IEC 051G05 JEDEC MO-015AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1996 Oct 25
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Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
TDA4680
PLCC28: plastic leaded chip carrier; 28 leads
SOT261-2
eE y X
eE
25
19 18 ZE
A
bp b1 w M
26
28
1
pin 1 index e k 5 e D HD 11 ZD B 4 12 k1
E
HE A A4 A1 (A 3) Lp detail X
v M A
v M B
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm inches
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.05 0.12
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
11.58 11.58 10.92 10.92 12.57 12.57 1.22 1.27 11.43 11.43 9.91 9.91 12.32 12.32 1.07
45 o
0.180 0.020 0.01 0.165
0.430 0.430 0.495 0.495 0.048 0.057 0.021 0.032 0.456 0.456 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.390 0.390 0.485 0.485 0.042 0.040 0.013 0.026 0.450 0.450
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT261-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-25
1996 Oct 25
23
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. PLCC REFLOW SOLDERING Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1996 Oct 25 24
TDA4680
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: · A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. · The longitudinal axis of the package footprint must be parallel to the solder flow. · The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Philips Semiconductors
Product specification
Video processor with automatic cut-off and white level control
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4680
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Oct 25
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