Text preview for : Tda4688.pdf part of Philips TDA4688 Philips Quality Data Sheet



Back to : Tda4688.pdf | Home

INTEGRATED CIRCUITS

DATA SHEET

TDA4688 Video processor with automatic cut-off control
Preliminary specification File under Integrated Circuits, IC02 July 1993

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control
FEATURES · Operates from an 8 V DC supply · Black level clamping of the colour difference, luminance and RGB input signals with coupling-capacitor DC level storage · Two analog RGB inputs, selected either by fast switch signals or the I2C-bus; brightness and contrast control of these RGB inputs · Saturation, contrast, brightness and white adjustment via I2C-bus · Same RGB output black levels for Y/CD and RGB input signals · Timing pulse generation from either a 2- or 3-level sandcastle pulse for clamping, vertical synchronization and cut-off timing pulses · Automatic cut-off control or clamped output selectable via I2C-bus · Automatic cut-off control with picture tube leakage current compensation · Cut-off measurement pulses after end of the vertical blanking pulse or end of an extra vertical flyback pulse · Ultra black or nominal black blanking selectable via I2C-bus in clamped output mode · Two switch-on delays to prevent discolouration before steady-state operation · Average beam current and peak drive limiting · PAL/SECAM or NTSC (Japan) matrix selection via I2C-bus · Emitter-follower RGB output stages to drive the video output stages · I2C-bus controlled DC output e. g. for hue-adjust of NTSC (multistandard) decoders · Positive amplification factor of cut-off control voltage. Note 1. SOT117-1; 1996 December 10. GENERAL DESCRIPTION The TDA4688 is a monolithic, integrated circuit with a luminance and a colour difference interface for video processing in TV receivers. (continued) QUICK REFERENCE DATA SYMBOL VP IP V8(p-p) V6(p-p) V7(p-p) V14 PARAMETER supply voltage (pin 5) supply current (pin 5) luminance input (peak-to-peak value) -(B-Y) input (peak-to-peak value) -(R-Y) input (peak-to-peak value) three-level sandcastle pulse H+V H BK two-level sandcastle pulse H+V BK Vi Vo(p-p) Tamb - - 2.5 4.5 0.7 2.0 - - - - 2.5 4.5 8.0

TDA4688

MIN. TYP. 7.2 - - - - 8.0 60 0.45 1.33 1.05

MAX. 8.8 - - - - - - - - - - - +70

UNIT V mA V V V V V V V V V V °C

RGB input signals at pins 2, 3, 4, - 10, 11 and 12 (black-to-white value) RGB outputs at pins 24, 22 and 20 (peak-to-peak value) operating ambient temperature - 0

ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER TDA4688 PINS 28 PIN POSITION DIL MATERIAL plastic CODE SOT117(1)

July 1993

2

Preliminary specification

TDA4688

Fig.1 Block diagram

handbook, full pagewidth

July 1993
hue control voltage 26
A45 to A40, A55 to A50, A65 to A60 AA5 to AA0 A05 to A00, A15 to A10, A25 to A20, A35 to A30

SDA

27 6-BIT D/A CONVERTER 19 cut-off control
RC

I2C-bus

Philips Semiconductors

SCL

28

I2C-BUS TRANSCEIVER

leakage and cut-off current input

BREN

TDA4688

1ST AND 2ND SWITCH-ON DELAYS CUT-OFF COMPARATORS

VFB 17 leakage storage

18

sandcastle pulse SANDCASTLE BK PULSE H+V DETECTOR (H) TIMING GENERATOR 16
BCOF FSDIS2, FSON2, FSDIS1, FSON1

14

SC5

peak drive limiting storage average beam current

2 x 8-BIT CONTROL REGISTERS timing pulses 15

PEAK DRIVE AND AVERAGE BEAM CURRENT LIMITING

FSW1
NMEN

13

R1 4 x 6-BIT D/A CONVERTERS 3 x 6-BIT D/A CONVERTERS

10

G1

11

Video processor with automatic cut-off control

3
R R CONTRAST ADJUST B G G B R R WHITE POINT ADJUST G B FAST SIGNAL G SOURCE SWITCH, BLANKING 1 B R BRIGHTNESS ADJUST, G BLANKING 2, MEASUREMENT B PULSES SUPPLY 5 9 VP = 8 V

B1

12

BCOF

Y

8

24 22 20

RO GO BO RGB outputs

-(R-Y)

7

-(B-Y)

6

SATURATION ADJUST

PAL/SECAM, NTSC MATRIX

CUT-OFF ADJUST, OUTPUT STAGES

FSW2

1

R2

2

G2

3

B2

4

21 B

23 G

25 R

MED760

I2C-bus data and control signals

cut-off storage

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control
PINNING SYMBOL FSW2 R2 G2 B2 VP -(B-Y) -(R-Y) Y GND R1 G1 B1 FSW1 SC BCL PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DESCRIPTION fast switch 2 input red input 2 green input 2 blue input 2 supply voltage colour difference input -(B-Y) colour difference input -(R-Y) luminance input ground red input 1 green input 1 blue input 1 fast switch 1 input sandcastle pulse input average beam current limiting input CL VFB CI BO CB GO CG RO CR HUE SDA SCL 17 18 19 20 21 22 23 24 25 26 27 28 CPDL 16

TDA4688

storage capacitor for peak drive limiting storage capacitor for leakage current vertical flyback pulse input cut-off measurement input blue output blue cut-off storage capacitor green output green cut-off storage capacitor red output red cut-off storage capacitor hue control output I2C-bus serial data input / acknowledge output I2C-bus serial clock input

GENERAL DESCRIPTION (continued) Its primary function is to process the luminance and colour difference signals from a colour decoder which is equipped e. g. with the multistandard decoder TDA4655 or TDA9160 plus delay line TDA4661 and the Picture Signal Improvement (PSI) IC TDA467X or from a Feature Module. The required input signals are · luminance and negative colour difference signals · 2- or 3-level sandcastle pulse for internal timing pulse generation · I2C-bus data and clock signals for microprocessor control Two sets of analog RGB colour signals can also be inserted, e.g. one from a peritelevision connector and the other from an on-screen display generator. The TDA4688 has I2C-bus control of all parameters and functions with automatic cut-off control of the picture tube cathode currents. It provides RGB output signals for the video output stages.

The TDA4688 is a simplified, pin compatible (except pin 18) version of the TDA4681. The module address via the I2C-bus can be used for both ICs; where a function is not included in the TDA4688 then the I2C-bus command is not executed. The differences with the TDA4681 are: ­ no automatic white level control; the white levels are determined directly by the I2C-bus data ­ RGB reference levels for automatic cut-off control are not adjustable via I2C-bus ­ clamping delay is fixed ­ only contrast and brightness adjust for the RGB input signals ­ the measurement lines are triggered either by the trailing edge of the vertical component of the sandcastle pulse or by the trailing edge of an optional external vertical flyback pulse (on pin 18), according to which occurs first. The difference compared to TDA4687 is the japanese type NTSC matrix.

July 1993

4

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688
I2C-BUS CONTROL

handbook, halfpage

FSW2 1 R2 2 G2 3 B2 4 VP 5 -(B-Y) 6 -(R-Y) 7

28 SCL 27 SDA 26 HUE 25 CR 24 RO 23 CG

The I2C-bus transmitter provides the data bytes to select and adjust the following functions and parameters: · brightness adjust · saturation adjust · contrast adjust · DC output e. g. for hue control · RGB gain adjust · peak drive limiting level adjust · selects either 3-level or 2-level (5 V) sandcastle pulse · enables cut-off control / enables output clamping (2 different modes) · selects either PAL/SECAM or NTSC matrix · enables/disables synchronization of the execution of I2C-bus commands with the vertical blanking interval · enables Y-CD, RGB1 or RGB2 input.

TDA4688
Y 8 GND 9 R1 10 G1 11 B1 12 FSW1 13 SC 14
MED761

22 GO 21 CB 20 BO 19 CI 18 VFB 17 CL 16 CPDL 15 BCL

Fig.2 Pin configuration.

I2C-BUS TRANSMITTER AND DATA TRANSFER I2C-bus specification The I2C-bus is a bi-directional, two-wire, serial data bus for intercommunication between ICs in an equipment. The microcontroller transmits data to the I2C-bus receiver in the TDA4688 over the serial data line SDA (pin 27) synchronized by the serial clock line SCL (pin 28). Both lines are normally connected to a positive voltage supply through pull-up resistors. Data is transferred when the SCL line is LOW. When SCL is HIGH the serial data line SDA must be stable. A HIGH-to-LOW

transition of the SDA line when SCL is HIGH is defined as a start bit. A LOW-to-HIGH transition of the SDA line when SCL is HIGH is defined as a stop bit. Each transmission must start with a start bit and end with a stop bit. The bus is busy after a start bit and is only free again after a stop bit has been transmitted. I2C-bus receiver (microcontroller write mode) Each transmission to the I2C-bus receiver consists of at least three bytes following the start bit. Each byte is acknowledged by an acknowledge bit immediately following each byte. The first byte is the Module ADdress

(MAD) byte, also called slave address byte. This includes the module address, 10001002 for the TDA4688. The TDA4688 is a slave receiver (R/W = 0), therefore the module address byte is 100010002 (88 Hex), see Fig.3. The length of a data transmission is unrestricted, but the module address and the correct sub-address must be transmitted before the data byte(s). The order of data transmission is shown in Fig.4 and Fig.5. Without auto-increment (BREN = 0 or 1) the Module ADdress (MAD) byte is followed by a Sub-ADdress (SAD) byte and one data byte only (Fig.4).

July 1993

5

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

handbook, full pagewidth

MSB 1 0 0 0 1 0

LSB 0 0 R/W
MED710

ACK

module address

Fig.3 The module address byte.

handbook, full pagewidth

STA

MAD SAD

STO
MED697

START condition

data byte

STOP condition

Fig.4 Data transmission without auto-increment (BREN = 0 or 1).

handbook, full pagewidth

STA START condition

MAD SAD

STO
MED698

data byte data bytes

STOP condition

Fig.5 Data transmission with auto-increment (BREN = 0).

July 1993

6

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control
Auto-increment The auto-increment format enables quick slave receiver initialization by one transmission, when the I2C-bus control bit BREN = 0 (see control register bits of Table 1). If BREN = 1 auto-increment is not possible. If the auto-increment format is selected, the MAD byte is followed by an SAD byte and by the data bytes of consecutive sub-addresses (Fig.5). All sub-addresses from 00 to 0F are automatically incremented, the sub-address counter wraps round from 0F to 00. Reserved sub-addresses 07, 08, 09, 0B and 0F are treated as legal but have no effect. Sub-addresses outside the range 00 and 0F are not acknowledged by the device. The sub-addresses are stored in the TDA4688 to address the following parameters and functions, see Table 1: · brightness adjust · saturation adjust · contrast adjust · hue control voltage · RGB gain adjust · peak drive limiting adjust · control register functions. The data bytes (D7-D0 of Table 1) provide the data of the parameters and functions for video processing. Control register 1 NMEN (NTSC-Matrix ENable): 0 = PAL/SECAM matrix 1 = NTSC matrix. BREN (Buffer Register ENable): 0 = new data is executed as soon as it is received 1 = data is stored in buffer registers and is transferred to the data registers during the next vertical blanking interval. The I2C-bus receiver does not accept any new data until this data is transferred into the data registers. SC5 (SandCastle 5 V): 0 = 3-level sandcastle pulse 1 = 2-level (5 V) sandcastle pulse. Control register 2 FSON2 - Fast Switch 2 ON FSDIS2 - Fast Switch 2 DISable FSON1 - Fast Switch 1 ON FSDIS1 - Fast Switch 1 DISable The RGB input signals are selected by FSON2 and FSON1 or FSW2 and FSW1:

TDA4688
· FSON2 has priority over FSON1; · FSW2 has priority over FSW1; · FSDIS1 and FSDIS2 disable FSW1 and FSW2 (see Table 2). BCOF - Black level Control OFf: 0 = automatic cut-off control enabled 1 = automatic cut-off control disabled; RGB outputs are clamped to fixed DC levels. Control register 3 MOD2 (output clamp MODe2): 0 = inactive 1 = output clamping, but brightness inactive When MOD2 = 1 and BCOF = 1 output clamp is enabled and brightness adjust is disabled (for clamping purpose of following RGB receivers). (BCOF = 0) AND (MOD2 = 1) is senseless When the supply voltage has dropped below approximately 6.0 V (usually occurs when the TV receiver is switched on or the supply voltage is interrupted) all data and function bits are set to 01Hex.

July 1993

7

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control
Table 1 Sub-address (SAD) and data bytes. SAD FUNCTION (HEX) Brightness Saturation Contrast Hue control voltage Red gain Green gain Blue gain Reserved Reserved Reserved Peak drive limit Reserved Control register 1 Control register 2 Control register 3 Reserved Note to Table 1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 7 0 0 0 0 0 0 0 0 0 0 0 x SC5 x x x 6 0 0 0 0 0 0 0 0 0 0 0 x x x x x 5 A05 A15 A25 A35 A45 A55 A65 x x x AA5 x BREN x MOD2 x 4 A04 A14 A24 A34 A44 A54 A64 x x x AA4 x x BCOF x x 3 A03 A13 A23 A33 A43 A53 A63 x x x AA3 x NMEN FSDIS2 x x 2 A02 A12 A22 A32 A42 A52 A62 x x x AA2 x x FSON2 x x MSB DATA BYTE

TDA4688

LSB 1 A01 A11 A21 A31 A41 A51 A61 x x x AA1 x x FSDIS1 x x 0 A00 A10 A20 A30 A40 A50 A60 x x x AA0 x x FSON1 x x

1. x is `don't care', but for software compatibility with other or future video ICs it is recommended to set all `x' to `0'. Table 2 Signal input selection by the fast source switches. I2C-BUS CONTROL BITS FSON2 L FSDIS2 L FSON1 L FSDIS1 L ANALOG SWITCH SIGNALS FSW2 (PIN 1) L L H L L L L L H Note to Table 2 1. Where L is a logic LOW (< 0.4 V), H is a logic HIGH (> 0.9 V), X is `don't care', and ON is the selected input signal. L L H H H X L H L L H X H X L H X X L H L H X X X X X FSW1 (PIN 13) L H X X X X X L H X X X ON ON ON ON ON ON ON ON ON ON ON INPUT SELECTED RGB2 RGB1 Y/CD ON

July 1993

8

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP VI PARAMETER supply voltage (pin 5) input voltage (pins 1 to 8, 10 to 13, 16, 21, 23 and 25) input voltage (pins 15, 18 and 19) input voltage (pins 27 and 28) V14 IAV IM I26 Tstg Tamb Ptot sandcastle pulse voltage average current (pins 20, 22 and 24) peak current (pins 20, 22 and 24) output current storage temperature operating ambient temperature total power dissipation - -0.1 -0.7 -0.1 -0.7 -10 -20 -8 -20 0 - MIN. 8.8 VP VP + 0.7 8.8 VP + 5.8 4 4 0.6 +150 +70 1.2 MAX.

TDA4688

UNIT V V V V V mA mA mA °C °C W

July 1993

9

handbook, full pagewidth

July 1993
25 24 23 22 21 20 19 18 17 16 15

Philips Semiconductors

28

27

26

TDA4688

CL

CL

CL

CL

CL

CL

CL

CL

CL

+ +

Video processor with automatic cut-off control

10
4 5 6 7 8 9 10 11 12 13 14

1

2

3

MED762

+

diode protection on all pins except pins 5, 14, 27 and 28

Preliminary specification

TDA4688

Fig.6 Internal circuits.

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

CHARACTERISTICS All voltages are measured in test circuit of Fig.7 with respect to GND (pin 9); VP = 8.0 V; Tamb = +25 °C: - at nominal signal amplitudes (black-to-white) at output pins 24, 22 and 20, - at nominal settings of brightness, contrast, saturation and white level control, - without beam current or peak drive limiting; unless otherwise specified. SYMBOL VP IP V6(p-p) V7(p-p) V6,7 I6,7 R6,7 Vi(p-p) V8 I8 R8 PARAMETER supply voltage (pin 5) supply current (pin 5) -(B-Y) input (peak-to-peak value) -(R-Y) input (peak-to-peak value) internal DC bias voltage input current input resistance CONDITIONS MIN. 7.2 - - - - - ±100 10 - - - ±100 10 - - - ±100 10 - - - ±100 10 60 TYP. 8.0 - - - - ±0.1 - - - - ±0.1 - - - - ±0.1 - - - - ±0.1 - - MAX. 8.8 UNIT V mA

Colour difference inputs notes 1 and 2 notes 1 and 2 at black level clamping during line scan at black level clamping Luminance/sync (VBS) luminance input at pin 8 (peak-to-peak value) internal DC bias voltage input current input resistance note 2 at black level clamping during line scan at black level clamping R1, G1 and B1 inputs Vi(p-p) V10/11/12 I10/11/12 R10/11/12 black-to-white input signals at pins 10, 11 and 12 (peak-to-peak value) internal DC bias voltage input current input resistance note 2 at black level clamping during line scan at black level clamping R2, G2 and B2 inputs Vi(p-p) V2/3/4 I2/3/4 R2/3/4 black-to-white input signals at pins 2, 3 and 4 (peak-to-peak value) internal DC bias voltage input current input resistance note 2 at black level clamping during line scan at black level clamping PAL/SECAM and NTSC matrix (note 3) PAL/SECAM matrix NTSC matrix control bit NMEN = 0 control bit NMEN = 1 0.7 5.7 - - - V V µA µA M 0.7 5.7 - - - V V µA µA M 0.45 4.1 - - - V V µA µA M 1.33 1.05 4.1 - - - V V V µA µA M

July 1993

11

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Fast signal switch FSW1 to select Y, CD or R1, G1, B1 inputs Control bits FSDIS1, FSON1 (see Table 2) V13 R13 t voltage to select Y and CD voltage range to select R1, G1, B1 internal resistance to ground difference between transit times for signal switching and signal insertion - 0.9 - - - - 4.0 - 0.4 5.0 - 10 V V k ns

Fast signal switch FSW2 to select Y, CD / R1, G1, B1 or R2, G2, B2 inputs Control bits FSDIS2, FSON2 (see Table 2) V1 R1 t voltage to select Y, CD/R1, G1, B1 voltage range to select R2, G2, B2 internal resistance to ground difference between transit times for signal switching and signal insertion - 0.9 - - - - 4.0 - 0.4 5.0 - 10 V V k ns

Saturation adjust Acts on -(R-Y) and -(B-Y) signals under I2C-bus control, sub-address 01Hex (bit resolution 1.5% of maximum saturation); data byte 3FHex for maximum saturation data byte 23Hex for nominal saturation data byte 00Hex for minimum saturation ds saturation below maximum at 23Hex at 00Hex; f = 100 kHz Contrast adjust Acts on internal RGB signals under I2C-bus control, sub-address 02Hex (bit resolution 1.5% of maximum contrast); data byte 3FHex for maximum contrast data byte 22Hex for nominal contrast data byte 00Hex for minimum contrast dc contrast below maximum at 22Hex at 00Hex Brightness adjust Acts on internal RGB signals under I2C-bus control, sub-address 00Hex (bit resolution 1.5% of maximum brightness); data byte 3FHex for maximum brightness data byte 26Hex for nominal brightness data byte 00Hex for minimum brightness dbr black level shift of nominal signal amplitude referred to cut-off measurement level at 3FHex at 00Hex - - 30 -50 - - % % - - 5 22 - - dB dB - - 5 50 - - dB dB

July 1993

12

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

White potentiometers, under I2C-bus control, sub-addresses 04Hex (red), 05Hex (green) and 06Hex (blue); note 4. data byte 3FHex for maximum gain data byte 19Hex for nominal gain data byte 00Hex for minimum gain Gv relative to nominal gain: increase of gain decrease of gain RGB outputs pins 24, 22 and 20 (positive going output signals; peak drive limiter set = 3FHex; note 5. Vo(b-w) nominal output signal amplitudes (black-to-white value) maximum output signal amplitudes (black-to-white value) Vo Vo V24,22,20 Iint Ro d spread between RGB output signals minimum output voltages maximum output voltages voltage of cut-off measurement line equivalent to voltage during ultra-black internal current sources output resistance BCOF = 1; output clamping - 3.0 - - 6.8 2.3 - - - - - - 2 - - - - 2.5 5.0 20 - - - - - - 10 0.8 - 2.7 - - V V % V V V mA at 3FHex at 00Hex - - 50 50 - - % %

Frequency response frequency response of Y path (from pin 8 to pins 24, 22, 20) frequency response of CD path (from pins 7 to 24 and 6 to 20) frequency response of RGB1 path (from pins 10 to 24, 11 to 22 and 12 to 20) frequency response of RGB2 path (from pins 2 to 24, 3 to 22 and 4 to 20) Sandcastle pulse detector (control bit SC5 = 0) Three level; notes 6 and 7 V14 required voltage range for H and V blanking pulses for H pulses (line count) for burst key pulses (clamping) Sandcastle pulse detector (control bit SC5 = 1) Two level; notes 6 and 7 2.0 4.0 7.6 2.5 4.5 - 3.0 5.0 VP + 5.8 V V V f = 10 MHz f = 8 MHz f = 10 MHz f = 10 MHz 3 3 3 3 dB dB dB dB

July 1993

13

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

SYMBOL V14

PARAMETER required voltage range for H and V blanking pulses for burst key pulses

CONDITIONS

MIN. 2.0 4.0 - - - 4.5 - - - - - -

TYP. 2.5 4.5 - 1.5 - - 5.0 -

MAX. 3.0 VP + 5.8 -100 -

UNIT V V µA µs

Sandcastle pulse detector I14 td V18 output current leading edge delay of the clamping pulse V14 = 0 V

VFB (note 7) vertical flyback pulse internal voltage I18 Vc(15) Vc(15) Vbr(15) Vbr(15) input current for LOW for HIGH pin 18 open-circuit; note 8 2.5 - - 5 - - - - V V V µA

Average beam current limiting (note 9) contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage voltage difference for full brightness reduction 4.0 -2.0 2.5 -1.6 V V V V

Peak drive limiting voltage (note 10) Internal peak drive limiting level (Vpdl) acts on RGB outputs I2C-bus control, sub-address 0AHex V20/22/24 I16 V16 Vc(16) Vc(16) Vbr(16) Vbr(16) level for minimum RGB outputs level for maximum RGB outputs charge current discharge current internal voltage limitation contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage voltage difference for full brightness reduction during peak white at byte 00Hex at byte 3FHex - 7.0 - - 4.5 - - - - - - -1 5 - 4.0 -2.0 2.5 -1.6 3.0 - - - - - - - - V V µA mA V V V V V

July 1993

14

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Automatic cut-off controls (notes 7, 11, 12 and 13) See Fig.9 V19 I19 external voltage output current input current additional input current V24,22,20 V19 monitor pulse amplitude (under I2C-bus control, sub-address 0AHex) voltage threshold for picture tube cathode warm-up internally controlled voltage (VREF) V19 voltage difference between VMEAS (cut-off measurement voltage) and VREF charge and discharge currents current Leakage storage I17 charge and discharge currents current V17 threshold voltage for reset to switch-on state during leakage measurement period outside measurement - - - ±0.4 - 2.5 - ±0.1 - mA µA V during cut-off measurement lines outside measurement switch-on delay 1 switch-on delay 1; note 12 switch-on delay 1 during leakage measurement period - - 150 - - - - - - - - 0.5 Vpdl - 1.0 4.5 2.7 1.0 VP - 1.4 -60 - - - - - - V µA µA mA V V V V

Cut-off storage I21/23/25 - - ±0.3 - - ±0.1 mA µA

Hue control (note 14) Under I2C-bus control, sub-address 03Hex Data byte 3FHex for maximum voltage Data byte 20Hex for nominal voltage Data byte 00Hex for minimum voltage V26 output voltage at byte 3FHex at byte 20Hex at byte 00Hex Iint current of the internal current source at pin 26 4.8 - - 500 - 3.0 - - - - 1.2 - V V V µA

July 1993

15

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I2C-bus receiver clock SCL (pin 28) fSCL VIL VIH IIL IIH td tr tf input frequency range LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current pulse delay time LOW pulse delay time HIGH rise time fall time 0 - 3.0 - - 4.7 4.0 - - - 3.0 - - 3.0 - - 0.25 - - - - - - - - - - - - - - - - - 100 1.5 6.0 -10 10 - - 1.0 0.3 kHz V V µA µA µs µs µs µs

I2C-bus receiver data input/output SDA (pin 27) VIL VIH IIL IIH IOL tr tf tSU;DAT LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current LOW level output current rise time fall time data set-up time 1.5 6.0 -10 10 - 1.0 0.3 - V V µA µA mA µs µs µs

Notes to the characteristics 1. The values of the -(B-Y) and -(R-Y) colour difference input signals are for a 75% colour-bar signal. 2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 . 3. PAL/SECAM signals are matrixed by the equation: VG-Y = -0.51VR-Y - 0.19VB-Y NTSC signals are matrixed by the equations (hue phase shift of -2 degrees): VR-Y* = 1.39VR-Y - 0.07VB-Y; VG-Y* = -0.46VR-Y - 0.15VB-Y; VB-Y* = VB-Y In the matrix equations: VR-Y and VB-Y are conventional PAL demodulation axes and amplitudes at the output of the NTSC demodulator. VG-Y*, VR-Y* and VB-Y* are the NTSC-modified colour difference signals; this is equivalent to the demodulator axes and amplification factors shown in table 3. 4. The white potentiometers affect the amplitudes of the RGB output signals. 5. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources. 6. Sandcastle pulses are compared with internal threshold voltages independent of VP. The threshold voltages separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14 exceeds the defined internal threshold voltage. The internal threshold voltages (control bit SC5 = 0) are: 1.5 V for horizontal and vertical blanking pulses (H and V blanking pulses), 3.5 V for horizontal pulses, 6.5 V for the burst key pulse. The internal threshold voltages, control bit SC5 = 1, are: 1.5 V for horizontal and vertical blanking pulses, 3.5 V for the burst key pulse.

July 1993

16

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

7. Vertical signal blanking is determined by the vertical component of the sandcastle pulse. The leakage and the RGB cut-off measurement lines are positioned in the first four complete lines after the end of the vertical component. In this case, the RGB output signals are blanked until the end of the last measurement line; see Fig.9(a). If an extra vertical flyback pulse VFB is applied to pin 18, the four measurement lines start in the first complete line after the end of the VFB pulse; see Fig.9b. In this case, the output signals are blanked either until the end of the last measurement line or until the end of the vertical component of the sandcastle pulse, according to which occurs last. 8. If no VFB pulse is applied, pin 18 can be left open-circuit or connected to VP. If pin 18 is always LOW neither automatic cut-off control nor output clamping can happen. 9. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness. 10. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness. The maximum RGB outputs are determined via the I2C-bus under sub-address 0AHex. When an RGB output exceeds the maximum voltage, peak drive limiting is delayed by one horizontal line. 11. During leakage current measurement, the RGB channels are blanked to ultra-black level. During cut-off measurement one channel is set to the measurement pulse level, the other channels are blanked to ultra-black. Since the brightness adjust shifts the colour signal relative to the black level, the brightness adjust is disabled during the vertical blanking interval (see Fig.8 and Fig.9). 12. During picture cathode warm-up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 4.5 V, the monitor pulse is switched off and cut-off control is activated (second switch-on delay). As soon as cut-off control stabilizes, RGB output blanking is removed. 13. The cut-off measurement level range at the RGB outputs is 1 to 5 V. The recommended value is 3 V. 14. The hue control output at pin 26 is an emitter follower with current source. Table 3 NTSC (B-Y)* demodulator axis (R-Y)* demodulator axis (G-Y)* demodulator axis (R-Y)* amplification factor (B-Y)* amplification factor (G-Y)* amplification factor 0° 95° 240° 1.59 2.03 0.606 0° 90° 236° 1.14 2.03 0.698 PAL

July 1993

17

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

SCL SDA
handbook, full pagewidth

hue

FSW2 R2 G2 B2 75 75 75 75 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 47 nF

FSW2 R2 G2 B2 VP -(B-Y) -(R-Y) Y GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22

SCL 100 SDA 100 HUE CR RO CG GO CB BO CI VFB CL 330 nF 1 µF 82 k 220 nF 220 nF 220 nF 1 2 3 4 5 6 7 8 9 10 CON2 BZX79 C6V2 VFB (optional) RO GO BO CI GND 200 V +12 V

-(B-Y) -(R-Y) Y

TDA4688
21 20 19 18 17 16 15

R1 G1 B1 FSW1 SC 75 75 22 µH VP = 8 V 75 75

10 nF 10 nF 10 nF

R1 G1 B1 FSW1 SC

CPDL BCL

1N4148

MED763

3.9 k 220 µF 3.9 k beam current information

1N4148 10 k 22 µF

BR1(1)

(1) Insert link BR1 if average beam current limiting is not applied.

Fig.7 Test and application circuit.

handbook, full pagewidth

MED713

maximum brightness

nominal brightness cut-off measurement line for red signal

ultra-black

Fig.8 Cut-off measurement pulse.

July 1993

18

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control

TDA4688

handbook, full pagewidth

sandcastle pulse with vertical component

R channel LM MR

G channel LM MG

B channel LM (a) Timing controlled by sandcastle pulse LM = leakage current measurement time MR, MG, MB = R, G, B cutt-off measurement pulses vertical flyback pulse (VFB) MB

R channel LM MR

G channel LM MG

B channel LM MB
MED714

(b) Timing controlled by additional vertical flyback pulse (VFB)

Fig.9 Leakage and cut-off current measurement timing diagram.

July 1993

19

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control
PACKAGE OUTLINE
handbook, plastic dual in-line package; 28 leads (600 mil) DIP28: full pagewidth

TDA4688

SOT117-1

seating plane

D

ME

A2

A

L

A1 c Z e b1 b 28 15 MH w M (e 1)

pin 1 index E

1

14

0

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.020 0.014 c 0.32 0.23 0.013 0.009 D (1) 36.0 35.0 1.41 1.34 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 1.7 0.067

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT117-1 REFERENCES IEC 051G05 JEDEC MO-015AH EIAJ EUROPEAN PROJECTION

ISSUE DATE 92-11-17 95-01-14

July 1993

20

Philips Semiconductors

Preliminary specification

Video processor with automatic cut-off control
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values

TDA4688

with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

July 1993

21