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INTEGRATED CIRCUITS
DATA SHEET
TDA4851 Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
Preliminary specification File under Integrated Circuits, IC02 November 1992
Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
FEATURES · VGA operation fully implemented including alignment-free vertical and E/W amplitude presettings · 4th VGA mode easy applicable (XGA, Super VGA) · Autosync operation externally selectable · Low jitter · All adjustments DC-controllable · Alignment-free oscillators · Sync separators for video or horizontal and vertical TTL sync levels regardless of polarity · Horizontal oscillator with PLL1 for sync and PLL2 for flyback · Constant vertical and E/W amplitude in autosync operation QUICK REFERENCE DATA SYMBOL VP IP Vi sync positive supply voltage (pin 1) supply current AC-coupled composite video signal with negative-going sync (peak-to-peak value, pin 9) sync slicing level DC-coupled TTL-compatible horizontal sync signal (peak-to-peak value, pin 9) slicing level DC-coupled TTL-compatible vertical sync signal (peak-to-peak value, pin 10) slicing level Io V Io H Tamb vertical differential output current (peak-to-peak value, pins 5 and 6) horizontal sink output current on pin 3 operating ambient temperature range PARAMETER MIN. TYP. 9.2 - - - 1.7 1.2 1.7 1.2 - - 0 12 40 1 120 - 1.4 - 1.4 1 - - GENERAL DESCRIPTION
TDA4851
· DC-coupling to vertical power amplifier · Internal supply voltage stabilization with excellent ripple rejection to ensure stable geometrical adjustments
The TDA4851 is a monolithic integrated circuit for economical solutions in VGA/XGA and autosync monitors. The IC incorporates the complete horizontal and vertical small signal processing. VGA-dependent mode detection and settings are performed on chip. In conjunction with TDA4860/61/65, or TDA8351 (vertical output circuits) the ICs offer an extremely advanced system solution.
MAX. 16 - - - - 1.6 - 1.6 - 60 +70
UNIT V mA V mV V V V V mA mA °C
ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER TDA4851 Note 1. SOT146-1; 1996 November 26. PINS 20 PIN POSITION DIL MATERIAL plastic CODE SOT146(1)
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
TDA4851
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Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
PINNING SYMBOL VP FLB HOR GND VERT1 VERT2 MODE CLBL HVS VS EW CVA RVA REW RVOS CVOS PLL1 RHOS CHOS PLL2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION positive supply voltage horizontal flyback input horizontal output ground (0 V) vertical output 1; negative-going sawtooth vertical output 2; positive-going sawtooth 4th mode output and autosync input clamping/blanking pulse output horizontal sync/video input vertical sync input E/W output (parabola to driver stage) capacitor for amplitude control vertical amplitude adjustment input E/W amplitude adjustment input (parabola) vertical oscillator resistor vertical oscillator capacitor PLL1 phase horizontal oscillator resistor horizontal oscillator capacitor PLL2 phase
TDA4851
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction An AC-coupled video signal or a DC-coupled TTL sync signal (H only or composite sync) is input on pin 9. Video signals are clamped with top sync on 1.28 V, and are sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync. DC-coupled TTL sync signals are also sliced at 1.4 V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected. The polarity information is fed to the VGA mode detector. The corrected sync is input signal for the vertical sync integrator and the PLL1 stage. Vertical sync separator, polarity correction and vertical sync integrator DC-coupled vertical TTL sync signals may be applied to pin 10. They are sliced at 1.4 V. The polarity of the separated sync is detected by internal integration, then the polarity is corrected. The polarity information is fed to the
VGA mode detector. If pin 10 is not used, it must be connected to ground. The separated Vi sync signal from pin10, or the integrated composite sync signal from pin 9 (TTL or video) triggers directly the vertical oscillator. VGA mode detector and mode output The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from VP to pin 7) is necessary to match this function. In all three VGA modes the correct amplitudes are activated. The presence of the 4th mode is indicated by a HIGH on pin 7. This signal can be used externally to switch any horizontal or vertical parameters. VGA mode detector input For autosync operation the voltage on pin 7 must be externally forced to a level of < 50 mV. Vertical amplitude pre-settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 µs to 300 µs (575 µs is
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 Hz up to 110 Hz. Clamping and V-blanking generator A combined clamping and V-blanking pulse is available on pin 8 (suitable for the video pre-amplifier TDA4881). The lower level of 1.9 V is the blanking signal derived from the vertical blanking pulse from the internal vertical oscillator. Vertical blanking equals the delay between vertical sync and start of vertical scan. By this, an optimum blanking is achieved for VGA/XGA and autosync operation (selectable via pin 7). The upper level of 5.4 V is the horizontal clamping pulse with an internally fixed pulse width of 0.8 µs. A monoflop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse. If composite sync is applied, one clamping pulse per H-period is generated during V-sync. The phase of the clamping pulse may change during V-sync (see Fig.8). PLL1 phase detector The phase detector is a standard type using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to pin 17. If composite sync is applied, the disturbed control voltage is corrected during V-sync (see Fig.8). Horizontal oscillator This oscillator is of the relaxation type and requires a fixed capacitor of 10 nF at pin 19. By changing the current into pin 18 the whole frequency range from 13 to 100 kHz can be covered. The current can be generated either by a frequency to voltage converter or by a resistor. A frequency adjustment may also be added if necessary. The PLL1 control voltage at pin 17 modulates via a buffer stage the oscillator thresholds. A high DC-loop gain ensures a stable phase relationship between horizontal sync and line flyback pulses. PLL2 phase detector This phase detector is similar to the PLL1 phase detector. Line flyback signals (pin 2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses. minimum frequency offset between f0 and the lowest trigger frequency spread of IC spread of R (22 k) spread of C (0.1 µF) Horizontal driver
TDA4851
A certain amount of phase adjustment is possible by injecting a DC current from an external source into the PLL2 filter capacitor at pin 20.
This open-collector output stage (pin 3) can directly drive an external driver transistor. The saturation voltage is less than 300 mV at 20 mA. To protect the line deflection transistor, the horizontal output stage does not conduct for VP < 6.4 V (pin 1). Vertical oscillator and amplitude control This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions. The free-running frequency f0 is determined by the values of RVOS and CVOS. The recommended values should be altered marginally only to preserve the excellent linearity and noise performance. The vertical drive currents I5 and I6 are in relation to the value of RVOS. Therefore, the oscillator frequency must be determined only by CVOS on pin 16. 1 f 0 = ----------------------------------------------------10.8 × R VOS × C VOS To achieve a stabilized amplitude the free-running frequency f0 (without adjustment) must be lower than the lowest occurring sync frequency. The following contributions can be assumed:
10% ±3% ±1% ±5% 19%
50 Result: f 0 = ---------- Hz = 42 Hz 1.19 (for 50 to 110 Hz application)
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
Table 1 VGA modes H / V SYNC POLARITY +/- -/+ -/- +/+ */* 31.45 31.45 31.45 fixed by external circuitry fixed by external circuitry FREQUENCY H (kHz) FREQUENCY V (Hz) 70 70 60 - - NUMBER OF ACTIVE LINES 350 400 480 - -
TDA4851
MODE 1 2 3 4 autosync
MODE OUTPUT PIN 7 LOW LOW LOW HIGH forced to GND
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VP V3,7 V8 Vn I2 I3 I7 I8 Tstg Tamb Tj VESD supply voltage (pin 1) voltage on pins 3 and 7 voltage on pin 8 voltage on pins 5, 6, 9, 10, 13, 14 and 18 current on pin 2 current on pin 3 current on pin 7 current on pin 8 storage temperature range operating ambient temperature range maximum junction temperature electrostatic handling for all pins (note 1) PARAMETER MIN. -0.5 -0.5 -0.5 -0.5 - - - - -55 0 0 - MAX. 16 16 7 6.5 ±10 100 20 -10 +150 70 +150 ±400 UNIT V V V V mA mA mA mA °C °C °C V
Note to the Limiting Values 1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient in free air THERMAL RESISTANCE 65 K/W
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
CHARACTERISTICS VP = 12 V; Tamb = +25 °C; measurements taken in Fig.3 unless otherwise specified SYMBOL VP IP PARAMETER positive supply voltage (pin 1) supply current I18 = -1.05 mA I18 = -3.388 mA Internal reference voltage Vref TC PSRR VP internal reference voltage temperature coefficient power supply ripple rejection supply voltage (pin 1) to ensure all internal reference voltages V10 = 5 V sync on green - 1.1 RS = 50 Vi sync > 200 mV during sync V9 > 1.5 V fH = 31 kHz; I18 = -1.050 mA fH = 64 kHz; I18 = -2.169 mA fH = 100 kHz; I18 = -3.388 mA Horizontal sync input (DC-coupled, TTL-compatible) Vi sync sync input signal (peak-to-peak value, pin 9) slicing level tp tr, tf I9 minimum pulse width rise time and fall time input current V9 = 0.8 V V9 = 5.5 V Automatic horizontal polarity switch tp H/tH horizontal sync pulse width related to tH (duty factor for automatic polarity correction) delay time for changing sync polarity H-sync on pin 9 - - 1.7 1.2 700 10 - - - 1.4 - - - - 90 - - 1.3 7 3.5 2.5 300 1.28 120 - 80 2 10 5 3.4 Tamb = +20 to +100 °C f = 1 kHz sinewave f = 1 MHz sinewave 6.0 - 60 25 9.2 6.25 - 75 35 - CONDITIONS MIN. 9.2 - - 12 36 40 TYP.
TDA4851
MAX. 16 44 49
UNIT V mA mA
6.5 ±90 - - 16
V 10-6/K dB dB V
Composite sync input (AC-coupled) Vi sync sync amplitude of video input signal (pin 9) top sync clamping level slicing level above top sync level RS r9 I9 tint allowed source resistance for 7% duty factor differential input resistance charging current of coupling capacitor vertical sync integration time to generate vertical trigger pulse
- 1.5 150 1.5 - 3 13 6.5 4.5
mV V mV k µA µs µs µs
- 1.6 - 500 -200 10
V V ns ns µA µA
30
%
tp
0.3
-
1.8
ms
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
SYMBOL PARAMETER CONDITIONS V-sync on pin 10 1.7 1.2 0 < V10 < 5.5 V - - VGA mode I7 = 6 mA mode 4 modes 1, 2 and 3 - - 2 0.275 - - - 1.4 - - MIN. TYP.
TDA4851
MAX. - 1.6 ±10 300
UNIT
Vertical sync input (DC-coupled, TTL-compatible) Vi sync sync input signal (peak-to-peak value, pin 10) slicing level I10 tp V input current maximum vertical sync pulse width for automatic vertical polarity switch
V V µA µs
Horizontal mode detector output V7 output saturation voltage LOW (for Modes 1, 2 and 3) output voltage HIGH I7 load current range to force VGA mode-dependent vertical and parabola amplitudes output current VGA / autosync mode switch V7 input voltage LOW to force autosync mode
0.33 VP 6
V V mA
mode 4
-
0 -
-
mA
0 Fig.6 - internal V blanking H-sync on pin 9 H and V scanning 1.6 5.15 2.3 - V8 = 3 V Vref = 6.25 V R15 = 22 k; C16 = 0.1 µF no f0 adjustment R15 = 22 k measured on pin 8 500 V7 < 50 mV 240 - - - 50 2.8 0.6 -
50
mV
Horizontal clamping / blanking generator output V8 output voltage LOW blanking output voltage clamping output voltage I8 t8 tclp S internal sink current for all output levels external load current clamping pulse start clamping pulse width steepness of rise and fall times
- 1.9 5.4 2.9 - 0.8 60
0.9 2.2 5.65 3.5 -3.0 1.0 75 - 110 3.2
V V V mA mA µs ns/V
with end of H-sync
Vertical oscillator f0 fv V15 td vertical free-running frequency nominal vertical sync range voltage on pin 15 delay between sync pulse and start of vertical scan in VGA/XGA mode, activated by an external resistor on pin 7 in autosync mode I12 C12 control current for amplitude control capacitor for amplitude control
42 - 3.0
Hz Hz V
575 300 ±200 -
650 360 - 0.18
µs µs µA µF
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
SYMBOL PARAMETER CONDITIONS Fig.7 mode 3; I13 > -135 µA; R15 = 22 k Io = 1 mA 0.9 - - - Io max (100%) Io min (typically 58%) Io/t VGA mode-dependent pre-settings activated by an external resistor on pin 7 Mode 1 Mode 2 Mode 3 Mode 4 autosync operation (VGA operation disabled) Horizontal comparator PLL1 V17 I17 fosc upper control voltage limitation lower control voltage limitation control current Fig.6 Horizontal oscillator centre frequency deviation of centre frequency temperature coefficient H/tH I18 V18 relative holding/catching range external oscillator current voltage at reference current input (pin 18) Fig.6 I2 = 6 mA I2 = -1 mA - - - - - - - 30 5.5 -0.75 3.0 3.0 6.2 4.8 ±0.083I18 - R18 = 2.4 k (pin 18); C19 = 10 nF (pin 19) - - 0 ±6 -0.5 2.35 31.45 - +200 ±6.5 - 2.5 - - - 5.9 5.1 ±0.083I18 V7 < 50 mV Table 1; note 1 116.2 101.6 - - - 116.8 102.2 100 100 100 -110 - 1.0 - - MIN. TYP.
TDA4851
MAX.
UNIT
Vertical differential output Io differential output current between pins 5 and 6 (peak-to-peak value) maximum offset-current error maximum linearity error
1.1 ±2.5 ±1.5 - -135 -
mA % %
Vertical amplitude adjustment (in percentage of output signal) V13 I13 input voltage adjustment current 5.0 -120 0 V µA µA
117.4 102.8 - - -
% % % % %
- - - - ±3 +300 ±7.3 -4.3 2.65
V V mA
kHz % 10-6/K % mA V
Horizontal PLL2 V2 upper clamping level of flyback input lower clamping level of flyback input H-flyback slicing level td/tH V20 I20 t/tH delay between middle of sync and middle of H-flyback related to tH upper control voltage limitation lower control voltage limitation control current PLL2 control range related to tH
- - - - - - - -
V V V % V V µA %
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
SYMBOL PARAMETER CONDITIONS Fig.6 I3 = 20 mA I3 = 60 mA tp/tH VP tH tH duty factor threshold to activate under voltage protection jitter of horizontal output horizontal output off horizontal output on f = 31 kHz f = 64 kHz f = 100 kHz E/W output V11 bottom output signal during mid-scan (pin 11) top output signal during flyback temperature coefficient of output signal E/W amplitude adjustment (parabola) V14 I14 input voltage (pin 14) adjustment current 100% parabola typically 28% parabola Notes to the characteristics 1. Io/t relative to value of Mode 3. Fig.7 - -110 - 5.0 -120 0 note 2 internally stabilized 1.05 4.2 - 1.2 4.5 - - - 42 - - - - - - - 45 5.6 5.8 - - - MIN. TYP.
TDA4851
MAX.
UNIT
Horizontal output (open-collector) V3 output voltage LOW
0.3 0.8 48 - - 3.5 1.9 1.2
V V % V V ns ns ns
1.35 4.8 250 - -135 -
V V 10-6/K
V µA µA
2. Parabola amplitude tracks with mode-dependent vertical amplitude but not with vertical amplitude adjustment. Tracking can be achieved by a resistor from vertical amplitude potentiometer to pin 14.
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
APPLICATION INFORMATION
TDA4851
Fig.3 Application circuit for 3-mode VGA (31.45 kHz).
Fig.4 64 kHz application circuit.
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
TDA4851
Fig.5 31 to 64 kHz application including 4-mode VGA.
Fig.6 Horizontal timing diagram.
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
TDA4851
Fig.7 Vertical and E/W timing diagram.
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Philips Semiconductors
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
14
(1) (2) (3) (4) (5)
clamp pulses triggered by H-sync clamp pulses triggered by leading edge of V-trigger pulse clamp pulses triggered by horizontal oscillator during V-trigger pulse clamp pulses are generated internally control voltage of PLL1 is corrected during V-trigger pulse
Preliminary specification
TDA4851
Fig.8 Pulse diagram for composite sync applications (showing reduced influence of V-sync on H-phase and drive pulses for F/V converters).
Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
TDA4851
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Fig.9 Internal circuits.
Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil)
TDA4851
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH w M (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-05-24
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Philips Semiconductors
Preliminary specification
Horizontal and vertical deflection controller for VGA/XGA and autosync monitors
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4851
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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