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INTEGRATED CIRCUITS
DATA SHEET
TDA4855 Autosync Deflection Controller (ASDC)
Preliminary specification File under Integrated Circuits, IC02 1996 Jul 18
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
FEATURES Concept features · Full Horizontal (H) plus Vertical (V) autosync capability · Completely DC controllable for analog and digital concepts · Excellent geometry control functions (e.g. automatic correction of East-West (EW) parabola during adjustment of vertical size and vertical shift) · Flexible Switched Mode Power Supply (SMPS) function block for feedback and feed forward converters · Horizontal focus parabola with amplitude control · X-ray protection · Start-up and switch-off sequence for safe operation of all power components · Very good vertical linearity · Internal supply voltage stabilization · SDIP32 package. Synchronization inputs · Can handle all sync signals (Horizontal, Vertical, Composite and Sync-on-video) · Combined output for video clamping, vertical blanking and protection blanking. Horizontal section · Extremely low jitter · Frequency locked loop for smooth catching of line frequency · Simple frequency preset of fmin and fmax by external resistors · DC controllable wide range linear picture position · Soft start for horizontal driver. Vertical section
TDA4855
· Vertical amplitude independent of frequency · Automatic correction of picture height for VGA350 and VGA400 modes · DC controllable picture height, picture position and S-correction · Differential current outputs for DC coupling to vertical booster. EW section · Output for DC adjustable EW parabola with smoothed top · DC controllable picture width and trapezium correction · Optional tracking of EW parabola with line frequency · Prepared for additional DC controls of vertical linearity, EW-corner, EW pin balance, EW parallelogram, vertical focus by extended application. GENERAL DESCRIPTION The TDA4855 is a high performance and efficient solution for autosync monitors. The concept is fully DC controllable and can be used in applications with a microcontroller and stand-alone in rock bottom solutions. The TDA4855 provides synchronization processing, H + V synchronization with full autosync capability, and very short settling times after mode changes. External power components are given a great deal of protection. The IC generates the drive waveforms for DC-coupled vertical boosters such as TDA486X and TDA8351. The TDA4855 provides extended functions e.g. as a flexible SMPS block and an extensive set of geometry control facilities, providing excellent picture quality. Together with the Philips TDA488X video processor family a very advanced system solution is offered.
1996 Jul 18
2
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
QUICK REFERENCE DATA SYMBOL VCC ICC HPOS VAMP VPOS VSCOR VEWPAR VEWWID VEWTRP Tamb supply voltage supply current horizontal shift adjustment range vertical size adjustment range vertical shift adjustment range vertical S-correction adjustment range EW parabola adjustment range horizontal size adjustment range trapezium correction adjustment range operating ambient temperature PARAMETER 9.2 - - 60 - 2 0.15 0.2 - 0 MIN. - 49 ±10.5 - ±11.5 - - - ±0.5 - TYP. 16 - - 100 - 46 3.0 4.0 - 70 MAX.
TDA4855
UNIT V mA % % % % V V V °C
ORDERING INFORMATION TYPE NUMBER TDA4855 PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) VERSION SOT232-1
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(1) See calculation of fH range. (2) See note 3 of Chapter "Characteristics". (3) See Figs 12 and 13.
Preliminary specification
TDA4855
Fig.1 Block diagram and application circuit.
handbook, full pagewidth
1996 Jul 18
VPOS VAMP VSCOR RVREF 39 k VOUT1 VOUT2 19 13 12 17 18 39 k 100 22 nF k 1% CVCAP 5% 220 k 220 k VREF VCAP 24 22 VAGC 23 100 220 k nF CVAGC 39 k POLARITY CORRECTION VERTICAL OSCILLATOR AGC VERTICAL POSITION VERTICAL SIZE VERTICAL OUTPUT STAGE S-CORRECTION 21 EWPAR 39 k 220 k VERTICAL SYNC INTEGRATOR EW PARABOLA 20 EWTRP 39 k 11 EWDRV 2 XRAY 6 BDRV 4 BSENS B+ CONTROL 3 BOP 5 BIN (3) B+ CONTROL APPLICATION 220 k VGA PRESETS 32 EWWID 39 k 220 k EW parabola horizontal size EW trapeziun
BLOCK DIAGRAM
Philips Semiconductors
VSYNC (TTL level)
14
VERTICAL SYNC INPUT
9.2 to 16 V
9
VCC
PGND 8
SGND 25
SUPPLY AND REFERENCE
TDA4855
clamping blanking
CLBL
16
VIDEO CLAMPING PULSE VERTICAL BLANKING
Autosync Deflection Controller (ASDC)
4
HFLB POLARITY CORRECTION PLL1 PLL2 HORIZONTAL OSCILLATOR 26 HPLL1 HREF HCAP 10 nF 2% RHBUF RHREF (1) (1) HBUF 27 30 28 29 31 HPLL2 HFLB 12 nF HDRV 1 7 27 k 47 nF 220 k (2) 1.5 nF 39 k HPOS
H-focus parabola FREQUENCY DETECTOR COINCIDENCE DETECTOR X-RAY PROTECTION
FOCUS 10
FOCUS
HSYNC (TTL level) 15
HORIZONTAL/ COMPOSITE SYNC INPUT
HORIZONTAL OUTPUT STAGE
(video)
MBG550
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PINNING SYMBOL PIN HFLB XRAY BOP BSENS BIN BDRV HDRV PGND VCC FOCUS EWDRV VOUT2 VOUT1 VSYNC HSYNC CLBL VPOS VAMP VSCOR EWTRP EWPAR VAGC VREF VCAP SGND HPLL1 HBUF HREF HCAP HPOS HPLL2 EWWID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION horizontal flyback input X-ray protection input B+ control OTA output; comparator input B+ control comparator input/output B+ control OTA input B+ control driver output horizontal driver output power ground supply voltage horizontal focus parabola input/output EW parabola output vertical output 2 (ascending sawtooth) vertical output 1 (descending sawtooth) vertical synchronization input/output (TTL level) horizontal/composite synchronization input (TTL level or sync-on-video) video clamping pulse/vertical blanking and protection output vertical shift input vertical size input vertical S-correction input EW trapezium correction input EW parabola amplitude input external capacitor for vertical amplitude control external resistor for vertical oscillator external capacitor for vertical oscillator signal ground external filter for PLL1 buffered f/v voltage output reference current for horizontal oscillator external capacitor for horizontal oscillator horizontal shift input external filter for PLL2/soft start horizontal size input
handbook, halfpage
TDA4855
HFLB XRAY BOP BSENS BIN BDRV HDRV PGND VCC
1 2 3 4 5 6 7 8
32 EWWID 31 HPLL2 30 HPOS 29 HCAP 28 HREF 27 HBUF 26 HPLL1 25 SGND
TDA4855
9 24 VCAP 23 VREF 22 VAGC 21 EWPAR 20 EWTRP 19 VSCOR 18 VAMP 17 VPOS
MBG549
FOCUS 10 EWDRV 11 VOUT2 12 VOUT1 13 VSYNC 14 HSYNC 15 CLBL 16
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to sync top. For DC-coupled TTL signals the input clamping current is limited. The slicing level for TTL signals is 1.4 V. The separated sync signal (either video or TTL) is integrated on an internal capacitor to detect and normalize the sync polarity. Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1 phase detector and the frequency-locked loop. Vertical sync integrator Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference current at HREF (pin 28). The integrator output directly triggers the vertical oscillator. This signal is available at VSYNC (normally vertical sync input; pin 14), which is used as an output in this mode. Vertical sync slicer and polarity correction Vertical sync signals (TTL) applied to VSYNC (pin 14) are sliced at 1.4 V. The output signal of the sync slicer is integrated on an internal capacitor to detect and normalize the sync polarity. If a composite sync signal is detected at HSYNC, VSYNC is used as output for the integrated vertical sync (e.g. for power saving applications). Video clamping/vertical blanking generator The video clamping/vertical blanking signal at CLBL (pin 16) is a two-level sandcastle pulse which is especially suitable for video ICs such as the TDA488X family, but also for direct applications in video output stages. The upper level is the video clamping pulse, which is triggered by the trailing edge of the horizontal sync pulse. The width of the video clamping pulse is determined by an internal monoflop. Table 1 VGA modes VGA mode detector
TDA4855
The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking. Blanking will be activated continuously, if one of the following conditions is true: No horizontal flyback pulses at HFLB (pin 1) X-ray protection is activated Soft start of horizontal drive (voltage at HPLL2 (pin 31) is low) Supply voltage at VCC (pin 9) is low (see Fig.14) PLL1 is unlocked while frequency-locked loop is in search mode. Blanking will not be activated if the horizontal sync frequency is below the valid range or there are no sync pulses available.
The polarities of horizontal and vertical sync are internally detected in order to provide an automatic adjustment of vertical size for VGA350 and VGA400 modes. These automatic VGA presets are activated only if the current ratio IHBUF/IHREF exceeds a fixed value (see Chapter "Characteristics"). Thus it is possible to disable this function for a part of the frequency range or even completely.
MODE VGA350 VGA400 VGA480 -
HORIZONTAL/VERTICAL SYNC POLARITY + - - + - + - +
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Frequency-locked loop The frequency-locked loop can lock the horizontal oscillator over a wide frequency range. This is achieved by a combined search and PLL operation. The frequency range is preset by two external resistors and the f min 1 recommended maximum ratio is ---------- = ------3.5 f max Larger ranges are possible by extended applications. Without a horizontal sync signal the oscillator will be free-running at fmin. Any change of sync conditions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency switches the horizontal section into search mode. This means that PLL1 control currents are switched off immediately. Then the internal frequency detector starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation. This operation ensures a smooth tuning and avoids fast changes of horizontal frequency during catching. In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistor from HBUF to HREF defines the frequency range. See also hints for locking procedure in note 3 of Chapter "Characteristics". PLL1 phase detector The phase detector is a standard type using switched current sources. It compares the middle of horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26). Horizontal oscillator The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed. The maximum oscillator frequency is determined by a resistor from HREF to ground. A resistor from HREF to HBUF defines the frequency range.
TDA4855
The reference current at HREF also defines the integration time constant of the vertical sync integration. Calculation of line frequency range First the oscillator frequencies fmin and fmax have to be calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies fS(min) and fS(max). The oscillator is driven by the difference of the currents in RHREF and RHBUF. At the highest oscillator frequency RHBUF does not contribute to the spread. The spread will increase towards lower frequencies due to the contribution of RHBUF. It is also f S ( max ) dependent on the ratio n S = -----------------f S ( min ) The following example is a 31.45 to 64 kHz application: f S ( max ) 64 kHz n S = ------------------ = --------------------------- = 2.04 f S ( min ) 31.45 kHz Table 2 Calculation of total spread for fmax 3% 2% 1% - 6% for fmin 3% 2% - 1% × (2.3 × nS - 1) 8.69%
spread of: IC CHCAP RHREF RHREF, RHBUF Total
Thus the typical frequency range of the oscillator in this example is: f max = f S ( max ) × 1.06 = 67.84 kHz f S ( min ) f min = ----------------- = 28.93 kHz 1.087 The resistors RHREF and RHBUF can be calculated with the following formulae: 74 × kHz × k R HREF = ------------------------------------- = 1.091 k f max [ kHz ] R HREF × 1.19 × n R HBUF = -------------------------------------------- = 2.26 k n1 f max Where: n = ---------- = 2.35 f min
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
The spread of fmin increases with the frequency f S ( max ) ratio ------------------ . f S ( min ) For higher ratios this spread can be reduced by using resistors with less tolerances. PLL2 phase detector The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB (pin 1) with the oscillator sawtooth voltage. The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV (pin 7) output pulse. The phase between horizontal flyback and horizontal sync can be controlled at HPOS (pin 30). If HPLL2 is pulled to ground, horizontal output pulses, vertical output currents and B+ control driver pulses are inhibited. This means, HDRV (pin 7), BDRV (pin 6) VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this state. PLL2 and the frequency-locked loop are disabled, and CLBL (pin 16) provides a continuous blanking signal. This option can be used for soft start, protection and power-down modes. When the HPLL2 voltage is released again, an automatic soft start sequence will be performed (see Fig.15). The soft start timing is determined by the filter capacitor at HPLL2 (pin 31), which is charged with an constant current during soft start. In the beginning the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty factor is reached. At this point BDRV (pin 6), VOUT1 (pin 13) and VOUT2 (pin 12) are re-enabled. The voltage at HPLL2 continues to rise until PLL2 enters its normal operating range. The internal charge current is now disabled. Finally PLL2 and the frequency-locked loop are enabled, and the continuous blanking at CLBL is removed. Horizontal phase adjustment HPOS (pin 30) provides a linear adjustment of the relative phase between the horizontal sync and oscillator sawtooth. Once adjusted, the relative phase remains constant over the whole frequency range. Application hint: HPOS is a current input, which provides an internal reference voltage while IHPOS is in the specified adjustment current range. By grounding HPOS the symmetrical control range is forced to its centre value,
TDA4855
therefore the phase between horizontal sync and horizontal drive pulse is only determined by PLL2. Output stage for line drive pulses An open collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for low supply voltage at VCC (see Fig.14). The duty factor of line drive pulses is slightly dependent on the actual line frequency. This ensures optimum drive conditions over the whole frequency range. X-ray protection The x-ray protection input XRAY (pin 2) provides a voltage detector with a precise threshold. If the input voltage at XRAY exceeds this threshold for a certain time, an internal latch switches the IC into protection mode. In this mode several pins are forced into defined states: Horizontal output stage (HDRV) is floating B+ control driver stage (BDRV) is floating Vertical output stages (VOUT1 and VOUT2) are floating CLBL provides a continuous blanking signal The capacitor connected to HPLL2 (pin 31) is discharged. To reset the latch and return to normal operation, VCC has to be temporarily switched off. Vertical oscillator and amplitude control This stage is designed for fast stabilization of vertical amplitude after changes in sync frequency conditions. The free-running frequency fosc(V) is determined by the resistor RVREF connected to pin 23 and the capacitor CVCAP connected to pin 24. The value of RVREF is not only optimized for noise and linearity performance in the whole vertical and EW section, but also influences several internal references. Therefore the value of RVREF must not be changed. Capacitor CVCAP should be used to select the free-running frequency of the vertical oscillator in accordance with the following formula: 1 f osc ( V ) = ---------------------------------------------------------10.8 × R VREF × C VCAP
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
To achieve a stabilized amplitude the free-running frequency fosc(V), without adjustment, should be at least 10% lower than the minimum trigger frequency. The contributions shown in Table 3 can be assumed. Table 3 Calculation of fosc(V) total spread Contributing elements: Minimum frequency offset between fosc(V) and lowest trigger frequency Spread of IC Spread of RVREF Spread of CVCAP Total Result for 50 to 110 Hz application: 50 Hz f osc ( V ) = -------------- = 42 Hz 1.19 Application hint: VAGC (pin 22) has a high input impedance during scan, thus the pin must not be loaded externally. Otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan. Application hint: The full vertical sync range of 1 : 2.5 can be made usable by incorporating an adjustment of the free-running frequency. Also the complete sync range can be shifted to higher frequencies (e.g. 70 to 160 Hz) by reducing the value of CVCAP. Adjustment of vertical size, vertical shift and S-correction VPOS (pin 17) is the input for the DC adjustable vertical picture shift. This pin provides a phase shift at the sawtooth output VOUT1 and VOUT2 (pins 13 and 12) and the EW drive output EWDRV (pin 11) in such a way, that the whole picture moves vertically while maintaining the correct geometry. The amplitude of the differential output currents at VOUT1 and VOUT2 can be adjusted via input VAMP (pin 18). This can be a combination of a DC adjustment and a dynamic waveform modulation. VSCOR (pin 19) is used to adjust the amount of vertical S-correction in the output signal. The adjustments for vertical size and vertical shift also affect the waveforms of the EW parabola and the vertical S-correction. The result of this interaction is that no ±10% ±3% ±1% ±5% 19%
TDA4855
readjustment of these parameters is necessary after an adjustment of vertical picture size or position. Application hint: VPOS is a current input, which provides an internal reference voltage while IVPOS is in the specified adjustment current range. By grounding VPOS (pin 17) the symmetrical control range is forced to its centre value. Application hint: VSCOR is a current input at 5 V. Superimposed on this level is a very small positive-going vertical sawtooth, intended to modulate an external long-tailed transistor pair. This enables further optional DC controls of functions which are not directly accessible such as vertical tilt or vertical linearity (see Fig.17). EW parabola (including horizontal size and trapezium correction) EWDRV (pin 11) provides a complete EW drive waveform. EW parabola amplitude, DC shift (horizontal size) and trapezium correction can be controlled via separate DC inputs. EWPAR (pin 21) is used to adjust the parabola amplitude. This can be a combination of a DC adjustment and a dynamic waveform modulation. The EW parabola amplitude also tracks with vertical picture size. The parabola waveform itself tracks with the adjustment for vertical picture shift (VPOS). Additional effort has been taken to generate a smooth waveform at the top of the parabola. This is to avoid ringing in the horizontal output stage. EWWID (pin 32) offers two modes of operation: 1. Mode 1 Horizontal size is DC controlled via EWWID (pin 32) and causes a DC shift at the EWDRV output. Also the complete waveform is multiplied internally by a signal proportional to the line frequency (which is detected via the current at HREF (pin 28). This mode is to be used for driving EW modulator stages which require a voltage proportional to the line frequency. 2. Mode 2 EWWID (pin 32) is grounded. Then EWDRV is no longer multiplied by the line frequency. The DC adjustment for horizontal size must be added to the input of the B+ control amplifier BIN (pin 5). This mode is to be used for driving EW modulators which require a voltage independent of the line frequency. EWTRP (pin 20) is used to adjust the amount of trapezium correction in the EW drive waveform.
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Application hint: EWTRP (pin 20) is a current input at 5 V. Superimposed on this level is a very small vertical parabola with positive tips, intended to modulate an external long-tailed transistor pair. This enables further optional DC controls of functions which are not directly accessible such as EW-corner, vertical focus or EW pin balance (see Fig.17). Application hint: By grounding EWTRP (pin 20) the symmetrical control range is forced to its centre value. Dynamic focus section This section generates a horizontal parabola waveform for dynamic focus applications. The amplitude of this parabola is internally stabilized, thus it is independent from the line frequency. FOCUS (pin 10) is designed as a current sink. The peak-to-peak amplitude of the output current can be adjusted by forcing the voltage at pin 10 to a value between 1 and 4 V. B+ control function block The B+ control function block of the ASDC consists of an Operational Transconductance Amplifier (OTA), a voltage comparator, a flip-flop and a discharge circuit. This configuration allows easy applications for different B+ control concepts. GENERAL DESCRIPTION The non-inverting input of the OTA is connected internally to a high precision reference voltage. The inverting input is connected to BIN (pin 5). An internal clamping circuit limits the maximum positive output voltage of the OTA. The output itself is connected to BOP (pin 3) and to the inverting input of the voltage comparator. The non-inverting input of the voltage comparator can be accessed via BSENS (pin 4). B+ drive pulses are generated by an internal flip-flop and fed to BDRV (pin 6) via an open collector output stage. This flip-flop will be set at the rising edge of the signal at HDRV (pin 7). The falling edge of the output signal at BDRV has a defined delay of td(BDRV) to the rising edge of the HDRV pulse. When the voltage at BSENS exceeds the voltage at BOP, the voltage comparator output resets the flip-flop, and therefore the open collector stage at BDRV is floating again.
TDA4855
An internal discharge circuit allows a well defined discharge of capacitors at BSENS. BDRV is active at a low level output voltage (see Figs 12 and 13), thus it requires an external inverting driver stage. The B+ function block can be used for B+ deflection modulators in either of two modes: · Feedback mode (see Fig.12) In this application the OTA is used as an error amplifier with a limited output voltage range. The flip-flop will be set at the rising edge of the signal at HDRV. A reset will be generated when the voltage at BSENS taken from the current sense resistor exceeds the voltage at BOP. If no reset is generated within a line period, the rising edge of the next HDRV pulse forces the flip-flop to reset. The flip-flop is set immediately after the voltage at BSENS has dropped below the threshold voltage VRESTART(BSENS). · Feed forward mode (see Fig.13) This application uses an external RC combination at BSENS to provide a pulse width which is independent from the horizontal frequency. The capacitor is charged via an external resistor and discharged by the internal discharge circuit. For normal operation the discharge circuit is activated when the flip-flop is reset by the internal voltage comparator. Now the capacitor will be discharged with a constant current until the internally controlled stop level VSTOP(BSENS) is reached. This level will be maintained until the rising edge of the next HDRV pulse sets the flip-flop again and disables the discharge circuit. If no reset is generated within a line period, the rising edge of the next HDRV pulse automatically starts the discharge sequence and resets the flip-flop (Fig.13). When the voltage at BSENS reaches the threshold voltage VRESTART(BSENS), the discharge circuit will be disabled automatically and the flip-flop will be set immediately. This behaviour allows a definition of the maximum duty cycle of the B+ control drive pulse by the relationship of charge current to discharge current.
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Supply voltage stabilizer, references and protection The ASDC provides an internal supply voltage stabilizer for excellent stabilization of all internal references. An internal gap reference especially designed for low-noise is the reference for the internal horizontal and vertical supply voltages. All internal reference currents and drive current for the vertical output stage are derived from this voltage via external resistors. A special protection mode has been implemented in order to protect the deflection stages and the picture tube during start-up, shut-down and fault conditions. This protection mode can be activated as shown in Table 4. Table 4 Activation of protection mode ACTIVATION Low supply voltage at pin 9 X-ray protection XRAY (pin 2) triggered HPLL2 (pin 31) pulled to ground RESET increase supply voltage remove supply voltage release pin 31
TDA4855
The return to normal operation is performed in accordance with the start-up sequence in Fig.14a, if the reset was caused by the supply voltage at pin 9. The first action with increasing supply voltage is the activation of continuous blanking at CLBL. When the threshold for activation of HDRV is passed, an internal current begins to charge the external capacitor at HPLL2 and a PLL2 soft start sequence is performed (see Fig.15). In the beginning of this phase the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. Then the PLL2 voltage passes the threshold for activation of BDRV, VOUT1 and VOUT2. For activation of these pins not only the PLL2 voltage, but also the supply voltage must have passed the appropriate threshold. A last pair of thresholds has to be passed by PLL2 voltage and supply voltage before the continuous blanking is finally removed, and the operation of PLL2 and frequency-locked loop is enabled. A return to the normal operation by releasing the voltage at HPLL2 will lead to a slightly different sequence. Here the activation of all functions is influenced only by the voltage at HPLL2 (see Fig.15). Application hint: Internal discharge of the capacitor at HPLL2 will only be performed, if the protection mode was activated via the supply voltage or X-ray protection.
When protection mode is active, several pins of the ASDC are forced into a defined state: HDRV (horizontal driver output) is floating BDRV (B+ control driver output) is floating VOUT1 and VOUT2 (vertical outputs) are floating CLBL provides a continuous blanking signal The capacitor at HPLL2 is discharged. If the protection mode is activated via the supply voltage at pin 9, all these actions will be performed in a well defined sequence (see Fig.14). For activation via X-ray protection or HPLL2 all actions will occur simultaneously.
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground. SYMBOL VCC VI(n) supply voltage input voltages BIN HSYNC, VPOS, VAMP, VSCOR, VREF, HREF and HPOS XRAY VO(n) output voltages VOUT1 and VOUT2 BDRV and HDRV VI/O(n) input/output voltages BOP and BSENS FOCUS and VSYNC IHDRV IHFLB ICLBL IBOP IBDRV IEWDRV Tamb Tj Tstg Vesd horizontal driver output current horizontal flyback input current video clamping pulse/vertical blanking output current B+ control OTA output current B+ control driver output current EW driver output current operating ambient temperature junction temperature storage temperature electrostatic discharge for all pins (note 1) machine model human body model Note 1. Machine model: 200 pF, 25 , 2.5 µH; human body model: 100 pF, 1500 , 7.5 µH. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 55 UNIT K/W -400 -3000 +400 +3000 V V -0.5 -0.5 - -10 - - - - 0 - -55 +6.0 +6.5 100 +10 -10 1 50 -5 70 150 +150 V V mA mA mA mA mA mA °C °C °C -0.5 -0.5 +6.5 +16 V V -0.5 -0.5 -0.5 +6.0 +6.5 +8.0 V V V PARAMETER MIN. -0.5 MAX. +16 V UNIT
QUALITY SPECIFICATION In accordance with "URF-4-2-59/601"; EMC emission/immunity test in accordance with "DIS 1000 4.6" (IEC 801.6) SYMBOL VEMC PARAMETER emission test immunity test Note 1. Tests are performed with application reference board. Tests with other boards will have different results. CONDITIONS note 1 note 1 - - MIN. TYP. 1.5 2.0 - - MAX. V UNIT mV
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
CHARACTERISTICS VCC = 12 V; Tamb = 25 °C; peripheral components in accordance with Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Horizontal sync separator INPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS [HSYNC (PIN 15)] VDC(HSYNC) tr(HSYNC) tf(HSYNC) tW(HSYNC) IDC(HSYNC) sync input signal voltage slicing voltage level rise time of sync pulse fall time of sync pulse minimum width of sync pulse input current VHSYNC = 0.8 V VHSYNC = 5.5 V VAC(HSYNC) sync amplitude of video input signal voltage slicing voltage level (measured from top sync) Vclamp(HSYNC) IC(HSYNC) tHSYNC(min) RS(max) rdiff(HSYNC) top sync clamping voltage level charge current for coupling capacitor minimum width of sync pulse maximum source resistance differential input resistance duty factor = 7% during sync fH < 45 kHz fH > 45 kHz VHSYNC > Vclamp(HSYNC) source resistance RS = 50 1.7 1.2 10 10 0.7 - - - 90 1.1 1.7 0.7 - - - - 0.3 - 1.4 - - - - - 300 120 1.28 2.4 - - 80 - - - - 1.6 500 500 - -200 10 - 150 1.5 3.4 - 1500 - V V ns ns µs µA µA mV mV V µA µs
INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY)
Automatic polarity correction for horizontal sync tP ( H) -----------tH tP(H) tint(V) horizontal sync pulse width related to tH delay time for changing polarity 20 25 1.8 % % ms µs µs µs
Vertical sync integrator integration time for generation of a vertical trigger pulse fH = 31.45 kHz; IHREF = 1.052 mA fH = 64 kHz; IHREF = 2.141 mA fH = 100 kHz; IHREF = 3.345 mA Vertical sync slicer (DC-coupled, TTL compatible) [VSYNC (pin 14)] VVSYNC IVSYNC sync input signal voltage slicing voltage level input current 0 V < VSYNC < 5.5 V 1.7 1.2 - - 1.4 - - 1.6 ±10 V V µA 7 3.9 2.5 10 5.7 3.8 13 6.5 4.5
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Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
SYMBOL
PARAMETER
CONDITIONS
MIN. -0.7 4.4 - - 0.3
TYP. -1.0 4.8 300 - -
MAX. -1.35 5.2 -
UNIT
VERTICAL SYNC OUTPUT AT VSYNC (PIN 14) DURING COMPOSITE SYNC AT HSYNC (PIN 15) IVSYNC VVSYNC output current internal clamping voltage level steepness of slopes Automatic polarity correction for vertical sync tVSYNC(max) td(VPOL) tclamp(CLBL) Vclamp(CLBL) td(clamp) maximum width of vertical sync pulse delay for changing polarity 300 1.8 µs ms µs V ns during internal vertical sync during internal vertical sync mA V ns/mA
Video clamping/vertical blanking output [CLBL (pin 16)] width of video clamping pulse top voltage level of video clamping pulse delay between trailing edge of horizontal sync and start of video clamping pulse maximum duration of video clamping pulse referenced to end of horizontal sync temperature coefficient of Vclamp(CLBL) steepness of slopes for clamping pulse Vblank(CLBL) tblank(CLBL) TCblank Vscan(CLBL) TCscan Isink(CLBL) Iload(CLBL) top voltage level of vertical blanking pulse width of vertical blanking pulse temperature coefficient of Vblank(CLBL) output voltage during vertical scan temperature coefficient of Vscan(CLBL) internal sink current external load current ICLBL = 0 RL = 1 M; CL = 20 pF notes 1 and 2 VGA presets active VGA presets disabled clamping pulse triggered on trailing edge of horizontal sync measured at VCLBL = 3 V measured at VCLBL = 3 V 0.6 4.32 - 0.7 4.75 130 0.8 5.23 -
tclamp(max)
-
-
1.0
µs
TCclamp
- - 1.7 500 240 - 0.59 - 2.4 -
+4 50 1.9 575 300 +2 0.63 -2 - -
- - 2.1 650 360 - 0.67 - - -3.0
mV/K ns/V V µs µs mV/K V mV/K mA mA
1996 Jul 18
14
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
SYMBOL
PARAMETER
CONDITIONS fH < 45 kHz; note 3 fH > 45 kHz; note 3 - - - notes 4 and 5 fH(min); note 6 fH(max); note 6 - - - IHSHIFT = 0 IHSHIFT = -135 µA HPOS = +10.5% HPOS = -10.5% note 7 - -
MIN. - -
TYP.
MAX.
UNIT
PLL1 phase comparator and frequency-locked loop [HPLL1 (pin 26) and HBUF (pin 27)] tHSYNC(max) maximum width of horizontal sync pulse (referenced to line period) total lock-in time of PLL1 control voltage buffered f/v voltage at HBUF (pin 27) maximum load current 20 25 80 - - -4.0 - - -135 - - 0.1 % % ms V V mA
tlock(HPLL1) VHPLL1 VHBUF Iload(HBUF) HPOS
40 5.6 2.5 - -10.5 +10.5 -120 0 5.1 -
ADJUSTMENT OF HORIZONTAL PICTURE POSITION horizontal shift adjustment range (referenced to horizontal period) input current reference voltage at input picture shift is centred if HPOS (pin 30) is forced to ground RHBUF = ; RHREF = 2.4 k; CHCAP = 10 nF; note 5 % % µA µA V V
IHPOS Vref(HPOS) Voff(HPOS)
-110 - - 0
Horizontal oscillator [HCAP (pin 29) and HREF (pin 28)] fH(0) free-running frequency without PLL1 action (for testing only) spread of free-running frequency (excluding spread of external components) temperature coefficient of free-running frequency maximum oscillator frequency voltage at input for reference current 30.53 31.45 32.39 kHz
fH(0)
-
-
±3.0
%
TC fH(max) VHREF
-100 - 2.43
0 - 2.55
+100 130 2.68
10-6/K kHz V
PLL2 phase detector [HFLB (pin 1) and HPLL2 (pin 31)] PLL2 PLL2 control (advance of horizontal drive with respect to middle of horizontal flyback) delay between middle of horizontal sync and middle of horizontal flyback maximum voltage for PLL2 protection mode/soft start charge current for external capacitor during soft start VHPLL2 < 3.7 V maximum advance minimum advance HPOS (pin 30) grounded 36 - - - 7 200 - - - % % ns
td(HFLB)
VPROT(HPLL2) Icharge(HPLL2)
- -
4.4 15
- -
V µA
1996 Jul 18
15
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
SYMBOL
PARAMETER
CONDITIONS - - - - -
MIN.
TYP. - -
MAX.
UNIT
HORIZONTAL FLYBACK INPUT [HFLB (PIN 1)] VHFLB IHFLB VHFLB positive clamping level negative clamping level positive clamping current negative clamping current slicing level Output stage for line driver pulses [HDRV (pin 7)] OPEN COLLECTOR OUTPUT STAGE VHDRV Ileakage(HDRV) tHDRV(OFF)/tH saturation voltage output leakage current IHDRV = 20 mA IHDRV = 60 mA VHDRV = 16 V IHDRV = 20 mA; fH = 31.45 kHz; see Fig.9 IHDRV = 20 mA; fH = 57 kHz; see Fig.9 IHDRV = 20 mA; fH = 90 kHz; see Fig.9 AUTOMATIC VARIATION OF DUTY FACTOR relative tOFF time of HDRV output; measured at VHDRV = 3 V; HDRV duty factor is determined by the relation IHREF/IVREF 42 45 46.6 45 46.3 48 48 47.7 49.4 % % % - - - - - - 0.3 0.8 10 V V µA IHFLB = 5 mA IHFLB = -1 mA 5.5 -0.75 - - 2.8 V V mA mA V
6 -2 -
X-ray protection [XRAY (pin 2)] VXRAY tW(XRAY) RI(XRAY) VRESET(VCC) slicing voltage level minimum width of trigger pulse input resistance at XRAY (pin 2) supply voltage for reset of X-ray latch VXRAY < 6.38 V + VBE VXRAY > 6.38 V + VBE 6.14 10 500 - - 6.38 - - 5 5.6 6.64 - - - - V µs k k V
Vertical oscillator (oscillator frequency in application without adjustment of free-running frequency fv(o)) fV fv(o) VVREF td(scan) free-running frequency vertical frequency catching range voltage at reference input for vertical oscillator delay between trigger pulse and start of ramp at VCAP (pin 24) (width of vertical blanking pulse) control currents of amplitude control external capacitor at VAGC (pin 22) VGA presets active VGA presets disabled RVREF = 22 k; CVCAP = 100 nF constant amplitude; notes 8, 9 and 10 40 50 - 500 240 42 - 3.0 575 300 43.3 110 - 650 360 Hz Hz V µs µs µA nF
IVAGC CVAGC
±120 -
±200 -
±300 150
1996 Jul 18
16
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Differential vertical current outputs ADJUSTMENT OF VERTICAL SIZE (see Figs 3 to 8) [VAMP (PIN 18)] VAMP vertical size adjustment range (referenced to nominal vertical size) input current for maximum amplitude (100%) input current for minimum amplitude (60%) Vref(VAMP) IHBUF/IHREF reference voltage at input PRESETS FOR VGA MODE DEPENDENT VERTICAL SIZE minimum current ratio IHBUF/IHREF for enable of VGA presets variation of vertical size for detected VGA modes (reference for all amplitude settings is VGA480 mode) note 12 2.25 2.5 2.75 IVAMP = 0; note 11 IVAMP = -135 µA; note 11 - - -110 - - 60 100 -120 0 5.0 - - -135 - - % % µA µA V
IVAMP
VAMP
VGA350 VGA400 VGA480
- - -
116.8 102.2 100.0
- - -
% % %
ADJUSTMENT OF VERTICAL SHIFT (see Figs 3 to 8) [VPOS (PIN 17)] VPOS vertical shift adjustment range (referenced to 100% vertical size) input current for maximum shift-up input current for maximum shift-down Vref(VPOS) Voff(VPOS) reference voltage at input vertical shift is centred if VPOS (pin 17) is forced to ground IVPOS = -135 µA; note 11 IVPOS = 0; note 11 - - -110 - - 0 -11.5 +11.5 -120 0 5.0 - - - -135 - - 0.1 % % µA µA V V
IVPOS
ADJUSTMENT OF VERTICAL S-CORRECTION (see Figs 3 to 8) [VSCOR (PIN 19)] VSCOR vertical S-correction adjustment range input current for maximum S-correction input current for minimum S-correction VSCOR Vref(VSCOR) VSAWM(p-p) symmetry error of S-correction reference voltage at input voltage amplitude of superimposed logarithmic sawtooth (peak-to-peak value) note 13 maximum VSCOR IVSCOR = 0; note 11 IVSCOR = -135 µA; note 11 - - -110 - - - - 2 46 -120 0 - 5.0 - - - -135 - ±0.7 - 145 % % µA µA % V mV
IVSCOR
1996 Jul 18
17
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
SYMBOL IVOUT(nom)
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vertical output stage [VOUT1 (pin 13) and VOUT2 (pin 12)] nominal differential output current (peak-to-peak value) (IVOUT = IVOUT1 - IVOUT2) maximum differential output current (peak value) (IVOUT = IVOUT1 - IVOUT2) allowed voltage at outputs maximum offset error of vertical nominal settings; note 11 output currents maximum linearity error of vertical output currents nominal settings; note 11 nominal settings; note 11 0.76 0.85 0.94 mA
IVOUT(max)
0.54
0.6
0.66
mA
VVOUT1, VVOUT2 V(offset) V(lin) EW drive output
0 - -
- - -
4.2 ±2.5 ±1.5
V % %
EW DRIVE OUTPUT STAGE [EWDRV (PIN 11)] VEWDRV bottom output voltage (internally stabilized) maximum output voltage IEWDRV TCEWDRV output load current temperature coefficient of output signal VPAR(EWDRV) = 0; VDC(EWDRV) = 0; EWTRP centred note 14 1.05 1.2 1.35 V
7.0 - -
- - -
- ±2.0 600
V mA 10-6/K
ADJUSTMENT OF EW PARABOLA AMPLITUDE (see Figs 3 to 8) [EWPAR (PIN 21)] VPAR(EWDRV) parabola amplitude IEWPAR = 0; note 11 IEWPAR = -135 µA; note 11 IEWPAR input current for maximum amplitude input current for minimum amplitude Vref(EWPAR) VDC(EWDRV) reference voltage at input IEWWID = -135 µA; note 11 IEWWID = 0; note 11 IEWWID input current for maximum DC shift input current for minimum DC shift Vref(EWWID) reference voltage at input ADJUSTMENT OF HORIZONTAL SIZE (see Figs 3 to 8) [EWWID (PIN 32)] EW parabola DC voltage shift - - - -110 - 0.1 4.2 0 -120 5.0 - - - -135 - V V µA µA V - - -110 - - 0.05 3 -120 0 5.0 - - -135 - - V V µA µA V
1996 Jul 18
18
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
SYMBOL
PARAMETER
CONDITIONS - -
MIN.
TYP. -0.5 +0.5 -120 0 5.0 - - -
MAX.
UNIT
ADJUSTMENT OF TRAPEZIUM CORRECTION (see Figs 3 to 8) [EWTRP (PIN 20)] VTRP(EWDRV) trapezium correction voltage IEWTRP = 0; note 11 IEWTRP = -135 µA; note 11 IEWTRP input current for maximum positive trapezium correction input current for maximum negative trapezium correction Vref(EWTRP) Voff(EWTRP) reference voltage at input trapezium correction is centred if EWTRP (pin 20) is forced to ground amplitude of superimposed logarithmic parabola (peak-to-peak value) note 15 V V µA µA V V
-110 - - 0
-135 - - 0.1
VPARM(p-p)
-
-
145
mV
TRACKING OF EWDRV OUTPUT SIGNAL WITH fH PROPORTIONAL VOLTAGE fH(MULTI) VPAR(EWDRV) fH range for tracking parabola amplitude at EWDRV (pin 11) IHREF = 1.052 mA; fH = 31.45 kHz; note 16 IHREF = 2.341 mA; fH = 70 kHz; note 16 VEWDRV VEWWID IFOCUS(p-p) VFOCUS(min) VFOCUS(max) linearity error of fH tracking voltage range to inhibit tracking 24 1.3 2.7 - 1.45 3.0 3.0 - - 80 1.6 3.3 3.3 8 0.1 - - 1.1 4.4 kHz V V V % V
function disabled; note 16 2.7 - 0 - - 0.9 3.65
Focus section [FOCUS (pin 10)] amplitude of horizontal parabola (peak-to-peak value) input voltage for minimum horizontal parabola amplitude input voltage for maximum horizontal parabola amplitude VFOCUS = 1 V VFOCUS = 4 V 0.03 1 1.0 4.0 mA mA V V
1996 Jul 18
19
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
B+ control section (see Figs 12 and 13) TRANSCONDUCTANCE AMPLIFIER [BIN (PIN 5) AND BOP (PIN 3)] VBIN IBIN(max) Vref(int) VBOP(min) VBOP(max) IBOP(max) g Gopen CBOP input voltage maximum input current reference voltage at internal non-inverting input of OTA minimum output voltage maximum output voltage maximum output current transconductance of OTA open-loop gain minimum value of capacitor at BOP (pin 3) note 17 note 18 IBOP < 1 mA 0 - 2.37 - 5 - 30 - 4.7 - - 2.5 0.4 5.3 ±500 50 86 - 5.25 ±1 2.58 - 5.6 - 70 - - V µA V V V µA mS dB nF
VOLTAGE COMPARATOR [BSENS (PIN 4)] VBSENS VBOP IBSENS IBDRV(max) Ileakage(BDRV) Vsat(BDRV) toff(min) td(BDRV) voltage range of positive comparator input voltage range of negative comparator input maximum leakage current discharge disabled 0 0 - 20 VBDRV = 16 V IBDRV < 20 mA measured at VHDRV, VBDRV = 3 V capacitive load; IBSENS = 0.5 mA VBSENS > 2.5 V fault condition - - - - - - - - - - 250 500 5 5 -2 - 3 300 - - V V µA mA µA mV ns ns
OPEN COLLECTOR OUTPUT STAGE [BDRV (PIN 6)] maximum output current output leakage current saturation voltage minimum off-time delay between BDRV pulse and HDRV pulse
BSENS DISCHARGE CIRCUIT VSTOP(BSENS) IDISC(BSENS) CBSENS discharge stop level discharge current minimum value of capacitor at BSENS (pin 4) 0.85 4.5 1.2 2 1.0 6 1.3 - 1.15 7.5 1.4 - V mA V nF
VRESTART(BSENS) threshold voltage for restart
Internal reference, supply voltage and protection VSTAB(VCC) external supply voltage for complete stabilization of all internal references supply current power supply rejection ratio of internal supply voltage f = 1 kHz 9.2 - 16 V
IVCC PSRR
- 50
49 -
- -
mA dB
1996 Jul 18
20
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Notes to the characteristics
TDA4855
1. For duration of vertical blanking pulse see characteristics of "Vertical oscillator (oscillator frequency in application without adjustment of free-running frequency fv(o))". 2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true: a) No horizontal flyback pulses at HFLB (pin 1) within a line b) X-ray protection is triggered c) Voltage at HPLL2 (pin 31) is low (for soft start of horizontal drive) d) Supply voltage at VCC (pin 9) is low e) PLL1 unlocked while frequency-locked loop is in search mode. 3. To ensure safe locking of the horizontal oscillator, one of the following procedures is required: a) Search mode starts always from fmin. Then the PLL1 filter components are a 3.3 nF capacitor from pin 26 to ground in parallel with an 8.2 k resistor in series with a 47 nF capacitor. b) Search mode starts either from fmin or fmax with HPOS in middle position (IHPOS = 60 µA). Then the PLL1 filter components are a 1.5 nF capacitor from pin 26 to ground in parallel with a 27 k resistor in series with a 47 nF capacitor. c) After locking is achieved, HPOS can be operated in the normal way. 4. Loading of HPLL1 (pin 26) is not allowed. 5. Oscillator frequency is fmin when no sync input signal is present (no continuous blanking at pin 16). 6. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed by an internal sample-and-hold circuit. kT 1 7. Input resistance at HPOS (pin 30): R HPOS = ----- × -------------q I HPOS 8. Full vertical sync range with constant amplitude (fV(min) : fV(max) = 1 : 2.5) can be made usable by choosing an application with adjustment of free-running frequency. 9. If higher vertical frequencies are required, sync range can be shifted by using a smaller capacitor at VCAP (pin 24). 10. Value of resistor at VREF (pin 23) may not be changed. 11. All vertical and EW adjustments are specified at nominal vertical settings, which means: a) VAMP = 100% (IVAMP = 135 µA) b) VSCOR = 0 (pin 19 open-circuit) c) VPOS centred (pin 17 forced to ground) d) VGA presets disabled (current ratio IHBUF : IHREF < 2.25) e) fH = 70 kHz. 12. VGA presets are enabled below the horizontal frequency at which the current ratio IHBUF : IHREF exceeds the specified value. 13. The superimposed logarithmic sawtooth at VSCOR (pin 19) tracks with internal VGA settings and with VPOS, but 1d kT not with VAMP settings. The superimposed waveform is described by ------ × In ------------ with `d' being the modulation 1+d q depth of a sawtooth from -5/6 to +5/6. A linear sawtooth with the same modulation depth can be recovered in an external long-tailed pair (see Fig.17). 14. The output signal at EWDRV (pin 11) may consist of parabola + DC shift + trapezium correction. These adjustments have to be carried out in a correct relationship to each other in order to avoid clipping due to the limited output voltage range at EWDRV.
1996 Jul 18
21
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
15. The superimposed logarithmic parabola at EWTRP (pin 20) tracks with internal VGA settings and with VPOS, but not with VAMP settings (see Fig.17). 16. If fH tracking is enabled, the amplitude of the complete EWDRV output signal (parabola + DC shift + trapezium) will be changed proportional to IHREF. The EWDRV low level of 1.2 V remains fixed. 17. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA operates as an integrator). V BOP 18. Open-loop gain is ------------- at f = 0 with no resistive load and CBOP = 4.7 nF (from BOP (pin 3) to GND). V BIN Vertical and EW adjustments
handbook, halfpage
MBG590
IVOUT1
handbook, halfpage
VEWDRV
MBG591
IVOUT2 VPAR(EWDRV)
l2
l1(1)
t
t
(1) I1 is the maximum amplitude setting at VAMP (pin 18); VGA presets disabled, VPOS centred and VSCOR = 0%. I 2 VAMP = ------- × 100% I 1
EWPAR = 0 to VPAR(EWDRV).
Fig.3 IVOUT1 and IVOUT2 as functions of time.
Fig.4 VEWDRV as a function of time.
1996 Jul 18
22
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
handbook, halfpage
MBG592
IVOUT1
handbook, halfpage
VEWDRV
MBG593
IVOUT2 l1(1) l2 VDC(EWDRV)
t
t
(1) I1 is VPOS adjustment centred; maximum amplitude setting at VAMP (pin 18) and VGA presets disabled. I 2 I 1 VPOS = --------------------- × 100% 2 × I 1 EWWID = 0 to VDC(EWDRV).
Fig.5 IVOUT1 and IVOUT2 as functions of time.
Fig.6 VEWDRV as a function of time.
handbook, halfpage
IVOUT1
MBG594
handbook, halfpage
MBG595
VEWDRV
IVOUT2
l2/t
VTRP(EWDRV)
l1(1)/t
t
t
(1) I1 is VSCOR = 0%; maximum amplitude setting at VAMP (pin 18) and VGA presets disabled. I 1 I 2 VSCOR = --------------------- × 100% I 1 EWTRP = ±VTRP(EWDRV).
Fig.7 IVOUT1 and IVOUT2 as functions of time. 1996 Jul 18 23
Fig.8 VEWDRV as a function of time.
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Pulse diagrams
TDA4855
handbook, full pagewidth
horizontal oscillator sawtooth at HCAP (pin 29)
horizontal sync pulse
PLL1 control current at HPLL1 (pin 26) video clamping pulse at CLBL (pin 16) triggered on trailing edge of horizontal sync
+
-
vertical blanking level
line flyback pulse at HFLB (pin 1)
PLL2 control current at HPLL2 (pin 31) PLL2 control range line drive pulse at HDRV (pin 7)
+
45 to 48% of line period
horizontal focus parabola at FOCUS (pin 10)
MBG598
Fig.9 Pulse diagram for horizontal part.
1996 Jul 18
24
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
handbook, full pagewidth
4.0 V automatic trigger level 3.8 V synchronized trigger level
vertical oscillator sawtooth at VCAP (pin 24)
1.4 V
vertical sync pulse
inhibited
internal trigger inhibit window (typical 6.7 ms)
vertical blanking pulse at CLBL (pin 16)
IVOUT1 differential output currents VOUT1 (pin 13) and VOUT2 (pin 12) IVOUT2
7.0 V maximum tip-parabola
EW parabola 3 V (p-p) maximum EW drive waveform at EWDRV (pin 11) DC shift 4 V maximum LOW level 1.2 V fixed
MBG597
Fig.10 Pulse diagram for vertical part.
1996 Jul 18
25
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
handbook, fullcomposite sync (TTL) pagewidth
at HSYNC (pin 15)
internal integration of composite sync
internal vertical trigger pulse
PLL1 control voltage at HPLL1 (pin 26) clamping and blanking pulses at CLBL (pin 16)
MGC947
a. Reduced influence of vertical sync on horizontal phase.
handbook, full pagewidth
composite sync (TTL) at HSYNC (pin 15)
clamping and blanking pulses at CLBL (pin 16)
MBG596
b. Generation of video clamping pulses during vertical sync with serration pulses.
Fig.11 Pulse diagrams for composite sync applications.
1996 Jul 18
26
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
APPLICATION INFORMATION
TDA4855
handbook, full pagewidth
2 VHDRV
VCC R6 6 S Q 3 VBDRV
Vi
7
L D2
2.5 V
OTA R Q INVERTING BUFFER
TR1 HORIZONTAL OUTPUT STAGE
DISCHARGE
5 1 horizontal flyback pulse D1 VBIN R1 C1 R2 R3 C2
3 VBOP
4 R5 4 VBSENS
C4
R4
MBG599
CBOP >4.7 nF
EWDRV For f < 50 kHz and C2 < 47 nF calculation formulas and behaviour of the OTA are the same as for an OP. An exception is the limited output current at BOP (pin 3). See Chapter "Characteristics", Row Head "B+ control section (see Figs 12 and 13)".
a. Feedback mode application.
handbook, full pagewidth
1 horizontal flyback pulse
2 VHDRV ton 3 VBDRV td(BDRV) VBSENS = VBOP 4 VBSENS
MBG600
toff(min) VRESTART(BSENS) VSTOP(BSENS)
b. Waveforms for normal operation.
c. Waveforms for fault condition.
Fig.12 Application and timing for feedback mode.
1996 Jul 18
27
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
handbook, full pagewidth
2 VHDRV
VCC R4 6 S Q INVERTING BUFFER
horizontal flyback pulse 1
7
2.5 V
OTA R Q 3 VBDRV
HORIZONTAL OUTPUT STAGE
EHT transformer
D2
DISCHARGE
5 IMOSFET TR1
5 EHT adjustment R1 VBIN D1 R2
3 VBOP
4 VBSENS R3 4
MBG601
TR2 power-down C1 CBSENS >2 nF
CBOP > 4.7 nF
a. Forward mode application.
handbook, full pagewidth 1 horizontal
flyback pulse
2 VHDRV ton 3 VBDRV td(BDRV) VBOP 4 VBSENS VBOP VRESTART(BSENS) VSTOP(BSENS) 5 IMOSFET
MBG602
toff
(discharge time of CBSENS)
b. Waveforms for normal operation.
c. Waveforms for fault condition.
Fig.13 Application and timing for feed forward mode.
1996 Jul 18
28
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Start-up and shut-down sequence
TDA4855
handbook, full pagewidth
MBG555
VCC 8.5 V continuous blanking off PLL2 enabled frequency detector enabled VCC > 8.5 V and VHPLL2 > 4.4 V
8.2 V
video clamping pulse enabled BDRV enabled VOUT1 and VOUT2 enabled
VCC > 8.2 V and VHPLL2 > 3.7 V
5.8 V
PLL2 soft start sequence begins(1)
4.0 V
continuous blanking CLBL (pin 16) activated
time
(1) See Fig.15 for PLL2 soft-start.
a. Start-up sequence.
handbook, full pagewidth
MBG554
VCC 8.5 V continuous blanking CLBL (pin 16) activated PLL2 disabled frequency detector disabled
8.0 V
video clamping pulse disabled BDRV floating VOUT1 and VOUT2 floating
5.6 V
HDRV floating
4.0 V
continuous blanking disappears
time
b. Shut-down sequence.
Fig.14 Start-up sequence and shut-down sequence.
1996 Jul 18
29
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PLL2 soft start sequence
TDA4855
handbook, full pagewidth
MBG553
VHPLL2 4.4 V continuous blanking off PLL2 enabled frequency detector enabled
ea se s
3.7 V
du ty
fa ct
or in cr
HDRV duty factor has reached nominal value BDRV enabled VOUT1 and VOUT2 enabled
0.5 V
HDRV duty factor begins to increase
time
a. PLL2 start-up sequence.
handbook, full pagewidth
MBG552
VHPLL2 4.4 V continuous blanking CLBL (pin 16) activated PLL2 disabled frequency detector disabled
3.7 V
du ty fa o ct rd ec re as es
HDRV duty factor begins to decrease BDRV floating VOUT1 and VOUT2 floating
0.5 V
HDRV floating
time
b. PLL2 shut-down sequence.
Fig.15 PLL2 soft start sequence.
1996 Jul 18
30
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Vertical linearity error
TDA4855
handbook, halfpage I
VOUT (µA)
(1)
MBG551
+415
I1(2)
0
I2(3)
-415
I3(4) VVCAP
(1) IVOUT = IVOUT1 - IVOUT2. (2) I1 = IVOUT at VVCAP = 1.9 V. (3) I2 = IVOUT at VVCAP = 2.6 V. (4) I3 = IVOUT at VVCAP = 3.3 V. I1 I3 Which means: I 0 = -------------2 I1 I2 I2 I3 Vertical linearity error = 1 max -------------- or -------------- I0 I0
Fig.16 Definition of vertical linearity error.
1996 Jul 18
31
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Usage of superimposed waveforms
TDA4855
handbook, halfpage
VSCOR 19 5V 120 mV (p-p)
VPOS VAMP EWPAR EWWID 17, 18, 21, 32 5 V DC
handbook, halfpage
EWTRP 20 5V 120 mV (p-p)
VPOS VAMP EWPAR EWWID 17, 18, 21, 32 5 V DC
MBG556
MBG557
a. VSCOR (pin 19).
b. EWTRP (pin 20).
Fig.17 Superimposed waveforms at pins 19 and 20 with pins 17, 18, 21 or 32.
1996 Jul 18
32
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Printed printed-circuit board layout
TDA4855
handbook, full pagewidth
further connections to other components or ground paths are not allowed
external components of horizontal section
external components of vertical section
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18 15
TDA4855
10
11
12
13
14
external components of driver stages
only this path may be connected to ground on PCB
MBG558
For optimum performance of the TDA4855 the ground paths must be routed as shown. Only one connection to other grounds on the PCB is allowed.
Fig.18 Hints for printed-circuit board (PCB) layout.
1996 Jul 18
33
16
1
2
3
4
5
6
7
8
9
17
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
INTERNAL CIRCUITRY Table 5 Internal circuitry of Fig.1 PIN 1 SYMBOL HFLB
1.5 k 1
TDA4855
INTERNAL CIRCUIT
7x
MBG561
2
XRAY
5 k 2
6.25 V
MBG562
3
BOP
3
5.3 V
MBG563
1996 Jul 18
34
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PIN 4
SYMBOL BSENS
INTERNAL CIRCUIT
4
MBG564
5
BIN
5
MBG565
6
BDRV
6
MBG566
7
HDRV
7
MBG567
8 9
PGND VCC
power ground, connected to substrate
9
MBG568
1996 Jul 18
35
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PIN 10
SYMBOL FOCUS
INTERNAL CIRCUIT
1 k 10
MBG569
11
EWDRV
108 11 108
MBG570
12
VOUT2
12
MBG571
13
VOUT1
13
MBG572
1996 Jul 18
36
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PIN 14
SYMBOL VSYNC
INTERNAL CIRCUIT
100 14 2 k 7.3 V 1.4 V
MBG573
15
HSYNC
1.28 V 85 15 1.4 V
MBG574
16
CLBL
16
MBG575
17
VPOS
2 VBE 7.2 k 17 1 k 5V
MBG576
1996 Jul 18
37
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PIN 18
SYMBOL VAMP
INTERNAL CIRCUIT
18
5V
MBG577
19
VSCOR
19
5V
MBG578
20
EWTRP
2 VBE
20
5V
MBG579
1996 Jul 18
38
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PIN 21
SYMBOL EWPAR
INTERNAL CIRCUIT
21 1 k
5V
MBG580
22
VAGC
22
MBG581
23
VREF
23
3V
MBG582
24
VCAP
24
MBG583
25
SGND
signal ground
1996 Jul 18
39
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PIN 26
SYMBOL HPLL1
INTERNAL CIRCUIT
26
5.5 V
MBG589
27
HBUF
27
MBG584
28 29
HREF HCAP
76 28 7.7 V 29
2.525 V
MBG585
30
HPOS
1.7 V 7.7 V
1 k 30 4.3 V
MBG586
1996 Jul 18
40
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PIN 31
SYMBOL HPLL2
7.7 V
INTERNAL CIRCUIT
31
HFLB
MBG587
32
EWWID
2 VBE 7.2 k 32 1 k 5V
MBG588
Electrostatic discharge (ESD) protection
pin pin 7.3 V
MBG559
7.3 V
MBG560
Fig.19 ESD protection for pins 4, 10 to 13 and 16.
Fig.20 ESD protection for pins 2 to 4, 17 to 24 and 26 to 32.
1996 Jul 18
41
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
TDA4855
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 w M (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Jul 18
42
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4855
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Jul 18
43