Text preview for : Tda4884.pdf part of Philips TDA4884 Philips Quality Data Sheet
Back to : Tda4884.pdf | Home
INTEGRATED CIRCUITS
DATA SHEET
TDA4884 Three gain control video pre-amplifier for OSD
Preliminary specification File under Integrated Circuits, IC02 June 1994
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
FEATURES · 85 MHz video controller · Fully DC controllable · 3 separate video channels · Input black level clamping · White level adjustment for 3 channels · Contrast control for all 3 channels simultaneously · Cathode feedback to internal reference for cut-off control, which allows unstabilized video supply voltage · Current outputs for RGB signal currents · RGB voltage outputs to external peaking circuits · Blanking and switch-off input for screen protection · Sync on green operation possible · OSD application very easily. QUICK REFERENCE DATA SYMBOL VP IP Vl(b-w) VO(b-w) supply current input voltage (black-to-white; pins 2, 5 and 8) output voltage (black-to-white; pins 19, 16 and 13) nominal contrast; pins 3, 1 and 11 open-circuit PARAMETER positive supply voltage (pin 7) CONDITIONS MIN. 7.2 - - - TYP. 8.0 48 0.7 0.79 GENERAL DESCRIPTION
TDA4884
The TDA4884 is a monolithic integrated RGB amplifier for colour monitor systems with super VGA performance, intended for DC or AC coupling of the colour signals to the cathodes of the CRT. With special advantages the circuit can be used in conjunction with the TDA485x monitor deflection IC family.
MAX. 8.8 - 1.0 -
UNIT V mA V V
IO(b-w) IM B Gnom
output current (black-to-white; pins 20, 17 and 14) peak output current (pins 20, 17 and 14) bandwidth -3 dB nominal gain (pins 2, 5 and 8 to pins 19, 16 and 13) nominal contrast; pins 3, 1 and 11 open-circuit gain control for all channels (relative to Gnom) contrast control minimum contrast for OSD operating ambient temperature V6 = 1 to 6 V V6 = 0.7 V
- - 70 -
50 - 85 1
- 100 - -
mA mA MHz dB
Gv Cv COSD Tamb
-5 -22 - -20
- - -40 -
+2.6 +3.4 - +70
dB dB dB °C
ORDERING INFORMATION EXTENDED TYPE NUMBER TDA4884 Note 1. SOT146-1; 1996 November 22. PACKAGE PINS 20 PIN POSITION DIL MATERIAL plastic CODE SOT146(1)
June 1994
2
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.1 Block diagram and basic application circuit for DC and AC coupling.
June 1994
3
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
PINNING SYMBOL GC2 VI1 GC1 GND VI2 CC VP VI3 HBL CL GC3 FB3 VO3 IO3 FB2 VO2 IO2 FB1 VO1 IO1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION gain control Channel 2 signal input Channel 1 gain control Channel 1 ground signal input Channel 2 contrast control, OSD switch supply voltage signal input Channel 3 horizontal blanking, switch-off input clamping, vertical blanking, test mode gain control Channel 3 feedback Channel 3 voltage output Channel 3 current output Channel 3 feedback Channel 2 voltage output Channel 2 current output Channel 2 feedback Channel 1 voltage output Channel 1 current output Channel 1 Fig.2 Pin configuration.
TDA4884
FUNCTIONAL DESCRIPTION The RGB input signals (0.7 V(p-p)) are capacitively coupled into the TDA4884 (pins 2, 5 and 8) from a low ohmic source and are clamped to an internal DC voltage (artificial black level). Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below black level. All channels have a maximum total voltage gain of 7 dB (maximum contrast and maximum individual channel gain). With the nominal channel gain of 1 dB and nominal contrast setting the nominal black-to-white output amplitude is 0.79 V(p-p). DC voltages are used for contrast and gain control. Contrast control is achieved by a voltage at pin 6 and affects the three channels simultaneously. To provide the correct white point, an individual gain control (pins 3, 1 and 11) adjusts the signals of Channels 1, 2 and 3. Each output stage provides a current output (pins 20, 17 and 14) and a voltage output (pins 19, 16 and 13). External cascode transistors reduce power consumption of the IC and prevent breakdown of the output transistors. Signal
output currents and peaking characteristics are determined by external components at the voltage outputs and the video supply. The channels have separate internal feedback loops which ensure large signal linearity and marginal signal distortion in spite of output transistor thermal VBE variation. The clamping pulse (pin 10) is used for input clamping only. The input signals have to be at black level during the clamping pulse and are clamped to an internal artificial black level. The coupling capacitors are used in this way for black level storage. Because the threshold for the clamping pulse is higher than that for vertical blanking (pin 10) the rise and fall times of the clamping pulse have to be faster than 75 ns/V during transition from 1 V to 3.5 V. The vertical blanking pulse will be detected if the input voltage (pin 10) is higher than the threshold voltage for approximately 320 ns but does not exceed the threshold for the clamping pulse in the time between. During the vertical blanking pulse the input clamping is disabled in order to avoid misclamping in the event of composite input signals.
June 1994
4
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
The input signal is blanked and the artificial black level is inserted instead, thus the output signal is at reference black level. The DC value of the reference black level will be adjusted by cut-off stabilization (see below). During horizontal blanking (pin 9) the output signal is set to reference black level as previously described and output clamping is activated. If the voltage at pin 9 exceeds the switch-off threshold the signal is blanked and switched to ultra black level for screen protection and spot suppression during V-flyback. Ultra black level is the lowest possible output voltage (at voltage outputs) and does not depend on cut-off stabilization. For cut-off stabilization (DC coupling to the CRT) respectively black level stabilization (AC coupling) the video signal at the cathode or the coupling capacitor is divided by an adjustable voltage divider and fed to the feedback inputs (pins 18, 15 and 12). During the horizontal
TDA4884
blanking time this signal is compared with an internal DC voltage of approximately 5.8 V. Any difference will lead to a reference black level correction by charging or discharging the integrated capacitor which stores the reference black level information between the horizontal blanking pulses. For OSD fast switching of control pin 6 to less than 1 V (e.g. 0.7 V) blanks the input signals. The OSD signals can easily be inserted to the external cascode transistor (see Fig.3). During test mode (pins 9 and 10 connected to VP) the black levels at the voltage outputs (pins 12, 16 and 13) are internally set to typical 0.5 V (3 V DC at signal inputs (pins 2, 5 and 8)).
Fig.3 OSD application.
June 1994
5
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP VI Vext supply voltage (pin 7) input voltage (pins 2, 5 and 8) external DC voltage pins 20, 17 and 14 pins 19, 16 and 13 pins 1, 3, 6 and 11 pin 9 pin 10 IO IM Ptot Tstg Tamb Tj VESD average output current (pins 20, 17 and 14; note 1) peak output current (pins 20, 17 and 14) total power dissipation storage temperature operating ambient temperature junction temperature electrostatic handling for all pins (note 2) -0.1 -0.1 -0.1 -0.1 0 0 - -25 -20 -25 -500 VP VP VP + 0.7 VP + 0.7 50 100 1200 +150 +70 +150 +500 PARAMETER 0 -0.1 MIN. VP MAX. 8.8
TDA4884
UNIT V V V V V V mA mA mW °C °C °C V
no external voltages
Notes to the limiting values 1. Signal amplitude of 50 mA black-to-white is possible if the average current (including blanking times and signal variation against time) does not exceed 50 mA. The maximum power dissipation of 1200 mW has to be considered. 2. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient in free air THERMAL RESISTANCE 65 K/W
June 1994
6
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
CHARACTERISTICS VP = 8.0 V; Tamb = +25 °C; all voltages measured to GND (pin 4); unless otherwise specified. SYMBOL VP IP VI(b-w) VIC2,5,8 I2,5,8 PARAMETER positive supply voltage (pin 7) supply current (pin 7) CONDITIONS MIN. 7.2 36 - note 1 no clamping; V2,5,8 = VIC2,5,8; Tamb = -20 to +70 °C during clamping; V2,5,8 = VIC2,5,8 ± 0.7 V Contrast control (pin 6; note 2) V6 VN6 I6 Cv input voltage maximum input voltage input voltage for nominal contrast input current contrast relative to nominal contrast note 3 V6 = 4.3 V V6 = 6.0 V; pins 3, 1 and 11 open-circuit V6 = 1.0 V; pins 3, 1 and 11 open-circuit VM6 Tr tdfC input voltage for minimum contrast tracking of output signals of Channels 1, 2 and 3 pins 3, 1 and 11 open-circuit 1 V < V6 < 6 V; note 4 1.0 - - -5 2.4 -26 - - - - - 4.3 -1 3.4 -22 0.7 0 7 2.8 -0.05 TYP. 8.0 48
TDA4884
MAX. 8.8 60
UNIT V mA
Video signal inputs (Channel 1: pin 2, Channel 2: pin 5 and Channel 3: pin 8) input voltage (black-to-white value; pins 2, 5 and 8) DC voltage during input clamping (artificial black + VBE) DC current 0.7 3.1 +0.05 1.0 3.4 +0.250 V V µA
±50
±75
±120
µA
6.0 VP - 1 - -0.1 - -19 - 0.5 20
V V V µA dB dB V dB ns
delay between leading edges (falling) V6 = 4.3 V to 0.7 V; of step in contrast voltage and output input fall time at pin 6: signals at voltage outputs (pins 19, tfCC = 2 ns; note 5 16 and 13) delay between trailing edges (rising) V6 = 0.7 V to 4.3 V; of step in contrast voltage and output input rise time at pin 6: signals at voltage outputs (pins 19, trCC = 2 ns; note 5 16 and 13) fall time of output signals at voltage outputs (pins 19, 16 and 13) rise time of output signals at voltage outputs (pins 19, 16 and 13) 90% to 10% amplitude; input fall time at pin 6: tfCC = 2 ns; note 5 10% to 90% amplitude; input rise time at pin 6: trCC = 2 ns; note 5
tdrC
-
15
25
ns
tfC
-
6
15
ns
trC
-
6
15
ns
June 1994
7
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - 3.75 55 2.6 -5
MAX.
UNIT
Gain control (pin 3 for Channel 1, pin 1 for Channel 2 and pin 11 for Channel 3; note 6) V3,1,11 VN3,1,11 R3,1,11 Gv input voltage input voltage for nominal gain input resistance gain relative to nominal gain V6 = 4.3 V; V3,1,11 = 6 V V6 = 4.3 V; V3, 1, 11 = 1 V Vint I18,15,12 VCRT TVint VVint VO(b-w) internal reference voltage maximum output current black level at CRT variation of Vint in the temperature range variation of Vint with supply voltage nominal signal output voltage (black-to-white value) maximum adjustable black level voltage black level voltage during switch-off, equal to minimum adjustable black level voltage black level voltage during test mode signal-to-noise ratio output thermal distortion black level between clamping pulses maximum offset during sync clipping variation of nominal output signal (black-to-white value) with temperature during output clamping; V18,15,12 = 3 V note 8 Tamb = -20 to +70 °C 7.2 V VP 8.8 V V6 = 4.3 V; Vl(b-w) = 0.7 V; pins 3, 1 and 11 open-circuit during output clamping; Tamb = -20 to +70 °C V9 = VP; RO = 33 ; Tamb = -20 to +70 °C V9 = VP; V10 = VP; pin 1 open-circuit; V2,5,8 = VIC2,5,8; note 9 note 10 IO(b-w) = 50 mA; note 11 line frequency 30 kHz V2,5,8 < VIC2,5,8; note 12 V6 = 4.3 V; Vl(b-w) = 0.7 V; Tamb = -20 to +70 °C; pins 3, 1 and 11 open-circuit pins 3, 1 and 11 open-circuit 1.0 3.6 44 2 -5.5 6.0 3.95 66 3.3 -4.5 V V k dB dB
Feedback input (Channel 1: pin 18, Channel 2: pin 15 and Channel 3: pin 12; note 7) 5.6 -500 0 0 0 5.8 -100 40 20 60 6.1 -60 200 50 100 V nA mV mV mV
Voltage outputs (Channel 1: pin 19, Channel 2: pin 16 and Channel 3: pin 13; note 1) 0.69 0.79 0.89 V
Vblx VblSO
1 30
1.2 45
1.4 100
V mV
VblT
0.3
0.7
1.2
V
S/N DTh LFVbl Voff TVO(b-w)
- - - 0 0
50 0.6 0.5 7 2.5
44 1 4.5 15 10
dB % mV mV %
Current outputs (Channel 1: pin 20, Channel 2: pin 17 and Channel 3: pin 14; note 13) IO(b-w) signal current (black-to-white value) - with peaking IO = 50 mA IO = 100 mA V9 = VP; RO = 33 8 - - - 0 50 - - - 20 - 100 2.0 2.2 900 mA mA V V µA
start of HF-saturation of output V20-19; V17-16; V14-13 transistors IblSO June 1994 output current during switch-off
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
SYMBOL
PARAMETER
CONDITIONS
MIN. - - -
TYP.
MAX.
UNIT
Frequency response at voltage outputs (note 14) Gvf trO dVO gain decrease by frequency response at pins 19, 16 and 13 rise time at voltage output (pins 19, 16 and 13) overshoot of output signal pulse related to actual output pulse amplitude 70 MHz; single channel 10% to 90% amplitude; input rise time = 1 ns single channel; input rise time = 2.5 ns; Vl(b-w) = 0.7 V; V6 = 4.3 V; pins 3, 1 and 11 open-circuit 1.3 4.1 4 3 5.0 8 dB ns %
Crosstalk at outputs with speed up circuit (note 15) Ctr V9 transient crosstalk - - 0.1 -
Threshold voltages for clamping, blanking and switch-off (pins 9 and 10; note 16) threshold for horizontal blanking (blanking, output clamping) threshold for switch-off (blanking, minimum black level, no output clamping) R9 V10 input resistance threshold for vertical blanking (blanking, no input clamping) threshold for clamping (input clamping, no blanking) threshold for test mode (no clamping, no blanking, for VblT see above) I10 tr,f10 tw10 current rise and fall time for clamping pulse width of clamping pulse against ground note 17 note 17 for test mode also V9 > 6.8 V (switch-off) V10 < VP - 1 V V10 VP - 1 V note 17 1.2 5.8 1.4 6.5 1.6 6.8 V V
50 1.2 2.6
80 1.4 3.0
110 1.6 3.5 VP
k V V V
VP - 1 -
-3 - - 0.6
-1 100 - -
- - 75 -
µA µA ns/V µs
June 1994
9
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
Notes to the characteristics 1. Definition of levels:
TDA4884
Artificial black level: internal signal level behind input emitter follower during input clamping and signal clipping. This level is inserted instead of the input signal during blanking. Reference black level: DC voltage during output clamping at voltage outputs, not influenced by contrast or gain setting, adjustable by cut-off stabilization. Cut-off level: corresponding DC voltage at CRT cathode in closed feedback loop. Black level: actual signal black level at either voltage outputs or cathode. At voltage outputs the black level is equal to reference black level because there is no brightness control via TDA4884. At cathode the black level is equal to cut-off level. Brightness can be adjusted via grid 1. Ultra black level, switch-off level: lowest adjustable reference black level, lowest signal level at voltage outputs. The minimum guaranteed control range for reference black level is 0.1 to 1 V. The ultra black level is depending on the external resistor RO at voltage outputs (pins 13, 16 and 19) to ground. RO V bISO ------------------------------ × 4.65 V. 3.5k + R O Signal processing see Fig.4. 2. Linear control range is 1 to 6 V for V6, independent from supply voltage. Open pin 6 leads to absolute maximum contrast setting. It is recommended to not exceed V6 = VP - 1 V in order to avoid saturation of internal circuitry. For V6 < VM6 ~ 0.7 V a small negative signal (~ -40 dB) will appear. For frequency dependence of contrast control see note 14. Typical contrast characteristic see Fig.5. 3. Definition for nominal output signals: input Vl(b-w) = 0.7 V, gain pins 3, 1 and 11 open-circuit, contrast control V6 = VN6. 4. Tr = 20 × maximum of A1 A 1 A 30 A 2 A 30 A 20 log -------- × -------- |; | log -------- × -------- |; | log -------- × -------- | [ dB ] A2 A 10 A 3 A 10 A 20 A 3
A×: signal output amplitude in Channel x at any contrast between 1 and 6 V. A×0: signal output amplitude in Channel x at nominal contrast and same gain setting. 5. Typical step in contrast voltage and response at signal outputs for nominal input signal Vl(b-w) = 0.7 V. Typical OSD fast blanking input/output see Fig.6. 6. Linear control range is 1 to 6 V for V3, V1 and V11, independent from supply voltage. Typical gain characteristic see Fig.7. 7. The internal reference voltage can be measured at pins 18, 15 and 12 during output clamping (V9 = 2 V) in closed feedback loop. Typical variation of Vint with temperature and power supply voltage see Fig.8. 8. Slow variations of video supply voltage VCRT (see Fig.1) will be suppressed at CRT cathode by cut-off stabilization. Change of VCRT by 5 V leads to specified change of cut-off voltage. 9. The test mode allows testing without input and output clamping pulses. The signal inputs (pins 2, 5 and 8) have to be biased via resistors to the previously measured clamp voltages of approximately 3 V (artificial black level + VBE). Signal blanking is not possible during test mode. 10. The signal-to-noise ratio is calculated by the formula (frequency range 1 to 70 MHz): peak-to-peak value of the nominal signal output voltage S --- = 20 log -------------------------------------------------------------------------------------------------------------------------------------------------- [ dB ] RMS value of the noise output voltage N 11. Large output swing e.g. IO(b-w) = 50 mA leeds to signal depending power dissipation in output transistors. Thermal VBE variation is compensated. 12. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below black level. Typical sync clipping see Fig.9.
June 1994
10
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
1 1 13. The output current approximately follows the equation I O = V O ------- + ----------------- 500 µA for V O > V blSO and with R O 2.2 k RO = external resistor at voltage output to ground. The external RC combination at pins 19, 16 and 13 (see Fig.1) enables peak currents during transients. 14. Frequency response, crosstalk and pulse response have been measured at voltage outputs in a special printed-circuit board with 50 line in/out connections and without peaking (see TEST PCB). Typical frequency response see Fig.10, typical pulse response see Fig.11 and typical characteristic of contrast control versus frequency see Fig.12. 15. Crosstalk between any two output pins. Input conditions: One channel (Channel A) with nominal input signal and minimum rise time. The inputs of the other channels capacitively coupled to ground (Channel B). Gain pins 3, 1 and 11 open-circuit. Output conditions: Output signal of Channel A controlled by contrast setting (pin 6) to VO(b-w) = VA = 0.7 V, the rise time should be 5 ns. Output signal of Channel B then is VO(b-w) = VB. VB Transient crosstalk: C tr = ------ . VA Crosstalk versus frequency has been measured without peaking circuit, with nominal input signal and nominal settings. Typical frequency dependent crosstalk between channels see Figs 13, 14 and 15. 16. The internal threshold voltages are derived from a stabilized voltage. The internal pulses are generated while the input pulses are higher than the thresholds. Voltages of less than -0.1 V at pins 9 and 10 can influence black level control and should be avoided. 17. For 75 ns/V < trf10 < 240 ns/V generation of internal input clamping and blanking pulse is not defined. Any pulses not exceeding the threshold of input clamping (typical 3 V) will be detected as blanking pulse. Timing of pulses at pin 10 see Fig.16.
June 1994
11
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.4 Signal processing.
June 1994
12
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.5 Typical contrast characteristic.
Fig.6 Typical OSD fast blanking input/output.
June 1994
13
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.7 Typical gain characteristic.
Fig.8 Typical variation of Vint with temperature and power supply voltage.
June 1994
14
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.9 Typical sync clipping.
Fig.10 Typical frequency response.
June 1994
15
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.11 Typical pulse response.
June 1994
16
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.12 Typical characteristic of contrast control versus frequency.
Fig.13 Typical crosstalk: Channel 1 2 and 3.
June 1994
17
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.14 Typical crosstalk: Channel 2 1 and 3.
Fig.15 Typical crosstalk: Channel 3 1 and 2.
June 1994
18
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.16 Timing of pulses at pin 10.
June 1994
19
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TEST PCB For high frequency measurements a special application and printed-circuit board with only a few external components is built. Fig.17 shows the application circuit and Fig.18 the layout of the double sided printed board. All components on the rear (below) are of SMD type as well as R13, R14 and R15 on the front. Short HF loops and minimum crosstalk between the channels as well as input and output are achieved by properly shaped ground areas star connected to the IC ground pin. The HF input signals can be fed to the subclick connectors X1, X2 and X3 by a 50 line. The line is then terminated by a 51 resistor on the board. With choice of jumper connections (JA1, JA2 and JA3) it is possible to connect channel inputs to its input connector, to connect all channels to one input connector (white pattern) and to ground each input via the coupling capacitor. For operation without input clamping (e.g. test mode) the DC bias can be provided by VIDC (connector X21) if a short at JA4, JA5 and JA6 is made (solder short or small SMD resistor). The output signal can be monitored via 50 terminated lines at the voltage outputs (subclick connectors X4, X5 and X6). With 100 in parallel to the 50 terminated line the effective load resistance at the voltage outputs is 33 . The mismatch seen from the line towards the IC has no significant effect if the line is match terminated. A peaking circuit (C15, R16 Channel 1) can be added for realistic loading of the voltage outputs.
TDA4884
Black level adjustment is done by VIOS, UFBX (connector X21) and resistors R19, R22 and R25 (Channel 1). If R19 is equal to the effective load resistor at the voltage output the reference black level is approximately U REF = VIOS V ( I01 ) and R22 V(I01) = V int + ( V int UFBX ) × ---------- . R25 Vint is the internal reference voltage at the feedback input (typical 5.8 V). By this it is possible to adjust the reference black level and the voltage at the current outputs independently. DC control for contrast and gain is prepared at connectors X21 and X22. Contrast control can also be set by the potentiometer P1 (jumper JA11). The series resistor R11 is necessary if fast OSD switching is activated via 50 line (X10), a line termination can be done at the connector X9. Clamping and blanking pulses are fed to the IC via connectors X7 and X8. Connector X23 is used for power supply. The capacitors C7 and C8 should be located as near as possible to the IC pins.
June 1994
20
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.17 Application circuit for test PCB.
June 1994
21
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
TDA4884
Fig.18 Double sided test PCB layout.
June 1994
22
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
RECOMMENDATIONS FOR BUILDING THE APPLICATION BOARD General · Double sided board · Short HF loops by large ground plane on the rear . Voltage outputs · Capacitive loads as small as possible · Short interconnection via resistor to ground. Supply voltage
TDA4884
· Capacitors as near as possible to the pins · Use of high frequency capacitors (low self inductance, e.g. SMD). Current outputs, emitter of cascode transistors · The external interconnection inductivity can build a resonance together with the internal substrate capacity, a damping resistor of some 10 near to the IC pin can suppress such oscillations.
Fig.19 Internal circuits.
June 1994
23
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil)
TDA4884
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH w M (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-05-24
June 1994
24
Philips Semiconductors
Preliminary specification
Three gain control video pre-amplifier for OSD
SOLDERING Introduction
TDA4884
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
June 1994
25