Text preview for : HP520.pdf part of HP 520 Ñõåìà íà ëàïòîï. HP520
Back to : HP520.rar | Home
A B C D E
1 1
2
Compal confidential 2
Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_GM+ ICH7-M core logic
3
2007-03-20 3
REV:0.5
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 1 of 47
A B C D E
A B C D E
Compal confidential
File Name : LA-3491P
Volga 2.0
1 1
Fan Control
page 4
Mobile Yonah/Merom Thermal Sensor Clock Generator
uFCPGA-478 CPU ADM1032AR ICS9LP306BGLFT
page 4,5,6 page 4 page 15
FSB
H_A#(3..31) 533/667MHz H_D#(0..63)
CRT DDR2-SO-DIMM X2
page 16 Intel Calistoga MCH DDR2 -400/533/667 BANK 0, 1, 2, 3 page 13,14
945GM
LVDS Conn PCBGA 1466 Dual Channel
page 17 page 7,8,9,10,11,12
2 2
DMI
USB2.0
USB Conn x2
page 29
MODEM AMOM
AC-LINK/Azalia
Audio Conexant CX20548
PCI-E BUS Intel ICH7-M CX20549-12
page 27
page 26
INTEL LAN PCI BUS mBGA-652
82562V 10 /100 AMP & Audio Jack
LED page 18,19,20,21 SATA TPA6017A2 page 28
page 23
page 31 SATA HDD Connector
3 3
SPI page 22
Mini-Card
CardBus Controller
RTC CKT. RJ45/11 CONN WLAN SPI ROM PATA Slave
IDE ODD Connector
page 19 page 23 page 25 CB-1410 25LF080A
page 31 page 22
page 24
LPC BUS
Power OK CKT.
page 34 Slot 0
page 24
Power On/Off CKT. SMSC KBC 1070
page 30
page 31
Touch Pad CONN. Int.KBD
4 DC/DC Interface CKT. page 32 page 30 4
page 33
Power Circuit DC/DC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
Page 37¡B 38¡ 39 ¡ 40
B B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 2 of 47
A B C D E
5 4 3 2 1
Symbol Note :
Voltage Rails
Power Plane Description S0-S1 S3 S5
: means Digital Ground
VIN Adapter power supply (18.5V) N/A N/A N/A
D
B+ AC or battery power rail for power circuit N/A N/A N/A : means Analog Ground D
+CPU_CORE Core voltage for CPU ON OFF OFF
+VCCP 1.05V power rail for Processor I/O and MCH/ICH core power ON OFF OFF NOXDP@ : means just build when XDP function disable.
+0.9V 0.9V switched power rail for DDRII Vtt ON OFF OFF LP@ : means just build when Low power clock gen. install
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF BATT@ : means need be mounted when 45 level assy or rework stage.
+1.8V 1.8V power rail for DDRII ON ON OFF 45@ : means need be mounted when 45 level assy or rework stage.
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF 14@ : means need be mounted when 14.1"
+3VALW 3.3V always on power rail ON ON ON* WLAN@ : means need be mounted when have wireless LED Function
+3VS 3.3V switched power rail ON OFF OFF WLAN14@ : means need be mounted when have wireless LED Function and 14"
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+RTC_VCC RTC power ON ON ON
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
CONN@ : means ME parts
Debug@ : means Mini debug card use
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Calistoga 945GM R3 SA0000059L0
C
Calistoga 945GM R1 SA0000059A0 C
Calistoga 940GML R3 SA000011C10
Calistoga 940GML R1 SA000011C00
ICH7 R3 SA00000V1A0
ICH7 R1 SA00000V1F0
IAT50 945GM FF 46147932L01
IAT50 940GML DF 46147932L02
IAT50 940GML DF 46147932L03 (No WLAN)
B IAT60 945GM FF 46147932L21 B
IAT60 940GML DF 46147932L22
External PCI Devices IAT60 940GML DF 46147932L23 (No WLAN)
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
CARD BUS D6 AD22 2 C
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
A
DDR SO-DIMM 1 A4 10100100 A
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 3 of 47
5 4 3 2 1
5 4 3 2 1
H_D#[0..63] <7>
<7> H_A#[3..31]
JP1A
+3VS
H_A#3 J4 E22 H_D#0
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 XDP_DBRESET#_R
R10
M3 E26 1 2 @ 1K_0402_5%
H_A#6
H_A#7
K5
M1
A5#
A6#
D2#
D3# H22
F23
H_D#3
H_D#4
ITP-XDP Connector Change to same as +VCCP
H_A#8 N2
A7# D4#
G25 H_D#5 Chimay 4/6 Change value in 5/02
H_A#9 A8# D5# H_D#6
J1 A9# D6# E25
D H_A#10 H_D#7 JP29 XDP_TDI R2 54.9_0402_1% D
N3 A10# D7# E23 1 2
H_A#11 P5 K24 H_D#8 1 2
H_A#12 A11# D8# H_D#9 XDP_BPM#5 GND0 GND1 XDP_TMS R3 54.9_0402_1%
P2 A12# D9# G24 3 OBSFN_A0 OBSFN_C0 4 1 2
H_A#13 L1 J24 H_D#10 XDP_BPM#4 5 6
H_A#14 A13# D10# H_D#11 OBSFN_A1 OBSFN_C1 XDP_TDO R4 54.9_0402_1%
P4 A14# D11# J23 7 GND2 GND3 8 1 2
H_A#15 P1 H26 H_D#12 XDP_BPM#3 9 10
H_A#16 A15# D12# H_D#13 XDP_BPM#2 OBSDATA_A0 OBSDATA_C0 XDP_BPM#5 R5 54.9_0402_1%
R1 A16# D13# F26 11 OBSDATA_A1 OBSDATA_C1 12 1 2
H_A#17 Y2 K22 H_D#14 13 14
H_A#18 A17# D14# H_D#15 XDP_BPM#1 GND4 GND5 XDP_HOOK1 R2199 1
U5 A18# D15# H25 15 OBSDATA_A2 OBSDATA_C2 16 2 @ 54.9_0402_1%
H_A#19 R3 N22 H_D#16 XDP_BPM#0 17 18
H_A#20 A19# D16# H_D#17 OBSDATA_A3 OBSDATA_C3 XDP_TRST# R6 51_0402_1%
W6 A20# D17# K25 19 GND6 GND7 20 1 2
H_A#21 U4 P26 H_D#18 21 22
H_A#22 A21# D18# H_D#19 OBSFN_B0 OBSFN_D0 XDP_TCK R7 54.9_0402_1%
Y5 A22# D19# R23 23 OBSFN_B1 OBSFN_D1 24 1 2
H_A#23 U2 L25 H_D#20 25 26
H_A#24 A23# D20# H_D#21 GND8 GND9
R4 A24# D21# L22 27 OBSDATA_B0 OBSDATA_D0 28
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 29 30 This shall place near CPU
H_A#26 A25# D22# H_D#23 OBSDATA_B1 OBSDATA_D1
T3 A26# D23# M23 31 GND10 GND11 32
H_A#27 W3 P25 H_D#24 33 34
H_A#28 A27# D24# H_D#25 R2200 XDP@ OBSDATA_B2 OBSDATA_D2
W5 A28# D25# P22 35 OBSDATA_B3 OBSDATA_D3 36
H_A#29 Y4 P23 H_D#26 1K_0402_5% 37 38
H_A#30 A29# D26# H_D#27 H_PW RGOOD GND12 GND13
W2 A30# D27# T24 1 2H_PWRGOOD_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_CPU_XDP CLK_CPU_XDP <15>
H_A#31 Y1 R24 H_D#28 XDP_HOOK1 41 42 CLK_CPU_XDP# CLK_CPU_XDP# <15>
<7> H_REQ#[0..4] A31# D28# HOOK1 ITPCLK#/HOOK5
L26 H_D#29 +VCCP 43 44 +VCCP
H_REQ#0 D29# H_D#30 VCC_OBS_AB VCC_OBS_CD H_RESET#_R R2201 1
K3 REQ0# D30# T25 2 1 45 HOOK2 RESET#/HOOK6 46 2 1K_0402_1% H_RESET#
H_REQ#1 H2 N24 H_D#31 C1455 0.1U_0402_16V7K 47 48 XDP_DBRESET#_R R2202 2 1 200_0402_1% XDP_DBRESET#
H_REQ#2 REQ1# D31# H_D#32 HOOK3 DBR#/HOOK7 XDP@
K2 REQ2# D32# AA23 XDP@ 49 GND14 GND15 50
H_REQ#3 J3 AB24 H_D#33 51 52 XDP_TDO XDP@
H_REQ#4 REQ3# D33# H_D#34 SDA TD0 XDP_TRST#
L5 REQ4# D34# V24 Removed at 5/30.(Follow 53 SCL TRST# 54
V26 H_D#35 55 56 XDP_TDI R2203 XDP@
H_ADSTB#0 L2
D35#
W25 H_D#36 Chimay) XDP_TCK 57
TCK1 TDI
58 XDP_TMS 0_0402_5%
<7> H_ADSTB#0 ADSTB0# D36# TCK0 TMS
H_ADSTB#1 V4 U23 H_D#37 59 60 XDP_PRE 1 2
<7> H_ADSTB#1 ADSTB1# D37# GND16 GND17
U25 H_D#38
C D38# H_D#39 CONN@ SAMTE_BSH-030-01-L-D-A C
D39# U22
AB25 H_D#40 Place R2203 within 200ps (~1") to CPU
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK A22 D42# H_D#43
<15> CLK_CPU_BCLK BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
D45# Y22
AC26 H_D#46
H_ADS# H1
D46#
D47# AA24
AC22
H_D#47
H_D#48
Thermal Sensor ADM1032AR-2
<7> H_ADS# ADS# D48#
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49# +3VS
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53 2
<7> H_DRDY# DRDY# D53#
R12 H_HIT# G6 AD20 H_D#54 C2
<7> H_HIT# HIT# D54#
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
<7> H_HITM# HITM# D55#
1
1 2 H_IERR# D20 AF23 H_D#56 0.1U_0402_16V4Z
+VCCP H_LOCK# IERR# D56# H_D#57 1 R13
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58 U1
<7> H_RESET# RESET# D58#
AD21 H_D#59 1 8 ICH_SMBCLK 10K_0402_5%
D59# H_D#60 VDD SCLK
<7> H_RS#[0..2] AE25
2
H_RS#0 D60# H_D#61 H_THERMDA ICH_SMBDATA
F3 RS0# D61# AF25 2 D+ SDATA 7
H_RS#1 F4 AF22 H_D#62 C3
H_RS#2 RS1# D62# H_D#63 H_THERMDC THERM_SCI#
G3 RS2# D63# AF26 1 2 3 D- ALERT# 6 THERM_SCI# <20>
H_TRDY# G2
<7> H_TRDY# TRDY# 2200P_0402_50V7K THERM# 4 5
H_DINV#0 THERM# GND
DINV0# J26 H_DINV#0 <7>
M26 H_DINV#1 R14
DINV1# H_DINV#1 <7>
XDP_BPM#0 AD4 V23 H_DINV#2 +3VS 1 2 ADM1032AR-2_MSOP8
BPM0# DINV2# H_DINV#2 <7>
XDP_BPM#1 AD3 AC20 H_DINV#3
BPM1# DINV3# H_DINV#3 <7>
XDP_BPM#2 AD1 10K_0402_5% Address:1001_101
B XDP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] <7>
H23 H_DSTBN#0 <13,14,15,20,25> ICH_SMBCLK ICH_SMBCLK
XDP_DBRESET# C20 DSTBN0# H_DSTBN#1 ICH_SMBDATA
<20> XDP_DBRESET# DBR# DSTBN1# M24 <13,14,15,20,25> ICH_SMBDATA
H_DBSY# E1 W24 H_DSTBN#2
<7> H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
<19> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0
<19,40> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
<7> H_DPWR# DPWR# DSTBP1#
XDP_BPM#4 AC2 MISC Y25 H_DSTBP#2
<40> H_PROCHOT# PRDY# DSTBP2#
XDP_BPM#5 AC1 AE24 H_DSTBP#3
PREQ# DSTBP3#
+VCCP 1 R15 2 H_PROCHOT# D21
PROCHOT#
56_0402_5% +5VS
<19> H_PWRGOOD H_PW RGOOD D6
H_CPUSLP# D7
PWRGOOD PWM Fan Control circuit
<7> H_CPUSLP# XDP_TCK SLP#
AC5 TCK
XDP_TDI AA6 A6 H_A20M# JP3
TDI A20M# H_A20M# <19>
1
XDP_TDO AB3 A5 H_FERR# 1 1
TDO FERR# H_FERR# <19> 1
R16 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# D1 C4 C5
TEST1 IGNNE# H_IGNNE# <19> 2
R17 2 1 51_0402_5% TEST2 D25 B3 H_INIT#
TEST2 INIT# H_INIT# <19>
XDP_TMS AB5 C6 H_INTR CH751H-40_SC76 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_85205-0200