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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
D
D
CANNES-L / BONN-L NVIDIA(N-10M-GE)
C
CPU :Intel Pentium Chip Set :Intel Cantiga & ICH9M Remarks : Montevina Platform
Model Name : R719 / R519 PBA Name : MAIN PCB Code : GCE BA41-01146A NANYA BA41-01147A HST BA41-01148A
B
Dev. Step Revision T.R. Date
Design
: PR : 1.0 : 2009.08.07
CHECK
APPROVAL
g l n a u ti s n m e a id S f n o C
DRAW DATE TITLE
C
B
A
Jun PARK
CHECK DEV. STEP
A
10/10/2008 PR
REV
CANNES-L_EXT
MAIN COVER
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
Owner : SEC Mobile R & D
4
Signature :
3
X
2
APPROVAL
HJ KIM
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FAN
BLOCK DIAGRAM
Intel Pentium Intel Celeron
T4300, T4200, T3400, T1600, T1700
CLOCK
CK-505M
Page 8 CPU Thermistor
EMC2112
D
Page 12
D
Page 8
Page 9~11
L2 Cache : 1MB FSB 800/667MHz Channel A (Reverse)
LED LCD / CCFL 17.3" HD+ / 15.6"
Page 26
Dual channel DDR II 800 LVDS(Dual Channel)
CRT
Page 27
C
SUB_USB
ANT
Bluetooth
B
CARDREADER
3-in-1
ALCOR AU6336
Page 31
SPI ROM
Page 25
g l n a u ti s n m e a id S f n o C
Internal Cantiga-GL40
DDR2-SODIMM x 2
P 0,2,6
Channel B (Reverse)
External Cantiga-PM45
nVidia N10M-GE
C
gDDR3
Page 25
USB 2.0
SATA
SATA0
P 10
2.5" HDD
Page 25
P5
SATA1
ICH9-M
FFC
12.7mm ODD
Page 25
0.3M
P8
WLAN
PCIe
PEX1
( Half Type)
PEX4
Page 32
P3
RTC
B
10/100 LAN Controller RTL8103EL
RJ45
Page 30
Transformer
SYNAPTICS
High Definition
16Mbit
MICOM MEC1308
Page 34
TOUCHPAD
ALC269
Page 28
For Cannes-L For Bonn-L
Space bar
A
L
R
KEYBOARD
Page 35
DRAW DATE TITLE
A
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
MAIN BLOCK DIAGRAM
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
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APPROVAL
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BOARD INFORMATION
D
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
I C / SMB Address
Devices ICH9M CK-505M (Clock Generator) SODIMM0 SODIMM1 MICOM BATTERY EMC2102 Address Master 1101 001X 1010 000X 1010 001X Master 0001 011X 0111 101X 16h 7Ah D2h A0h A4h Hex Bus SMBUS Master Clock, Unused Clock Output Disable Power Rail VDC_ADPT VDC VDC_CHG PRTC_BAT P5.0V_ALW P12.0V_ALW P1.7V_VREF P2.0V_VREF P5.0V_VREF_FILT Descriptions Primary DC system power supply (9 to 19V) Charger Reference Voltage Source 3.3V supply for the RTC well. 5.0V always power well 12.0V always power well Power Chip Reference Power Chip Reference Power Chip Reference Output voltage of TPS51125 (if VDC is removed, it will be off) 3.3V (LED LCD) Power Rail P1.05V_PEG P5.0V P3.3V P1.05 P0.9V P5.0V_AUX P3.3V_AUX P1.8_AUX CPU_CORE Descriptions P1.05V (Direct Media Interface Compensation) 5.0V Power Rail (off in S3-S5) 3.3V Power Rail (off in S3-S5) 1.05V Power Rail (off in S3-S5) DDR2 Termination 5.0V Power Rail (off in S4-S5) 3.3V Power Rail (off in S4-S5) 1.8V Power Rail (off in S4-S5) Core Voltage for CPU
2
Voltage Rails
C
USB PORT Assignation
Port Number UHCI_0 UHCI_1 UHCI_2 0 1 2 3 4 5 ASSIGNED TO USB PORT (LEFT, BOTTOM) USB PORT (LEFT,CENTER ) CARD READER(AU6336) BLUETOOTH Port Number UHCI_3 6 7 8 UHCI_4 9 10 UHCI_5 11
SATA Assignation
Port Number SATA0 SATA2 ASSIGNED TO HDD Port Number SATA1 SATA3
B
PCI EXPRESS Assignation
Port Number PCIe1 PCIe3 ASSIGNED TO WLAN Port Number PCIe2 PCIe4
Crystal / Oscillator
TYPE Crystal Crystal Crystal Crystal PREQUENCY 32.768KHz 10MHz 14.318MHz 25MHz DEVICE ICH9-M MICOM CLOCK-Generator LAN
g l n a u ti s n m e a id S f n o C
P3.3V_MICOM LCD_VDD3V AUD_P5V P4.75V_AUD P5.0V_STB P5.0V_ODD ASSIGNED TO KBC3_CHG4.2V To charge battery USB PORT (LEFT, TOP) CAMERA P1.2V_LAN Internal Regulator's Power of LAN Controller 3.3V (3-in-1 Socket) SUB_USB(TBD) P3.3V_MCD EGFX_CORE P1.5V P1.5_AUX P1.8V ASSIGNED TO ODD ASSIGNED TO Wired LAN -
5.0V supply for Audio Auido Analog Voltage
C
To charge USB device at sleep status 5.0V supply at SUB_ODD Board
nVidia Graphic Chip power 1.5V Power Rail (off in S3-S5) 1.5V Power Rail (off in S4-S5) 1.8V Power Rail (off in S3-S5)
Power source of External
B
REVISION HISTORY
USAGE
See rev notes for more information.
A
DRAW DATE TITLE
A
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
MAIN BOARD INFO
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
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BA41PAGE
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POWER DIAGRAM
KBC3_SUSPWR (CHP3_S4_STATE*) KBC3_PWRON (CHP3_SLPS3*) KBC3_VRON
D
D
AC ADAPTER TPS51125 DC BATTERY P5.0V_ALW
USB, Swithched Power
P5.0V_AUX
GL40
P5.0V P5.0V_AUD
VDC
P3.3V_MICOM
C
P12.0V_ALW RT8107
TPS51124
TPS51620
B
SC471
g l n a u ti s n m e a id S f n o C
ALC269Q
EMC2112 GL40 CRT HDD
ODD TOUTCHPAD CAMERA FAN
P3.3V_AUX
SPI ROM, MICOM, LEDs
ICH9M, LED, Wire LAN, LED LCD RTL8103EL, EMC2112
P3.3V
P5.0V_STB
CK505M 80 PORT LED LCD GL40 ALC269Q DDR2 AU6336 ICH9M 3-in-1 Socket
WLAN HDD MICOM LID SW
LEDs
P3.3V_MCD
C
N10M-GE
P1.8V_AUX
P1.8V
GL40, DDR II
DDR II Termination
P0.9V
P1.5V_AUX
P1.5V
PENTIUM CPU gDDR3 CK505M GL40 ALC269Q PENTIUM CPU GL40 ICH9M
ICH9M
P1.05V
PENTIUM CPU
CPU_CORE P1.2V_LAN
B
RTL8103EL
N10M-GE
EGFX_CORE
S5-S4
A
S3
DRAW DATE TITLE
S0
A
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
MAIN POWER DIAGRAM
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
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23) KBC3_CPURST#
23
RTC Battery
PRTC_BAT CHP3_RTCRST#
1
POWER SEQUENCE
9) P3.3V_AUX
PRTC_BAT D 25) PLT3_RST# 16) P1.5V
POWER S/W
4) P3.3V_MICOM 16) P3.3V
11) CHP3_SLPS5#/4#/3# 12) KBC3_RSMRST#
13
ICH9-M
9) P3.3V_AUX 16) P3.3V 17) P1.5V 18) P1.05V
VRMPWRGD
22
17) P3.3V
22) CLK3_PWRGD
CK-505M
Sheet 12
15) P5.0V
EMC21112
Sheet 8
D
12
14 24
4) P3.3V_MICOM 9) P3.3V_AUX 2) VDC LCD_VDD3V VDD_LED 16) P3.3V 15) P5.0V
MX25L
Sheet 25
KBC
14) KBC3_PWRBTN#
6
6) KBC3_PWRSW#
LED LCD
Sheet 26
24) KBC3_PWRGD
20) VRM3_CPU_PWRGD 7) KBC3_SUSPWR 14) KBC3_PWRON
C
Sheet 35
(KBC3_VRON)
** KBC3_USBCHG **
ADAPTER
4) P3.3V_MICOM
VDC_ADPT / VDC_CHG
ISL6255
BATTERY
2
2-1) P12.0V_ALW
B
3
3) P5.0V_ALW
P3.3V_AUX & P5V_ALW
9) P3.3V_AUX 8) P5.0V_AUX
9 8
TPS51125
0 OHM
5
5) P5.0V_STB
4) P3.3V_MICOM
4
16) P3.3V
9) P3.3V_AUX 14) KBC3_PWRON SI3456
Sheet 44
16
14-1
14-1) KBC3_PWRON_INV# 8) P5.0V_AUX 14) KBC3_PWRON
AP4435
Sheet 44
15) P5.0V
15 17
g l n a u ti s n m e a id S f n o C
26) CHP3_SUSSTAT#
PWROK
25
CRT
Sheet 27
26
25) CPU1_PWRGDCPU 27) PLT3_RST#
15) P5.0V
P5.0V_AUD ALC 269
Sheet 28
7
P5.0V_AUD
14
27
P4.75V_AUD 17) P1.5V 16) P3.3V
Sheet 20~24
20) VRM3_CPU_PWRGD
C RTL8103EL
Sheet 30
2) VDC
9) P3.3V_AUX
7) KBC3_SUSPWR
P1.8V_AUX
10) P1.8V_AUX P0.9V
10
7) KBC3_SUSPWR
RT8207
20) CPU_CORE 17) P1.5V
16) P3.3V
AU6336
Sheet 31
P3.3V_MCD
14) KBC3_PWRON
Sheet 41
MEM1_VREF
PENTIUM CPU
11) P1.5V_AUX
2) VDC
2) VDC
P1.5V_AUX & P1.05V
11
18) P1.05V
16) P3.3V
WLAN
Sheet 32
Sheet 9~11
28
7) KBC3_SUSPWR
TPS51124
Sheet 42
18) P1.05V
18
28) CPU1_CPURST#
24) KBC3_PWRGD
15) P5.0V
PWROK
ODD
Sheet 33
14) KBC3_PWRON
19) VCCP3_PWRGD
19
CL_PWROK
26) PLT3_RST# 18) P1.05V
16) P3.3V 15) P5.0V 2.5" HDD
Sheet 8
B
CHP3_DPRSLPVR
GL40
CPU1_DPRSTP#
10) P1.8V_AUX 16) P1.5V
15) P5.0V
TOUCHPAD
Sheet 36
2) VDC
CPU_CORE
20) CPU_CORE
20
17) P3.3V
Sheet 13~17
TPS51620
Sheet 43
19) VCCP3_PWRGD GCORE3_PWRGD
4) P3.3V_MICOM 16) P3.3V 9) P3.3V_AUX
LED
Sheet 36
21) VRM3_CPU_PWRGD
10) P1.8V_AUX MEM1_VREF 17) P3.3V
21
DDR2
8) P5.0V_ALW
TOUCHPAD
Sheet 36
Sheet 18~19
2) VDC 17) P1.5V
EGFX_CORE
EGFX_CORE A
DRAW DATE TITLE
A
11) P1.5V_AUX 14-1) KBC3_PWRON_INV# VCCP3_PWRGD 10) P1.8V_AUX VCCP3_PWRGD 4 SI3456 P1.8V SI3456
VCCP3_PWRGD
SC471
GCORE3_PWRGD
CHECK APPROVAL
Jun PARK
DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
MAIN POWER SEQUENCE
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
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THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG. P3.3V
CLOCK DISTRIBUTION
266 MHz CLK0_HCLK/CLK#
FS(2:0)
D
CLK3_PWRGD*
1
MUX Main PLL SSC
266 MHz CLK0_HCLK1/HCLK1#
CPU FSB
BSEL
D
ITP_EN CPU_STP*
667/800 MHz
333/400 MHz CLK1_MCLK0/0# 333/400 MHz CLK1_MCLK1/1#
HPLL MPLL
SODIMM #0
100 MHz (SRC0) CLK1_DREFSSCLK/DREFSSCLK#
100 MHz (SRC4)
96 MHz
C
SS(96/100) SEL
PLL3 SSC
100 MHz
100 MHz (SRC 6,9)
100 MHz (SRC 3)
48MHz PLL MUX
48 MHz
100 MHz (SRC 2)
14.318 MHz 33 MHz
B
PCI_STP*
33 MHz Buffer
33 MHz
CLK3_PCLKMICOM
g l n a u ti s n m e a id S f n o C
PEG
MCH3_CLKREQ#
PCI Express Gfx
MUX
Cantiga MCH
333/400 MHz
CLK1_MCLK3/3#
CLK1_MCH3GPLL/MCH3GPLL#
333/400 MHz
PCIE PLL DPLLA DPLLB
CLK1_MCLK4/4#
SODIMM #1
CLK1_DREFCLK/DREFCLK#
CLK1_DREFSSCCLK/DREFSSCCLK#
MIN3_CLKREQ*#
C
CK-505M (w/ CLKREQ* & SSDC) xSLG8SP513r05)
100 MHz (SRC 6)
CLK1_MINIPCIE/MINIPCIE#
WLAN
DMI
CLK1_PCIEICH/PCIEICH#
PCIEPLL USBPLL
ICH9-M
LOM3_CLKREQ*#
CLK3_USB48
100 MHz (SRC 9)
CLK1_PCIELOM/PCIELOM#
WIRED LAN
25 MHz
CHP3_SATACLKREQ# CLK1_SATA/SATA#
SATAPLL
CLK3_PCLKICH
32.768 KHz OSC
B
AUD3_BCLK
HD Audio
KBC
10 MHz
RTC Clock 32.768 KHz
KBC3_SPI_CLK
17.86 MHz
SPI
A
14 MHz OSC
A
DRAW DATE TITLE
14.318 MHz Page 8
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
MAIN CLOCK DIAGRAM
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
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THERMAL SENSOR & FAN CONTROL
D D
P5.0V P3.3V_AUX P3.3V P3.3V_AUX R546
49.9 1%
10K 1% 10K 1% 10K 1%
C550
10000nF-X5R 6.3V
C535
100nF 10V
C549
100nF 10V
KBC3_PWRGD
13-B1,27-B3 39-C4,54-B3
C
FAN5_VDD FAN3_FDBACK# CPU3_THRMTRIP#
7-B2,54-D4 7-B2,54-C2 7-B3
P3.3V_AUX
R549
nostuff R534 R1
200K 1%
R2
R536
51.1K 1%
93 degree C R537
20K 1%
TRIP_SET pin voltage = (T-75)/21 3.3 * [R2/(R1+R2)] = (T-75)/21
B
P1.05V
R538
2K 1% 3 1 2
CPU1_THRMTRIP#
9-C4,13-B1 25-B1 7-C4
CPU3_THRMTRIP#
nostuff nostuff
Q509 MMBT3904
40V
g l n a u ti s n m e a id S f n o C
R530 R531 R532 U506 EMC2102
1 24 27 14 16 VDD_3V VDD_5V_1 VDD_5V_2 SMDATA SMCLK 22 23 19 12 2 3 4 5 6 7
R535
10K 1%
39-B3,55-B3 39-B3,55-C3
KBC3_THERM_SMDATA KBC3_THERM_SMCLK
POWER_OK RESET#
ALERT# SYS_SHDN# DN1 DP1 DN2 DP2 DN3 DP3
54-B2 27-C3,39-C3 39-D1,54-B4 9-C4,54-D2 9-C4,54-D2 22-C4 22-C4
THM3_ALERT# THM3_STP#
10 25 26 28 13
FAN_MODE FAN_1 FAN_2 TACH
C551 C552
2.2nF
CPU2_THERMDC CPU2_THERMDA GFX3_THERMDN GFX3_THERMDP
0.47nF 50V
For Intel 45nm(From penryn)
C
50V
10mil width and 10mil spacing.
THERMTRIP# SHDN_SEL TRIP_SET NC_1 NC_2 NC_3
0
9 11 8 15 21
2
CLK_SEL CLK_IN
17 18
C553
2.2nF 50V
1
MMBT3904 Q510
GND THRM_PAD
20 29
3
Opposite side of CPU.
1209-001718 5.5V
SMBUS Address 7Ah
B
P3.3V
Line Width = 20 mil
R547
10K 1%
M503 HEAD DIA LENGTH
BA61-01090A
M501 HEAD DIA LENGTH
BA61-01090A
M504 HEAD DIA LENGTH
BA61-01090A
M502 HEAD DIA LENGTH
BA61-01090A
SHDN_SEL MODE
0 HIGH Z 1
INTEL TR MODE
J1 HDR-4P-1R-SMD
1 2 3 4 MNT1 MNT2
AMD CPU/DIODE MODE
FAN5_VDD
7-C4,54-D4
EXT.DIODE 2 MODE
FAN3_FDBACK#
7-C4,54-C2
C6
5 6
10000nF-X5R 6.3V
3711-000456
ADDRESSS_SEL MODE 0101 111xb 0111 101xb (7A) 0101 110xb
To support heatsink
GFX3_THERM#
R533
22-B3
0
0 HIGH Z 1
nostuff
A
DESIGN DATE TITLE
A
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
THERMAL SENSOR THERMAL SENSOR EMC2112
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
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APPROVAL
HJ KIM
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D
D
P1.05V
R642 CPU1-1 PENRYN
CPU1_A#(16:3)
12-D1
56
CPU1_D#(15:0)
12-D4
CPU1-2 PENRYN
2/4
12-D4 12-C1 12-C1 12-C1
1/4
3 4 5 6 7 8 9 10 11 12 13 14 15 16
C
CPU1_ADSTB0#
12-C1
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0#
ADS# BNR# BPRI# BR0# DEFER# DRDY# DBSY# CONTROL IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM# A20M# FERR# IGNNE# ICH STPCLK# LINT0 LINT1 SMI# REQ0# REQ1# REQ2# REQ3# REQ4#
H1 E2 G5 F1 H5 F21 E1
D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 A6 A5 C4 D5 C6 B4 A3 K3 H2 K2 J3 L1
CPU1_A#(35:17)
12-D1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
12-C1
CPU1_ADSTB1#
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1#
0143854500|bga_479p_sock
B
CPU Socket : 3704-001153
g l n a u ti s n m e a id S f n o C
CPU1_ADS# CPU1_BNR# CPU1_BPRI#
12-C1
CPU1_BREQ#
DATA GRP 0
CPU1_IERR#_MN
25-C1,54-C3
CPU1_INIT#
DATA GRP 2
12-C1 12-B1 12-B1
CPU1_DEFER# CPU1_DRDY# CPU1_DBSY#
12-B1
CPU1_LOCK#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
12-B4,54-A2
12-A1 12-A1 12-A1 12-B1
CPU1_CPURST#
CPU1_RS0# CPU1_RS1# CPU1_RS2# CPU1_TRDY# CPU1_HIT# CPU1_HITM#
C793
0.1nF 50V
CPU1_DSTBN0# CPU1_DSTBP0# CPU1_DBI0# CPU1_D#(31:16)
12-B1 12-B1 12-B1 12-D4
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
CPU1_D#(47:32)
0 ADDR GROUP
C
12-B1 12-B1 12-B1 12-D4
12-B1 12-B1
nostuff
1 ADDR GROUP
25-C1 25-C1,54-C3 25-C1,54-C2 25-B1,54-D2 25-B1,54-D4 25-B1,54-C4 12-B1
DATA GRP 1
CPU1_STPCLK#
25-C1
CPU1_INTR
0 1 2 3 4
CPU1_NMI CPU1_SMI# CPU1_REQ#(4:0)
DATA GRP 3
CPU1_A20M# CPU1_FERR# CPU1_IGNNE#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CPU1_DSTBN1# CPU1_DSTBP1# CPU1_DBI1#
12-B1 12-B1 12-B1
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
CPU1_DSTBN2# CPU1_DSTBP2# CPU1_DBI2# CPU1_D#(63:48)
12-B1 12-B1 12-B1
CPU1_DSTBN3# CPU1_DSTBP3# CPU1_DBI3#
0143854500|bga_479p_sock
B
M505 SUPLECODE
1 MNT1 2 MNT2 3 MNT3 4 MNT4
BA75-02034A
CPU Mount
A
DRAW DATE TITLE
A
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
CPU PENRYN (1/3)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
undefined
8
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
CLK0_HCLK0 CLK0_HCLK0# CPU1_SLP# CPU1_DPSLP# CPU1_DPRSTP# CPU1_DPWR# 25-C1,55-B4 C125 P1.05V
0.1nF 50V
H CLK
D
CPU1-3 PENRYN 3/4
11-C1 11-C1
P1.5V
VCCA_1 VCCA_2 VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7 VCCP_8 VCCP_9 VCCP_10 VCCP_11 VCCP_12 VCCP_13 VCCP_14 VCCP_15 VCCP_16 B26 C26
A22 A21
BCLK0 BCLK1 SLP# DPSLP# DPRSTP# DPWR# PWRGOOD PSI# VID_6 VID_5 VID_4 VID_3 VID_2 VID_1 VID_0 PROCHOT# THRMDA THRMDC THERMTRIP# BSEL2 BSEL1 BSEL0 GTLREF COMP3 COMP2 COMP1 COMP0 VCCSENSE VSSSENSE TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7
C690
K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21
10nF 25V
C691
10000nF-X5R 6.3V
CPU Core Voltage Table
Active Mode
D
IMVP-6
12-B4 D7 25-C1,54-C2 B5 13-B1,25-C1 49-C4,54-A2 E5 12-B1 D24 49-D4,54-C4 49-C4,54-C2
Active/Deeper Sleep Dual Mode Region
Voltage VID(6:0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Voltage 1.0000 V 0.9875 V 0.9750 V 0.9625 V 0.9500 V 0.9375 V 0.9250 V 0.9125 V 0.9000 V 0.8875 V 0.8750 V 0.8625 V 0.8500 V 0.8375 V 0.8250 V 0.8125 V 0.8000 V 0.7875 V 0.7750 V 0.7625 V 0.7500 V 0.7375 V 0.7250 V 0.7125 V 0.7000 V 0.6875 V 0.6750 V 0.6625 V 0.6500 V 0.6375 V 0.6250 V 0.6125 V 0.6000 V 0.5875 V 0.5750 V 0.5625 V 0.5500 V 0.5375 V 0.5250 V 0.5125 V 0.5000 V
CPU1_PWRGDCPU
CPU1_PSI# CPU1_VID(6:0) P1.05V
D6 AE6 AE2 AF3 AE3 AF4 AE5 AF5 AD6 D21 A24 B25 C7
Deeper Sleep/Extended Deeper Sleep Dual Mode Region
VID(6:0) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage 0.4875 V 0.4750 V 0.4625 V 0.4500 V 0.4375 V 0.4250 V 0.4125 V 0.4000 V 0.3875 V 0.3750 V 0.3625 V 0.3500 V 0.3375 V 0.3250 V 0.3125 V 0.3000 V 0.2875 V 0.2750 V 0.2625 V 0.2500 V 0.2375 V 0.2250 V 0.2125 V 0.2000 V 0.1875 V 0.1750 V 0.1625 V 0.1500 V 0.1375 V 0.1250 V 0.1125 V 0.1000 V 0.0875 V 0.0750 V 0.0625 V 0.0500 V 0.0375 V 0.0250 V 0.0125 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V
VID(6:0)
nostuff R641
56
CPU1_PROCHOT#_MN
nostuff
R703
56
6 5 4 3 2 1 0
P1.05V EC512 220uF
2.5V AD
CPU2_THERMDA P1.05V CPU2_THERMDC CPU1_THRMTRIP# R635
1K 1%
7-C2,54-D2 7-C2,54-D2 7-A4,13-B1 25-B1 11-C4,12-A3 11-C4,12-A3 11-C4,12-A3
CPU1_BSEL2 CPU1_BSEL1 CPU1_BSEL0
C21 B23 B22 AD26
C
CPU1_GTLREF_MN
R636
2K 1%
C655
100nF 10V
R702 R701 R637 R638
54.9 27.4 54.9 27.4
1% CPU1_COMP3_MN 1% CPU1_COMP2_MN 1% CPU1_COMP1_MN 1% CPU1_COMP0_MN
Y1 AA1 U26 R26
nostuff CPU1_VCCSENSE CPU1_VSSSENSE SI team request
10-C4,49-A4 55-B4AF7 10-B4,49-A4 55-B4AE7
C23 D25 C24 AF26 AF1 A26 C3
0143854500|bga_479p_sock
CPU Socket : 3704-001153
B
FSC 0 0 0
54.9
P1.05V
FSB 0 1 1
FSA 0 0 1
FRQ 266M 200M 166M
near the CPU R90 R93
9-C3,54-D4 9-C3,54-D4 9-C3,54-D4 9-C3,54-C3
BSEL
CPU1_TDI CPU1_TMS CPU1_TCK CPU1_TRST# FSB 1067 MHz FSB 800 MHz
A
R92 R91
DRAW DATE TITLE
54.9 1%
54.9 1%
g l n a u ti s n m e a id S f n o C
C780
100nF 10V
C779
100nF 10V
C778
100nF 10V
C688
100nF 10V
C687
100nF 10V
C686
100nF 10V
XDP/ITP SIGNALS
PREQ# PRDY# BPM3# BPM2# BPM1# BPM0#
AC1 AC2 AC4 AD1 AD3 AD4 AC5 AA6 AB3 AB5 AB6 C20
nostuff nostuff -> delete and change layout (ECAE)
nostuff
TCK TDI TDO TMS TRST# DBR#
9-A4,54-D4 9-A4,54-D4
CPU1_TCK CPU1_TDI
9-A4,54-D4 9-A4,54-C3 27-D3,55-D4
CPU1_TMS CPU1_TRST# ITP3_DBRESET#
RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9
M4 N5 T2 V3 B2 D2 D22 D3 F6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1.5000 V 1.4875 V 1.4750 V 1.4625 V 1.4500 V 1.4375 V 1.4250 V 1.4125 V 1.4000 V 1.3875 V 1.3750 V 1.3625 V 1.3500 V 1.3375 V 1.3250 V 1.3125 V 1.3000 V 1.2875 V 1.2750 V 1.2625 V 1.2500 V 1.2375 V 1.2250 V 1.2125 V 1.2000 V 1.1875 V 1.1750 V 1.1625 V 1.1500 V 1.1375 V 1.1250 V 1.1125 V 1.1000 V 1.0875 V 1.0750 V 1.0625 V 1.0500 V 1.0375 V 1.0250 V 1.0125 V
THERMAL
C
RSVD
Active DPRSLPVR 0 DPRSTP* 1 PSI2* 0 or 1
Deeper Slp DPRSLPVR 1 DPRSTP* 0 PSI2* 0 or 1
*"1111111" : 0V power good asserted.
54.9 1%
*Yonah Processor (2.33 GHz / 800 MHz : TBD)
GTLREF : Keep the Voltage divider within 0.5" of the first GTLREF0 pin with Zo=55ohm trace. Minimize coupling of any switching signals to this net.
COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm) trace shorter than 1/2" to their respective Banias socket pins.
Pull-down
BSEL0, BSEL1, BSEL2 BSEL0, BSEL2
GND test points within 100mil of the VCC/VSSsense at the end of the line. Route the VCC/VSSsense as a Zo=55ohm traces with equal length. Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away (preferred 50mil) from any other signal. And GND via 100mil away from each of the VCC/VSS test point vias.
A
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
CPU PENRYN (2/3)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
undefined
9
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141
K23 K26 K4 L21 L24 L3 L6 M2 M22 M25 M5 N1 N23 N26 N4 P21 P24 P3 P6 R2 R22
D
D
CPU_CORE
C
R700
9-C4,49-A4 55-B4
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
10000nF-X5R6.3V
C105
C104
C109
C102
C106
C101
C107
C108
C100
CPU1_VSSSENSE
R699
9-C4,49-A4 55-B4
100
1%
Prodlizer & Cbulk common used(Socket inside)
B
C103
C83
C81
C84
C82
C98
C99
10000nF-X5R6.3V
CPU1_VCCSENSE
100
1%
g l n a u ti s n m e a id S f n o C
CPU1-4 PENRYN 4/4
Y6 Y3 Y24 Y21 W4 W26 W23 W1 V5 V25 V22 V2 U6 U3 U24 U21 T4 T26 T23 T1 R5 R25 VSS_163 VSS_162 VSS_161 VSS_160 VSS_159 VSS_158 VSS_157 VSS_156 VSS_155 VSS_154 VSS_153 VSS_152 VSS_151 VSS_150 VSS_149 VSS_148 VSS_147 VSS_146 VSS_145 VSS_144 VSS_143 VSS_142
DRAW DATE TITLE
A11 A14 A16 A19 A2 A23 A25 A4 A8 AA11 AA14 AA16 AA19 AA2 AA22 AA25 AA5 AA8 AB1 AB11 AB13 AB16 AB19 AB26 AB4 AB8 AC11 AC14 AC16 AC19 AC21 AC24 AC3 AC6 AC8 AD11 AD13 AD16 AD19 AD2 AD22 AB23 AD25 AD5 AD8 AE1 AE11 AE14 AE16 AE19 AE23 AE26 AE4 AE8 AF11 AF13 AF16 AF19 AF2 AF21
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60
CPU_CORE
A10 A12 A13 A15 A17 A18 A20 A7 A9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AA7 AA9 AB10 AB12 AB14 AB15 AB17 AB18 AB20 AB7 AB9 AC10 AC12 AC13 AC15 AC17 AC18 AC7 AC9 AD10 AD12 AD14 AD15 AD17 AD18 AD7 AD9 AE10 AE12 AE13 AE15 AE17 AE18 AE20
CPU_CORE
AE9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 AF9 B10 B12 B14 B15 B17 B18 B20 B7 B9 C10 C12 C13 C15 C17 C18 C9 D10 D12 D14 D15 D17 D18 D9 E10 E12 E13 E15 E17 E18 E20 E7 E9 F10 F12 F14 F15 F17 F18 F20 F7 F9
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50
VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 0143854500|bga_479p_sock VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100
VSS_120 VSS_119 VSS_118 VSS_117 VSS_116 VSS_115 VSS_114 VSS_113 VSS_112 VSS_111 VSS_110 VSS_109 VSS_108 VSS_107 VSS_106 VSS_105 VSS_104 VSS_103 VSS_102 VSS_101 VSS_100 VSS_99 VSS_98 VSS_97 VSS_96 VSS_95 VSS_94 VSS_93 VSS_92 VSS_91 VSS_90 VSS_89 VSS_88 VSS_87 VSS_86 VSS_85 VSS_84 VSS_83 VSS_82 VSS_81 VSS_80 VSS_79 VSS_78 VSS_77 VSS_76 VSS_75 VSS_74 VSS_73 VSS_72 VSS_71 VSS_70 VSS_69 VSS_68 VSS_67 VSS_66 VSS_65 VSS_64 VSS_63 VSS_62 VSS_61
K1 J5 J25 J22 J2 H6 H3 H24 H21 G4 G26 G23 G1 F8 F5 F25 F22 F2 F19 F16 F13 F11 E8 E6 E3 E24 E21 E19 E16 E14 E11 D8 D4 D26 D23 D19 D16 D13 D11 D1 C8 C5 C25 C22 C2 C19 C16 C14 C11 B8 B6 B24 B21 B19 B16 B13 B11 AF8 AF6 AF25
C
10%
10%
B
A
Jun PARK
CHECK DEV. STEP
A
9/23/2008 PR
REV
CANNES-L_EXT
CPU PENRYN (3/3)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
undefined
10
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
CK505M
D
P1.5V P3.3V B522 BLM18PG181SN1 VDD_SRC_IO
10000nF-X5R 10V 100nF 10V 100nF 10V
D
FSA
FSB
FSC HOST CLK 266 MHz 333 MHz 200 MHz 400 MHz 133 MHz 100 MHz 166 MHz RSVD
BSEL0 BSEL1 BSEL2
C876
C871
C907
C900
C872
C874
C873
C901
C899
C870
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
B523 BLM18PG181SN1 VDD_REF
10V
VDD_CPU_IO VDD_PLL3_IO
10000nF-X5R 10000nF-X5R 10000nF-X5R 10V 10V
VDD_IO
100nF 10V
VDD_48
10000nF-X5R
VDD_PCI
10V
VDD_PLL3 VDD_SRC VDD_CPU
10V 10V 10000nF-X5R
6.3V
6.3V
6.3V
6.3V
100nF
100nF
6.3V
nostuff
nostuff
C
CLK3_FM48 CLK3_USB48 CPU1_BSEL0
36-B4 27-A3 9-C4,12-A3
R178 R179 R177
33 33 2.2K
CPU1_BSEL1 CPU1_BSEL2 CLK3_ICH14 CHP3_CPUSTP# CHP3_PCISTP# CLK3_PWRGD CLK3_PCLKICH CLK3_DBGLPC
9-C4,12-A3 9-C4,12-A3 27-A3
R187 R186
10K 1% 33
27-C3,54-B2 27-C3,54-B2 27-B3 26-C2 30-A4
R233 R236
22 22
5% 5%
CLK3_PCLKMICOM
39-B4 13-A1,54-B2 27-B3,55-C3
R184 R237 R185
22 475 475
5% 1% 1%
B
MCH3_CLKREQ# CHP3_SATACLKREQ# SMB3_CLK SMB3_DATA
17-B4,18-B4 27-B4,54-D4 17-B4,18-B4 27-B4,54-B4
Y2
1 2
C250
C251
C252
C253
R183
2801-004667
R182
14.31818MHz C254
0.018nF
50V
C255
0.018nF 50V
CLK REQ CLK REQ A CLK REQ B
DEVICE SATA GMCH MINI CARD EXP3_CLKREQ# Pin 20/21
SRC PORT SRC2 SRC4 SRC6 SRC8 Pin 24/25 PEG_CLK/PEG_CLK# Place 14.318MHz within 500mils of CK-505
A
CLK REQ E CLK REQ F SEL_LCDCLK* LOW HIGH
This part is 64pin QFN package.
IDT : 1205-003159 SL : 1205-003533
DRAW DATE TITLE
65
g l n a u ti s n m e a id S f n o C
100nF 100nF 100nF 100nF 100nF
100nF
C906
C902
C905
C903
C908
C904
C875
100nF
CLK3_VDD_SRC_IO_MN
CLK3_VDD_REF_MN
nostuff
P3.3V
U10 SLG8SP513
C909
6.3V
10V
10V
C
nostuff C249
0.022nF 50V
R235 10K 1%
R234 10K 1%
nostuff
19 33 43 52 56 27 55
VDD_IO VDD_SRC_IO1 VDD_SRC_IO2 VDD_SRC_IO3 VDD_CPU_IO VDD_PLL3_IO NC
VDD_REF VDD_48 VDD_PCI VDD_PLL3 VDD_SRC VDD_CPU CPU0 CPU0#
4 16 9 23 46 62
CLK3_USB48_R_MN CLK3_ICH14_R_MN
17 64 5
USB_FS_A FSB_TESTMODE REF_FS_C_TEST_SEL CPUSTOP# PCISTOP#
61 60
9-D4 9-D4
CLK0_HCLK0 CLK0_HCLK0# CLK0_HCLK1 CLK0_HCLK1# LOM3_CLKREQ#
44 45
CPU1_MCH CPU1_MCH#
58 57
12-B1 12-B1
63
SRC11_CLKREQH# SRC11#_CLKREQG# SRC10 SRC10# SRC9 SRC9#
40 39 41 42
35-A3,54-B2
CLKPWRGD_PWRDN# PCIF_5_ITP_EN
CLK3_PCLKICH_R_MN CLK3_DBGLPC_R_MN
14
13 12
PCI_4_SEL_LCDCLK# PCI_3 PCI_2
37 38 54 53
35-A4 35-A4
CLK1_PCIELOM CLK1_PCIELOM#
CLK3_PCLKMICOM_R_MN 11 MCH3_CLKREQ#_R_MN
SRC8_ITP SRC8#_ITP#
10
PCI_1_CLKREQ_B# PCI_0_CLKREQ_A#
CHP3_SATACLKREQ#_R_MN 8
SRC7_CLKREQF# SRC7#_CLKREQE# SRC6 SRC6#
51 50 48 47
B
37-C4,55-C4 37-C4 37-C4
MIN3_CLKREQ#
7 6
SCL SDA
CLK1_MINIPCIE CLK1_MINIPCIE# CLK1_MCH3GPLL CLK1_MCH3GPLL# CLK1_PCIEICH CLK1_PCIEICH# CLK1_SATA CLK1_SATA# CLK3_GFX_27M CLK3_GFX_27M_SS
3 2
XTAL_IN XTAL_OUT
SRC4 SRC4#
34 35 31 32 28 29
13-B1 13-B1
0.033nF50V 5%
0.033nF50V 5%
0.033nF50V 5%
0.1nF 50V
10K 1%
10K 1%
THERM_GND
18 59 22 15 26 1 30 36 49
VSS_48 VSS_CPU VSS_IO VSS_PCI VSS_PLL3 VSS_REF VSS_SRC1 VSS_SRC2 VSS_SRC3
SRC3_CLKREQC# SRC3#_CLKREQD# SRC2 SRC2#
27-C1 27-C1
25-B1 25-B1
LCDCLK_27M LCDCLK#_27M_SS SRC0_DOT96 SRC0#_DOT96#
24 25
R181
22
22-A4 22-A4
20 21
R180
22
19-C4 19-C4
CLK1_PEG CLK1_PEG#
nostuff nostuff
1205-003156
A
Jun PARK
CHECK DEV. STEP
CANNES-L_EXT
PR
REV
SAMSUNG
ELECTRONICS
PART NO.
DOT_96/DOT_96# SRC_0/SRC_0#
YM AN
APPROVAL
MAIN_CLOCK_CIRCUIT CK_CLOCK_505M
August 07, 2009 15:14:35 PM
27M & 27M_SS
MODULE CODE
HJ KIM
LAST EDIT
1.0
BA41PAGE
undefined
11
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
4
3
P1.05V EC504 220uF
2.5V AD
2
P1.05V
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG. C594
10000nF-X5R 6.3V
C592
100nF 10V
C644
100nF 10V
C590
100nF 10V
nostuff C556
1000nF-X5R 6.3V
nostuff C555
10000nF-X5R 6.3V
C554
10000nF-X5R 6.3V
EC501 220uF
2.5V AD
nostuff
AA28 AA33 AA34 AB34 AC26 AC28 AC33 AC34 AE26 AE33 AF23 AF25 AF28 AF33 AG24 AG25 AG26 AG33 AG34 AH23 AH25 AH28 AJ23 AJ26 AJ33 AK33 AM33 T32 U33 U34 V33 V34 W33 Y33 Y34 T10 T11 T12 T13 T2 T5 T6 T7 T8 T9 U1 U10 U11 U12 U13 U2 U3 U5 U6 U7 U8 U9 V1 V2 V3
8-C4
D
CPU1_D#(63:0)
8-C1
CPU1_A#(35:3)
P1.05V
R539
221 1%
12-B4,54-B2
MCH1_HXSWING
R41
100 1%
C34
100nF 10V
C
P1.05V
R551
1K 1%
12-A4,54-A3
MCH1_HVREF
R550
2K 1%
B
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
8-C3,54-A2 9-D4 12-C4,54-B2
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 C12 E11 C5 E3
CPU1_CPURST# CPU1_SLP# MCH1_HXSWING
MCH1_H_RCOMP_MN
R540 MCH1_HVREF
24.9 1%
1608
MCH1_VTTLF1_MN MCH1_VTTLF2_MN MCH1_VTTLF3_MN
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44
12-B4,54-A3
B11 A11
VTTLF
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
A8 AB2 L1
g l n a u ti s n m e a id S f n o C
U2-1 EB88CTPM 1 OF 5
0904-002376
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
VCC CORE
VTT
HOST DATA BUS
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 J11 F9 H9 E12 H11 C9 AH7 AH6 J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
0 1 2 3 4
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
8-C3 8-C4 8-B4 8-C3 8-C3 8-C3 8-C3 8-C3 9-D4 8-C3 8-C3 8-C3 8-C3 8-C3 11-C1 11-B1 8-C2 8-B2 8-C1 8-B1 8-C2 8-B2 8-C1 8-B1 8-C2 8-B2 8-C1 8-B1 8-B3
D
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 HOST ADDRESS BUS
C
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
CPU1_ADS# CPU1_ADSTB0# CPU1_ADSTB1# CPU1_BNR# CPU1_BPRI# CPU1_BREQ# CPU1_DEFER# CPU1_DBSY# CPU1_DPWR# CPU1_DRDY# CPU1_HIT# CPU1_HITM# CPU1_LOCK# CPU1_TRDY# CLK0_HCLK1 CLK0_HCLK1# CPU1_DBI0# CPU1_DBI1# CPU1_DBI2# CPU1_DBI3# CPU1_DSTBN0# CPU1_DSTBN1# CPU1_DSTBN2# CPU1_DSTBN3# CPU1_DSTBP0# CPU1_DSTBP1# CPU1_DSTBP2# CPU1_DSTBP3# CPU1_REQ#(4:0)
HOST CONTROL
HPLL_CLK HPLL_CLK# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
B
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
H_CPURST# H_CPUSLP#
CFG
NC
H_SWING H_RCOMP
H_DVREF H_AVREF VTTLF_1 VTTLF_2 VTTLF_3
8-C3 8-C3 8-C3
CPU1_RS0# CPU1_RS1# CPU1_RS2#
470nF 470nF 470nF
*POCAFEB-12 Only (Remove in MP Model) CFG# Current Setting (def. : default Option) High Low DMIx4 (def.) DMIx2 iTPM Host Interface Enable iTPM Host Interface Disable (def.) ME Crypto no confidentiality ME Crypto confidentiality (def.) Normal PEG Reversal (def.) PCIE Loop Back Disable(def) PCIE Loop Back Enable Dynamic ODT Disabled Dynamic ODT Enabled (def.) DMI Lane Reversal DMI Lane Normal (def.) SDVO or PCIE X1 SDVO and PCIE X1 Only(def.) Simultaneously
16V 16V 16V
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
AA29 AA30 AA32 AB30 AC29 AC30 AC32 AE29 AE30 AE32 AF30 AG29 AG30 AG32 AH29 AH30 AH32 AJ29 AJ32 AK23 AK24 AK25 AK26 AK28 AK29 AK30 AK32 AL26 AL28 AL29 AL30 AL32 AM30 AM32 U30 U32 V29 V30 W29 W30 W32 Y29 Y30 Y32
C37 C537 C536
A
CFG(5) CFG(6) CFG(7) CFG(9) CFG(10) CFG(16) CFG(19) CFG(20)
CPU1_BSEL0 CPU1_BSEL1 CPU1_BSEL2
9-C4,11-C4 9-C4,11-C4 9-C4,11-C4
P1.05V
MCH1_CFG6_MN
A
DRAW DATE TITLE
R581
2.2K
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
nostuff iTPM option
CANNES-L_EXT
MCH_CANTIGA_GM_DDR2 CANTIGA (1/5)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
undefined
12
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
A
B
C
D
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
SAMSUNG PROPRIETARY
4
4
M32 M33 M29 G32 L32 E28 G28 J28 E29 G29 A41 H38 G37 J37 B42 G38 F37 K37 H47 E46 G40 A40 F25 H25 K25 C31 E32 H32 J32 H24 C44 B43 E37 E38 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL H48 D45 F40 B40 B28 A28 B30 B29 C29 HDA_BCLK HDA_SYNC HDA_RST# HDA_SDI HDA_SDO HDA C40 C41 A37 B37 LVDSB_CLK LVDSB_CLK# K33 J33 J29 L29 TV_RTN TVA_DAC TVB_DAC TVC_DAC TV_DCONSEL_0 TV_DCONSEL_1 CRT_BLUE CRT_GREEN CRT_RED CRT_HSYNC CRT_VSYNC CRT_DDC_CLK CRT_DDC_DATA CRT_TVO_IREF CRT_IRTN LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 L_VDD_EN L_BKLT_EN L_BKLT_CTRL L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_CLK LVDSA_CLK# LVDS TV VGA A43 A44 A46 A47 A5 A6 B4 B45 B47 B48 BC1 BC48 BD1 BD48 BE2 BE47 BF1 BF3 BF46 BF48 BG1 BG2 BG4 BG45 BG47 BG48 BH2 BH3 BH43 BH44 BH46 BH47 BH5 BH6 C3 C46 C48 D2 D47 E1 E48 F1 F48 AH10 AH12 AH13 AH9 AK34 AL34 AM35 AN35 AY21 B2 B31 BF18 BF23 BG23 BH18 K12 M1 M36 N36 R33 T24 T33 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22
PEG1_RXN(15:0)
19-C4
RSVD11 RSVD10 RSVD13 RSVD12
RSVD
AE16 AE17 AE19 AF16 AF17 AF19 AG16 AG17 AG19 AH16 AH17 AH19 AJ16 AJ19 AK16 AK17 AK19 AK20 AK21 AL16 AL19 AL21 AM16 AM17 AM19 AM20 AM21 U16 U19 U20 U21 V16 V17 V19 V21 V23 V24 V25 V26 V28 W16 W17 W19 W20 W21 W23 W24 W25 W26 W28 Y16 Y17 Y19
VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
AA15 AA20 AA21 AA23 AA24 AA25 AB15 AB20 AB23 AB25 AC20 AC21 AC23 AC24 AE15 AE20 AE21 AE23 AE24 AE25 AF15 AF20 AG15 AG21 AH15 AH20 AJ15 AJ21 AL15 AM14 AM15 AN14 T14 T16 T17 U14 U15 V15 Y15 Y21 Y24 Y26
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 C46 M46 C50 M47 C51 M40 C54 M42 C56 R48 C57 N38 C59 T40 C62 U37 C63 U40 C65 Y40 C67 AA46 C70 AA37 C71 AA40 C73 AD43 C77 AC46 C92 J42 C47 L46 C48 M48 C49 M39 C52 M43 C53 R47 C55 N37 C58 T39 C60 U36 C61 U39 C64 Y39 C66 Y46 C68 AA36 C69 AA39 C72 AD42 C75 AD46 C91
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
g g g un al un al un al ms nti ms nti ms nti Sa de Sa de Sa de nfi nfi nfi Co Co Co
NC PCIE GFX GFX VCC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
3
3
2 OF 5
0904-002376
EB88CTPM
U2-2
GFX VCC NCTF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
19-C4
PEG1_RXP(15:0)
ME Debug Port
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
19-B4
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7
AA16 AA19 AB16 AB17 AB19 AC16 AC17
GFX VCC NCTF
For ESD
PEG1_TXN(15:0)
2
DRAW MODULE CODE APPROVAL CHECK
2
PCIE GFX
19-B4
MISC
PM
ME
CLK
DMI
Jun PARK
P3.3V
undefined
LAST EDIT
PEG1_TXP(15:0)
HJ KIM
REV
YM AN
DEV. STEP
DPLL_REF_SSCLK DPLL_REF_SSCLK#
SDVO_CTRLCLK SDVO_CTRLDATA
DDPC_CTRLCLK DDPC_CTRLDATA
DPLL_REF_CLK DPLL_REF_CLK#
THERMTRIP# PM_EXT_TS#_0 PM_EXT_TS#_1
R629
PM_SYNC# PM_DPRSTP# DPRSLPVR
PEG_COMPI PEG_COMPO
DATE
GFX_VR_EN
ICH_SYNC# TSATN#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
CL_CLK CL_DATA CL_PWROK CL_RST#
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
PEG_CLK PEG_CLK#
CLKREQ#
CL_VREF
PWROK RSTIN#
9/23/2008
10K
1.0 August 07, 2009 15:14:35 PM
PR
H36 B12
B38 A38
AD35 AE44 AF46 AH43
AE35 AE43 AE46 AH42
27-D3,55-B4 R29 B749-C4,54-A2 9-D4,25-C1 R32 55-B4 27-C3,49-C4
E41 F41
AE40 AE38 AE48 AH40
AE41 AE37 AE47 AH39
G36 E36
T20 N33 P32
C34
AT40 AT11
AH37 AH36 AN36 AJ35
B33 B32 G33 F33 E33
AH34
K36
N28 M28
F43 E43
T37 T36
TITLE
11-B4,54-B2
PLT3_RST#_R_MN
7-C4,27-B3 39-C4,54-B3
27-D1 27-D1 27-D1 27-C1
27-D1 27-D1 27-D1 27-C1
27-D1 27-D1 27-D1 27-C1
27-D1 27-D1 27-D1 27-C1
R552
MCH_CANTIGA_GM_DDR2
MCH1_COMPIO_R_MN
CANNES-L_EXT
27-C1,55-D3
27-C1,55-B4 27-C1,55-A4
0.1nF 50V
C646
nostuff
DMI1_RXP_0 DMI1_RXP_1 DMI1_RXP_2 DMI1_RXP_3
DMI1_RXN_0 DMI1_RXN_1 DMI1_RXN_2 DMI1_RXN_3
DMI1_TXP_0 DMI1_TXP_1 DMI1_TXP_2 DMI1_TXP_3
DMI1_TXN_0 DMI1_TXN_1 DMI1_TXN_2 DMI1_TXN_3
CANTIGA (1/5)
1608
27-B3,55-D4
11-B4,54-B2
MCH1_CL_VREF_MN
0
R580 R630 R578
MCH3_CLKREQ#
R631
11-B1 11-B1
56
KBC3_PWRGD
nostuff CLK1_MCH3GPLL CLK1_MCH3GPLL#
7-A4,9-C4,25-B1
CHP3_PM_SYNC# CPU1_DPRSTP# CHP3_DPRSLPVR
MCH3_ICHSYNC# P1.05V
0.1nF 50V
C543
CHP3_CL_CLK_0 CHP3_CL_DATA_0 KBC3_PWRGD CHP3_CL_RST_0#
CPU1_THRMTRIP#
nostuff
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
49.9 1%
MCH3_CLKREQ#
1
1
10K 10K
1% 1%
R543 100 1%
P1.05V_PEG
PAGE
0.1nF 50V
C928
nostuff
PART NO.
SAMSUNG
C597 100nF
10V
7-C4,27-B3 39-C4,54-B3
P3.3V
13
OF
19-D4,26-C1 30-A4,35-B3 37-C3,39-B3
ELECTRONICS
P1.05V
PLT3_RST#
499 1%
R632
1K 1%
R583
BA41-
55
D
B
A
C
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG. PLACE EACH CAP NEAR AV42 PIN MEM1_ADQ(63:0)
17-D4
MEM1_VREF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
MEM1_SM_REXT_MN
17-C3,18-C3 46-B2,54-B4
C649
100nF
10V
C648
100nF
10V
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
R42
BF17 AV42 BC36 AR36 BG16 AU17 BF14 AV16 AR13 BF15 AY13
499 1%
0 1 2
17-B4
BD21 BG18 AT25 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
D
MEM1_ABS(2:0)
17-C2
nostuff nostuff
SA_BS_0 SA_BS_1 SA_BS_2 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_CAS# SA_RAS# SA_WE# SA_CS#_0 SA_CS#_1 SA_ODT_0 SA_ODT_1 SA_CKE_0 SA_CKE_1 SA_CK_0 SA_CK#_0 SA_CK_1 SA_CK#_1 SM_RCOMP SM_RCOMP#
SM_REXT SM_VREF SM_DRAMRST# SM_PWROK SB_CAS# SB_RAS# SB_WE# SB_CS#_0 SB_CS#_1 SB_ODT_0 SB_ODT_1
17-C3,18-C3 46-B2,54-B4
D
MEM1_VREF SM_PWROK DDR2 : GND DDR3 : Connect to VRM.
MEM1_ADM(7:0)
0 1 2 3 4 5 6 7
17-B4
SYSTEM MEMORY A
18-B4 18-B4 18-B4 18-C1 18-C1 18-B4 18-B4 18-C1 18-C1 18-C4 18-C4 18-C4 18-C4 18-B4
MEM1_BCAS# MEM1_BRAS# MEM1_BWE# MEM1_CS2# MEM1_CS3# MEM1_ODT2 MEM1_ODT3 MEM1_CKE2 MEM1_CKE3 CLK1_MCLK2 CLK1_MCLK2# CLK1_MCLK3 CLK1_MCLK3# MEM1_BDM(7:0)
MEM1_ADQS#(7:0)
0 1 2 3 4 5 6 7
17-B4
MEM1_ADQS(7:0)
SYSTEM MEMORY A
C
MEM1_AMA(14:0)
17-D2
0 1 2 3 4 5 6 7
SYSTEM MEMORY B
0 BA21 1 BC24 2 BG24 3 BH24 4 BG25 5 BA24 6 BD24 7 BG27 8 BF25 9 AW24 10 BC21 11 BG26 12 BH26 13 BH17 14 AY25
17-C2 17-C2 17-B4 17-C2 17-C2 17-B4 17-B4 17-C2 17-C2 17-C4 17-C4 17-C4 17-C4
MEM1_ACAS# MEM1_ARAS# MEM1_AWE# MEM1_CS0# MEM1_CS1# MEM1_ODT0 MEM1_ODT1 P1.8V_AUX MEM1_CKE0 MEM1_CKE1 CLK1_MCLK0 CLK1_MCLK0# CLK1_MCLK1 CLK1_MCLK1#
MCH1_SM_RCOMP_MN MCH1_SM_RCOMP#_MN
BD20 BB20 AY20 BA17 AY16 BD17 AY17 BC28 AY28 AP24 AR24 AT21 AR21 BG22 BH21 BF28 BH28
B
R585
80.6
1%
R587
80.6
1%
MCH1_SM_RCOMP_V_OH_MN MCH1_SM_RCOMP_V_OL_MN
SM_RCOMP_V_OH SM_RCOMP_V_OL
P1.8V_AUX Route as short as possible R588
1K
1%
10nF->100nF C605
100nF
g l n a u ti s n m e a id S f n o C
SB_CKE_0 SB_CKE_1 SB_CK_0 SB_CK#_0 SB_CK_1 SB_CK#_1 SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AY36 BB36 AV24 AU24 AU20 AV20
U2-3 EB88CTPM 3 OF 5
0904-002376
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
C
18-A4
MEM1_BDQS#(7:0)
SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
18-B4
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6
0 1 2 3 4 5 6 7
MEM1_BDQS(7:0)
18-D1
SYSTEM MEMORY B
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 BC16 BB17 BB33
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 2
MEM1_BMA(14:0)
B
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
18-C1
MEM1_BBS(2:0)
SB_BS_0 SB_BS_1 SB_BS_2
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
18-D4
MEM1_BDQ(63:0)
C609
2200nF-X5R 10V
R586
A
3.01K
1%
10V
A
Cantiga DDR2 SM_RCOMP : 80 ohm to P1.8V_AUX SM_RCOMP# : 80 ohm to VSS
DRAW DATE TITLE
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
R584
1K
1%
C606
100nF
CANNES-L_EXT
MCH_CANTIGA_GM_DDR2 CANTIGA (2/5)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
C607
2200nF-X5R 10V
YM AN
10V
nostuff nostuff
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
14
OF
55
4
3
2
1
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS P1.8V_AUX EXCEPT AS AUTHORIZED BY SAMSUNG. EC506 220uF
2.5V AD
C610
10000nF-X5R 6.3V
C608
10000nF-X5R 6.3V
C602
100nF 10V
C603
100nF 10V
D
nostuff
D
BD16 BB24 BB21 BA36 AW16 AW13 AT13
C586 nostuff
C587
VCC_SM_NC_7 VCC_SM_NC_6 VCC_SM_NC_5 VCC_SM_NC_4 VCC_SM_NC_3 VCC_SM_NC_2 VCC_SM_NC_1
VCC_SM_35 VCC_SM_34 VCC_SM_33 VCC_SM_32 VCC_SM_31 VCC_SM_30 VCC_SM_29 VCC_SM_28 VCC_SM_27 VCC_SM_26 VCC_SM_25 VCC_SM_24 VCC_SM_23 VCC_SM_22 VCC_SM_21 VCC_SM_20 VCC_SM_19 VCC_SM_18 VCC_SM_17 VCC_SM_16 VCC_SM_15 VCC_SM_14 VCC_SM_13 VCC_SM_12 VCC_SM_11 VCC_SM_10 VCC_SM_9 VCC_SM_8 VCC_SM_7 VCC_SM_6 VCC_SM_5 VCC_SM_4 VCC_SM_3 VCC_SM_2 VCC_SM_1
BH32 BH31 BH29 BG32 BG31 BG30 BG29 BF32 BF31 BF29 BD32 BD29 BC32 BC29 BB32 BB29 BA32 BA29 AY32 AY29 AW32 AW29 AV32 AV29 AU32 AU29 AT32 AT29 AR32 AR29 AP33 AP32 AP29 AN33 AN32
P1.05V
P3.3V
P1.05V
10000nF-X5R 1000nF-X5R 6.3V 6.3V
MCH1_P3.3V_HV_R_MN
3 2 1
P1.05V_PEG
A21 B21 B22
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
VCC_HV
C74
VCC AXG
100nF 10V
AF48 AG47 AH47 AH48
VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
C
B27 A26
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
A25
CRT / TV POWER
VCCA_DAC_BG
A24 B24
VCCA_TV_DAC_1 VCCA_TV_DAC_2
P1.5V
M25 VCCD_TVDAC VCCD_QDAC VCCA_LVDS LVDS POWER
C588
100nF 10V
C589
10nF 25V
L28 J48
B
L37 M38 K47
AXG SENSE
VCCD_LVDS_1 VCCD_LVDS_2 VCC_TX_LVDS
P1.05V C591
1nF 50V
MCH1_P1.8VAUX_SM_CK_MN
C561 C650 C544 C647 C601 C645 C558
100nF 10V 1000nF-X5R 6.3V 220nF 10V 1000nF-X5R 6.3V 220nF 10V 470nF 16V 100nF 10V
g l n a u ti s n m e a id S f n o C
VCC HAD
10V
C39 100nF
R43 12.1
1%
30V BAT54A D3
VCC AXG
VCC_SM
VCC_HDA
A32
HDMI OPTION
P1.05V_PEG EC3 220uF
2.5V AD
INSTPAR
P1.05V
VCC_HV_1 VCC_HV_2 VCC_HV_3
A35 B35 C35
2A routing C78 C76
22000nF-X5R 20% 6.3V 4700nF-Y5V 10V
SHORT1
INSTPAR
SHORT2 P1.05V
U2-4 EB88CTPM 4 OF 5
0904-002376
PEG POWER
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
U46 U47 U48 V47 V48
nostuff
P1.5V
C
R582 C595 100nF
10V
Cantiga : 1.5V
VCCA_PEG_BG
AD48
1
B506 BLM18PG181SN1
C677 100nF
10V
VCCA_PEG_PLL
AA48
C593
10000nF-X5R 6.3V
VCCD_PEG_PLL VCCA_DPLLA VCCA_DPLLB VCCA_HPLL
AA47
MCH1_P1.05V_PEG_PLL_MN
PLL POWER
F47 L48
C539
AD1
10000nF-X5R 6.3V
C538
VCCA_MPLL
AE1
MCH1_P1.05V_MPLL_MN
100nF 10V
P1.05V
VCCD_HPLL
AF1
R554
0
VCC_SM_LF
VCC_SM_CK VCCA_SM_CK_NCTF
VCCA_SM_CK
VCCA_SM
VCC_AXG_SENSE VSS_AXG_SENSE
AJ14
C540
100nF 10V
B
B504 BLM18PG181SN1 R541
1
VCCA_SM_CK_NCTF_8 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_1
AH14
R553
0
VCCA_SM_CK_5 VCCA_SM_CK_4 VCCA_SM_CK_3 VCCA_SM_CK_2 VCCA_SM_CK_1
VCC_SM_CK_4 VCC_SM_CK_3 VCC_SM_CK_2 VCC_SM_CK_1
VCC_SM_LF_7 VCC_SM_LF_6 VCC_SM_LF_5 VCC_SM_LF_4 VCC_SM_LF_3 VCC_SM_LF_2 VCC_SM_LF_1
VCCA_SM_9 VCCA_SM_8 VCCA_SM_7 VCCA_SM_6 VCCA_SM_5 VCCA_SM_4 VCCA_SM_3 VCCA_SM_2 VCCA_SM_1
nostuff nostuff
R542
1
P1.05V
C541
100nF 10V
C542
10000nF-X5R 6.3V
MCH1_VCC_AXG_SENSE_MN MCH1_VSS_AXG_SENSE_MN
BB13 BA37 AY5 AV44 AV21 AM40 AM10
BH20 BG20 BF21 BF20
AM28 AM26 AM25 AM24 AM23 AL25 AL24 AL23
AT16 AR20 AR17 AR16 AP20 AP17 AP16 AN20 AN17
AP28 AP25 AN28 AN25 AN24
MCH1_P1.05V_MPLL_R_MN
P1.05V
C560
1000nF-X5R 6.3V
C557
10000nF-X5R 6.3V
C559
10000nF-X5R 6.3V
C599 22000nF-X5R
20%
6.3V
EC505 220uF
2.5V AD
nostuff nostuff
P1.8V_AUX
A
B505 BLM18PG181SN1 R555
1
P1.05V
DRAW DATE TITLE
A
Jun PARK
CHECK DEV. STEP
C596 C564 100nF
10V 100nF 10V
C598
2200nF-X5R 10V
C600
10000nF-X5R 6.3V
9/23/2008 PR
REV
CANNES-L_EXT
MCH_CANTIGA_GM_DDR2 CANTIGA (3/5)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
C566
10000nF-X5R 6.3V
nostuff
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
15
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
AJ25 AJ28 AJ34 AJ37 AJ39 AJ42 AJ47 AJ7 AK15 AL3 AL33 AL48 AM1 AM12 AM34 AM36 AM39 AM41 AM43 AM46 AM6 AM9 AN11 AN13 AN16 AN21 AN29 AN37 AN40 AN42 AN47 AN7 AN9 AP2 AP21 AR2 AR25 AR28 AR33 AR46 AR48 AT10 AT12 AT17 AT20 AT24 AT28 AT37 AT39 AT42 AT6 AT8 AU16 AU2 AU21 AU36 AU38 AU41 AU43 AU48 AU7 AV10 AV12 AV25 AV28
D
A12 A15 A18 A20 A23 A29 A31 A34 AA1 AA10 AA12 AA14 AA26 AA35 AA38 AA41 AA44 AA7 AB21 AB24 AB26 AB28 AB33 AB47 AC15 AC2 AC25 AD12 AD2 AD38 AD41 AD44 AD47 AD5 AD9 AE10 AE13 AE2 AE28 AE34 AE36 AE39 AE42 AE7 AF2 AF21 AF24 AF26 AF34 AF47 AG20 AG23 AG28 AH11 AH2 AH21 AH24 AH26 AH33 AH35 AH38 AH41 AH44 AH5 AH8 AJ10 AJ13 AJ2 AJ20 AJ24 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70
D
AV3 AV33 AV40 AV43 AV46 AV6 AV8 AW17 AW2 AW20 AW21 AW37 AW47 AY11 AY24 AY42 AY46 AY7 B23 B26 B34 B36 B39 B41 B8 B9 BA13 BA16 BA2 BA20 BA28 BA33 BA38 BA46 BA5 BB11 BB25 BB37 BB40 BB47 BB8 BC13 BC17 BC20 BC3 BC33 BC38 BC43 BC9 BD11 BD25 BD28 BD36 BD41 BD46 BD6 BE4 BF12 BF24 BF26 BF34 BF37 BF44 BF9 BG10 BG13 BG14 BG15 BG17 BG19
VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS F38 F44 F46 F5 G11 G13 G16 G21 G24 G25 G41 G47 G9 H1 H17 H28 H29 H33 H37 H40 H46 H5 J12 J21 J24 J25 J36 J38 J43 J5 J7 K16 K2 K20 K24 K28 K29 K32 L12 L13 L24 L25 L33 L36 L39 L42 L47 L5 L8 M10 M17 M2 M21 M41 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 M44 M6 N11 N13 N16 N20 N25 N29 N32 N39 N42 N47 N7 P1 P28 P3 P33 P36 P46 R17 R21 R24 R3 R46 T29 T35 T38 T41 T44 T47 U24 U25 U28 U29 U35 U38 U41 U44 V46 W15 W34 Y11 Y2 Y20 Y23 Y25 Y28 Y35 Y38 Y41 Y44 Y47 Y5 Y8
C
B
g l n a u ti s n m e a id S f n o C
U2-5 EB88CTPM 5 OF 5
0904-002376
TV & LVDS VSS VSS SCB
VSS NCTF
VSS
VSSA_DAC_BG
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16
VSSA_LVDS
VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5
B25
J47
AA17 AB29 AB32 AC19 AF29 AF32 AJ17 AJ30 AL17 AL20 AM29 U17 U23 U26 V20 V32
AJ6 BG21 BG28 BG33 BG36 BG40 BG42 BG6 BH23 BH25 BH38 BH8 C11 C14 C17 C20 C26 C28 C32 C37 C38 C43 C6 E13 E16 E24 E25 E40 E8 F20 F24 F28 F29 F3 F32 F36
A3 A48 BH1 BH48 C1
VSS_349 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240
VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205
C
VSS
VSS
VSS
VSS
B
A
DRAW DATE TITLE
A
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
MCH_CANTIGA_GM_DDR2 CANTIGA (4/5)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
16
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
DDR SO-DIMM #0
Height : 5.2mm (Reverse)
D
MEM1_ADQ(63:0)
14-D3
D
P0.9V
DDR2M_1-1 DDR2-SODIMM-200P-RVS
MEM1_AMA(14:0)
14-C4,17-D2
MEM1_AMA(14:0)
ME POWER RAIL UNDER ME ENABLE
14-C4,17-D4
1/2
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0* S1* CK0 CK0* CK1 CK1* CKE0 CKE1 CAS* RAS* WE* SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS*0 DQS*1 DQS*2 DQS*3 DQS*4 DQS*5 DQS*6 DQS*7
3709-001341
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
14-D4,17-C2 14-D4,17-C2 14-D4,17-C2 14-B4,17-C2 14-B4,17-C2 14-B4 14-B4 14-B4 14-B4 14-B4,17-C2 14-B4,17-C2 14-B4,17-C2 14-B4,17-C2 14-B4,17-C2
MEM1_ABS(2)
C
MEM1_ABS(0) MEM1_ABS(1) MEM1_CS0# MEM1_CS1# CLK1_MCLK0 CLK1_MCLK0# CLK1_MCLK1 CLK1_MCLK1# MEM1_CKE0 MEM1_CKE1 MEM1_ACAS# MEM1_ARAS# MEM1_AWE#
10K R522 10K R523 SMB3_CLK SMB3_DATA
1% 1%
MEM3_CHA_SA0_MN MEM3_CHA_SA1_MN
11-B4,18-B4 27-B4,54-D4 11-B4,18-B4 27-B4,54-B4 14-B4,17-C2 14-B4,17-C2
MEM1_ODT0 MEM1_ODT1 MEM1_ADM(7:0)
14-D4
B
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
MEM1_ADQS(7:0)
14-C4
MEM1_ADQS#(7:0)
14-D4
0 1 2 3 4 5 6 7
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
g l n a u ti s n m e a id S f n o C
DDR2M_1-2 DDR2-SODIMM-200P-RVS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
P1.8V_AUX
2/2
P3.3V
C525
C526
100nF 10V
2200nF-X5R 10V
nostuff
112 111 117 96 95 118 81 82 87 103 88 104 199 83 120 50 69 163 1
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12
VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF
MEM1_VREF
14-D1,18-C3 46-B2,54-B4
C720
10V
C719
10V
100nF
2200nF-X5R
201 202
GND0 GND1
nostuff
47 133 183 77 12 48 184 78 71 72 121 122 196 193 8
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57
18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
R600 R596 R599 R591 R601 R597 R605 R606 R593 R589 R557 R602 R594 R562 R603 R564 R559 R592 R604 R563 R560 R590 R598 R595 R558 R561 R556
56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56
MEM1_CS0# MEM1_CS1#
14-B4,17-C4 14-B4,17-C4 14-B4,17-C4 14-B4,17-C4 14-B4,17-B4 14-B4,17-B4
MEM1_CKE0 MEM1_CKE1
MEM1_ODT0 MEM1_ODT1
C
MEM1_ABS(0) MEM1_ABS(1) MEM1_ABS(2)
14-D4,17-C4 14-D4,17-C4 14-D4,17-C4 14-B4,17-C4 14-B4,17-C4 14-B4,17-B4
MEM1_ACAS# MEM1_ARAS# MEM1_AWE#
Place one cap close to every 2 pull-up resistors terminated to P0.9V
Place one cap close to every 2 pull-up resistors terminated to P0.9V
P0.9V
B
C615
100nF
C619
10V
C618
10V
C617
10V
C616
10V
C569
10V
C570
100nF
10V
100nF
100nF
100nF
100nF
100nF
3709-001341
10V
ME POWER RAIL UNDER ME ENABLE
P1.8V_AUX
Place near SO-DIMM0
P1.8V_AUX
C604
C563
C562
C565
EC502 220uF
2.5V AD
C622
C613
C568
C614
C621
2200nF-X5R 10V
C612
100nF 10V
C620
100nF 10V
C567
100nF 10V
C624
100nF 10V
0.047nF 50V
0.047nF 50V
0.047nF 50V
0.047nF 50V
2200nF-X5R 10V
2200nF-X5R 10V
2200nF-X5R 10V
2200nF-X5R 10V
nostuff
A
Tyco/Foxcn : 3709-001341 Suyin : 3709-001502
nostuff
nostuff
A
DRAW DATE TITLE
Jun PARK
CHECK DEV. STEP
9/23/2008 PR
REV
CANNES-L_EXT
MCH_CANTIGA_GM_DDR2 CANTIGA (5/5)
August 07, 2009 15:14:35 PM
SAMSUNG
ELECTRONICS
PART NO.
YM AN
APPROVAL
HJ KIM
MODULE CODE LAST EDIT
1.0
BA41PAGE
17
OF
55
4
3
2
1
D:/users/mobile24/mentor/cannes-l_ext/Cannes-L-Ext_MAIN
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO'S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
DDR SO-DIMM #1
Height : 9.2mm (Reverse)
D
MEM1_BDQ(63:0)
14-A1
D
ME POWER RAIL UNDER ME ENABLE
P0.9V MEM1_BMA(14:0)
14-B1,18-D4
DDR2M_2-1 DDR2-SODIMM-200P-RVS
MEM1_BMA(14:0)
14-B1,18-D1
P1.8V_AUX
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
1/2
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 10 26 52 67 130 147 170 18