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Chapter 6 Sync, Deflection and High Voltage
Like the Video-Color Signal Processing circuitry, the Sync, Deflection and High voltage circuitry is also more complex than that used in a standard NTSC receiver. This chapter will cover: Sync Signal Path Deflection Signal Path High Voltage Generation Block diagrams are included for circuit analysis and future troubleshooting needs.
Basic Block Diagram
Figure 6-1 shows a basic block diagram of the Sync, Deflection and High Voltage circuits. The Vertical and Horizontal Sync Signals can originate from three different sources. NTSC Y/V -- When an NTSC signal source is selected, Vertical and Horizontal Sync pulses are selected and separated from the Y Signal in the NTSC Decoder. DVD Component-- If the component inputs are used, Vertical and Horizontal Sync is selected and separated from the Y Signal in the Multi-Component Processor.
DTV -- Sync from an ATV receiver can be input either separately, as Sync on Green, or as part of the Y signal if Component Video is used. Incoming Horizontal Sync can be one of three frequencies depending on the format of the signal received. 480i -- 15.75 KHZ, or the same as NTSC. 480p -- 31.5 KHZ, or twice the NTSC rate. 1080i -- 33.75 KHZ. The Vertical Sync frequency is 59.94 or 60 HZ depending on the source.
When the selected signal is NTSC or 480i SDTV/ DVD, the signal is enhanced by Line Doubling. In these instances, the Horizontal Sync frequency is doubled in the Pulse Timing Controller located in the Scan Doubler circuit. This results in a horizontal sync frequency of 31.5 KHZ. The output format is customer selectable, 480p or 960i. The Multi-Component Processor, IC2B00, outputs to the Deflection Jungle either the direct input DTV 1080i/480p sync signals, the direct input DVD 480p sync or the 480p/960i line doubled sync sources. The sync signals are then used by the Deflection Jungle, IC4A01, to synchronize the internal Vertical and Horizontal Drive circuits. Vertical Drive is applied to conventional Vertical Output IC circuitry to power the Deflection Yokes. Horizontal Drive is sent to the Output circuitry, amplified, then directed to the Horizontal Deflection Yokes. A sample of the Horizontal Deflection drive signal is coupled to the High Voltage Regulator. Regulation is performed by Pulse Width Modulating the High Voltage drive signal. More details on the Sync, Deflection and High voltage circuits are provided in this chapter.
Sync Block Diagram
The signal path for vertical and horizontal sync is much longer than in a conventional TV receiver. In addition to the switching required by the different signal sources, timing for the PIP, Scalar and Line Doubler circuits is provided by the sync signals. A block diagram of the sync signal path is shown in Figure 6-2. The sync path for each of the three types of inputs, NTSC, DVD Component and DTV, will be explained further. NTSC Sync NTSC signals can be sourced from the tuner or external Video Inputs, 1-4. The external inputs can be Composite or S-Video. The Y or V signal sourced from the PCB-TERMINAL is applied to the sync separation circuitry in the Main Decoder, IC2200 by way of two signal switching ICs, IC2160 and IC2170. If Composite Video is the source, IC2160 selects the signal from the Comb Filter, IC2000. If S-Video is the source, IC2160 selects the signal from Q2160, since the comb filter is not used to process the Y signal in this mode. IC2170 can select either the NTSC signal or DVD/SDTV 480i signals from the Multi-Component Processor, IC2B00. The remainder of the path is the same for either of these formats. NTSC or SD/DVD sync is provided to the PCBPIP/Scalar for timing and is then processed by the Pulse Timing Control circuit in IC7D06 where it is used for timing of the line doubling process. At this
IC2B00, Multi-Component Processor: Function by Input / Format Input Signal Format Horiz Freq 480i 480p 480i DTV 480p 1080i 480p 960i Process Performed Sync Separation 15.75 KHZ 5 Signal Switching Sync Separation 31.5 KHZ 5 Signal Switching 23 or Sync Separation 15.75 KHZ 19, 20 Signal Switching 23 or Sync Separation 31.5 KHZ 19, 20 Signal Switching 23 or Sync Separation 33.75 KHZ 19, 20 Signal Switching 31.5 KHZ 65,66 Signal Switching 31.5 KHZ 65,66 Signal Switching Table 6-1 Input Pins Output Pins 79, 80 28, 29 79, 80 28, 29 28, 29 28, 29 28, 29
point, the frequency of the horizontal sync signal is also doubled to 31.5 KHZ. As mentioned, the format output from the doubler is customer selectable, 480p or 960i. The signals are applied to the Multi-Component Processor and are then switched out pins 28 and 29 to pins 2 and 32 of the Deflection Jungle, IC4A01, to provide synchronization for vertical and horizontal deflection drive. Table 6-1 provides a reference for the various functions performed to the sync signals by the Multi-Component Processor. DTV Sync As explained earlier, when an ATV Receiver is the selected signal source, the format can be 480i, 480p or 1080i. In all cases, the sync signals are input to the PCB-Terminal and applied to the Multi-Component Processor, IC2B00, on the PCB-RGB. Format detection is performed by monitoring the horizontal sync frequency of the horizontal sync input to IC2B00.
If an ATV channel is selected and the horizontal sync frequency is detected to be 31.5 KHZ (480p) or 33.75 KHZ (1080i), sync is switched out Pins 28 and 29 directly to the Deflection Jungle, IC4A01. If an ATV channel is selected and horizontal sync is detected to be 15.75 KHZ, the 480i (SD) sync signals are sent out Pins 79 and 80 where they are directed back along the same path as NTSC sync signals. DVD Component Sync The DVD Component format can be 480i or 480p. Like the DTV inputs, the sync signals are input to the PCB-Terminal and applied to the Multi-Component Processor where format detection is performed by monitoring the horizontal sync frequency. Sync is switched to the same paths as DTV 480i and 480p signals. Sub Sync Sub sync, used to time PIP/POP processing, is selected as shown in Figure 6-3.
Deflection Drive is generated by the Deflection Jungle, IC4A01, located on PCB-Jungle. A block diagram of the Deflection Jungle and Vertical Output circuitry is shown in Figure 6-4. Inputs and Outputs to the DS Connector between the PCB-Power and PCB-Jungle are shown in the block diagram starting from the left. Table 6-2 lists the function of each. Connector DS - Inputs Pins 10 and 9 are the I2C inputs for uPC control over deflection. The ACL input at Pin 7 represents the beam current and is used to for raster size control asbeam current demand changes. Horizontal Sync is input Pin 15. The FBP is fed back from the FBT for Phase Control of the Horizontal Drive signal. Pin 4 feeds back a sawtooth from the Vertical Yoke ground return for vertical linearity correction. This waveform is also sent to the Video Blanking circuit. If Vertical Deflection is lost, video will be blanked to prevent CRT phosphor damage. Vertical Sync is input to Pin 2.
Pin 10 9 7 15 14 4 2 3 1 6 12 13
PCB-JUNGLE / PCB-POWER Connector DS INPUTS Nomenclature Signal Waveform Function SCL2 SDA2 ACL HD FBP NF VD 5.0 Vp-p Clock I C Serial Clock
5.0 Vp-p Data I C Serial Data 5.0 VDC DC Beam current 3.5 Vp-p Spike Horizontal Sync 5.0 Vp-p Pulse Horizontal APC 2.5 Vp-p Saw Vertical Linearity 3.5 Vp-p Spike Vertical Sync OUTPUTS VTIM 5.0 Vp-p Spike Vertical Timing SCP 4.0 Vp-p Pulse Sand Castle Pulse VD 1.0 Vp-p Saw Vertical Drive EW 0.5 Vp-p Parabola Side Pin Cushion HD 8.0 Vp-p Square Horizontal Drive Table 6-2 PCB-JUNGLE Inputs and Outputs
Connector DS - Outputs The VTIM and SCP at Pins 3 and 1 are directed to IC2B00 to time signal processing. The Vertical Drive signal is output Pin 6. A Vertical Parabola for Side Pin Cushion Correction is fed out Pin 12. The Horizontal Drive signal is output Pin 13.
The Vertical Deflection circuitry remains largely unchanged from previous designs. Since the V16N and V16W have 2 different aspect ratios, the value of R401 is modified for the different vertical deflection requirements.
While much of the Horizontal Deflection circuit is conventional in design, some of the supporting circuitry is new. A block diagram of the Horizontal Deflection circuit is depicted in Figure 6-5. The Horizontal Drive signal from the Deflection Jungle drives the Horizontal Output transistor, Q501, by way of Q510, Q500 and T501. The ground return for the yokes is provided through C508, C509, R572 and the Linearity Coil, L502. The values of C508 and C509 are different between models using the 16:9 and 4:3 aspect ratios.
Supporting Circuitry Q503 has two functions. 1) Voltage Regulation 2) Pin Cushion Correction Drive. The conduction of Q503 is controlled by the three inputs to IC5A00 - FH1, DEFL-MUTE and SIDEPCC. Since this chassis is capable of two deflection frequencies, the deflection circuit has different voltage requirements for the different signal sources. The
FH1 input at connector DL Pin 6 changes the regulation. HIGH = 31.5 KHZ LOW = 33.75 KHZ FH1 changes the DC bias on the Op-amp, IC5A00, by switching Q5A03. This results in a bias change on Q503, raising or lowering the source voltage to the Horizontal Deflection circuit. FH1 also switches Q507 and Q506, removing or placing R507 in parallel with R505 and R506. This alters the voltage source for the Horizontal Drive circuit, T501 and Q500. To reduce circuit stresses caused when changing frequencies, the DEFL-MUTE input provides a momentary HIGH to the base of Q5A00 during the transition period. The change in bias briefly lowers the output at the emitter of Q503 to about 85 volts while the circuit stabilizes. The Pin Cushion Correction waveform, SIDE-PCC, generated by the Deflection Jungle is also added to the input of IC5A00 to be coupled into the deflection circuit. C504 couples a sample of the Horizontal Deflection Output pulse to the Video Blanking circuit on the PCB-RGB. If deflection is lost, the video will be blanked to prevent damage to the CRTs' phosphor. C504 is also coupled to the High Voltage Regulator, IC500, to develop the High Voltage Drive signal.
erated by the Oscillator is timed to the HD input to Pin 4. This, in turn, determines the leading edge of the PWM. The On time pulse duration of the PWM is determined by the Error Amp.
IC500 achieves High Voltage regulation by Pulse Width Modulating the High Voltage Drive. Figure 6-6 demonstrates how this is performed. The PWM is controlled by the Oscillator and Error Amp Inputs. The leading edge of the Sawtooth gen-
The HV ADJ input to the Error Amp is a DC reference from the Convergence Generator circuit. The HV FB is a Feed Back voltage proportional to the High Voltage. During normal brightness and high voltage, the output of the Error Amp is timed to trigger the trailing edge of the PWM to give less than a 50% pulse duration. If an increase in beam current creates a load on the high voltage, the Feed Back is lowered. The Output of the Error Amp will increase resulting in a delay of the sample timing and a longer pulse duration. A decrease in beam current and resulting rise in High Voltage will produce the opposite results. IC500 also has protection circuitry, Over Current input to Pin 7 and Over Voltage (XRAY) input to Pin 10. If the threshold of either input is exceeded, the PWM will be shut down. During shut down, the Sense outputs at Pins 8 or 3 will be high. Checking these pins will help determine if the shutdown is current or voltage related. Figure 6-7 shows how IC500 is used with the High Voltage, Regulation and Shut Down circuits. The PWM Output drives Q500 and the Fly Back Transformer. The resultant High Voltage is applied to the CR Block and split to the CRTs. The DX connector from the CR Block provides: AC HV Feed Back sample DC HV Feed Back sample Ground return for the voltage divider. R559 couples the AC and DC HV Feed Back samples together and routes them to Pin 6 of IC500. Caution: Due to high impedances within the CR Block, if measurements are attempted between DX Pin 3 and the buffer transistor Q531, a DVM will load down the DC Feed Back. This load will cause an undesirable increase in High Voltage.
Caution: An open condition in the HV FB path can result in excessive High Voltage. With no beam current, HV can exceed 60 KV. Do not operate the set with connections at DX disconnected or with the Anode Lead between the FBT and the CR Block disconnected. Protection Circuitry The V16 chassis X-ray protection works in conjunction with IC500 to shutdown under excessive voltage or current conditions. Current in the High Voltage circuit is detected by the voltage drop across Q500's ground return resistor, R531. If the increase in current is excessive, it will be detected at the DCL input at Pin 7, causing IC500 to shut down. Excessive High Voltage and Beam Current conditions are detected by the comparators on the PCBDEFL-MINI. If either is excessive, a High is output on the XRAY line at Connector DR, Pin 3. The XRAY line is coupled to the IC700 and IC500. While the High to the uPC, IC700 will cause the TV to shut down, for faster response, it is also sent to IC500. IC500 will shut down HV Drive. Beam Current is detected by monitoring the Automatic Current Limiter voltage produced at the ground return side of the FBT, Pin 8. This voltage is divided and input to 2 comparators, Q5A02 and IC5A01. An increase in beam current will cause the ACL voltage to decrease. If the voltage falls below a stable reference, the output will go High, causing shut down. The High Voltage Feed Back voltage is also compared to a stable reference by IC5A01. Again, if excessive, the output will cause a shut down condition. Note: The oscillator in IC500 will not operate without the HD-IN drive input. So, it is important to check this signal if there is no High Voltage.