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Chapter 7 Convergence
Convergence circuitry in the V16 Chassis is similar to the NTSC VZ5 and VZ7 digital convergence designs and identical to that used in the first generation HDTV capable VZ6 and V15 Chassis. This chapter will cover: Input Buffer Circuitry Convergence Output Circuitry PCB-CONVERGENCE Signal Path Convergence Control Circuitry Edge Convergence Enhancement Convergence Shutdown Control

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A Basic Block Diagram of the Convergence Circuitry in the V16 chassis is shown above. Horizontal and vertical pulses from the Deflection circuitry are shaped and timed by the Input Buffer circuitry. The outputs of the Buffer circuit are applied to the Convergence Generator. The Convergence Generator generates red, green and blue horizontal and vertical convergence correction signals. The correction signals from the Generator are in a serial digital format and are applied to Digital to Analog (D/A) Converter circuitry. The signals are converted from digital to analog and any remaining high frequency digital signals are removed by Low Pass Filters (LPFs). The analog signals are then directed to Summing Amplifiers. In the Summing circuitry, the signals are amplified, and green correction is added to the red and blue signals. The green signals are used for overall ras-

ter correction. Although raster correction is performed while viewing a green raster, the adjustments also affect the red and blue rasters. The signals from the Summing Amplifiers are amplified by Convergence Output Amplifiers and are directed to the Sub Coils in the Deflection Yokes. Although the Block Diagram of the Convergence Circuitry is the same as that in the VZ5 and VZ7 chassis, differences do exist. The main differences in the circuitry are: A Schmitt Trigger IC is added to the Vertical and Horizontal Pulse Input Buffer circuit. Different Convergence Output ICs are used. Three additional A/D Converter ICs are added. Edge Convergence correction is increased by momentarily increasing the Output ICs' DC Supplies.

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Figure 7-1 illustrates the Vertical and Horizontal Pulse Input Buffer circuitry, and the Convergence Output circuitry. Both circuits are located on the PCB-POWER. A Schmitt Trigger IC, IC402 is added to the Buffer circuitry. It is inserted between the Deflection circuits and the D-Type FF, IC403. IC402 provides cleaner pulses to drive IC403. The Clock signal for IC403 is the same as in the VZ5, supplied by the WCLK output at pin 27 of IC800, the Convergence Generator. Horizontal and vertical pulses from IC403 are directed to the HBLK and VBLK inputs of IC800, respectively. All convergence correction signals are derived from the horizontal and vertical pulses applied to IC800.

Input Buffer Circuit

vergence signals, and IC8D02 amplifies Vertical Convergence signals. Different Output ICs (Generic #STK392-040) are used in the VZ6 and V15 chassis, resulting in different input and output pin numbers. There are three Pre Amplifiers, and three Output Amplifiers in each IC. Four DC supplies furnish power for the Output ICs. +24 Volts -24 Volts +34 Volts -34 Volts The positive and negative 34 Volts supplies are the DC power source for the Pre Amplifiers. The positive and negative 24 Volt supplies provide power for the Output Amplifiers. The correction signals from the two Output ICs are directed to their respective sub coils in the Deflection Yokes.

The Convergence Output Circuitry is also shown in Figure 7-1. IC8D01 amplifies the Horizontal Con-

Convergence Output Circuitry

NOTES _____________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________

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Figure 7-2 illustrates the Convergence Generator and the correction signal path on the PCB-CONV. IC800 is the Convergence Generator which generates six correction signals: 1) Red Horizontal Correction (pin 60) 2) Green Horizontal Correction (pin 59) 3) Blue Horizontal Correction (pin 58) 4) Red Vertical Correction (pin 46) 5) Green Vertical Correction (pin 45) 6) Blue Vertical Correction (pin 44) The correction signals from IC800 are in a serial digital format, and are directed to six Digital to Analog Converter ICs. In the VZ5 and VZ7 chassis only three D/A Converter ICs were used. In the VZ6, V15 and V16 chassis, three additional D/A

PCB-CONV Signal Path

Converters have been added, IC8E04, IC8E05 and IC8E06. The signals from the D/A Converters pass through LPF circuitry, removing any remaining high frequency digital signal. The signals are then amplified in Summing Amplifiers and directed to the Convergence Output ICs on the PCB-POWER. Note that green correction signals are added to the red and blue signals at the inputs to the Summing Amplifiers. Power for the LPF and Summing Amplifier ICs is from the plus and minus 9 volt supplies. Therefore, the output signals from these ICs swings both positive and negative. An output of 0 volts denotes no correction at that point in time.

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If either the positive, or negative 9 Volt supply is missing, maximum drive would be applied to the Output ICs. Protection circuitry has been added to protect the Output ICs should one of the 9 Volt supplies be lost. The Protection circuitry is described later in this section.

period of time, the uPC assumes that IC810 is locked up. When this occurs, IC700 outputs a momentary HIGH at pin 19. The HIGH, through Q8F01 and Q8F02, momentarily removes the Vcc voltage at pin 8 of IC810, to unlock the IC. The CONV-RST line from pin 26 of IC700 is driven HIGH when Convergence Reset is selected from the Setup Menu. When this occurs, all convergence data is set to its nominal value, and a complete Raster Correction and Convergence Adjustment is required. Timing for the D/A Converter ICs is provided by the BCLK (Bit Clock) signal from pin 28 of IC800, and the WCLK (Word Clock) signal at pin 27. Note that the WCLK signal is inverted by Q801 for the three added D/A Converter ICs, IC8E04, IC8E05 and IC8E06. Two additional outputs are shown in Figure 7-3, PM1 at pin 16, and DAOUT at pin 38 of IC800. The PM1 output is the analog voltage controlling HV adjustment. The DAOUT output is a parabolic signal directed to the Dynamic Focus circuitry to improve edge focus. The parameters of the parabolic waveform are determined by the DF data settings in the Coarse Convergence mode.

Figure 7-3 shows the Convergence Control Circuitry. As in the VZ5, timing for the operation of IC800 is provided by IC809, a PLL IC. The output of the PLL is phase locked to horizontal sync, input to the IC at pin 4. The Main uPC, IC700 controls the Convergence circuitry over the SDA-1 line from pin 21 of the uPC. Data transfer is timed by the SCL-1 signal from pin 23 of IC700. IC800 acknowledges receiving a uPC command over the NOT ACK line from pin 12 of the IC. If no acknowledgment is received to a command, the uPC automatically repeats the command. When IC800 is busy, performing a previous command, or communicating with the E2PROM (IC810), it pulls the NOT BUSY line LOW. If the NOT BUSY line remains LOW for an extended

Convergence Control Circuitry

NOTES _____________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________ ___________________________________________________________________________________

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Maximum convergence correction is required at the extreme sides of the picture. In the VZ5 and VZ7 chassis, drive to the Convergence Output ICs was momentarily increased at the sides of the picture. In the VZ6,V15 and V16 chassis, the DC supplies for the Convergence Output stages are momentarily increased from 24 volts to 34 volts. The increase in the DC supplies increases convergence correction at the sides of the picture. Figure 7-4 illustrates the circuitry used to momentarily increase the Convergence Output supplies to 34 volts. A horizontal pulse (BLKOUT) from Pin 23 of IC800 is applied to the base of Q8D81. The resulting negative going pulse at the collector of Q8D81 momentarily:

Edge Convergence Enhancement

Turns ON Q8D82, Q8D83 and Q8D84 applying +34 volts to pins 15 and 18 of the Output ICs. Turns ON Q8D85 and Q8D86 applying -34 volts to pin 16, 17 and 19 of the Output ICs. If the pulse width, and phase, of the BLKOUT pulse are incorrect, crosshatch lines at the corners of the picture may break up, and the Output ICs may run hot. The pulse width and phase are determined by the preset data in the CONV-MISC mode. If this symptom occurs, check the data values in the CONV-MISC mode against those given in the Service Manual for that specific model.

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The circuitry in Figure 7-5 protects the Output ICs if an imbalance in the positive and negative 9 Volt supplies occurs. The 9V Tracking Circuit insures that the magnitude of the plus and minus 9 Volt supplies remains equal. When both supplies are equal, the voltage at the junction of R8D92 and R8D94 is zero. With zero volts at their base, neither Q8D87 or Q8D88 conduct. If a difference in the two 9 volt supplies exists, the voltage at the junction of R8D92 and R8D94 will go positive or negative. Positive if the +9V supply is higher, and negative if the -9V supply is higher. A positive voltage turns ON Q8D87, reducing the +9V supply. A negative voltage turns ON Q8D88, reducing the negative supply.

Convergence Shutdown Control

Since the positive and negative 9 Volt supplies are held at the same magnitude, this prevents excessive drive to the Output ICs due to a 9 Volt Supply problem. To further protect the Output ICs, the SW 5V supply is also monitored. This supply provides DC power for the Convergence Generator and the A/ D Converters. The presence of the SW 5V supply holds Q8D91 ON, through zener diode D892. With Q8D91 conducting, the base of Q8D90 is held LOW. If the 5 Volt supply drops below the zener point of D892 (4.3 volts), Q8D91 turns OFF. This allows Q8D90 to conduct, pulling the +9 Volt supply low. The Tracking circuit responds by reducing the -9 Volt supply, preventing any excessive drive to the Output ICs.

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