Text preview for : Toshiba Satellite Pro L450 (Schematic).pdf part of Toshiba Satellite Pro L450 Toshiba Satellite Pro L450 (Schematic)
Back to : Toshiba Satellite Pro L45 | Home
A
B
C
D
E
1
1
NBWAA
2
Low Cost Los Angeles 10L
LA-5821P REV 1.0 Schematics
Intel Penryn/ Cantiga/ ICH9M 2008-08-10 Rev. 1.0
2
3
3
4
4
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Cover Page
Size Date: Document Number
NBWAA LA5821P M/B
Thursday, August 06, 2009 Sheet
E
Rev 1.0 1 of 41
A
B
C
D
E
Compal Confidential
Model Name : NBWAA File Name : LA-5821P
1
Fan Control
Intel Penryn Processor
uPGA-478 Package (Socket P) page
H_A#(3..35) 5,6,7
Thermal Sensor
EMC1402-1
page 5
Clock Generator
SLG8SP556VTR
page 17
1
page 5
FSB
667/800/1066MHz
H_D#(0..63)
CRT
page 18
Memory BUS(DDRII)
Intel Cantiga
GM45/GL40 Level Shifter
page 19
Dual Channel
1.8V DDRII 533/667/800
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
page 15,16
LCD Conn. HDMI Conn.
page 18
uFCBGA-1329
page 8,9,10,11,12,13,14
page 19
2
DMI x 4
PCIeMini Card WLAN
USB port 7 page 25 PCIe port 4 page 25
C-Link USB/B
USB port 0,1
USB
5V 480MHz
2
USB
5V 480MHz
USB conn
USB port 3
page 24
PCIe 1x [2,4,5]
1.5V 2.5GHz(250MB/s)
page 24
Intel ICH9-M
BGA-676
PCIe 1x
1.5V 2.5GHz(250MB/s)
Int. Camera
USB port 11
page 18,25
RJ45
page 26
RTL8103EL 10/100M
PCIe port 3 page 26
SATA port 1
page 19,20,21,22
5V 1.5GHz(150MB/s)
SATA HDD SATA ODD
page 24
SATA port 4
5V 1.5GHz(150MB/s)
page 24
RTS5159-VDD 3IN1
3
USB
5V 480MHz
3
USB port 10
page 29
LPC BUS
3.3V 33 MHz
HD Audio
3.3V 24.576MHz/48Mhz
MDC 1.5 Conn Debug Port ENE KB926 D3
page 30 page 25
HDA Codec
ALC272
page 27
RTC CKT.
page 21
NBWAA Sub-boards
page 31
USB/B DC/DC Interface CKT.
page 33
4
page 24
Touch Pad
page 31
Int.KBD
SPI ROM
page 31
page 31
Int. MIC CONN page 28
AMP.
MIC CONN page 28 HP CONN page 28
TPA6017
page 28
Power/B CS/B
page 32 SPK CONN page 28
4
Power Circuit DC/DC
page 34~40
page 31
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Block Diagrams
Size Date: Document Number
NBWAA LA5821P M/B
Thursday, August 06, 2009 Sheet
E
Rev 1.0 of 41
2
5
4
3
2
1
DESIGN CURRENT 0.1A
+3VL +5VALW +5V_SB +5VS +HDMI_5V_OUT
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9
DESIGN CURRENT 5A
SBPWR_EN#
D
N-CHANNEL 2N7002DW
SUSP
DESIGN CURRENT 2mA
D
N-CHANNEL SI4800
DESIGN CURRENT 4A
TPS51125RGER
DIODE PMEG2010AEH FUSE 1.1A_6V
DESIGN CURRENT 0.5A
Ipeak=5A, Imax=3.5A, Iocp min=7.7
WOL_EN#
DESIGN CURRENT 5A
+3VALW
P-CHANNEL AO-3413
DESIGN CURRENT 330mA
+3V_LAN
SBPWR_EN#
C
N-CHANNEL SI3456
SUSP
DESIGN CURRENT 225mA
+3V_SB
C
N-CHANNEL SI4800 P-CHANNEL AO-3413
VR_ON
DESIGN CURRENT 4A
+3VS +LCD_VDD
UMA_ENVDD
DESIGN CURRENT 1.5A
DESIGN CURRENT 47A
ISL6262ACRZ-T
SYSON
+CPU_CORE
TPS51117RGYR
B
Ipeak=8A, Imax=5.6A, Iocp min=19.8
SUSP
DESIGN CURRENT 10A
+1.8V +0.9VS
B
DESIGN CURRENT 1.5A
APL5331KAC
SUSP#
Ipeak=5A, Imax=3.5A, Iocp min=16.5
DESIGN CURRENT 4A
+1.5VS +1.05VS
TPS51124RGER
Ipeak=10A, Imax=7A, Iocp min=16.5
DESIGN CURRENT 10.2A
A
A
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Power Tree
Size Date: Document Number
NBWAA LA5821P M/B
Thursday, August 06, 2009 Sheet
1
Rev 1.0 of 41
3
A
B
C
D
E
Voltage Rails
Power Plane VIN
1
STATE
Description Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU 0.9V switched power rail for DDR terminator 1.05V switched power rail 1.5V switched power rail 1.8V power rail for DDR 3.3V always on power rail 3.3V always on power rail 3.3V power rail for LAN 3.3V power rail for LAN 3.3V power rail for LAN 3.3V switched power rail 5V always on power rail 5V always on power rail 5V power rail for SB 5V switched power rail VSB always on power rail RTC power Core voltage for VGA chip 1.1V switched power rail for VGA PCIE 1.8V power rail for VRAM S1 ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON S3 ON ON OFF OFF OFF OFF ON ON ON ON ON ON OFF ON ON ON OFF ON ON ON ON ON S5 ON ON OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF ON ON OFF OFF ON ON OFF OFF OFF G3 OFF ON OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# HIGH LOW LOW LOW LOW LOW HIGH HIGH LOW LOW LOW LOW HIGH HIGH HIGH LOW LOW LOW HIGH HIGH
1
Full ON S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) G3
B+ +CPU_CORE +0.9VS +1.05VS +1.5VS +1.8V +3VALW +3VL +3V_SB +3V_LAN +3V_WLAN +3VS +5VALW +5VL
2
HIGH HIGH LOW LOW
BTO Option Table
Function description explain BTO
North Bridge GM GM45 GM45R3@ GM45R1@ GL GL40 GL40R3@ GL40R1@ MODEM MDC@ CAMERA CAM@ MIC MIC@ RJ11 CAMERA MIC Y HDMI IHDMI@ Non-HDMI NIHDMI@ HDMI
2
+5V_SB +5VS +VSB +RTCVCC +CPU_CORE +VGA_PCIE_1.1VS +1.8VS
External PCI Devices EC SM Bus1 address
3
EC SM Bus2 address
Power
+3VS 0001 011X b +3VS
Power
+3VL +3VL +3VL
Device
EC KB926 D3 Smart Battery FUN/B (CAP Sensor)
Address
Device
EC KB926 D3 CPU THM Sen SMSC SMC1402
Address
3
0100 110x b
ICH9M SM Bus address
Power
+3V_SB
4
Device
ICH9M Clock Generator (SLG8SP556V) DDR DIMM0 DDR DIMM1
Address
1101 001Xb
4
+3VS +3VS +3VS +3VS
1001 000Xb 1001 010Xb Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Notes List
Size Date: Document Number
NBWAA LA5821P M/B
Thursday, August 06, 2009 Sheet
E
Rev 1.0 41
4
of
5
4
3
2
1
8
H_A#[3..16] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
@ JCPUA
+3VS
CONTROL
D
8 8 8 8 8 8 8
H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK#
H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_RESET# H_IERR# H_INIT# R1 1
H_DEFER# 8 H_DRDY# 8 H_DBSY# 8 H_BR0# 8 +1.05VS C2 1
0.1U_0402_16V4Z
ADS# BNR# BPRI#
H1 E2 G5
H_ADS# H_BNR# H_BPRI#
8 8 8
ADDR GROUP_0
1
C1 U1
2 1
H_THERMDA
2 56_0402_5% H_INIT# 21
H_LOCK# 8 H_RESET# 8 H_RS#0 8 H_RS#1 8 H_RS#2 8 H_TRDY# 8 H_HIT# 8 H_HITM# 8
VDD DP DN THERM#
SMCLK SMDATA ALERT# GND
8 7 6 5 1 R2 2 10K_0402_5% @ Reserve
EC_SMB_CK2 30 EC_SMB_DA2 30 +3VS
D
2 3 4
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
H_THERMDC 2 2200P_0402_50V7K CPU_THERM#
for source control
if use XDP,these resistor are 51ohm +1.05VS XDP_TDO XDP_TMS XDP_TDI XDP_TCK XDP_TRST#
8 21 21 21 21 21 21 21
H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#
A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 D2 D22 D3 F6
PROCHOT# THERMDA THERMDC THERMTRIP#
D21 A24 B25 C7
H_PROCHOT# H_THERMDA H_THERMDC H_THERMTRIP# 9,21
Q6 @ MMBT3904_SOT23
1
C
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
1 R14 1 R4 1 R5 1 R6 1 R7
2 54.9_0402_1% 2 54.9_0402_1% 2 54.9_0402_1% 2 54.9_0402_1% 2 54.9_0402_1%
+3VS
R3 1 2 10K_0402_5%
EMC1402-1-ACZL-TR_MSOP8
Address:0100_1100 EMC1402-1 Address:0100_1101 EMC1402-2
XDP/ITP SIGNALS
+1.05VS XDP_DBRESET# 22
2
1 R8 1 R9
2 @ 56_0402_5% 2 56_0402_5%
E
2
B B C3 10U_0805_10V4Z
1
1SS355_SOD323-2 @ D1
2
A20M# FERR# IGNNE#
2
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]
Reserve for debug close to South Bridge
H_FERR# 2 C596
Penryn
B
1 180P_0402_50V8J
RESERVED
ADDR GROUP_1
+5VS
FAN Control Circuit
XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
1A
PAD T13
JFAN
THERMAL
H_PROCHOT#
3
1
OCP#
22 U2 +FAN1
1 2
+FAN1
1 2 3 4 5
1 2 3 GND GND
C
PROCHOT# PU: 68Ohm near CPU and MVP6. 56Ohm near CPU if no used.
30 EN_DFAN1
C
1 2 3 4 1
EN VIN VOUT VSET
GND GND GND GND
8 7 6 5
D2 @
C4 @ 1000P_0402_25V8J 1
ICH
BAS16_SOT23-3
ACES_85204-0300N @ R10 10K_0402_5% 1 +3VS FAN_SPEED1 30
10mil H CLK
BCLK[0] BCLK[1] A22 A21
CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
2
APL5607KI-TRG_SO8 C5 10U_0805_10V4Z
2 2
C6 0.01U_0402_16V7K 1 @
B
H_SMI# H_INIT# H_NMI H_A20M# H_INTR H_IGNNE# H_STPCLK#
2 C597 2 C598 2 C599 2 C600 2 C601 2 C602 2 C603
1 180P_0402_50V8J 1 180P_0402_50V8J 1 180P_0402_50V8J 1 180P_0402_50V8J 1 180P_0402_50V8J 1 180P_0402_50V8J 1 180P_0402_50V8J
Reserve for debug close to CPU
A A
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Penryn(1/3)-AGTL+/THM/FAN
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009 Sheet
1
Rev 1.0 of 41
5
5
4
3
2
1
@ JCPUD
8
H_D#[0..15] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
@ JCPUB
H_D#[32..47]
8
8 8 8 8
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
DATA GRP 2
D
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]
Penryn
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3]
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 8 H_DSTBP#2 8 H_DINV#2 8 H_D#[48..63] 8 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 8 H_DSTBP#3 8 H_DINV#3 8 COMP0 COMP1 COMP2 COMP3 H_DPRSTP# H_DPSLP# H_PW RGOOD H_CPUSLP# H_DPRSTP# 9,21,40 H_DPSLP# 21 H_DPW R# 8 H_PW RGOOD 21 H_CPUSLP# 8 H_PSI# 40
C
+1.05VS Close
R11 1K_0402_1%
to CPU pin AD26 within 500mils.
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
COMP0 COMP1
8 8 8
H_DSTBN#1 H_DSTBP#1 H_DINV#1 +CPU_GTLREF
+CPU_GTLREF
R17 2K_0402_1%
1
MISC
1 R12 1 R13 COMP2 1 R15 COMP3 1 R18
2 27.4_0402_1% 2 54.9_0402_1% 2 27.4_0402_1% 2 54.9_0402_1%
9,17 CPU_BSEL0 9,17 CPU_BSEL1 9,17 CPU_BSEL2
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
layout note: Please use "Daisy Chain" to layout and the signal (H_DPRSTP#) is routed from ICH9 to power IC, then to NB and CPU
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
B
CPU_BSEL 166 200 266
CPU_BSEL2 0 0 0
CPU_BSEL1 1
CPU_BSEL0 1 0 0
2 C650 H_PW RGOOD 2 C651 H_DPRSTP# 2 C652 H_DPSLP# 2 C653
H_CPUSLP#
1
0
1 180P_0402_50V8J 1 180P_0402_50V8J 1 180P_0402_50V8J 1 180P_0402_50V8J
Reserve for debug close to CPU
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
Penryn
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
.
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
DATA GRP 3
DATA GRP 0 DATA GRP 0 DATA GRP 1
D
C
2
2
1
B
A
A
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Penryn(2/3)-AGTL+/GND
Size Date: Document Number
NBWAA LA5821P M/B
Thursday, August 06, 2009 Sheet
1
Rev 1.0 of 41
6
5
4
3
2
1
Near CPU CORE regulator
+CPU_CORE 330U_D2_2.5VY_R9M 1 330U_D2_2.5VY_R9M 1 + C9 C10 +CPU_CORE
1
+
1
+
ESR <= 1.5m ohm Capacitor > 1980uF
D
+ C7 @ C8
1
Place these capacitors on L8 (North side,Secondary Layer)
C11 10U_0805_6.3V6M
1
C12 10U_0805_6.3V6M
1
C13 10U_0805_6.3V6M
1
C14 10U_0805_6.3V6M
1
C15 10U_0805_6.3V6M
1
C16 10U_0805_6.3V6M
1
C17 10U_0805_6.3V6M
1
C18 10U_0805_6.3V6M
2
2 330U_D2_2.5VY_R9M
2
2 330U_D2_2.5VY_R9M
2
2
2
2
2
2
2
2
Change to SGA00002680
+CPU_CORE @ JCPUC +CPU_CORE +CPU_CORE
D
C
B
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
Penryn
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
.
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
VCCSENSE VSSSENSE
1
Place these capacitors on L8 (North side,Secondary Layer)
C19 10U_0805_6.3V6M
1
C20 10U_0805_6.3V6M
1
C21 10U_0805_6.3V6M
1
C22 10U_0805_6.3V6M
1
C23 10U_0805_6.3V6M
1
C24 10U_0805_6.3V6M
1
C25 10U_0805_6.3V6M
1
C26 10U_0805_6.3V6M
2
2
2
2
2
2
2
2
+CPU_CORE
1
Place these capacitors on L8 (Sorth side,Secondary Layer)
C27 10U_0805_6.3V6M
1
C28 10U_0805_6.3V6M
1
C29 10U_0805_6.3V6M
1
C30 10U_0805_6.3V6M
1
C31 10U_0805_6.3V6M
1
C32 10U_0805_6.3V6M
1
C33 10U_0805_6.3V6M
1
C34 10U_0805_6.3V6M
2
2
2
2
2
2
2
2
+CPU_CORE
1
Place these capacitors on L8 (Sorth side,Secondary Layer)
C35 10U_0805_6.3V6M
1
C36 10U_0805_6.3V6M
1
C37 10U_0805_6.3V6M
1
C38 10U_0805_6.3V6M
1
C39 10U_0805_6.3V6M
1
C40 10U_0805_6.3V6M
1
C41 10U_0805_6.3V6M
1
C42 10U_0805_6.3V6M
C
2
2
2
2
2
2
2
2
Mid Frequence Decoupling
+1.05VS
1
+
1
+
+1.05VS (North side Secondary)
Place these inside socket cavity on L8
@ C43 C912 2 2 330U_D2_2VY_R7M 330U_6.3V_M_R15
1
C44 0.1U_0402_10V6K
1
C45 0.1U_0402_10V6K
1
C46 0.1U_0402_10V6K
1
C47 0.1U_0402_10V6K
1
C48 0.1U_0402_10V6K
1
C49 0.1U_0402_10V6K
2
2
2
2
2
2
reserve for test
Near pin B26
+1.5VS 1 C51 C50 0.01U_0402_16V7K 10U_0805_6.3V6M 2 2
1
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 40 40 40 40 40 40 40
B
VCCSENSE 40 VSSSENSE 40
+CPU_CORE
VCCSENSE
100_0402_1% 2
1
R19
VSSSENSE
100_0402_1% 2
1
R20
A
Close to CPU pin within 500mils. Length match within 25 mils. The trace width/space/other is 14/7/25.
5 4
A
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Penryn(3/3)-PWR/Bypass
Size Date: Document Number
NBWAA LA5821P M/B
Thursday, August 06, 2009 Sheet
1
Rev 1.0 of 41
7
5
4
3
2
1
6
H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SW NG H_RCOMP
U3A
H_A#[3..35]
5
D
C
Layout Note: H_RCOMP / +H_VREF / H_SWNG trace width and spacing is 10/20 within 100 mils from NB
+1.05VS +1.05VS
B
R21 1K_0402_1%
R22 221_0402_1% +H_VREF H_RCOMP
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 C5 E3
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# 5 H_ADSTB#0 5 H_ADSTB#1 5 H_BNR# 5 H_BPRI# 5 H_BR0# 5 H_DEFER# 5 H_DBSY# 5 CLK_MCH_BCLK 17 CLK_MCH_BCLK# 17 H_DPW R# 6 H_DRDY# 5 H_HIT# 5 H_HITM# 5 H_LOCK# 5 H_TRDY# 5
D
C
HOST
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
6 6 6 6 6 6 6 6 6 6 6 6
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 5 5 5 5 5 5 5 5
1
1
B
1 2
2
H_SWING=0.3125*VCCP
H_SW NG
1
R23 2K_0402_1%
1
1
2
2
2
2
C52 0.1U_0402_16V4Z @
R24 24.9_0402_1%
1
R25 100_0402_1% C53 0.1U_0402_16V4Z 5 6 H_RESET# H_CPUSLP# +H_VREF
2
C12 E11 A11 B11
H_CPURST# H_CPUSLP# H_AVREF H_DVREF
Near B3 pin
CANTIGA ES_FCBGA1329 GM45R3@
A
A
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Cantiga GMCH(1/7)-GTL
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009 Sheet
1
Rev 1.0 41
8
of
5
4
3
2
1
Strap Pin Table
CFG[2:0] CFG5 CFG6
Internal pull-up Internal pull-up
U3B
+1.8V SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_O SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK# AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43 SMRCOMP SMRCOMP# +SM_RCOMP_VOH +SM_RCOMP_VOL +SM_VREF SM_PWROK SM_REXT R29 R30 DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1 DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1# DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1 DDRA_SCS0# DDRA_SCS1# DDRB_SCS0# DDRB_SCS1# DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 1 1 15 15 16 16 15 15 16 16 15 15 16 16 15 15 16 16 15 15 16 16 +SM_RCOMP_VOH 1 C54 0.01U_0402_16V7K 1 2.2U_0603_6.3V6K C55 R27 3.01K_0402_1% 1 R26 1K_0402_1% 2 2 2 1
011 = FSB667 010 = FSB800 000 = FSB1067
0 = iTPM Host Interface is enabled
1 = iTPM Host Interface is Disabled
can support disble by SW.
*(Default)
0 = Intel Management Engine Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
D
COMPENSATION
0 = DMI x 2 1 = DMI x 4 *(Default)
CFG7
Internal pull-up
1 = Intel Management Engine Crypto TLS cipher suite with confidentiality *(Default)
Internal pull-up Internal pull-up
+SM_RCOMP_VOL 1 C56 0.01U_0402_16V7K +1.8V +1.8V 2 1 2.2U_0603_6.3V6K C57 R28 1K_0402_1% 2 1
CFG10
0 = PCIe Loopback Enable 1 = Disable*(Default) 01 00 10 11 = All Z Mode Enabled = Reserved = XOR Mode Enabled = Normal Operation*(Default)
DDR CLK/ CONTROL/
CFG9
0 = Lane Reversal Enable 1 = Normal Operation *(Default)
B31 B2 M1 AY21
RSVD15 RSVD16 RSVD17 RSVD20
For Cantiga
80 Ohm
2
2
CFG[13:12]
Internal pull-up
CFG16
Internal pull-up
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled *(Default)
BG23 BF23 BH18 BF18
RSVD22 RSVD23 RSVD24 RSVD25
2 80.6_0402_1% 2 80.6_0402_1%
R31 1K_0402_1%
CFG19 Internal pull-down CFG20
Internal pull-down
0 = Normal Operation 1 = DMI Lane Reversal Enable
20mil
R32 R33 1 1 2 0_0402_5% 2 499_0402_1% 1 C58 0.1U_0402_16V4Z 2 @
*(Default) * (Default)
2
1
0 = Only PCIE or [SDVO/DP/HDMI] is operational. 1 = PCIE/[SDVO/DP/HDMI] are operating simu.
(PCIE/SDVO select)
R34 1K_0402_1% 1
CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#
CLK
CLK_DREF_96M 17 CLK_DREF_96M# 17 CLK_DREF_SSC 17 CLK_DREF_SSC# 17 CLK_MCH_3GPLL 17 CLK_MCH_3GPLL# 17
C
2
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
SM_DRAMRST# would be needed for DDR3 only
D
RSVD RSVD
C
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 6,17 CPU_BSEL0 6,17 CPU_BSEL1 6,17 CPU_BSEL2 R35 R36 R37 R39 R40 R43 R44 R45 R46 R47 +3VS R48 R49 R50
B
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+1.05VS
2 2 2 1 1 1 1 1 1 1 1 1 1
1 1K_0402_5% MCH_CLKSEL0 1 1K_0402_5% MCH_CLKSEL1 1 1K_0402_5% MCH_CLKSEL2 T14 PAD T15 PAD MCH_CFG_5 @ 2 2.21K_0402_1% MCH_CFG_6 @ 2 2.21K_0402_1% MCH_CFG_7 @ 2 2.21K_0402_1% @ 2 2.21K_0402_1% @ 2 2.21K_0402_1% @ 2 2.21K_0402_1% @ 2 2.21K_0402_1% @ 2 2.21K_0402_1% MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16
T16 PAD MCH_CFG_19 2 4.02K_0402_1% MCH_CFG_20 @ 2 4.02K_0402_1%
GRAPHICS VID
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
1
+3VS R38 1K_0402_5%
Lane reversal
1 R41 54.9_0402_1% 2 E E MCH_TSATN# 2
DMI
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
1 2 R42 1K_0402_5% 2 B B 3 1 Q7 MMBT3904_SOT23-3 C
CFG CFG
MCH_TSATN_EC# 30
+3VS
1 R52
2 PM_EXTTS#_R 10K_0402_5%
22
PM_SYNC#
R51 R53 R54 R55 R56
1 2 0_0402_5% 6,21,40 H_DPRSTP# 1 1 1 1 2 0_0402_5%
PM_SYNC#_R
15,16 PM_EXTTS# 20,25,26,30,31 PLT_RST# 5,21 H_THERMTRIP# 22,40 PM_DPRSLPVR
PM_EXTTS#_R GMCH_PWROK 2 100_0402_5% MCH_RSTIN# NB_THERMTRIP# 2 0_0402_5% DPRSLPVR 0_0402_5% 2
R29 B7 N33 P32 AT40 AT11 T20 R32 BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
Strap Pin Table
SDVO_CTRLDATA (Internal pull-down) DDPC_CTRLDATA (Internal pull-down)
0 = SDVO interface disabled *(Default) 1 = SDVO interface Port B enabled 0 = Digital display (iHDMI/DP) interface disabled *(Default) 1 = Digital display (iHDMI/DP) interface Port C enabled
+1.05VS 2
B
PM PM
GFX_VR_EN
C34
ME
Use VGATE for GMCH_PWROK
22,30,40 VGATE 22,30 ICH_PWROK 1 R58 1 R59 GMCH_PWROK 2 @ 0_0402_5% 2 0_0402_5%
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN#
AH37 AH36 AN36 AJ35 AH34 N28 M28 G36 E36 K36 H36 B12
ICH_PWROK +CL_VREF
CL_CLK0 22 CL_DATA0 22 CL_RST#0 22
R57 1K_0402_1%
Width:Spacing 12mil:12mil
1
C59 0.1U_0402_16V4Z SDVO_SCLK SDVO_SDATA SDVO_SCLK 19 SDVO_SDATA 19 CLKREQ_3GPLL# 17 MCH_ICH_SYNC# 22
2 1 2
+CL_VREF=0.355V
CL_VREF should be 0.35 V
R60 499_0402_1% +3VS SDVO_SCLK 2 1 2.2K_0402_5% R61 SDVO_SDATA 2 1 2.2K_0402_5% R62 IHDMI@
MISC
MCH_TSATN#
1
NC NC
the strap pin will impact no IHDMI SKU if mount
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 AZ_SDIN2_MCH_R AZ_BITCLK_MCH 21 AZ_RST_MCH# 21 1 R63 AZ_SDOUT_MCH 21 AZ_SYNC_MCH 21 2 33_0402_5% IHDMI@ AZ_SDIN2_MCH 21
A
A
CANTIGA ES_FCBGA1329 GM45R3@ Security Classification
HDA
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Cantiga GMCH(2/7)-GTL
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009
1
Rev 1.0 41
Sheet
9
of
5
4
3
2
1
D
D
15 DDR_A_D[0..63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
U3D
16 DDR_B_D[0..63]
U3E DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
MEMORY
C
B
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
CANTIGA ES_FCBGA1329 GM45R3@
SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE#
BD21 BG18 AT25 BB20 BD20 AY20
DDR_A_BS0 15 DDR_A_BS1 15 DDR_A_BS2 15 DDR_A_RAS# 15 DDR_A_CAS# 15 DDR_A_W E# 15
DDR_A_DM[0..7]
15
A
MEMORY
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_DQS[0..7]
15
B
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
SYSTEM
DDR_A_MA[0..14]
15
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
SYSTEM
AJ43 DDR_A_DQS#0 AT43 DDR_A_DQS#1 BA44 DDR_A_DQS#2 BD37 DDR_A_DQS#3 AY12 DDR_A_DQS#4 BD8 DDR_A_DQS#5 AU9 DDR_A_DQS#6 AM8 DDR_A_DQS#7
DDR_A_DQS#[0..7]
15
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
CANTIGA ES_FCBGA1329 GM45R3@
SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE#
BC16 BB17 BB33 AU17 BG16 BF14
DDR_B_BS0 16 DDR_B_BS1 16 DDR_B_BS2 16 DDR_B_RAS# 16 DDR_B_CAS# 16 DDR_B_W E# 16
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
DDR_B_DM[0..7]
16
DDR_B_DQS[0..7]
16
C
AL46 DDR_B_DQS#0 AV47 DDR_B_DQS#1 BH41 DDR_B_DQS#2 BH37 DDR_B_DQS#3 BG9 DDR_B_DQS#4 BC2 DDR_B_DQS#5 AT2 DDR_B_DQS#6 AN5 DDR_B_DQS#7 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_DQS#[0..7]
16
DDR_B_MA[0..14]
16
DDR
DDR
B
A
A
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Cantiga GMCH(3/7)-GTL
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009 Sheet
1
Rev 1.0 41
10
of
5
4
3
2
1
+3VS
U3C
within 500 mils
1 R64 1 R66 1 R67 1 R68
D
L_DDC_DATA
LCTLA_CLK 2 L32 18 NB_INVT_PW M 10K_0402_5% G32 30 UMA_ENBKL LCTLB_DATA LCTLA_CLK 2 M32 10K_0402_5% LCTLB_DATA M33 UMA_LCD_EDID_CLK UMA_LCD_EDID_CLK K33 2 18 UMA_LCD_EDID_CLK 2.2K_0402_5% UMA_LCD_EDID_DATAJ33 18 UMA_LCD_EDID_DATA UMA_LCD_EDID_DATA UMA_ENVDD 2 M29 18 UMA_ENVDD 2.2K_0402_5% R69 1 2 LVDS_IBG C44 2.37K_0402_1% Spacing=20mil B43 E37 E38 18 UMA_LCD_TXCLK18 UMA_LCD_TXCLK+
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
PEG_COMP 1 R65
2 49.9_0402_1%
+1.05VS
10mils
D
0 = LFP Disable *(Default) 1 = LFP Card Present; PCIE disable
C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37
LVDS LVDS
18 UMA_LCD_TXOUT018 UMA_LCD_TXOUT118 UMA_LCD_TXOUT218 UMA_LCD_TXOUT0+ 18 UMA_LCD_TXOUT1+ 18 UMA_LCD_TXOUT2+
GRAPHICS
PCIE_GTX_C_MRX_P3
1 2 R505 IHDMI@ 0_0402_5%
PCIE_GTX_C_MRX_HDMI_P3 19
C
PCI-EXPRESS
C
1 R70 1 R71 1 R72
2 TV_COMPS 75_0402_1% 2 TV_LUMA 75_0402_1% 2 TV_CRMA 75_0402_1%
TV_COMPS TV_LUMA TV_CRMA
F25 H25 K25 H24
TVA_DAC TVB_DAC TVC_DAC
PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3
C61 1 C63 1
C60 1 2 IHDMI@ 0.1U_0402_16V7K C62 1 2 IHDMI@ 0.1U_0402_16V7K
2 IHDMI@ 0.1U_0402_16V7K 2 IHDMI@ 0.1U_0402_16V7K
PCIE_MTX_C_GRX_HDMI_N0 PCIE_MTX_C_GRX_HDMI_N1 PCIE_MTX_C_GRX_HDMI_N2 PCIE_MTX_C_GRX_HDMI_N3
19 19 19 19
TV TV
TV_RTN
C31 E32 1 1 1
UMA_CRT_B 2 150_0402_1% UMA_CRT_G 2 150_0402_1% UMA_CRT_R 2 150_0402_1%
TV_DCONSEL_0 TV_DCONSEL_1
R73 R74 R75
18 18 18
UMA_CRT_B UMA_CRT_G UMA_CRT_R
UMA_CRT_B UMA_CRT_G UMA_CRT_R
E28 G28 J28 G29
CRT_BLUE CRT_GREEN
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3
C65 1 C67 1
C64 1 2 IHDMI@ 0.1U_0402_16V7K C66 1 IHDMI@ 0.1U_0402_16V7K 2
2 IHDMI@ 0.1U_0402_16V7K 2 IHDMI@ 0.1U_0402_16V7K
PCIE_MTX_C_GRX_HDMI_P0 PCIE_MTX_C_GRX_HDMI_P1 PCIE_MTX_C_GRX_HDMI_P2 PCIE_MTX_C_GRX_HDMI_P3
19 19 19 19
VGA VGA
CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
+3VS
R76
B
1 1
R77
UMA_CRT_CLK 2 4.7K_0402_5% UMA_CRT_DATA 2 4.7K_0402_5%
18 UMA_CRT_CLK 18 UMA_CRT_DATA 18 UMA_CRT_HSYNC 2 R78 18 UMA_CRT_VSYNC
UMA_CRT_CLK UMA_CRT_DATA UMA_CRT_HSYNC 1UMA_CRT_IREF 1.02K_0402_1%
H32 J32 J29 E29
B
UMA_CRT_VSYNC L29
CANTIGA ES_FCBGA1329 GM45R3@
A
A
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Cantiga GMCH(4/7)-GTL
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009 Sheet
1
Rev 1.0 41
11
of
5
4
3
2
1
U3F
DDR2,667MHz,2600mA DDR2,800MHz,3000mA
+1.8V
+1.05VS
Int. Graphic
VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA Intel Management Engine Link:508.12mA
DDR PWR
10U_0805_10V4Z
1
D
1 + C68 220U_D2_4VM_R15 @ 2 1 C69 2 C70 2 1 C71 2 1
+ C78 220U_6.3V_M 2
10U_0805_10V4Z
0.1U_0402_16V4Z
GFX NCTF
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35
+1.05VS NB 1 + C72 C73 2 220U_6.3V_M
Core,Intel Management Engine Link
0.22U_0402_10V4Z 1 C74 2 C75 1 C76 1 C77 2 0.1U_0402_16V4Z 1 AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33
U3G VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
D
C
Could be NC for DDR2 Board.
BA36 BB24 BD16 BB21 AW16 AW13 AT13
VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC
POWER
VCC
8700mA
For layout placement un-mound C123 and mound C84
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
Int. Graphic
+1.05VS 220U_D2_4VM_R15 1 + C83 2 2 220U_D2_4VM_R15 C84 @ C85 1 C86 10U_0805_10V4Z 1 C87 1 C88 2 0.47U_0603_10V7K 1 C89 1 C90 2 0.1U_0402_16V4Z 1
1 +
POWER
2 2 2 10U_0805_10V4Z 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm
For layout issue to separate 220u*2 to +1.05VS
B
VCC
NCTF
VCC SM LF
VCC SM
220U_6.3V_M 1 +
VCC CORE VCC CORE
2 2 2 10U_0805_10V4Z 0.22U_0402_10V4Z
Intel: VCC -- 220U*2, ESR 12mOhm
AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32
VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35
+1.05VS
C
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
VCC GFX
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 AV44 VCCSM_LF1 BA37 VCCSM_LF2 AM40 VCCSM_LF3 AV21 VCCSM_LF4 AY5 VCCSM_LF5 AM10 VCCSM_LF6 BB13 VCCSM_LF7 1 C91 0.1U_0402_16V4Z 1 C93 1 0.22U_0603_10V7K 1 C95 1 0.47U_0603_10V7K 1 C96 1U_0402_6.3V4Z 2 C97 1U_0402_6.3V4Z 1 CANTIGA ES_FCBGA1329 GM45R3@
B
PAD T3 PAD T4
AJ14 AH14
VCC_AXG_SENSE VSS_AXG_SENSE
2
A
C92 2 0.1U_0402_16V4Z 2
C94 2 0.22U_0603_10V7K 2
2
A
CANTIGA ES_FCBGA1329 GM45R3@
Security Classification Issued Date 2009/07/28
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Cantiga GMCH(5/7)-GTL
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009
1
Rev 1.0 41
Sheet
12
of
5
4
3
2
1
+3VS_TVCRT_DACBG
CRT
+3VS_TVCRT_DAC
+3VS_TVCRT_DACBG
TV
+3VS
+3VS_TVCRT_DACBG
R80 1 0.01U_0402_25V4Z 2 0_0603_5% 1 1 C99 C100 2 C101
0.01U_0402_25V4Z 1 1 C102 2
Pin A25 GNDtoB25
R79 2 1 BLM18PG181SN1D_0603 1 C98 10U_0805_10V4Z
U3H
2 0.1U_0402_16V4Z +1.05VS R81
D
Pin B27
FSB=1067Mhz,852mA 73mA
+3VS_TVCRT_DAC B27 A26 VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1 1 1 1 1
+1.05VS
2 0.1U_0402_16V4Z +1.05VS R82
AGTL+
1 C104 C105 C106 C107 0.47U_0603_10V7K 2.2U_0603_6.3V6K 4.7U_0805_10V4Z 4.7U_0805_10V4Z 2 2 2 2 + C103 220U_D2_4VM_R15 2
D
2
+1.05VS_DPLLA
+1.05VS_DPLLB +3VS_TVCRT_DACBG A25 B25 VCCA_DAC_BG VSSA_DAC_BG
+1.05VS_DPLLA +1.05VS_DPLLB
F47 L48 AD1 AE1 J48 J47 AD48
64.8mA VCCA_DPLLA 64.8mA VCCA_DPLLB
VCCA_HPLL 24mA VCCA_MPLL 139.2mA
+1.05VS R83
+1.05VS_AHPLL
+1.05VS R84
+1.05VS_MPLL +1.8V_TXLVDS
+1.05VS_AHPLL
C115 4.7U_0805_10V4Z
C116 2 0.1U_0402_16V4Z 2
2
C118 1000P_0402_50V7K
+1.8V_TXLVDS
VCCA_LVDS VSSA_LVDS
Pin AD1
Pin J48 GND to J47
+1.5VS_PEG_BG
A PEG A LVDS
2 1 KC FBM-L11-160808-121LMT 0603 1 1
2 1 MBK2012121YZF_0805 1 C117 1 2 C114 R85 0.5_0805_1% 10U_0805_10V4Z Pin AE12 0.1U_0402_16V4Z
LVDS
1
+1.05VS_MPLL
13.2mA
PLL
VTT
10U_0805_10V4Z 2 1 10U_FLC-453232-100K_0.25A_10% 1 1 1 C108 + 220U_B2_2.5VM C110 C111 @ Pin 2 2 2 0.1U_0402_16V4Z
F47
10U_0805_10V4Z 2 1 10U_FLC-453232-100K_0.25A_10% 1 1 1 C109 + 220U_B2_2.5VM C112 C113 @ Pin 2 2 2 0.1U_0402_16V4Z
CRT
5mA
Intel: VTT 270U*1 ESR 12mOhm
L48
414uA
VCCA_PEG_BG
+1.05VS_AXF
NB I/O
2 C119 1U_0402_6.3V4Z
PCIe&DMI
+1.5VS R87
+1.5VS_PEG_BG
+1.05VS_PEGPLL 1
50mA
+1.05VS_PEGPLL AA48 VCCA_PEG_PLL
+1.05VS R86 1 2 1 0_0603_5% C120 10U_0805_10V4Z 2 @
1 2 0_0603_5% C122 0.1U_0402_16V4Z
1
1
C121 2 0.1U_0402_16V4Z
667MTs,480mA 800MTs,720mA
+1.05VS R88 1 2 1 0_0805_5% C123 220U_D2_4VM_R15 @ + 2
Pin B22
+1.8V_SM_CK
C
Pin AD48
2
PCIe&DMI Pin AA48
DDR2
+1.05VS_A_SM
C124
C125
C126
AXF
4.7U_0805_10V4Z 1 1
1
2 2 2 10U_0805_10V4Z 1U_0402_6.3V4Z
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9
POWER
Host Interface I/O and HSIO DDR2
A SM
321.35mA
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
B22 B21 A21
+1.05VS_AXF
1 C127 0.1U_0402_16V4Z R90 1_0805_1% C129 1 2
+1.8V R89 1 2 0_0805_5% 1 C128 10U_0805_10V4Z 2 @
C
Pin AR20 DDR2
DDR2,667MHz,119.85mA DDR2,800MHz,124mA
2
Pin BF21
+1.8V_SM_CK +1.8V_TXLVDS
667MTs,24mA 800MTs,26mA
+1.05VS_A_SM_CK AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8
SM CK
+1.05VS R92 1 2 0_0603_5% 1 C132 10U_0805_10V4Z +3VS_TVCRT_DAC
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
BF21 BH20 BG20 BF20
10U_0805_10V4Z
LVDS
1 K47 +1.8V_TXLVDS 2 C130 1000P_0402_50V7K
0.1U_0402_16V4Z 1 1 C133 @ @ C134 2
118.8mA
+1.8V R91 1 2 1 0_0603_5% C131 10U_0805_10V4Z
A CK
VCC_TX_LVDS
2
2
2 2.2U_0603_6.3V4Z
105.3mA
VCC_HV_1 VCC_HV_2 VCC_HV_3 C35 B35 A35 +3VS
Pin K47
D3 2 R93 1 1 2 +1.05VS 10_0603_5% CH751H-40PT_SOD323-2 C137 0.1U_0402_16V4Z
R94 1 2 0_0402_5% 1 IHDMI@ C138 0.1U_0402_16V4Z IHDMI@ 2
0.01U_0402_25V4Z 1 1 C135 0.1U_0402_16V4Z
B
HDMI's HDA
HV
TV
+1.5VS
+1.5VS_HDA
Pin AP28
C136 2 2
1782mA
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 V48 U48 V47 U47 U46 +1.05VS
+3VS 1
PEG
Pin B24
Pin A32
79mA
2
Pin C35
B
HDA
DMI
+1.5VS R95 2 1 0_0603_5% 1 C139 @ 10U_0805_10V4Z
+1.5VS_TVDAC 0.1U_0402_16V4Z 1 1 C140 C141
+1.5VS
+1.5VS_QDAC +1.5VS_HDA A32
TV
R96 TV 2 1 0.01U_0402_25V4Z 0_0603_5% 1 1 C142 0.1U_0402_16V4Z C143
50mA
VCC_HDA
TV
+3VS_TVCRT_DAC
B24 A24
VCCA_TV_DAC_1 VCCA_TV_DAC_2
456mA
VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4 AH48 AF48 AH47 AG47 +1.05VS +1.05VS
PCIe&DMI
10U_0805_10V4Z 1 C144 C145 2
+1.5VS_QDAC +1.05VS_DHPLL
L28 AF1 AA47 M38 L37
500uA VCCD_QDAC 157.2mA
VCCD_HPLL
D TV/CRT
2
2 2 0.01U_0402_25V4Z
Pin M25
Pin L282 2
35mA
+1.5VS_TVDAC M25 VCCD_TVDAC
1
2 10U_0805_10V4Z
Pin V48
+1.05VS R98 1 2 0_0402_5%
+1.05VS_DHPLL
50mA
VTTLF
+1.05VS_PEGPLL
VCCD_PEG_PLL
60.31mA
VTTLF1 VTTLF2 VTTLF3
VTTLF1 A8 VTTLF2 L1 AB2 VTTLF3 1 1 1
+1.05VS 1
PCIe&DMI
LVDS
2 +1.8V_LVDS 1
C150 0.1U_0402_16V4Z
VCCD_LVDS_1 VCCD_LVDS_2
Pin AF1
C147 C148 C149 0.47U_0603_10V7K 0.47U_0603_10V7K 0.47U_0603_10V7K 2 2 2
C151 0.1U_0402_16V4Z
CANTIGA ES_FCBGA1329 GM45R3@
2
Pin AH48
+1.05VS
A
L1 2 1 BLM18PG121SN1D_0603 R100 1_0805_1%
PCIe&DMI
+1.05VS_PEGPLL 0.1U_0402_16V4Z 1 C152 2 R99 2 1 0_0603_5%
+1.8V_LVDS
A
LVDS
1
+1.8V
2
1 C154 10U_0805_10V4Z
C153 1U_0402_6.3V4Z 2
Pin AA47
Pin M38
Security Classification Issued Date 2009/07/28
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Crestline GMCH (6/7)-VCC
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009
1
Rev 1.0 41
Sheet
13
of
5
4
3
2
1
U3I AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6 BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
U3J VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_235 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 A3
D
D
VSS
VSS
C
C
B
VSS NCTF
B
VSS SCB
CANTIGA ES_FCBGA1329 GM45R3@
NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42
E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
A
CANTIGA ES_FCBGA1329 GM45R3@
NC
A
Security Classification Issued Date 2009/07/28
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Cantiga GMCH(1/7)-GTL
Size Date: Document Number
NBWAA LA5821P M/B
Monday, August 10, 2009 Sheet
1
Rev 1.0 41
14
of
5
4
3
2
1
JDDRL +DIMM_VREF
@
1
C155 2.2U_0603_6.3V6K C156 0.1U_0402_16V4Z
1
DDR_A_D4 DDR_A_D1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D14 DDR_A_DQS#1 DDR_A_DQS1
2
2
+1.8V
1
D
R101 1K_0402_1%
20mils
+DIMM_VREF
DDR_A_D9 DDR_A_D15
R102 1K_0402_1% DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D29 DDR_A_D24 DDR_A_DM3 DDR_A_D26 DDR_A_D27
C
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1
0.1U_0402_16V4Z
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_A_D5 DDR_A_D0 DDR_A_DM0 DDR_A_D6 DDR_A_D7 DDR_A_D13 DDR_A_D12 DDR_A_DM1 DDRA_CLK0 9 DDRA_CLK0# 9 2.2U_0603_6.3V6K DDR_A_D11 DDR_A_D10 +1.8V
DDR_A_DQS#[0..7] DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..14]
10 10 10 10 10
Layout Note: Place near JP3
2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D
1 1
C166 + C157 220U_Y_4VM @ 2 4.4
2
1
1
1
1
1
1
1
1
C158 C158
C159
C160
C161
C162
C163
C164
C165 C165
2
2
2
2
2
2
2
2
2
2
DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D23 DDR_A_D22 DDR_A_D28 DDR_A_D25 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D31 DDR_A_D30 DDRA_CKE1 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDRA_SCS0# DDRA_ODT0 DDR_A_MA13 DDR_A_BS1 10 DDR_A_RAS# 10 DDRA_SCS0# 9 DDRA_ODT0 9 DDRA_CKE1 9 +1.8V PM_EXTTS# 9,16
+0.9VS
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
1
1
1
1
1
1
C
9 10
DDRA_CKE0 +1.8V DDR_A_BS2
DDRA_CKE0 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS0 DDR_A_W E# DDR_A_CAS# DDRA_SCS1# DDRA_ODT1 DDR_A_D37 DDR_A_D36 DDR_A_DQS#4 DDR_A_DQS4
2
C167
2
C168
2
C169
2
C170
2
C171
2
C172
2
C173
2
C174
2
C175
2
C176
2
C177
2
C178
2
C179
10 10
DDR_A_BS0 DDR_A_W E#
10 DDR_A_CAS# 9 DDRA_SCS1# 9 DDRA_ODT1
Layout Note: Place these resistor closely JP3,all trace length Max=1.5"
+0.9VS RP1 RP2
DDR_A_D39 DDR_A_D38 DDR_A_DM4 DDR_A_D34 DDR_A_D33 DDR_A_D45 DDR_A_D43 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D47 DDR_A_D42 DDR_A_D52 DDR_A_D53 DDRA_CLK1 9 DDRA_CLK1# 9 DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63
DDR_A_MA8 DDR_A_BS2 DDR_A_MA12 DDR_A_MA1
8 7 6 5
1 2 3 4
8 7 6 5
1 2 3 4
DDR_A_MA13 DDRA_ODT0 DDR_A_RAS# DDRA_SCS0#
56_0804_8P4R_5% RP3 DDR_A_MA14 DDR_A_MA11 DDR_A_MA6 DDR_A_MA7
56_0804_8P4R_5% RP4
B
B
DDR_A_D35 DDR_A_D32 DDR_A_D40 DDR_A_D44 DDR_A_DM5 DDR_A_D41 DDR_A_D46 DDR_A_D49 DDR_A_D48
8 7 6 5
1 2 3 4
8 7 6 5
1 2 3 4
DDR_A_MA5 DDR_A_MA3 DDR_A_MA9 DDR_A_MA10
56_0804_8P4R_5% RP5 DDRA_ODT1 DDR_A_CAS# DDR_A_W E# DDR_A_BS0
56_0804_8P4R_5% RP12 DDR_A_MA4 DDR_A_MA2 DDR_A_BS1 DDR_A_MA0
8 7 6 5
1 2 3 4
1 2 3 4
8 7 6 5
56_0804_8P4R_5% DDRA_SCS1#R480 1 DDRA_CKE0 R481 1 DDRA_CKE1 R482 1
56_0804_8P4R_5% 56_0402_5% 56_0402_5% 56_0402_5%
DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D54 DDR_A_D50 DDR_A_D61 DDR_A_D60 DDR_A_DM7 DDR_A_D59 DDR_A_D58
A
2 2 2
SUPPORT_PAD SUPPORT_PAD
A
16,17,22,25 PM_SMBDATA 16,17,22,25 PM_SMBCLK +3VS
SO-DIMM A REVERSE
Top side
5
203 204
C180
FOX_AS0A426-M2RN-7F
Security Classification
Issued Date
Compal Secret Data
2009/07/28
Deciphered Date
Compal Electronics, Inc.
2010/07/28
Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT