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Compal Confidential
2 2
ISKAE LA-3661P Schematics Document
Intel Yonah/Merom with 945GM/943GML/940GML+ DDRII + ICH7M
3
2006-12-22 REV: 0.1
3
4
4
Security Classification Issued Date 2006/10/31
Compal Secret Data
Deciphered Date 2009/11/13
Title
Compal Electronics, Inc.
Cover Sheet
Size Date: Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
ISKAE M/B LA-3661P
Tuesday, December 26, 2006
E
Rev 0.1 of 37
Sheet
1
A
B
C
D
E
Compal confidential
Model : ISKAE File Name : LA-3661P Fan Control
page 4
Yonah/Merom
uFCPGA-479 CPU
page 4,5,6
Thermal Sensor ADM1032ARM
page 4
Clock Generator
ICS9LPRS325AKLFT
page 14
1
NAPA Platform
1
FSB LCD Conn.
page 15
H_A#(3..31) H_D#(0..63)
CRT & TV-out
page 15
533/667MHz
NVIDIA NB7P-GS NB7M-SE with 64/128/256/512 MB VRAM
VGA/B Conn.
page 16
Intel Calistoga GMCH 945PM/GM
PCI-Express x16 PCBGA 1466
page 7,8,9,10,11
DDR2-533/667
Dual Channel
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
page 12, 13
PCI-E BUS
(port 3)
2
2.5GHz
DMI x 4 10/100/1000 LAN
RTL8111B/RTL8101E
page 22
USB1.1 Finger page 24 Print
USB 3.3V 480MHz
USB port 7
USB Camera
page 24
Blue Tooth
page 24
USB x 1 conn x 2 26 page
USB port 2,4
USB/B conn
page 24
USB port 6
USB port 5
USB port 0, 1
2
New Card Slot
page 23
USB port 3
Intel ICH7-M
mBGA-652
page 16,17,18 3.3V 33 MHz
Azalia
3.3V 24.576MHz/48Mhz
MDC1.5 Audio Codec
ALC861
page 22
page 24
Mini Express Card RJ45/11 CONN
page 22 page 23
SATAI/II PATA
1.5GHz/3G
AMP & Audio Jack & Int-MIC
SPK/JP-AMP: APA2056
page 23
PCI BUS
3.3V ATA-100
CardBus Controller
TI PCI8412
page 19,20
3
SATA 0
SATA HDD Connector
page 16
3.3V 33 MHz
LPC BUS
SATA 1
SATA HDD Connector
page 16
3
Slot 0
page 20
1394 port
page 19
5in1 Slot
page 19
PATA Master
PATA ODD Connector
page 16
ISKAE Sub-board SW/B LS-3482P Rev1 CRT/B LS-3483P Rev1
LED
page 26
ENE KB910
page 25
RTC CKT.
page 17
Power On/Off CKT.
4
Touch Pad
page 24
Int.KBD
page 26
BIOS
page 25
page 26
USB/B LS-3484P Rev1
4
DC/DC Interface CKT.
page 27
Security Classification
Compal Secret Data
2006/10/31 Deciphered Date 2009/11/13
Title
Compal Electronics, Inc.
Block Diagram
Size Date: Document Number
Power Circuit DC/DC
Page 28~34
A B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
ISKAE M/B LA-3661P
Tuesday, December 26, 2006
E
Rev 0.1 of 37
Sheet
2
A
B
C
D
E
Voltage Rails
Power Plane VIN B+
1
Board ID / SKU ID Table for AD channel
Description Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU 0.9V switched power rail for DDR terminator 1.05V switched power rail 1.5V switched power rail 1.8V power rail for DDR 1.8V switched power rail 2.5V switched power rail 3.3V always on power rail 3.3V switched power rail 5V always on power rail 5V switched power rail +VSB always on power rail RTC power S1 N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON S3 N/A N/A O FF O FF O FF O FF ON O FF O FF ON O FF ON O FF ON ON S5 N/A N/A O FF O FF O FF O FF O FF O FF O FF ON* O FF ON* O FF ON* ON
Vcc Ra
Board ID
+CPU_CORE +0.9VS +VCCP +1.5VS +1.8V +1.8VS +2.5VS +3VALW +3VS +5VALW +5VS +VSB +RTCVCC
0 1 2 3 4 5 6 7
3.3V +/- 5% 100K +/- 5% Rb 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC
V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V
V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V
V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V
1
BOARD ID Table
Board ID 0 1 2 3 4 5 6 7 PCB Revision 0.1
BTO Option Table
BOM Structure NEWCARD@ 100M@ LAN 1000M@ WLAN KS@ GM@ NB PM@ BT BT@ MIC MIC@ CIR@ CIR FINGER PRINT FP@ 5IN1 CAMERA PCMCIA MDC 5IN1@ CAMERA@ PCMCIA@ MDC@ BTO Item NEW CARD
2
2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
DEVICE
1394 CARD BUS 5IN1
SKU ID Table
IDSEL #
AD20 AD20 AD20
PCI Device ID
D0 D4 D4
REQ/GNT #
2 2 2
PIRQ
A ,B,C A ,B,C A ,B,C
KB910 I2C / SMBUS ADDRESSING
DEVICE
3
SKU ID 0 1 2 3 4 5 6 7
SKU 10 (10E) 10C 10G 10GC 10J (10EJ) 10CJ 10GJ 10GCJ
HEX
A0H 16H 98H
ADDRESS
3
SM1 24C16 SM1 SMART BATTERY SM2 ADM0132 CPU THERMAL MONITOR
1010000Xb 0001011Xb 1001100Xb
ICH7-M SM Bus address
DEVICE
DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)
HEX
A0 A4 D2
ADDRESS
10100000 10100100 11010010
4
4
Security Classification Issued Date 2006/10/31
Compal Secret Data
Deciphered Date 2009/11/13
Title
Compal Electronics, Inc.
Notes
Size Date: Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
ISKAE M/B LA-3661P
Tuesday, December 26, 2006
E
Rev 0.1 of 37
Sheet
3
5
4
3
2
1
Place close to CPU within 500mil
7 H_A#[3..31] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 7 7 H_ADSTB#0 H_ADSTB#1 H_ADSTB#0 H_ADSTB#1 J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 K3 H2 K2 J3 L5 L2 V4 JP1A A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# H_D#[0..63] 7 +VCCP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 XDP_TDI XDP_TMS 1 R88 1 R84
YONAH
D
ADDR GROUP
DATA GROUP
7
H_REQ#[0..4]
REQ0# REQ1# REQ2# REQ3# REQ4# ADSTB0# ADSTB1#
P
C
14 CLK_CPU_BCLK 14 CLK_CPU_BCLK#
CLK_CPU_BCLK A22 CLK_CPU_BCLK# A21
BCLK0 BCLK1
HOST CLK
R100 +VCCP 1 2 56_0402_5%
7 7 7 7 7 7 7 7 7 7
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM# H_LOCK# H_RESET#
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRD Y# H_HIT# H_HITM# H_IERR# H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
H1 E2 G5 F1 H5 F21 G6 E4 D20 H4 B1 F3 F4 G3 G2
ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET# RS0# RS1# RS2# TRDY#
CONTROL
7
H_RS#[0..2]
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 J26 M26 V23 AC20 H23 M24 W24 AD23 G22 N25 Y25 AE24
2 56_0402_5% 2 56_0402_5%
D
Thermal Sensor ADM1032ARM
+3VS
XDP_BPM#5 XDP_TRST# XDP_TCK
1 R83 1 R90
2 56_0402_5% 2 56_0402_5% 1 R102 2 56_0402_5%
1 C1 0.1U_0402_16V4Z
1 C2 2200P_0402_50V7K U1 2 H_THERMDA H_THERMDC 15,26 EC_SMB_CK2 15,26 EC_SMB_DA2 2 3 8 7 D+ DSCLK SDATA
2
VDD1 ALERT# THERM# GND
1 6 4 5
ADM1032ARM_RM8 +5VS
4
1
D37
1N4148_SOT23
1 R439 2 8.2K_0402_5%
+FAN1_VOUT
2
0.1U_0402_16V4Z
3
R594 2 1 10K_0402_5%
G
6
0 -
7
R674 2 1 100_0402_5%
C820 1 2
FAN1_ON 2 B E
Q50 FMMT619_SOT23 D36
1
26
EN_DFAN1
PU5B 5 +
1SS355_SOD323
1
P@ LM358DT_SO8
8
C
C
JP2 1 2 3 4 5 1 1 2 3 GND GND
2
+3VS
1
2 R440 10K_0402_5%
26 FAN_SPEED1
1 C632 @1000P_0402_50V7K 2
ACES_85205-03001 C633 @1000P_0402_50V7K
2
7
H_TRDY#
B
AD4 AD3 AD1 AC4 18 DBRESET# 7 H_DBSY# 17 H_DPSLP# 17,36 H_DPRSTP# 7 H_DPWR# R98 +VCCP 1 2 56_0402_5% 17 H_PWRGOOD 7 H_CPUSLP# R85 @ 1K_0402_5% 2 2 R103 51_0402_5% DBRESET# H_DBSY# H_DPSLP# H_DPRSTP# H_DPWR# C20 E1 B5 E5 D24 AC2 XDP_BPM#5 AC1 H_PROCHOT# D21
BPM0# BPM1# BPM2# BPM3# DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT# PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST# THERMDA THERMDC THERMTRIP#
DINV0# DINV1# DINV2# DINV3# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
7 7 7 7
B
H_DSTBN#[0..3] 7
H_DSTBP#[0..3] 7 H_FERR#
Placement near to ICH7
2 C341 1 @180P_0402_50V8J
MISC
1 1
H_PW RGOOD D6 H_CPUSLP# D7 XDP_TCK AC5 XDP_TDI AA6 AB3 TEST1 C26 TEST2 D25 XDP_TMS AB5 XDP_TRST# AB6 H_THERMDA A24 H_THERMDC A25 H_THERMTRIP# C7
THERMAL DIODE
LEGACY CPU
A20M# FERR# IGNNE# INIT# LINT0 LINT1
A6 A5 C4 B3 C6 B4 D5 A3
H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI H_STPCLK# H_SMI#
H_A20M# 17 H_FERR# 17 H_IGNNE# 17 H_INIT# 17 H_INTR 17 H_NMI 17 H_STPCLK# 17 H_SMI# 17
H_SMI# H_INIT# H_NMI H_A20M# H_INTR H_IGNNE# H_STPCLK#
2 2 2 2 2 2 2 2 2
STPCLK# SMI#
7,17 H_THERMTRIP#
H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil
A
FOX_PZ47903-2741-42_YONAH H_PW RGOOD H_CPUSLP#
1 C403 @180P_0402_50V8J 1 C180 @180P_0402_50V8J 1 C387 @180P_0402_50V8J 1 C225 @180P_0402_50V8J 1 C394 @180P_0402_50V8J 1 C176 @180P_0402_50V8J 1 C397 @180P_0402_50V8J 1 C402 @180P_0402_50V8J 1 C178 @180P_0402_50V8J
A
Placement near to CPU side
Security Classification Issued Date 2006/10/31
Compal Secret Data
Deciphered Date 2009/11/13
Title Size Date:
Compal Electronics, Inc.
Yonah CPU in mFCPGA479
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAE M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 4 of 37
Sheet
5
4
3
2
1
D
+VCCP 1
+V_CPU_GTLREF 2
R138 1K_0402_1%
+CPU_CORE R137 1 R136 VCCSENSE 2 100_0402_1% VSSSENSE 2 100_0402_1%
Length match within 25 mils The trace width 18 mils space 36 VCCSENSE 7 mils 36 VSSSENSE
+1.5VS +VCCP 1 C406 10U_0805_10V4Z 1 C408 0.01U_0402_16V7K
+CPU_CORE JP1B VCCSENSE VSSSENSE AF7 AE7 B26 K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21 H_PSI# CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 AE6 AD6 AF5 AE5 AF4 AE3 AF2 AE2 AD26 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 COMP0 COMP1 COMP2 COMP3 B22 B23 C21 R26 U26 U1 V1 E7 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17 D2 F6 D3 C1 AF1 D22 C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25 VCCSENSE VSSSENSE VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP PSI# VID0 VID1 VID2 VID3 VID4 VID5 VID6 GTLREF BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1 AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7 JP1C VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21
D
1
R135 2K_0402_1% 2
1
YONAH
2
2
36 36 36 36 36 36 36 36
H_PSI# CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 +V_CPU_GTLREF
C
POWER, GROUNG, RESERVED SIGNALS AND NC
Close to CPU pin AD26 within 500mils.
Close to CPU pin within 500mils.
YONAH
C
CPU_BSEL 133 166
CPU_BSEL2 0 0
CPU_BSEL1 0
CPU_BSEL0 1 1
POWER, GROUND
1
14 14 14
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
+CPU_CORE
R328 2
R329 2
R105 2
R104 2
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal.
1
1
1
B
27.4_0402_1% 27.4_0402_1% 54.9_0402_1% 54.9_0402_1%
1
B
FOX_PZ47903-2741-42_YONAH
FOX_PZ47903-2741-42_YONAH
A
A
Security Classification Issued Date 2006/10/31
Compal Secret Data
Deciphered Date 2009/11/13
Title Size Date:
Compal Electronics, Inc.
Yonah CPU in mFCPGA479
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAE M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 5 of 37
Sheet
5
4
3
2
1
D
+CPU_CORE
D
1 C18 10U_0805_6.3V6M
1 C19 10U_0805_6.3V6M
1 C20 10U_0805_6.3V6M
1 C21 10U_0805_6.3V6M
1 C22 10U_0805_6.3V6M
1 C23 10U_0805_6.3V6M
1 C24 10U_0805_6.3V6M
1 C25 10U_0805_6.3V6M
2
2
2
2
2
2
2
2
+CPU_CORE
1 C26 10U_0805_6.3V6M
1 C27 10U_0805_6.3V6M
1 C28 10U_0805_6.3V6M
1 C29 10U_0805_6.3V6M
1 C30 10U_0805_6.3V6M
1 C31 10U_0805_6.3V6M
1 C32 10U_0805_6.3V6M
1 C33 10U_0805_6.3V6M
2
2
2
2
2
2
2
2
+CPU_CORE
1 C34 10U_0805_6.3V6M
1 C35 10U_0805_6.3V6M
1 C36 10U_0805_6.3V6M
1 C37 10U_0805_6.3V6M
1 C38 10U_0805_6.3V6M
1 C39 10U_0805_6.3V6M
1 C40 10U_0805_6.3V6M
1 C41 10U_0805_6.3V6M
2
2
2
2
2
2
2
2
C
C
+CPU_CORE
1 C42 10U_0805_6.3V6M
1 C43 10U_0805_6.3V6M
1 C44 10U_0805_6.3V6M
1 C45 10U_0805_6.3V6M
1 C46 10U_0805_6.3V6M
1 C47 10U_0805_6.3V6M
1 C48 10U_0805_6.3V6M
1 C49 10U_0805_6.3V6M
2
2
2
2
2
2
2
2
Mid Frequence Decoupling 10uF X32 PCS
+CPU_CORE @ 330U_D2E_2.5VM_R9 @ 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
South Side Secondary
1 C50 + 2
B
North Side Secondary
1 C51 + 2 C52 1 + 2 C53 1 + 2 C54 1 + 2 C55 1 + 2
ESR <= 1.5m ohm Capacitor > 1980uF
B
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
330uF ESR 9m ohm X 6 PCS
+VCCP
330U_D2E_2.5VM_R9
1 C56 + 2
1 C57 0.1U_0402_16V4Z
1 C58 0.1U_0402_16V4Z
1 C59 0.1U_0402_16V4Z
1 C60 0.1U_0402_16V4Z
1 C61 0.1U_0402_16V4Z
1 C62 0.1U_0402_16V4Z
Place these inside socket cavity on Bottom layer (North side Secondary)
2
2
2
2
2
2
A
A
Security Classification Issued Date 2006/10/31
Compal Secret Data
Deciphered Date 2009/11/13
Title Size Date:
Compal Electronics, Inc.
CPU Bypass capacitors
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAE M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 6 of 37
Sheet
5
4
3
2
1
U6B 4 H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 U6A HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# HVREF0 HVREF1 HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#[3..31] 4 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 DMI_TXP3 DMI_TXP2 DMI_TXP1 DMI_TXP0 DMI_TXN3 DMI_TXN2 DMI_TXN1 DMI_TXN0 DMI_RXP3 DMI_RXP2 DMI_RXP1 DMI_RXP0 DMI_RXN3 DMI_RXN2 DMI_RXN1 DMI_RXN0 DMI_TXP3 DMI_TXP2 DMI_TXP1 DMI_TXP0 DMI_TXN3 DMI_TXN2 DMI_TXN1 DMI_TXN0 DMI_RXP3 DMI_RXP2 DMI_RXP1 DMI_RXP0 DMI_RXN3 DMI_RXN2 DMI_RXN1 DMI_RXN0 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 AE37 AF41 AG37 AH41 AC37 AE41 AF37 AG41 AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMITXP0 DMITXP1 DMITXP2 DMITXP3 SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CS0# SM_CS1# SM_CS2# SM_CS3# SM_OCDCOMP0 SM_OCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 SM_RCOMPN SM_RCOMPP SM_VREF0 SM_VREF1 PM_BMBUSY# PM_EXTTS0# PM_EXTTS1# PM_THERMTRIP# PWROK RSTIN# ICH_SYNC# RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 G_CLKP G_CLKN K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 MCH_CLKSEL0 14 MCH_CLKSEL1 14 MCH_CLKSEL2 14
DMI
Lane Reversal Polarity Reversal
D
CFG
Refer Strap Pin Table
CFG19
D
CLK
12 12 13 13 12 12 13 13 12 12 13 13 H_ADSTB#0 4 H_ADSTB#1 4 CLK_MCH_BCLK# 14 CLK_MCH_BCLK 14 H_DSTBN#[0..3] 4 +1.8V H_DSTBP#[0..3] 4 12 12 13 13 12 12 13 13
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
AG33 CLK_MCH_3GPLL AF33 CLK_MCH_3GPLL# A27 A26 C40 D41 H32 MCH_CLKREQ#
CLK_MCH_3GPLL 14 CLK_MCH_3GPLL# 14 CLK_MCH_DREFCLK# 14 CLK_MCH_DREFCLK 14 CLK_PCIE_GMCH# 14 CLK_PCIE_GMCH 14 MCH_CLKREQ# 14
D_REF_CLKN D_REF_CLKP D_REF_SSCLKN D_REF_SSCLKP CLK_REQ#
HOST
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1 HCLKN HCLKP HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDINV#0 HDINV#1 HDINV#2 HDINV#3 HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# HRS0# HRS1# HRS2#
D8 G8 B8 F8 A8 B9 C13 AG1 AG2 K4 T7 Y5 AC4 K3 T6 AA5 AC5 J7 W8 U3 AB10 B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3 B4 E6 D6
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 H_ADSTB#1 CLK_MCH_BCLK# CLK_MCH_BCLK H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_RESET# H_ADS# H_TRDY# H_DPWR# H_DRD Y# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP# H_RS#0 H_RS#1 H_RS#2
H_REQ#[0..4] 4
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
DDR MUXING
DDR_CS0_DIMMA# AW13 DDR_CS1_DIMMA# AW12 DDR_CS2_DIMMB# AY21 DDR_CS3_DIMMB# AW21 AL20 AF10
C
L
H_XSCOMP/H_YSCOMP trace width and spacing is 5/20.
+VCCP
M_ODT0 M_ODT1 M_ODT2 M_ODT3 2 80.6_0402_1% 2 80.6_0402_1% +SM_VREF0 +SM_VREF1
M_ODT0 M_ODT1 M_ODT2 M_ODT3 SMRCOMPN SMRCOMPP +SM_VREF0
BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41
1 R688 1 R689 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 4 4 4 4
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1 T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35
+3VS R687 1 2 10K_0402_5% DDR_TS
NC
C
R690 2 54.9_0402_1% 2
R691 54.9_0402_1%
J13 H_VREF K13 H_XRCOMP E1 H_XSCOMP E2 H_YRCOMP Y1 H_YSCOMP U1 H_SWNG0 E4 H_SWNG1 W1 1
B
H_RESET# 4 H_ADS# 4 H_TRDY# 4 H_DPWR# 4 H_DRDY# 4 H_DEFER# 4 H_HITM# 4 H_HIT# 4 H_LOCK# 4 H_BR0# 4 H_BNR# 4 H_BPRI# 4 H_DBSY# 4 H_CPUSLP# 4
2 R692 1 100_0402_1%
18 MCH_ICH_SYNC#
K28
CALISTOGA_FCBGA1466~D PMR3@
R693 24.9_0402_1% 2 2
R694 24.9_0402_1% CALISTOGA_FCBGA1466~D PMR3@
Layout Note: +SM_VREF0 & +SM_VREF1 trace width and +1.8V spacing is 20/20.
R695 1K_0402_1% +SM_VREF1 2 1
Strap Pin Table CFG[3:17] have internal pull up CFG[19:18] have internal pull down
CFG[2:0] CFG5 CFG7 CFG9 011 001 = 667MT/s FSB = 533MT/s FSB
B
1
RESERVED
18 PM_BMBUSY# 12,13 DDR_TS 18,36 DPRSLPVR 4,17 H_THERMTRIP# 18,26 PWROK 15,18,22,25,27 PLT_RST#
PM_BMBUSY# G28 DDR_TS F25 DPRSLPVR H26 H_THERMTRIP# G6 PWROK AH33 PLTRST_R# AH34
1
1
PM
0 = DMI x 2 *1 = DMI x 4 (Default)
H_RS#[0..2] 4
*1 = Mobile Yonah CPU (Default) *1 = Normal Operation
0 = Reserved 0 = Lane Reversal Enable (Default) (Default)
0 = Reserved
15mils Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 18/20.
+VCCP +VCCP 1 1 1 +VCCP 1 C832 0.1U_0402_16V4Z
R696 1K_0402_1% 2
1
CFG11 CFG[13:12]
*1 = Calistoga
00 01 10 *11 = = = =
2
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation (Default) (Default)
+1.8V +3VS R699 221_0603_1% 2 +SM_VREF0 2 H_SWNG1 R700 1K_0402_1% R701 2 1 1K_0402_5% CFG19 1
CFG16 CFG18 CFG19 SDVO_CTRLDATA
R697 100_0402_1% 2 2 H_VREF
R698 221_0603_1% H_SWNG0
*1 = Dynamic ODT Enabled 1.05V (Default) *0 = 1.5V 1 =
0 = Normal Operation
0 = Dynamic ODT Disabled
1
1 1 C833 0.1U_0402_16V4Z R703 100_0402_1% 2 C834 0.1U_0402_16V4Z
R704
1 C835 0.1U_0402_16V4Z
15mils
1 C836 0.1U_0402_16V4Z
Modified
*1 = DMI Lane Reversal Enable No SDVO Device Present *0 = (Default)
1 = SDVO Device Present
(Default)
1
1
A
1
2
2 2
2
2
R702 200_0402_1%
2
100_0402_1% 2
R705 1K_0402_1%
A
CFG20 (PCIE/SDVO select) Compal Secret Data
2006/11/05 Deciphered Date 2009/11/05
Title Size Date:
*0 = Only PCIE or SDVO is (Default) operational.
1 = PCIE/SDVO are operating simu.
Security Classification Issued Date
Compal Electronics, Inc.
Calistoga (1/5)
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAA M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 7 of 37
Sheet
5
4
3
2
1
D
D
U6D 12 12 12 DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 AU12 AV14 BA20 SA_BS0 SA_BS1 SA_BS2 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_D[0..63] 12 13 13 13 DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 AT24 AV23 AY28
U6E SB_BS0 SB_BS1 SB_BS2 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_B_D[0..63] 13
12 DDR_A_DM[0..7]
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4
13 DDR_B_DM[0..7]
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
12 DDR_A_DQS[0..7]
DDR SYS MEMORY A
C
DDR SYS MEMORY B
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5
13 DDR_B_DQS[0..7]
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
C
12 DDR_A_DQS#[0..7]
13 DDR_B_DQS#[0..7]
12 DDR_A_MA[0..13]
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
13 DDR_B_MA[0..13]
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
B
B
12 12 12
DDR_A_CAS# DDR_A_RAS# DDR_A_WE#
DDR_A_CAS# DDR_A_RAS# DDR_A_WE#
AY13 AW14 AY14 AK23 AK24
SA_CAS# SA_RAS# SA_WE# SA_RCVENIN# SA_RCVENOUT#
13 13 13
DDR_B_CAS# DDR_B_RAS# DDR_B_WE#
DDR_B_CAS# DDR_B_RAS# DDR_B_WE#
AR24 AU23 AR27 AK16 AK18
SB_CAS# SB_RAS# SB_WE# SB_RCVENIN# SB_RCVENOUT#
CALISTOGA_FCBGA1466~D PMR3@
CALISTOGA_FCBGA1466~D PMR3@
A
A
Security Classification Issued Date 2006/11/05
Compal Secret Data
Deciphered Date 2009/11/05
Title Size Date:
Compal Electronics, Inc.
Calistoga (2/5)
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAA M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 8 of 37
Sheet
5
4
3
2
1
15 PCIE_MTX_C_GRX_N[0..15] 15 PCIE_MTX_C_GRX_P[0..15] 15 PCIE_GTX_C_MRX_N[0..15]
D
PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]
D
15 PCIE_GTX_C_MRX_P[0..15]
+3VS
GM@ 2 GM@ 2 1 1
R706 1 2.2K_0402_5% R707 1 2.2K_0402_5% R710 2 2.2K_0402_5% R709 2 2.2K_0402_5%
GMCH_LCD_CLK GMCH_LCD_DATA GMCH_CRT_CLK GMCH_CRT_DATA 15 GMCH_TXOUT0+ 15 GMCH_TXOUT1+ 15 GMCH_TXOUT2+ 15 GMCH_TXOUT015 GMCH_TXOUT115 GMCH_TXOUT2GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+ GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2B37 B34 A36 C37 B35 A37 F30 D29 F28 G30 D30 F29 15 GMCH_TXCLK+ 15 GMCH_TXCLKGMCH_TXCLK+ GMCH_TXCLKA32 A33 E26 E27 D32 J30 H30 H29 G26 G25 F32 B38 C35 C33 C32 A16 C18 A19 TV_REFSET J20 B16 B18 B19 J29 K30 LA_DATA0 LA_DATA1 LA_DATA2 LA_DATA#0 LA_DATA#1 LA_DATA#2 LB_DATA0 LB_DATA1 LB_DATA2 LB_DATA#0 LB_DATA#1 LB_DATA#2 LA_CLK LA_CLK# LB_CLK LB_CLK# LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL TVDAC_A TVDAC_B TVDAC_C TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC TV_DCONSEL1 TV_DCONSEL0 H27 H28 U6C SDVOCTRL_DATA SDVOCTRL_CLK
L
PEGCOMP trace width and spacing is 18/25 mils.
D40 D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40 PEGCOMP R708 1 2 24.9_0402_1%
+1.5VS_PCIE
EXP_COMPI EXP_COMPO EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 C553 C461 C549 C548 C537 C579 C577 C516 C555 C426 C554 C518 C560 C551 C576 C570 C568 C574 C567 C536 C575 C578 C550 C545 C552 C515 C517 C569 C547 C559 C541 C422 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15
B C
LVDS
1 R711
C
2 2 2 2
1.5K_0402_1% 75_0402_5% 150_0402_1% 150_0402_1%
LIBG GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA 26 GMCH_ENBKL GMCH_ENBKL
1 R712 1 R713 1 R714
15 GMCH_LCD_CLK 15 GMCH_LCD_DATA 15 GMCH_ENVDD
GMCH_LCD_CLK GMCH_LCD_DATA GMCH_ENVDD LIBG
16 GMCH_TV_LUMA 16 GMCH_TV_CRMA
GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA R715 1 2 4.99K_0402_1%
B
16 GMCH_CRT_CLK 16 GMCH_CRT_DATA 16 GMCH_CRT_VSYNC 16 GMCH_CRT_HSYNC 16 GMCH_CRT_B 16 GMCH_CRT_G 16 GMCH_CRT_R R716 1 2 150_0402_1% R717 1 2 150_0402_1% R718 1 2 150_0402_1%
GMCH_CRT_CLK GMCH_CRT_DATA
C26 C25 H23 G23 E23 D23 C22 B22 A21 B21
DDCCLK DDCDATA VSYNC HSYNC BLUE BLUE# GREEN GREEN# RED RED# CRT_IREF
PCI-EXPRESS GRAPHICS
TV CRT
R719 1 2 255_0402_1%
J22
PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15
CALISTOGA_FCBGA1466~D PMR3@
A
A
Security Classification Issued Date 2006/11/05
Compal Secret Data
Deciphered Date 2009/11/05
Title Size Date:
Compal Electronics, Inc.
Calistoga (3/5)
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAA M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 9 of 37
Sheet
5
4
3
2
1
+2.5VS
C838 +VCCP AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1 U6H VCC_SYNC VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51 VTT52 VTT53 VTT54 VTT55 VTT56 VTT57 VTT58 VTT59 VTT60 VTT61 VTT62 VTT63 VTT64 VTT65 VTT66 VTT67 VTT68 VTT69 VTT70 VTT71 VTT72 VTT73 VTT74 VTT75 VTT76 VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC2 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS H22 B30 C30 A30 AB41 AJ41 L41 N41 R41 V41 Y41 AC33 G41 H41 E21 F21 G21 B26 C39 AF1 A38 B39 AF2 H20 G20 E19 F19 C20 D20 E20 F20 AH1 AH2 A28 B28 C28 +2.5VS +2.5VS
1
C839
1
C840
1
C841
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +1.5VS_PCIE
+3VS_TVDACB 2
+3VS R721 1 0_0805_5%
+3VS_TVDACA 2 R720 1 0_0805_5% 1 1 C845 0.1U_0402_16V4Z
+3VS
D
W=40 mils
220U_D2_4VM 1 C846+ 2 +1.5VS_3GPLL +2.5VS 10U_0805_6.3V6M C847 1 1
R722 2 1 0_0805_5% +1.5VS C842 2200P_0402_50V7K
1
1 C843 0.1U_0402_16V4Z C844 2200P_0402_50V7K
D
2
2
2
2
2
2
C848 10U_0805_6.3V6M
C837
+ 2
330U_D2E_2.5VM_R9
1
+2.5VS_CRTDAC 2200P_0402_50V7K 22U_0805_6.3V6M C850 1
1
2 L35 2.2_0603_5%
+2.5VS +3VS_TVBG +3VS 2 R723 1 0.5_0805_1% 1 C854 0.1U_0402_16V4Z 1 C855 22U_0805_6.3V6M 1 +3VS_TVDACC 2 C856 2200P_0402_50V7K C857 0.1U_0402_16V4Z R724 1 0_0805_5% +3VS
C849 +1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL +2.5VS
1
1 C851 0.1U_0402_16V4Z
1
1
C853 2200P_0402_50V7K
C852 22U_0805_6.3V6M
2
2
2
1
2 +1.5VS_MPLL +3VS_TVBG
2
2
2
2
2
P O W E R
VCCA_MPLL VCCA_TVBG VSSA_TVBG VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCD_TVDAC VCCDQ_TVDAC VCCHV0 VCCHV1 VCCHV2 VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31
C
1 C858 4.7U_0805_10V4Z
1 C859 2.2U_0603_6.3V6K
C
+3VS_TVDACA +3VS_TVDACB +3VS_TVDACC
2
2
PCI-E/MEM/FSB PLL decoupling
KC FBM-L11-201209-221LMAT_0805 +1.5VS_3GPLL KC FBM-L11-201209-221LMAT_0805 R726 1 R725 2 0.5_0805_1% 1 1 C861 10U_0805_6.3V6M 2 1 0.022U_0402_16V7K 2 +1.5VS +1.5VS_TVDAC R727 1 +1.5VS
+1.5VS
MCH_A6
D21 H19 A23 B23 B25 AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14
+1.5VS_TVDAC +3VS_VCCHV 1 L36 1 C868 22U_0805_6.3V6M 2 0_0603_5% +3VS
C860 0.1U_0402_16V4Z
2
2
1 C862 C865 0.1U_0402_16V4Z @ 2 2
1
1 C863 @10U_0805_6.3V6M
1
C864 0.022U_0402_16V7K
2
2
C866 0.47U_0402_6.3V6K
1
1
2
C867 0.1U_0402_16V4Z 2 2
+1.5VS_MPLL +1.5VS
C869 0.22U_0603_10V7K
B
45mA Max.
1 C870 0.1U_0402_16V4Z C871 0.1U_0402_16V4Z 1
KC FBM-L11-201209-221LMAT_0805 R728 2 1 +1.5VS
+1.5VS_HPLL
45mA Max.
1
KC FBM-L11-201209-221LMAT_0805 R729 2 1 +1.5VS
B
1 C875 0.22U_0603_10V7K
MCH_D2
1
1 C874 10U_0805_6.3V6M
2
MCH_AB1
1
2
2
2
C872 10U_0805_6.3V6M
C873 0.1U_0402_16V4Z
2
2
2
1
C876 0.47U_0402_6.3V6K
2 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40 CALISTOGA_FCBGA1466~D PMR3@
+1.5VS_DPLLB
KC FBM-L11-201209-221LMAT_0805 R730
+1.5VS_DPLLA KC FBM-L11-201209-221LMAT_0805 R731 2 1 +1.5VS 1 1 + 2 C879 0.1U_0402_16V4Z C880 330U_D2E_2.5VM_R9 GM@
A
+1.5VS
40mA Max.
1 1 C877 0.1U_0402_16V4Z +
2
1
+1.5VS
40mA Max.
2
C878 330U_D2E_2.5VM_R9 2 GM@
2
A
Security Classification Issued Date 2006/11/05
Compal Secret Data
Deciphered Date 2009/11/05
Title Size Date:
Compal Electronics, Inc.
Calistoga (4/5)
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAA M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 10 of 37
Sheet
5
4
3
2
1
POWER
GND
+VCCP AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
U6F VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72 VCC100 VCC101 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC110 CALISTOGA_FCBGA1466~D PMR3@ VCCSM_LF2 VCCSM_LF1 C718 0.47U_0402_6.3V6K C719 0.47U_0402_6.3V6K VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57 VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17
+1.5VS
+VCCP AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19
U6G VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC_SM0 VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4 VCC_SM5 VCC_SM6 VCC_SM7 VCC_SM8 VCC_SM9 VCC_SM10 VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15 VCC_SM16 VCC_SM17 VCC_SM18 VCC_SM19 VCC_SM20 VCC_SM21 VCC_SM22 VCC_SM23 VCC_SM24 VCC_SM25 VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36 VCC_SM37 VCC_SM38 VCC_SM39 VCC_SM40 VCC_SM41 VCC_SM42 VCC_SM43 VCC_SM44 VCC_SM45 VCC_SM46 VCC_SM47 VCC_SM48 VCC_SM49 VCC_SM50 VCC_SM51 VCC_SM52 VCC_SM53 VCC_SM54 VCC_SM55 VCC_SM56 VCC_SM57 VCC_SM58 VCC_SM59 VCC_SM60 VCC_SM61 VCC_SM62 VCC_SM63 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99 AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6
+1.8V U6I VCCSM_LF4 VCCSM_LF5 C722 0.47U_0402_6.3V6K C723 0.47U_0402_6.3V6K AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 AK34 AG34 AF34 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11 J11 D11 B11 AV10 AP10 AL10 AJ10 U6J VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS265 VSS264 VSS263 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS292 VSS291 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
D
D
1
1
C703 0.22U_0603_10V7K
C704 0.22U_0603_10V7K
C705 0.22U_0603_10V7K
2
2
1
1
1
2
2
2
Place near pin AT41 & AM41
+1.8V
C706 0.1U_0402_16V4Z
C707 0.1U_0402_16V4Z
C709 0.1U_0402_16V4Z
C708 10U_0805_6.3V6M
C711 10U_0805_6.3V6M
C712 1U_0603_10V4Z
P O W E R
1
1
1
1
C710 0.1U_0402_16V4Z
1
1
1
P O W E R
2
2
2
P O W E R
2
2
2
2
P O W E R
C
C
330U_D2E_2.5VM_R9
1 C713 + 2
0.47U_0402_6.3V6K
1
C714
2
Place near pin BA23
C715 10U_0805_6.3V6M C724 10U_0805_6.3V6M
C716
B
1 + 2
330U_D2E_2.5VM_R9
1
1
2
2
B
+1.8V VCC_SM100 VCC_SM101 VCC_SM102 VCC_SM103 VCC_SM104 VCC_SM105 VCC_SM106 VCC_SM107 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 VCCSM_LF2 AJ1 VCCSM_LF1
0.47U_0402_6.3V6K
1 C717 2
CALISTOGA_FCBGA1466~D PMR3@
Place near pin BA15
1
1
A
A
2
2 CALISTOGA_FCBGA1466~D PMR3@
CALISTOGA_FCBGA1466~D PMR3@
Place near pin AV1 & AJ1
Security Classification Issued Date 2006/11/05
Compal Secret Data
Deciphered Date 2009/11/05
Title Size Date:
Compal Electronics, Inc.
Calistoga (5/5)
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAA M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 11 of 37
Sheet
5
4
3
2
1
+1.8V 8 DDR_A_DQS#[0..7] 8 DDR_A_D[0..63] 8 DDR_A_DM[0..7] 8 DDR_A_DQS[0..7] 8 DDR_A_MA[0..13] DDR_A_D0 DDR_A_D4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D14 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 JP3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
+1.8V
+DDR_VREF
DDR_A_D7 DDR_A_D1 DDR_A_DM0 DDR_A_D5 DDR_A_D6
1 C881 2.2U_0603_6.3V6K 2
1 C882 0.1U_0402_16V4Z
+1.8V 1 R732 1K_0402_1% 2
D
2
D
Layout Note: Place near JP27
DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_D9 DDR_A_D15 M_CLK_DDR0 7 M_CLK_DDR#0 7
15mils
1 R733 1K_0402_1% 2
DDR_A_D12 DDR_A_D13
+DDR_VREF
+1.8V DDR_A_D21 DDR_A_D17 C883 2.2U_0603_6.3V6K C884 2.2U_0603_6.3V6K C885 2.2U_0603_6.3V6K C886 2.2U_0603_6.3V6K C887 2.2U_0603_6.3V6K C888 0.1U_0402_16V4Z C889 0.1U_0402_16V4Z C890 0.1U_0402_16V4Z C891 0.1U_0402_16V4Z DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D22 DDR_A_D19 DDR_A_D25 DDR_A_D24 DDR_A_DM3 DDR_A_D27 DDR_A_D30
C
DDR_A_D20 DDR_A_D16 DDR_TS DDR_A_DM2 DDR_A_D18 DDR_A_D23 DDR_A_D29 DDR_A_D28 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D26 DDR_A_D31 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 7
C
DDR_TS 7,13
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
7 DDR_CKE0_DIMMA 8 DDR_A_BS#2
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1 DDR_A_D35 DDR_A_D32 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D39 DDR_A_D33 DDR_A_D45 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D52 DDR_A_D53
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13 DDR_A_BS#1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# 7 M_ODT0 7
+0.9VS
8 8
DDR_A_BS#0 DDR_A_WE#
8 DDR_A_CAS# 7 DDR_CS1_DIMMA# C892 0.1U_0402_16V4Z C893 0.1U_0402_16V4Z C894 0.1U_0402_16V4Z C895 0.1U_0402_16V4Z C896 0.1U_0402_16V4Z C897 0.1U_0402_16V4Z C898 0.1U_0402_16V4Z C899 0.1U_0402_16V4Z C900 0.1U_0402_16V4Z C901 0.1U_0402_16V4Z C902 0.1U_0402_16V4Z C903 0.1U_0402_16V4Z C904 0.1U_0402_16V4Z 7 M_ODT1
1
1
1
1
1
1
1
1
1
1
1
1
1
DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D34 DDR_A_D38 DDR_A_D40 DDR_A_D44
B
2
2
2
2
2
2
2
2
2
2
2
2
2
B
DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D47 DDR_A_D46 DDR_A_D48 DDR_A_D49 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_DM6 DDR_A_D50 DDR_A_D54 DDR_A_D60 DDR_A_D57 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 M_CLK_DDR1 7 M_CLK_DDR#1 7
+0.9VS RP32 1 2 RP33 56_0404_4P2R_5% 4 1 DDR_A_BS#2 3 2 DDR_CKE0_DIMMA
DDR_A_MA5 DDR_A_MA8 DDR_A_MA1 DDR_A_MA3
4 3
Layout Note: Pla ce these resistor closely JP27,all trace length Max=1.5"
DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D51 DDR_A_D55 DDR_A_D56 DDR_A_D61 DDR_A_DM7 DDR_A_D58 DDR_A_D59 13,14 CLK_SMBDATA 13,14 CLK_SMBCLK CLK_SMBDATA CLK_SMBCLK +3VS
RP34 56_0404_4P2R_5% RP35 56_0404_4P2R_5% 1 4 4 1 DDR_A_MA7 2 3 3 2 DDR_A_MA6
RP36 56_0404_4P2R_5% RP37 56_0404_4P2R_5% DDR_CS0_DIMMA# 1 4 4 1 DDR_A_MA9 DDR_A_RAS# 2 3 3 2 DDR_A_MA12 DDR_A_BS#0 DDR_A_MA10 DDR_A_CAS# DDR_A_WE#
A
RP38 56_0404_4P2R_5% RP39 56_0404_4P2R_5% 1 4 4 1 DDR_A_MA2 2 3 3 2 DDR_A_MA4 RP40 56_0404_4P2R_5% RP41 56_0404_4P2R_5% 1 4 4 1 DDR_A_MA0 2 3 3 2 DDR_A_BS#1
RP42 56_0404_4P2R_5% RP43 56_0404_4P2R_5% DDR_CS1_DIMMA# 2 3 4 1 DDR_A_MA13 M_ODT1 1 4 3 2 M_ODT0 56_0404_4P2R_5% RP44 56_0404_4P2R_5% 4 1 DDR_CKE1_DIMMA 3 2 DDR_A_MA11
2
PTI_A5652D-A0G16-P C905 0.1U_0402_16V4Z
DIMM0 RVS H:5.2mm (BOT)
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
Size Date: Document Number
A
Security Classification Issued Date 2006/11/05
Compal Secret Data
Deciphered Date 2009/11/05
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAA M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 12 of 37
Sheet
5
4
3
2
1
8 DDR_B_DQS#[0..7] 8 DDR_B_D[0..63] 8 DDR_B_DM[0..7] 8 DDR_B_DQS[0..7] 8 DDR_B_MA[0..13] DDR_B_D0 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0
D
+1.8V
+1.8V +DDR_VREF
JP4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDR_B_D4 DDR_B_D1 DDR_B_DM0 DDR_B_D6 DDR_B_D2
D
1 C906 2.2U_0603_6.3V6K 2
1 C907 0.1U_0402_16V4Z
2
Layout Note: Place near JP26
DDR_B_D7 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11
DDR_B_D12 DDR_B_D13 DDR_B_DM1 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_D14 DDR_B_D15 M_CLK_DDR3 7 M_CLK_DDR#3 7
+1.8V
C908 2.2U_0603_6.3V6K
C909 2.2U_0603_6.3V6K
C910 2.2U_0603_6.3V6K
C911 2.2U_0603_6.3V6K
C912 2.2U_0603_6.3V6K
C913 0.1U_0402_16V4Z
C914 0.1U_0402_16V4Z
C915 0.1U_0402_16V4Z
C916 0.1U_0402_16V4Z
C917 220U_D2_4VM
220U_D2_4VM
1
1
1
1
1
1
1
1
1
1 + 2
1 + 2 C918
DDR_B_D21 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D30 DDR_B_D31
DDR_B_D16 DDR_B_D20 DDR_TS DDR_B_DM2 DDR_B_D18 DDR_B_D19 DDR_B_D26 DDR_B_D28 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D29 DDR_B_D27
C
DDR_TS 7,12
2
2
2
2
2
2
2
2
2
C
7 DDR_CKE2_DIMMB
DDR_CKE2_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 7
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
8
DDR_B_BS#2
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 DDR_B_MA13 DDR_B_BS#1 8 DDR_B_RAS# 8 DDR_CS2_DIMMB# 7 M_ODT2 7
+0.9VS
8 8
DDR_B_BS#0 DDR_B_WE#
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS3_DIMMB# M_ODT3 DDR_B_D37 DDR_B_D36 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D35 DDR_B_D34
C919 0.1U_0402_16V4Z
C920 0.1U_0402_16V4Z
C921 0.1U_0402_16V4Z
C922 0.1U_0402_16V4Z
C923 0.1U_0402_16V4Z
C924 0.1U_0402_16V4Z
C925 0.1U_0402_16V4Z
C926 0.1U_0402_16V4Z
C927 0.1U_0402_16V4Z
C928 0.1U_0402_16V4Z
C929 0.1U_0402_16V4Z
C930 0.1U_0402_16V4Z
1
1
1
1
1
1
1
1
1
1
1
1
1
C931 0.1U_0402_16V4Z
8 DDR_B_CAS# 7 DDR_CS3_DIMMB# 7 M_ODT3
2
2
2
2
2
2
2
2
2
2
2
2
2
DDR_B_D33 DDR_B_D32 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D43 DDR_B_D46 DDR_B_D49 DDR_B_D52 M_CLK_DDR2 M_CLK_DDR#2 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 M_CLK_DDR2 7 M_CLK_DDR#2 7
B
B
DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D47
+0.9VS RP45 1 2 RP46 56_0404_4P2R_5% DDR_B_MA9 1 DDR_B_MA12 2
DDR_B_MA1 DDR_B_MA3 DDR_B_MA10 DDR_B_BS#0 DDR_B_MA0 DDR_B_BS#1
Layout Note: Pla ce these resistor closely JP26,all trace length Max=1.5"
DDR_B_D48 DDR_B_D53
4 3
4 3
DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D51 DDR_B_D50 DDR_B_D60 DDR_B_D61 DDR_B_DM7 DDR_B_D58 DDR_B_D59 12,14 CLK_SMBDATA 12,14 CLK_SMBCLK CLK_SMBDATA CLK_SMBCLK +3VS
RP47 56_0404_4P2R_5% RP48 56_0404_4P2R_5% DDR_CKE3_DIMMB 1 4 4 1 DDR_B_MA11 2 3 3 2 RP49 56_0404_4P2R_5% RP50 56_0404_4P2R_5% DDR_B_MA5 1 4 4 1 DDR_B_MA8 2 3 3 2
RP51 56_0404_4P2R_5% RP52 56_0404_4P2R_5% DDR_B_RAS# DDR_B_MA7 1 4 4 1 DDR_CS2_DIMMB# 2 DDR_B_MA6 3 3 2 RP53 56_0404_4P2R_5% RP54 56_0404_4P2R_5% DDR_B_MA4 1 4 4 1 DDR_B_MA2 2 3 3 2 RP55 56_0404_4P2R_5% RP56 56_0404_4P2R_5% M_ODT3 M_ODT2 2 3 4 1 DDR_CS3_DIMMB# 1 DDR_B_MA13 4 3 2 DDR_B_WE# DDR_B_CAS#
A
+3VS
A
2
P-TWO_A5692B-A0G16-P C932 0.1U_0402_16V4Z
56_0404_4P2R_5% RP57 4 3
DIMM1 RVS H:9.2mm (BOT)
Deciphered Date 2009/11/05
Title Size Date:
1 2
DDR_B_BS#2 DDR_CKE2_DIMMB
Security Classification Issued Date 2006/11/05
Compal Secret Data
56_0404_4P2R_5%
Compal Electronics, Inc.
DDRII-SODIMM SLOT2
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
ISKAA M/B LA-3661P
Tuesday, December 26, 2006
1
Rev 0.1 13 of 37
Sheet
5
4
3
2
1
+CK_VDD_MAIN1 +3VS +3VS 1 PCIEC_CLKREQ# R736 10K_0402_5% 2 1 SATA_CLKREQ# R737 10K_0402_5% 2 1 MCH_CLKREQ# R738 10K_0402_5% 2 1 MINI_CLKREQ# R739 10K_0402_5% 2 +3VS R740 1 2 1 C941 10U_0805_10V4Z 1 C942 0.1U_0402_16V4Z 1 C943 0.1U_0402_16V4Z R734 1 2 1 C933 10U_0805_10V4Z 1 C934 0.1U_0402_16V4Z 1 C935 0.1U_0402_16V4Z 1 C936 0.1U_0402_16V4Z +3VS R735 1 2
+CK_VDD_DP
KC FBM-L11-201209-221LMAT_0805
1 KC FBM-L11-201209-221LMAT_