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1
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PCB STACK UP
LAYER 1 : TOP LAYER 2 : SGND LAYER 3 : IN1
A
BL5S Block Diagram
HDMI
Page 20
Transmitter Sil1392
Page 20
Azalia
Intel
Merom
(35W)
CLOCK GENERATOR
CK505 ICS9LPR363
Page 2
A
LAYER 4 : IN2 LAYER 5 : VCC
Page 3,4
TV-OUT LAYER 6 : BOT
Page 22
FSB(667/800MHZ) SDVO R.G.B LVDS X2 CRT Azalia HDMI PCI-E X16
CRT
Page 18
VCC_CORE
LCD(WXGA+ 15.4W)
Page 18
Crestline GM
VGA CONNECTOR
Page 19
LCD TV-OUT
+1.5V
SATA - TWO HDD
Page 22
SATA X2
533/ 667 MHZ DDR II
Page 5,7,8,9,10,11
+1.05V
IDE - ODD
Page 22
B
PATA
DMI(x2/x4)
DDRII-SODIMM1 DDRII-SODIMM2
Page 12,13
B
+1.25V +1.8VSUS
+3VPCU +3V_S5 +3VSUS +3V +5VPCU +5V_S5 +5V SMDDR_VTERM SMDDR_VREF
USB CONN 1
Page 19
PCI-Express
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USB CONN 2
Page 19
MINI CARD WLAN
Page 25
MINI CARD
Page 25
MINI CARD
Page 25
NEW CARD
Page 28
USB CONN3
Page 19
USB 2.0
ICH8M
Giga/100/10 LAN Marvell_8040 8055 Page 24
USB CONN 4
Page 19
Azalia
RJ45
DAUGHTER BOARD
WLAN
PCI Bus
Page 14,15,16,17
Page 25
Finger Printer
Page 28
C
LPC
32.768KHz
Card Reader/1394 OZ129T
Page 23
Port-A
AUDIO CODEC (CX20561)
Page 26 Port-B DIB_P
HP(SPDIF)
Page 27
Bluetooth
Page 28
New Card
Page 28 Page 29
WPC8769LDG WPCE775L
5 IN 1
1394
DIB_N
SPK AMP
Page 26 Port-C
INT SPK
Page 26
C
MODEM CONN (CX20548)
Page 26
INT MIC
Page 18,27
Felica
Page 28
MIC JACK
Page 27
Camera
Page 18
FAN
Touch PAD
Key Board
FLASH ROM
CIR USB X2 RJ11
FM TUNER
Page 27
D
Digitally signed by fdsf DN: cn=fdsf, o=fsdfsd, ou=ffsdf, email=fdfsd@fsdff, c=US Date: 2009.11.04 18:25:59 +07'00'
1 2 3 4 5
RJ11/USB DAUGHTER BOARD
D
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date:
6 7
Document Number
Block Diagram
Tuesday, January 22, 2008 Sheet
8
Rev 1A 1 of 37
5
4
3
2
1
Clock Generator Clock Gen Differential IO power
+3V L21 PBY160808T-301Y-N_6 C270 C299 10u/10V_8
D
+1.25V_VDD
+1.25V
C291
0.1u/10V_4 C281 0.1u/10V_4 *10u/10V_8 10u/10V_8 C282 10u/10V_8 0.1u/10V_4 C257 C260 0.1u/10V_4 0.1u/10V_4 C297 C256 0.1u/10V_4 0.1u/10V_4 C296
L22 PBY160808T-301Y-N_6 C300 0.1u/10V_4
D
C271
H=1.2mm
C253 0.1u/10V_4 0.1u/10V_4 VDD_CK_VDD_48 VDD_CK_VDD_48 VDD_CK_VDD_48 VDD_CK_VDD_48 VDD_CK_VDD_48 VDD_CK_VDD_48 +1.25V_VDD 2 9 16 61 39 55 12 20 26 45 36 49 U9
ICS9LPRS365BGLFT
IC(64P) ICS9LPRS365BGLFT(TSSOP) IO_VOUT SCLK SDA 48 64 63 38 37 54 53 51 50 47 46 35 34 33 32 30 31 44 43 41 40 27 28 CLK_CPU_BCLK_R CLK_CPU_BCLK#_R CLK_MCH_BCLK_R CLK_MCH_BCLK#_R CLK_PCIE_MINI3_R CLK_PCIE_MINI3#_R CLK_PCIE_3GPLL#_R CLK_PCIE_3GPLL_R CLK_MCH_OE#_R NEW_CLKREQ#_R CLK_PCIE_NEW_R CLK_PCIE_NEW_R# CLK_PCIE_MINI2_R CLK_PCIE_MINI2#_R CLK_PCIE_MINI_R CLK_PCIE_MINI#_R CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_PCIE_ICH_R CLK_PCIE_ICH#_R RP46 RP35 RP36 RP45 RP44 RP43 RP32 RP33 RP34 RP40 1 3 1 3 1 3 1 3 R237 R262 3 1 1 3 1 3 3 1 3 1 3 1 2 0X2 4 2 0X2 4 2 0X2 4 2 0X2 4 475_4 475_4 4 0X2 2 2 0X2 4 2 0X2 4 4 0X2 2 4 0X2 2 4 0X2 2 CGCLK_SMB CGDAT_SMB CGCLK_SMB (13) CGDAT_SMB (13) PM_STPPCI# (16) PM_STPCPU# (16) CLK_CPU_BCLK (3) CLK_CPU_BCLK# (3) CLK_MCH_BCLK (5) CLK_MCH_BCLK# (5) CLK_PCIE_MINI3 (25) CLK_PCIE_MINI3# (25) CLK_PCIE_3GPLL# (6) CLK_PCIE_3GPLL (6) CLK_MCH_OE# (6) NEW_CLKREQ# (28) CLK_PCIE_NEW (28) CLK_PCIE_NEW# (28) CLK_PCIE_MINI2 (25) CLK_PCIE_MINI2# (25) CLK_PCIE_MINI (25) CLK_PCIE_MINI# (25) CLK_PCIE_LAN (24) CLK_PCIE_LAN# (24) CLK_PCIE_ICH (15) CLK_PCIE_ICH# (15)
H=1.5mm
C272 27p_4 2 CG_XIN Y2 14.318MHZ 1 C280 27p_4 CG_XOUT
C295
VDD_PCI VDD_48 VDD_PLL3 VDD_REF VDD_SRC VDD_CPU
C259
0.1u/10V_4
CK505
CL=20p
C255 0.1u/10V_4
SRC5/PCI_STOP# SRC5#/CPU_STOP# CPU0 CPU0# CPU1 CPU1# SRC8/ITP SRC8#/ITP#
To SB To CPU To NB To MINI3 To NB
10/26 REV_A1 Change Value
R259 R277 R271 +3V (29) PCLK_591
C
VDD_96_IO VDD_PLL3_IO VDD_SRC_IO_1 VDD_SRC_IO_3 VDD_SRC_IO_2 VDD_CPU_IO
(25) PCLK_DEBUG T49 +3V (23) PCLK_OZ129 PCLK_PCM 10K_4 *10K_4
33_4 33_4 33_4
PCLK_DEBUG_R PCLK_PCM_R PCLK_R5C833_R
1 3 4 5 6 7 60 59 10 57 62
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCIF5/ITP_EN XTAL_IN XTAL_OUT USB_48/FSA
R264 R265 R266
SRC10# SRC10 SRC11/CR#_H SRC11#/CR#_G SRC9 SRC9# SRC7/CR#_F SRC7#/CR#_E SRC6 SRC6# SRC4 SRC4#
10K_4 PCI_CLK_SIO_R 33_4 33_4 PCLK_591_R PCLK_ICH_R CG_XIN
R278 R272
*10K_4 R267 10K_4 R268 *10K_4 10K_4 CG_XOUT R274 33_4 FSA
To New Card To MINI2 To WLAN To LAN To SB To SB
C
+3V (15) PCLK_ICH
R279 R273
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(16) CLKUSB_48 CLK_BSEL0 R275 CLK_BSEL1 CLK_BSEL2 R231 R228 2.2K_4 10K_4 33_4 FSB/TEST/MODE FSC SRC3/CR#_C SRC3#/CR#_D SRC2/SATA SRC2#/SATA# 24 25 REF0/FSC/TESTSEL VSS_PCI VSS_48 VSS_IO VSS_PLL3 VSS_CPU VSS_SRC1 VSS_SRC2 VSS_SRC3 VSS_REF (16) 14M_ICH 8 11 15 19 52 23 29 42 58 21 22 CLK_PCIE_SATA_R CLK_PCIE_SATA#_R DREFSSCLK_R DREFSSCLK#_R DREFCLK_R DREFCLK#_R CLK_PCIE_SATA (14) CLK_PCIE_SATA# (14) SRC1/SE1 SRC1#/SE2 17 18 SRC0/DOT96 SRC0#/DOT96# 13 14 RP41 3 1 4 IV@0X2 2 DREFCLK (6) DREFCLK# (6)
To NB
CKPWRGD/PWRDWN#
56
CK_PWRGD (16)
ICS9LPRS365AGLFT/ SLG8SP512T
ICS9LPRS365 RTM875T-606 (ALPRS365K13) (AL000875K06) PCI2/TME internal PD PCI-3/SRC5_EN internal PD
PULL HIGH
PULL DOWN DREFSSCLK#_R DREFSSCLK_R RP42 1 3 3 1 2 IV@0X2 4 4 2 DREFSSCLK# (6) DREFSSCLK (6) CLK_MXM (19) CLK_MXM# (19)
Pin 4
B
PCI2/TME
NO OVERCLOCKING
(default)
NORMAL RUN PIN37/38 IS PCI_STOP/CPU_STOP PIN 17/18 IS SRC/DOT
10/31 REV_A1 Change Value
(default) PCLK_PCM PCLK_591 CLKUSB_48 14M_ICH PCLK_ICH PCLK_DEBUG C311 C312 C324 C258 C323 C304 *33p_4 *33p_4 15p_4 *33p_4 *33p_4 *33p_4 RP47 EV@0X2
To NB
B
Pin 5
PCI-3
PIN37/38 IS SRC5
To MXM
Pin 6
PCI-4/27M_SEL PCI-4/27M_SEL internal PD PCIF-5/ITP_EN PCIF-5/ITP_EN internal PD
PIN 17/18 IS 27MHz
(default)
Pin 7
PIN 46/47 IS CPUITP
PIN 46/47 IS SRC8
(default)
CPU Clock select
BSEL Frequency Select Table
FSC 0 0 0
A
(3) CPU_BSEL0 +1.05V
R282 R281 R280
0_4 *56_4 *1K_4
CLK_BSEL0
MCH_BSEL0 (6)
2
Clock Gen I2C
(16,21,25,28) SDATA
+3V Q17 RHU002N06
R242 10K_4 CGDAT_SMB
FSA
CLK_BSEL1
3
1
FSB 0 0 1 1 1 1 0 0
FSA 0 1 1 0 0 1 1 0
5
Frequency 266Mhz 133Mhz 166Mhz 200Mhz 400Mhz Reserved 100Mhz 333Mhz
+1.05V (3) CPU_BSEL2 +1.05V (3) CPU_BSEL1
+3V Q18 RHU002N06 R225 R227 R226 0_4 *0_4 *1K_4 MCH_BSEL1 (6) (16,21,25,28) SCLK 3 1 R250 10K_4 CGCLK_SMB
A
FSB
C685 *0.1u/10V_4 +3V
0 1 1 1 1
01/21 REV_3B Add for ESD
R233 R234 R232
0_4 *0_4 *1K_4
CLK_BSEL2
MCH_BSEL2 (6)
FSC
3
R261
10K_4 NEW_CLKREQ#_R Size Date:
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Document Number
2
CLK. GEN./ CK505
Tuesday, January 22, 2008
1
Rev 1A Sheet 2 of 37
4
2
5
4
3
2
1
(5) H_A#[16:3]
U22A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# H1 E2 G5 H5 F21 E1 F1 D20 H_IERR# B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 R40 56.2_4 +1.05V H_INIT# (14) H_LOCK# (5) H_CPURST# (5) H_RS#0 (5) H_RS#1 (5) H_RS#2 (5) H_TRDY# (5) H_HIT# (5) H_HITM# (5) T28 T25 T26 T27 T24 T29 T77 R43 R41 D21 H_PROCHOT_R# A24 H_THERMDA B25 H_THERMDC C7 THERMTRIP#_PWR R42 0_4 56.2_4 *2.2K_4 H_CPURST# C666 0.1u/10V_4 +3V Q37 RHU002N06 1 +3V C674 0.1u/10V_4 SYS_RST# (16) +1.05V H_PROCHOT# (32) (16) THERM_ALERT# +3V +3V R434 R435 R436 10K_4 *0_4 10K_4 (29) 2ND_MBDATA 3 Q38 RHU002N06 1 THERM_MBDATA 2 THERM_MBCLK 2 H_ADS# (5) H_BNR# (5) H_BPRI# (5) H_DEFER# (5) H_DRDY# (5) H_DBSY# (5) H_BREQ#0 (5)
U19
CPU(HOST)
CONTROL
ADDR GROUP 0
THERM_MBCLK THERM_MBDATA THERM_ALERT#_R THER_SHD#
8 7 6 4
SCLK SDA ALERT# OVERT# LM95245
VCC DXP DXN GND
1 2 3 5
LM86VCC H_THERMDA H_THERMDC
IERR# INIT# LOCK#
12/06 REV_3A Add C666
CPU Thermal monitor
01/17 REV_3B mount C666
+3V
D
D
(5) H_ADSTB0# (5) H_REQ#[4:0]
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
(5) H_A#[35:17]
R440 10K_4
R438 10K_4
R445 200_6 LM86VCC C458
XDP/ITP SIGNALS
ADDR GROUP 1
01/17 REV_3B Add C674
(29) 2ND_MBCLK 3
XDP_TCK XDP_TDI XDP_TMS XDP_TRST# XDP_DBRESET#
H=1.75mm
U20 8 7 6 4 SCLK SDA ALERT# OVERT# *MAX6657 THERM_ALERT#_R THER_SHD# VCC DXP DXN GND 1 2 3 5
0.1u/10V_4 H_THERMDA C459 2200p_4 H_THERMDC
THERMAL
PROCHOT# THERMDA THERMDC THERMTRIP#
10/22 REV_A1 Mount R434
(5) H_ADSTB1# (14) H_A20M# (14) H_FERR# (14) H_IGNNE# (14) H_STPCLK# (14) H_INTR (14) H_NMI (14) H_SMI#
C
A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
ADDRESS: 98H
C
(5) H_D#[15:0]
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CPU FAN
+3V
RESERVED
Q36 MMBT3904
2
2 1
Merom Ball-out Rev 1a U22B D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL[0] BSEL[1] BSEL[2]
1
3
SYS_SHDN# (31)
2
ICH ICH
H CLK
BCLK[0] BCLK[1] A22 A21 CLK_CPU_BCLK (2) CLK_CPU_BCLK# (2)
R431 330_4
10/29 REV_A1 Add for ESD
+3V
10/26 REV_A1 Add for ESD
*VPORT_6 D50
R423
THER_SHD#
H_D#[47:32] (5)
VPORT_6 D49
10K_4
FANPWR = 1.6*VSET
H_DSTBN#2 (5) H_DSTBP#2 (5) H_DINV#2 (5) H_D#[63:48] (5)
2
B
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
(5) (5) (5) (5)
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[31:16] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3]
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
+5V
H=1.75mm
U17 VIN VO GND /FON GND GND VSET GND G995
(29) FANSIG
1
CN17 1 2 3
DATA GRP 2
DATA GRP 0
C433 (19) SYSFANON# (29) VFAN R415 2.2u/6.3V_6 0_4
2 1 4
3 5 6 7 8
TH_FAN_POWER 1 D44 C440 VPORT_6 10u/10V_8 0.01u_4 *0.01u_4 C436 C434
4 5
PTI_CWY030-B0G1Z
B
12/04 REV_3A DNI C440
+1.05V
PU/PD (ITP700)
+1.05V
Thermal Trip
+1.05V
R51 (5) H_DSTBN#1 1K/F_4 (5) H_DSTBP#1 (5) H_DINV#1 R45 R44 T9 T73 T23 T8 (2) CPU_BSEL0 (2) CPU_BSEL1 (2) CPU_BSEL2
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
DATA GRP 3
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 (5) H_DSTBP#3 (5) H_DINV#3 (5) COMP0 COMP1 COMP2 COMP3 R49 R48 R170 R173 27.4/F_6 54.9/F_4 27.4/F_6 54.9/F_4 ICH_DPRSTP# (6,14,32) H_DPSLP# (14) H_DPWR# (5) H_PWRGD (14) H_CPUSLP# (5) PSI# (32)
10/22 REV_A1 Del C452,Add R614
Q39 FDV301N R437 *10K_4 D36 *BAS316 R614
(6,16,32) DELAY_VR_PWRGOOD
2
+1.05V XDP_TMS R174 39_4 R439 XDP_TDI XDP_TCK R175 R171 150_4 27_4 THERMTRIP#_PWR XDP_TRST# R172 680_4 R442 1
1
3
2
DATA GRP 1
R613 1K_4 Q40 MMBT3904 3
100K_6
10/22 REV_A1 Add R613
56.2_4
A
R50 2K/F_6
H_GTLREF AD26 *1K_4 CPU_TEST1 C23 *1K_4 CPU_TEST2 D25 CPU_TEST3 C24 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26 B22 B23 C21
SYS_SHDN# (31)
A
MISC
*0_4
PM_THRMTRIP# (6,14)
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date: Document Number
Merom Ball-out Rev 1a
CPU(1 of 2)/FAN/Thermal
Tuesday, January 22, 2008
1
Rev 1A 3 of 37
Sheet
5
4
3
2
5
4
3
2
1
CPU(Power)
VCC_CORE U22D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
U22C C495
D
C172
C156
C174
C487
C133
C499
C497
C171
C488
10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8
C477
C134
C157
C498
C484
C185 *10u/6.3V_8
C154 *10u/6.3V_8
C184 *10u/6.3V_8
C494 *10u/6.3V_8
C479 *10u/6.3V_8
10u/6.3V_8 10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8
C191
C131
C486
C483
C183
C485
*10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8
C
C496
C132
C478
C155
C182
C173
*10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8
+ C152 330u/2.5V_7343
+ C151
330u/2.5V_7343
12/04 REV_3A Mount C152,C151
www.kythuatvitinh.com
+1.5V VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] B26 C26 +VCCA_PROC R39 0_6 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7 . H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 (32) (32) (32) (32) (32) (32) (32) VCC_CORE C56 C54 0.01u_4 10u/10V_8 R134 100/F_6 VCCSENSE VSSSENSE VCCSENSE (32) VSSSENSE (32)
B
B
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
D
+1.05V
C
+ C475 330u/2.5V_7343
C192 0.1u/16V_6
C53 0.1u/16V_6
C52 0.1u/16V_6
C207 0.1u/16V_6
C206 0.1u/16V_6
C114 0.1u/16V_6
Merom Ball-out Rev 1a R133 100/F_6
Merom Ball-out Rev 1a .
A
A
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date:
5 4 3 2
Document Number
CPU(2 of 2)
Tuesday, January 22, 2008
1
Rev 1A Sheet 4 of 37
5
4
3
2
1
NB(HOST)
(3) H_D#[63:0] +1.05V H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B3 C2 W1 W2 B6 E5 U21A H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# (3) H_ADSTB0# (3) H_ADSTB1# (3) H_BNR# (3) H_BPRI# (3) H_BREQ#0 (3) H_DEFER# (3) H_DBSY# (3) CLK_MCH_BCLK (2) CLK_MCH_BCLK# (2) H_DPWR# (3) H_DRDY# (3) H_HIT# (3) H_HITM# (3) H_LOCK# (3) H_TRDY# (3) H_A#[35:3] (3)
D
R430 221/F_4 H_SWING R429 100/F_4 C447 0.1u/10V_4
D
H_RCOMP R428 24.9/F_4
C
C
www.kythuatvitinh.com
+1.05V R30 54.9/F_4 H_SCOMP
B
HOST
+1.05V
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
K5 L2 AD13 AE13
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DINV#[3:0]
(3)
B
R29 54.9/F_4 H_SCOMP# +1.05V
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
M7 K3 AD2 AH11 L7 K2 AC2 AJ10 M14 E13 A11 H13 B12 E12 D7 D8
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
H_DSTBN#[3:0]
(3)
H_DSTBP#[3:0]
(3)
H_SWING H_RCOMP
H_SWING H_RCOMP H_SCOMP H_SCOMP# H_CPURST# H_CPUSLP#
H_REQ#[4:0]
(3)
12/05 REV_3A Add L53 for ESD
R432 1K/F_4 (3) H_CPURST# (3) H_CPUSLP# L53
H_SCOMP H_SCOMP# BK1608LM252-T_6
H_RS#[2:0]
(3)
H_AVREF
A
B9 A9
H_AVREF H_DVREF CRESTLINE_1p0
A
R433 2K/F_4
C449 0.1u/10V_4
965GM : AJSLA5T0T20 965PM : AJSLA5U0T25 960GL : AJSLA5V0T09
5 4 3 2
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date: Document Number
GMCH HOST(1 of 7)
Tuesday, January 22, 2008 Sheet
1
Rev 1A 5 of 37
5
4
3
2
1
U21B
R452 R456
EV@0_4 CTCLK EV@0_4 CTDA U21C
+VCC_PEG
D
P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1
AV29 BB23 BA25 AV23 AW30 BA23 AW25 AW23 BE29 AY32 BD39 BG37 BG20 BK16 BG16 BE13 BH18 BJ15 BJ14 BE16 BL15 BK14 BK31 BL31 AR49 AW4
M_RCOMP M_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4 M_CKE0 M_CKE1 M_CKE3 M_CKE4 M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_ODT0 M_ODT1 M_ODT2 M_ODT3
(13) (13) (13) (13) (13) (13) (13) (13)
(18) INT_LVDS_PWM (18) INT_LVDS_BLON +3V (18) INT_LVDS_EDIDCLK (18) INT_LVDS_EDIDDATA (18) INT_LVDS_DIGON R116 R124 (18) (18) (18) (18)
R451 R454
J40 H39 IV@10K_4 CTCLK E39 IV@10K_4 CTDA E40 C37 D35 K40
[email protected]_4 LVDS_IBG IV@0_4 T22
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
N43 EXP_A_COMPX M43 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
PEG_RXN0 PEG_RXN1_H PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP0 PEG_RXP1_H PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15
R462
24.9/F_4
PEG_RXN0 (19) PEG_RXN2 (19) PEG_RXN3 (19) PEG_RXN4 (19) PEG_RXN5 (19) PEG_RXN6 (19) PEG_RXN7 (19) PEG_RXN8 (19) PEG_RXN9 (19) PEG_RXN10 (19) PEG_RXN11 (19) PEG_RXN12 (19) PEG_RXN13 (19) PEG_RXN14 (19) PEG_RXN15 (19) PEG_RXP0 (19) PEG_RXP2 (19) PEG_RXP3 (19) PEG_RXP4 (19) PEG_RXP5 (19) PEG_RXP6 (19) PEG_RXP7 (19) PEG_RXP8 (19) PEG_RXP9 (19) PEG_RXP10 (19) PEG_RXP11 (19) PEG_RXP12 (19) PEG_RXP13 (19) PEG_RXP14 (19) PEG_RXP15 (19) [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 PEG_TXN0 (19) PEG_TXN1 (19) PEG_TXN2 (19) PEG_TXN3 (19) PEG_TXN4 (19) PEG_TXN5 (19) PEG_TXN6 (19) PEG_TXN7 (19) PEG_TXN8 (19) PEG_TXN9 (19) PEG_TXN10 (19) PEG_TXN11 (19) PEG_TXN12 (19) PEG_TXN13 (19) PEG_TXN14 (19) PEG_TXN15 (19) PEG_TXP0 (19) PEG_TXP1 (19) PEG_TXP2 (19) PEG_TXP3 (19) PEG_TXP4 (19) PEG_TXP5 (19) PEG_TXP6 (19) PEG_TXP7 (19) PEG_TXP8 (19) PEG_TXP9 (19) PEG_TXP10 (19) PEG_TXP11 (19) PEG_TXP12 (19) PEG_TXP13 (19) PEG_TXP14 (19) PEG_TXP15 (19)
RSVD RSVD
(12,13) (12,13) (12,13) (12,13) (12,13) (12,13) (12,13) (12,13) (12,13) (12,13) (12,13) (12,13)
INT_TXLCLKOUTINT_TXLCLKOUT+ INT_TXUCLKOUTINT_TXUCLKOUT+
L41 L43 N41 N40 D46 C45 D44 E42 G51 E51 F49 G50 E50 F48 G44 B47 B45 E44 A47 A45
D
LVDS
(12,13) M_A_A14 (12,13) M_B_A14
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
B42 C42 H48 H47 K44 K45
DREFCLK (2) DREFCLK# (2) DREFSSCLK (2) DREFSSCLK# (2) CLK_PCIE_3GPLL (2) CLK_PCIE_3GPLL# (2) DMI_TXN[3:0] (15) (22) INT_TV_Y/G (22) INT_TV_C/R
CLK
PEG_CLK PEG_CLK#
INT_TV_COMP INT_TV_Y/G INT_TV_C/R
PCI-EXPRESS
C
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
MUXING
(18) INT_TXLOUT0(18) INT_TXLOUT1(18) INT_TXLOUT2(18) INT_TXLOUT0+ (18) INT_TXLOUT1+ (18) INT_TXLOUT2+ (18) INT_TXUOUT0(18) INT_TXUOUT1(18) INT_TXUOUT2(18) INT_TXUOUT0+ (18) INT_TXUOUT1+ (18) INT_TXUOUT2+
+SMDDR_VREF
SMDDR_VREF_MCH R35 R31 DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#
R33
0_6 +1.8VSUS
*10K_6 *10K_6
GRAPHICS
DDR
E27 G27 K27 F27 J27 L27
TVA_DAC TVB_DAC TVC_DAC TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 TV_DCONSEL_1
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
(2) MCH_BSEL0 (2) MCH_BSEL1 (2) MCH_BSEL2 (11) MCH_CFG_5
AN47 AJ38 AN42 AN46 AM47 AJ39 AN41 AN45
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
+3V R117 R120 R119 R118 [email protected]_4 [email protected]_4 EV@0_4 EV@0_4
DMI_TXP[3:0] (15)
M35 P33
(11) MCH_CFG_9 (11) MCH_CFG_12 (11) MCH_CFG_13 (11) MCH_CFG_16 (11) MCH_CFG_19 (11) MCH_CFG_20
GRAPHICS VID
www.kythuatvitinh.com
T74 T75 T16 T17 T11 T14 T18 T10 T15 T12 T21 MCH_CFG_3 MCH_CFG_4 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_10 MCH_CFG_11 MCH_CFG_14 MCH_CFG_15 MCH_CFG_17 MCH_CFG_18
P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_RXN[3:0] (15)
C_PEG_TXN0_H C518 C_PEG_TXN1_H C509 C_PEG_TXN2_H C521 C_PEG_TXN3_H C519 C_PEG_TXN4 C228 C_PEG_TXN5 C219 C_PEG_TXN6 C217 C_PEG_TXN7 C230 C_PEG_TXN8 C226 C_PEG_TXN9 C508 C_PEG_TXN10 C215 C_PEG_TXN11 C224 C_PEG_TXN12 C516 C_PEG_TXN13 C514 C_PEG_TXN14 C512 C_PEG_TXN15 C510 C_PEG_TXP0_H C525 C_PEG_TXP1_H C524 C_PEG_TXP2_H C522 C_PEG_TXP3_H C520 C_PEG_TXP4 C227 C_PEG_TXP5 C218 C_PEG_TXP6 C216 C_PEG_TXP7 C229 C_PEG_TXP8 C225 C_PEG_TXP9 C523 C_PEG_TXP10 C214 C_PEG_TXP11 C223 C_PEG_TXP12 C517 C_PEG_TXP13 C515 C_PEG_TXP14 C513 C_PEG_TXP15 C511
TV
PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15
C
DMI
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40 DMI_RXN2 AM44 DMI_RXN3
(18) INT_CRT_BLU
INT_CRT_BLU
DMI_RXP[3:0] (15)
(18) INT_CRT_GRN (18) INT_CRT_RED
INT_CRT_GRN INT_CRT_RED
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39 DMI_RXP2 AM43 DMI_RXP3
H32 G32 K29 J29 F29 E29 K33 G35 F33 C32 E33
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
(18) INT_CRT_DDCCLK (18) INT_CRT_DDCDAT (18) INT_HSYNC (18) INT_VSYNC
R106 R89
INT_CRT_DDCCLK INT_CRT_DDCDAT HSYNC_A CRTIREF VSYNC_A IV@30/F_4 IV@30/F_4 EV@0_4 EV@0_4
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
R108 R103
HSYNC_A VSYNC_A CRESTLINE_1p0
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
CFG CFG
PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
VGA
(16) PM_BMBUSY# (3,14,32) ICH_DPRSTP# (13) PM_EXTTS#0 (13) PM_EXTTS#1 3,16,32) DELAY_VR_PWRGOOD (15) PLTRST#_NB (3,14) PM_THRMTRIP# (16,32) PM_DPRSLPVR
B
R61 R54
G41 L39 PM_EXTTS#0 L36 J36 AW49 RST_IN#_MCH 100_4 AV20 PM_THRMTRIP#_GMCH N20 *0_4 G36
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN
E35 A39 C38 B39 E36
+1.25V_AXD
Close U3023
To HDMI
C_PEG_TXN0_H C_PEG_TXP0_H C209 C208 [email protected]/10V_4 [email protected]/10V_4 SDVOB_RED- (20) SDVOB_RED+ (20)
B
PM PM
Close U3023
For EV@ CRT R/G/B TV A/B/C USE 0 ohm R For IV@ CRT R/G/B TV A/B/C USE 150 ohm R
C_PEG_TXN2_H C_PEG_TXP2_H C213 C212 [email protected]/10V_4 [email protected]/10V_4
M_RCOMP# R36 20/F_4
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
ME
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AM49 AK50 AT43 AN49 AM50 +1.25V_CL_VREF
CL_CLK0 (16) CL_DATA0 (16) MPWROK (16) CL_RST#0 (16)
R461 1K/F_4
SDVOB_BLUE- (20) SDVOB_BLUE+ (20)
C506
R463 392/F_6 R90 R86 R91 R78 R75 150/F_4 150/F_4 150/F_4 150/F_4 150/F_4 150/F_4 INT_CRT_BLU INT_CRT_GRN INT_CRT_RED
C_PEG_TXN1_H C_PEG_TXP1_H
C211 C210
[email protected]/10V_4 [email protected]/10V_4
SDVOB_GREEN- (20) SDVOB_GREEN+ (20)
MISC
NC NC
0.1u/10V_4
SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2
SM_RCOMP_VOH
H35 K36 G39 CLK_MCH_OE# G40 A37 GMCH_TEST1 R450 R32 GMCH_TEST2 R88
SDVO_CTRLCLK (20) SDVO_CTRLDATA (20) CLK_MCH_OE# (2) MCH_ICH_SYNC# (16) 0_4 20K_4 R126 R127 EV@0_4 EV@0_4 INT_CRT_DDCCLK INT_CRT_DDCDAT DREFCLK DREFCLK#
C_PEG_TXN3_H INT_TV_COMP INT_TV_Y/G INT_TV_C/R PEG_RXN1_H R448 1.3K_6 CRTIREF PEG_RXP1_H C_PEG_TXP3_H
C204 C203
[email protected]/10V_4 [email protected]/10V_4
SDVOB_CLK- (20) SDVOB_CLK+ (20)
+1.8VSUS
A
CRESTLINE_1p0 R113 1K/F_4 R112
R76
C120
C129 2.2u/6.3V_6 RP49 RP53
R191 R205 R190 R204
EV@0_4 IV@0_4 EV@0_4 IV@0_4
PEG_RXN1 (19) SDVOB_INT- (20) PEG_RXP1 (19) SDVOB_INT+ (20)
A
+1.8VSUS +3V
3.01K/F_4 0.01u_4
3 1 1 3
4 2
SM_RCOMP_VOL R46 R123 20/F_4 R121 M_RCOMP R122 10K_4 PM_EXTTS#1 1K/F_4 0.01u_4 2.2u/6.3V_6 10K_4 PM_EXTTS#0 R104 C115 C123 10K_4 CLK_MCH_OE#
EV@0X2 2 EV@0X2 DREFSSCLK DREFSSCLK# 4
For IV@ USE 1.3K ohm R For EV@ USE 0 ohm R
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date: Document Number
GMCH DMI/VIDEO(2 of 7)
Tuesday, January 22, 2008
1
Rev 1A 6 of 37
Sheet
5
4
3
2
5
4
3
2
1
NB(Memory controller)
(13) M_A_DQ[63:0]
D
U21D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
(13) M_B_DQ[63:0]
U21E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
C
DDR
B
www.kythuatvitinh.com
DDR
SA_RAS# SA_RCVEN# SA_WE# BE18 AY20
TP_SA_RCVEN# M_A_RAS# (12,13) M_A_WE# (12,13)
AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
BB19 BK19 BF29 BL17 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13
M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS#
(12,13) (12,13) (12,13) (12,13)
M_A_DM[7:0] (13)
A
M_A_DQS[7:0] (13)
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
M_A_DQS#[7:0] (13)
M_A_A[13:0] (12,13)
T20
BA19
AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
AY17 BG18 BG36 BE17 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 AV16 AY18
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13
M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS#
(12,13) (12,13) (12,13) (12,13)
D
M_B_DM[7:0] (13)
M_B_DQS[7:0] (13)
MEMORY
MEMORY
B
M_B_DQS#[7:0] (13)
C
M_B_A[13:0] (12,13)
SYSTEM
SYSTEM
SB_RAS# SB_RCVEN# SB_WE#
TP_SB_RCVEN#
M_B_RAS# (12,13) T13 M_B_WE# (12,13)
B
BC17
CRESTLINE_1p0
CRESTLINE_1p0
A
A
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date:
5 4 3 2
Document Number
MCH DDR(3 of 7)
Tuesday, January 22, 2008 Sheet
1
Rev 1A 7 of 37
5
4
3
2
1
NB(Power-1)
+1.05V U21G AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 U21F VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83 T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 +1.05V + C442 330u/2.5V_3528 C139 22u/10V_8 C128 0.22u/6.3V_4 C143 0.22u/6.3V_4 C117 0.1u/10V_4 AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
D
R30
VCC_13
+1.05V
+1.8VSUS
+1.8VSUS
C136 0.1u/10V_4
C
C144 22u/10V_8
C145 22u/10V_8
+1.8VSUS
C87 C112 22u/10V_8 0.22u/6.3V_4
C118 0.22u/6.3V_4
C124 0.1u/10V_4
C104 0.1u/10V_4
C142 0.1u/10V_4
+1.05V_VCC_AXG_NCTF
B
A
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
VCC AXM NCTF
VCC AXM
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C457 C464 *0.1u/10V_4 *0.1u/10V_4
AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
+1.05V_VCC_AXG_NCTF C71 [email protected]/10V_6 C64 C65 C84 IV@22u/10V_8 C63 [email protected]/10V_4 C70 [email protected]/10V_4 R74 EV@0_4
IV@1u/10V_6 IV@10u/10V_8
VCC NCTF
POWER
R82 IV@0_8
R81 IV@0_8
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
D
VCC CORE
VSS NCTF
C
POWER
VSS SCB
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 A3 B2 C1 BL1 BL51 A51
VCC SM
VCC GFX NCTF
+1.05V AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
+1.05V
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
B
VCC GFX
CRESTLINE_1p0
VCC SM LF
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
AW45 BC39 BE39 BD17 BD4 AW8 AT6
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 C62 C167 C49 0.1u/10V_4 C48 0.1u/10V_4 C46 0.22u/6.3V_4 1u/10V_6 Size 0.22u/6.3V_4 1u/10V_6 C150 0.47u/10V_6 C146
A
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Document Number
CRESTLINE_1p0 Date:
5 4 3 2
GMCH Power-1(4 of 7)
Tuesday, January 22, 2008 Sheet
1
Rev 1A 8 of 37
5
4
3
2
1
NB(Power-2)
IV&EV Dis/Enable setting
+3V R107 IV@0_6
+3V_VCCSYNC
CRT/TV Disable/Enable guideline
R105 Ball EV@0_4 VCCA_CRT VCCD_CRT Enable 3.3V 1.5V Disable GND GND GND GND GND U21H Ball VCCA_C_TVO VCCD_TVO Enable 3.3V 1.5V Disable GND 1.5V GND GND
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Signal VCCD_LVDS VCCA_LVDS VCCTX_LVDS If SDVO Disable LVDS Disable GND GND GND EXTERNAL If SDVO enable LVDS Disable 1.8V GND GND If SDVO enable LVDS enable 1.8V 1.8V 1.8V INTERNAL
D
C122 [email protected]/10V_4 +1.25V L13 C500 + IV@220u/6.3V_7343 C178 [email protected]/10V_4 +3V L35 IV@PBY160808T-301Y-N_6 C470
D
IV@10uh_8 VCCDQ_CRT 1.5V VCCA_A_TVO 3.3V C472 [email protected]/10V_4 C473 IV@22n/16V_4 R449 VCCA_B_TVO 3.3V IV@22u/10V_8 EV@0_4 VCC_SYNC 3.3V GND +1.05V +1.05V VCCABG_DAC 3.3V VSSABG_DAC GND
+1.25V
L15
IV@10uh_8 C504 + C175
+3V_TV_DAC
R444
IV@0_6 +3V_VCCA_CRT_DAC C467 C468 R447 EV@0_4 +3V_VCCA_DAC_BG [email protected]/10V_4 IV@22n/16V_4
J32 A33 B33 A30 B32 +1.25V_VCCA_DPLLA +1.25V_VCCA_DPLLB B49 H49 AL2 AM2 A41 B41
VCCSYNC VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
IV@220u/6.3V_7343
[email protected]/10V_4
VCCA_DAC_BG VSSA_DAC_BG
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL VCCA_LVDS VSSA_LVDS
+1.25V
L32
PBY160808T-301Y-N_6 C443 22u/10V_8 C45 0.1u/10V_4
+1.25VM_VCCA_HPLL +1.25VM_VCCA_MPLL
IV&EV Dis/Enable setting
+1.8VSUS_VCC_TX_LVDS
A LVDS
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 AT23 AU28 AU24 AT29 AT25 AT30 AR29 B23 B21 A21
C47 4.7u/10V_8 +1.25V_AXD
C39 4.7u/10V_8
C55 2.2u/10V_8
C44 0.47u/10V_6
CRT
VTT
R92 C90 1u/10V_6 C88 *22u/10V_8
0_6
+1.25V
PLL
R441 C450 C451 10u/10V_8
0_6
+1.25V
L33
PBY160808T-301Y-N_6 C40 R427 0.5_6 0.1u/10V_4 +3V R145 0_8 C193
C491 IV@1000p_4 +3V_VCCA_PEG_BG 0.1u/10V_4 +1.25V_VCCD_PEG_PLL +1.25VM_VCCA_SM C58 C61 4.7u/10V_6 C59 22u/10V_8 C69 1u/10V_6
C445
22u/10V_8 V1.25M_MPLL_RC C188 0.1u/10V_4 U51 AW18 AV19 AU19 AU18 AU17 AT22 AT21 AT19 AT18 AT17 AR17 AR16 VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_CK_1 VCCA_SM_CK_2
A PEG
K49
VSSA_PEG_BG
AXD
K50
VCCA_PEG_BG
VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 VCC_AXD_NCTF VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI
1u/10V_6
R467 C505 +1.25V_VCC_AXF 0.1u/10V_4
0_6
+1.25V
C
R135 R140
EV@0_4 +1.25V_VCCA_DPLLA EV@0_4 +1.25V_VCCA_DPLLB
+1.25V C444 +
R37
0_6
C
AXF
POWER
A SM
L7 C82 0.1u/10V_4 C83 R67
1uh_8 1_6 +V1.8_SMCK_RC C68
100u/6.3V_3528 *22u/10V_8
AJ50 +1.25V_VCC_DMI BK24 +1.8VSUS_VCC_SM_CK BK23 BJ24 BJ23
+1.8VSUS 22u/10V_8
+3V_TV_DAC IV@PBY160808T-301Y-N_6 +3V L34
R84
IV@0_6
+1.5V_VCCD_CRT +1.5V_VCCD_TVDAC +1.5V_VCCD_QDAC
C454
C462
M32 L29 N28
VCCD_CRT VCCD_TVDAC VCCD_QDAC VCCD_HPLL
D TV/CRT
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+1.25V R71 0_6
SM CK
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
22u/10V_8
C98
C99
C100
C102
IV&EV Dis/Enable setting
L36 IV@1uh_8
+1.25VM_VCCA_SM_CK BC29 BB29 C25 B25 C27 B27 B28 A28
A CK
IV&EV Dis/Enable setting
C463 R443
*1u/16V_6
*1u/16V_6
22u/10V_8
0.1u/10V_4
VCC_TX_LVDS VCC_HV_1 VCC_HV_2
A43
+1.8VSUS_VCC_TX_LVDS
+1.8VSUS
R130
C453
[email protected]/10V_4
IV@22n/16V_4
EV@0_4
PEG
R87
EV@0_4
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
HV
C40 B40
+3V_VCC_HV
C492
+ C489
EV@0_4
IV@1000p_4
IV@220u/6.3V_7343
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
AD51 W50 W51 V49 V50
TV
+VCC_PEG
[email protected]/10V_4
IV@22n/16V_4 +1.25V R27 0_6 C43 0.1u/10V_4 +1.25VM_MCH_VCCD_HPLL +1.25V_VCCD_PEG_PLL
DMI
VCC_RXR_DMI_1 VCC_RXR_DMI_2 VTTLF1 VTTLF2 VTTLF3
AH50 AH51
L37
91nH
+1.05V
C503 + C501 10u/10V_8 220u/6.3V_7343 C42 0.47u/6.3V_4 C446 0.47u/6.3V_4 C448 0.47u/6.3V_4
AN2 U48 J41 H42
VCCD_PEG_PLL VCCD_LVDS_1 VCCD_LVDS_2
B
LVDS
VTTLF
A7 F2 AH1
C455 IV@22u/10V_8
C456 IV@10u/10V_8
C461 [email protected]/10V_4
C460 IV@22n/16V_4 +1.25V L17 PBY160808T-301Y-N_6
B
CRESTLINE_1p0 R149 1_8 +V1.25S_PEGPLL_FB C197 10u/10V_8 C180 0.1u/10V_4
INT VGA disable VCCD_TVDAC still +1.5V
+1.5V R68 0_6 C97 0.1u/10V_4 R69 IV@100/F_6 IV@1u/10V_6 C75 [email protected]/10V_4 C76 IV@22n/16V_4 C77 IV@1u/10V_6 R77 EV@0_4 IV@10u/10V_8 EV@0_4 C103 22n/16V_4 +1.8VSUS R457 IV@0_6 C153 +1.8V_VCCD_LVDS C482 R455 +3V R453 0_4 C480 0.1u/10V_4 R446 10_4 +1.05V D37 2 1 PDZ5.6B +1.05V_SD +3V_VCC_HV
A
A
+3V_VCCSYNC R109 IV@10_4 VCCGFPLLOW D8 1 2
+1.05V [email protected]
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date:
5 4 3 2
Document Number
GMCH Power-2(5 of 7)
Tuesday, January 22, 2008
1
Rev 1A 9 of 37
Sheet
5
4
3
2
1
NB(Power-3)
U21I U21J
D
C
www.kythuatvitinh.com
VSS
B
A
A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286
VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
D
VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
C
K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
B
CRESTLINE_1p0
A
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Date: Document Number
CRESTLINE_1p0
GMCH Power-3(6 of 7)
Tuesday, January 22, 2008 Sheet
1
Rev 1A 10 of 37
5
4
3
2
5
4
3
2
1
Strap table
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal CFG[17:3] Have internal Pull-up CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin Pin Name CFG[2:0]
D
Strap description FSB Frequency Select
Configuration 010 = FSB 800MHz 011 = FSB 667MHz
D
CFG[4:3] CFG5
Reserved DMI X2 Select 0 = DMI X2 1 = DMI X4(Default)
CFG6 CFG7
Reserved CPU Strap 0 = Reserved 1 = Mobile CPU(Default) 0 = Normal mode 1 = Low Power mode 0 = Reverse Lanes 1 = Normal operation(Default)
CFG8
Low power PCI Express
CFG9
PCI Express Graphics Lane Reversal
CFG[11:10]
C
Reserved XOR/ALLZ 00 01 10 11 = = = = Reserved XOR Mode Enable All-Z Mode Enabled Normal operation(Default)
C
CFG[13:12]
CFG[15:14] CFG16
CFG[18:17]
SDVO_CTRLDATA
CFG19
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Reserved FSB Dynamic ODT 0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default) Reserved SDVO Present 0 = No SDVO Card present(Default) 1 = SDVO Card Present 0 = Normal operation(Default) 1 = Reverse Lanes DMI Lane Reversal SDVO/PCIe concurrent 0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
B
CFG20
B
DMI X2 Select
MCH_CFG_5 Low = DMIX2 High = IDMIX4(Default)
DMI Lane Reversal
MCH_CFG_19 Low = Normal operation(Default) High = Reverse Lane
XOR /ALLz /Clock Un-gating
MCH_CFG_12MCH_CFG_13 0 0 1 0 1 Configuration Clock gating disable XOR Mode Enable ALL-z Mode Enable
PCI Express Graphics
MCH_CFG_9 Low = Reverse Lane High = Normal operation(Default)
SDVO Present Strap define at External DVI control page
(6) MCH_CFG_5
+3V 0 1 R59 R115 *4.02K_4 *4.02K_4 1 Normal operation(Default)
(6) MCH_CFG_9
R62 *4.02K_4
(6) MCH_CFG_19
FSB Dynamic ODT
MCH_CFG_16 Low = ODT Disable High = ODT Enable(Default)
SDVO/PCIE Concurrent operation
MCH_CFG_20 Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port (6) MCH_CFG_12 (6) MCH_CFG_13
A
A
(6) MCH_CFG_16
+3V
R58 R53 *4.02K_4 *4.02K_4 R114 *4.02K_4
R60 *4.02K_4
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Size Document Number
(6) MCH_CFG_20 Date:
5 4 3 2
GMCH Strap(7 of 7)
Tuesday, January 22, 2008
1
Rev 1A Sheet 11 of 37
1
2
3
4
5
6
7
8
DDR2 Dual channel A/B PU
A
A
M_A_A[13..0] M_B_A[13..0]
M_A_A[13..0] (7,13) M_B_A[13..0] (7,13)
DDRII A CHANNEL
+SMDDR_VTERM
DDRII B CHANNEL
+SMDDR_VTERM
C85 0.1u/10V_4
C148 0.1u/10V_4
C93 0.1u/10V_4
C189 0.1u/10V_4
C141 0.1u/10V_4
C164 0.1u/10V_4
C89 0.1u/10V_4
C96 0.1u/10V_4
C186 0.1u/10V_4
C176 0.1u/10V_4
C86 0.1u/10V_4
C177 0.1u/10V_4
C91 0.1u/10V_4
C187 0.1u/10V_4
C160 0.1u/10V_4
C92 0.1u/10V_4
C111 0.1u/10V_4
C95 0.1u/10V_4
C166 0.1u/10V_4
C181 0.1u/10V_4
C190 0.1u/10V_4
C140 0.1u/10V_4
C110 0.1u/10V_4
C161 0.1u/10V_4
C179 0.1u/10V_4
C138 0.1u/10V_4
B
B
M_A_A3 M_A_A1 M_A_A9 M_A_A5 M_A_A4 M_A_A2
RP17
1 3 1 3 1 3 1 3 1 3 1 3 1 3
2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4
+SMDDR_VTERM
(6,13) M_CKE1
(7,13) M_A_BS#2
(6,13) M_CKE0
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RP22 M_A_A7 M_A_A6 RP23 1 3 1 3 1 3 2 56X2 4 2 56X2 4 +SMDDR_VTERM RP20 (6,13) M_CKE3 (7,13) M_B_BS#2 RP30 RP28 M_A_A11 (6,13) M_CS#1 (6,13) M_ODT1 RP6 2 56X2 4 RP25 M_A_A8 (6,13) M_ODT3 (7,13) M_B_CAS# RP7 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 2 56X2 4 2 56X2 4 2 56X2 4
C
RP29
M_A_A12
M_A_A10
RP16
(7,13) M_A_BS#0 (7,13) M_A_RAS# (7,13) M_A_BS#1
C
RP15
(7,13) M_A_WE# (7,13) M_A_CAS# (6,13) M_CS#0
RP12
RP11 M_A_A0 RP10
2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4
M_B_A10 (7,13) M_B_BS#0 M_B_A5 M_B_A3
RP14
1 3 1 3 1 3 1 3 1 3 1 3 1 3
2 56X2 4 2 56X2 4 2 56X2 4 2 56X2 4
+SMDDR_VTERM (7,13) M_B_WE# (6,13) M_CS#3 (6,13) M_CKE4
RP19
RP27 M_B_A6 RP9
(7,13) M_B_BS#1
RP13 M_B_A0 M_B_A7 M_B_A11 M_B_A8 M_B_A1 M_B_A4 M_B_A2 M_B_A9 M_B_A12 RP21
(6,13) M_ODT2 (7,13) M_B_RAS# M_A_A13 (6,13) M_ODT0
RP5
RP24
2 56X2 4 2 56X2 4 2 56X2 4
(6,13) M_CS#2
RP8 M_B_A13
RP18
RP26
D
D
(6,13) M_A_A14 (6,13) M_B_A14
R128 R125
56_4 56_4
+SMDDR_VTERM Size Date:
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Document Number
DDR RES. ARRAY
Tuesday, January 22, 2008
7
Rev 1A Sheet 12
8
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37
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8
DDR2 Dual channel A/B CONN SMDDR_VREF_DIMM
+1.8VSUS CN21 M_A_DQ5 M_A_DQ6 M_A_DQS#0 M_A_DQS0
A
+1.8VSUS
M_A_DM[0..7] (7) M_A_DQ[0..63] (7) M_A_DQS[0..7] (7) M_A_DQS#[0..7] (7) M_A_A[0..13] (7,12)
SMDDR_VREF_DIMM +1.8VSUS CN22 M_B_DQ5 M_B_DQ4 M_B_DQS#0 M_B_DQS0 M_B_DQ2 M_B_DQ3 M_B_DQ8 M_B_DQ9 M_B_DQS#1 M_B_DQS1 M_B_DQ14 M_B_DQ15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 M_B_DQ0 M_B_DQ1 +1.8VSUS
M_B_DM[0..7] (7) M_B_DQ[0..63] (7) M_B_DQS[0..7] (7) M_B_DQS#[0..7] (7) M_B_A[0..13] (7,12)
+1.8VSUS
M_A_DQ3 M_A_DQ2 M_A_DQ9 M_A_DQ8 M_A_DQS#1 M_A_DQS1 M_A_DQ14 M_A_DQ11
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD)
VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
M_A_DQ4 M_A_DQ0 M_A_DM0 M_A_DQ7 M_A_DQ1 M_A_DQ13 M_A_DQ12 M_A_DM1 M_CLK_DDR0 (6) M_CLK_DDR#0 (6) M_A_DQ10 M_A_DQ15
+ C465 M_B_DM0 *330u/2.5V_3528 M_B_DQ7 M_B_DQ6 M_B_DQ12 M_B_DQ13 M_B_DM1 C169 M_CLK_DDR3 (6) M_CLK_DDR#3 (6) M_B_DQ11 M_B_DQ10 0.1u/10V_4 C135 +1.8VSUS
C163 2.2u/6.3V_6
C130 2.2u/6.3V_6
C481 2.2u/6.3V_6
C476 2.2u/6.3V_6 +3V
C113 2.2u/6.3V_6
A
C33 C471 0.1u/10V_4 C108 2.2u/6.3V_6 0.1u/10V_4 0.1u/10V_4 SMDDR_VREF_DIMM
C31 0.1u/10V_4
M_A_DQ16 M_A_DQ21 M_A_DQS#2 M_A_DQS2 M_A_DQ23 M_A_DQ19 M_A_DQ28 M_A_DQ25 M_A_DM3 M_A_DQ26 M_A_DQ27
B
PC4800 DDR2 SDRAM SO-DIMM (200P)
(6,12) M_CKE0 (7,12) M_A_BS#2 M_A_A12 M_A_A9 M_A_A8 M_A_A5 M_A_A3 M_A_A1
M_A_A10 (7,12) M_A_BS#0 (7,12) M_A_WE# (7,12) M_A_CAS# (6,12) M_CS#1 (6,12) M_ODT1
M_A_DQ36 M_A_DQ33
M_A_DQS#4 M_A_DQS4 M_A_DQ39 M_A_DQ34 M_A_DQ40 M_A_DQ41
C
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C34 C32 M_A_A4 M_A_A2 M_A_A0 M_B_A5 M_B_A3 M_B_A1 M_B_A4 M_B_A2 M_B_A0 2.2u/6.3V_6 C121 C159 C149 C168 SMDDR_VREF_DIMM M_B_A10 M_A_BS#1 (7,12) M_A_RAS# (7,12) M_CS#0 (6,12) M_ODT0 (6,12) (7,12) M_B_BS#0 (7,12) M_B_WE# M_B_BS#1 (7,12) M_B_RAS# (7,12) M_CS#2 (6,12) M_ODT2 (6,12) 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 C237 C234 M_A_A13 (7,12) M_B_CAS# (6,12) M_CS#3 0.1u/10V_4 2.2u/6.3V_6 M_B_A13
M_A_DM5 M_A_DQ46 M_A_DQ42 M_A_DQ48 M_A_DQ53
M_A_DQS#6 M_A_DQS6 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ60 M_A_DM7 M_A_DQ62 M_A_DQ63 CGDAT_SMB CGCLK_SMB +3V
+3V
VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1
M_A_DQ20 M_A_DQ17 M_A_DM2 M_A_DQ18 M_A_DQ22 M_A_DQ29 M_A_DQ24 M_A_DQS#3 M_A_DQS3 M_A_DQ30 M_A_DQ31 (6,12) M_CKE3 M_CKE1 (6,12) (7,12) M_B_BS#2 M_A_A14 (6,12) M_A_A11 M_A_A7 M_A_A6 PM_EXTTS#0 (6)
M_B_DQ20 M_B_DQ17 M_B_DQS#2 M_B_DQS2 M_B_DQ23 M_B_DQ22 M_B_DQ28 M_B_DQ25 M_B_DM3 M_B_DQ30 M_B_DQ31
M_B_DQ21 M_B_DQ16 M_B_DM2 M_B_DQ18 M_B_DQ19 M_B_DQ24 M_B_DQ29 +1.8VSUS M_B_DQS#3 M_B_DQS3 M_B_DQ26 M_B_DQ27 M_CKE4 (6,12) M_B_A14 (6,12) M_B_A11 M_B_A7 M_B_A6 + C474 *330u/2.5V_3528 C493 2.2u/6.3V_6 C466 PM_EXTTS#1 (6)
C236 0.1u/10V_4
C233 2.2u/6.3V_6
PC4800 DDR2 SDRAM SO-DIMM (200P)
Close to DIMM0
C158 2.2u/6.3V_6
C490 2.2u/6.3V_6
C147 2.2u/6.3V_6
B
2.2u/6.3V_6
+3V
INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM
M_B_A12 M_B_A9 M_B_A8
+1.8VSUS 0.1u/10V_4
Close to DIMM1
(6,12) M_ODT3
M_A_DQ32 M_A_DQ37 M_A_DM4
M_B_DQ32 M_B_DQ36
M_B_DQ37 M_B_DQ38 M_B_DM4
M_B_DQS#4 M_B_DQS4 M_B_DQ35 M_B_DQ34 M_B_DQ41 M_B_DQ40 M_B_DM5
M_A_DQ35 M_A_DQ38 M_A_DQ44 M_A_DQ45 M_A_DQS#5 M_A_DQS5 M_A_DQ43 M_A_DQ47 M_A_DQ49 M_A_DQ52 M_CLK_DDR1 (6) M_CLK_DDR#1 (6) M_A_DM6 M_A_DQ55 M_A_DQ54 M_A_DQ61 M_A_DQ57 M_A_DQS#7 M_A_DQS7 M_A_DQ58 M_A_DQ59 R23 R21 10K_4 10K_4
M_B_DQ39 M_B_DQ33 M_B_DQ44 M_B_DQ45
M_B_DQS#5 M_B_DQS5 M_B_DQ42 M_B_DQ47 M_B_DQ53 M_B_DQ48 CGCLK_SMB M_CLK_DDR4 (6) M_CLK_DDR#4 (6) M_B_DM6 M_B_DQ51 M_B_DQ54 M_B_DQ60 M_B_DQ61 M_B_DQS#7 M_B_DQS7 M_B_DQ62 M_B_DQ59 R24 R22 +3V 10K_4 10K_4 R194 R203 *10K_4 R195 0_6 *10K_4 +SMDDR_VREF +1.8VSUS SMDDR_VREF_DIMM CGDAT_SMB CGCLK_SMB (2) CGDAT_SMB (2)
C
M_B_DQ43 M_B_DQ46 M_B_DQ52 M_B_DQ49
M_B_DQS#6 M_B_DQS6 M_B_DQ55 M_B_DQ50 M_B_DQ56 M_B_DQ57 M_B_DM7 M_B_DQ58 M_B_DQ63 CGDAT_SMB CGCLK_SMB +3V
TYCO_292532-4
TYCO_1775803-2
D
SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30
SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34
D
Standard Type H: 6.5mm
CLOCK 0,1
CKE 0,1
Standard Type H: 11mm
CLOCK 3,4
CKE 2,3
Size Date:
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
Document Number
DDR SO-DIMM(200P)
Tuesday, January 22, 2008
7
Rev 1A Sheet 13
8
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37
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6
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4
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1
RTC
+3VPCU D24
VCCRTC
CH500H-40
VCCRTC
C636
1u/10V_6
01/21 REV_3B Change footprint
D25 CH500H-40 R571 2 1M_6 CN14 1 1 2 2 ACS_85204-0200L R579 20K_6 1
VCCRTC_4 R569 1K_4
D
Delay 18~25ms
G1 *SHORT_PAD C642 1u/10V_6
C367
15p_4 3 4
32.768KHZ Y4 2 1
R323 10M_6 CLK_32KX1 CLK_32KX2 RTCRST# AG25 AF24 AF23 U33A RTCX1 RTCX2 RTCRST# INTRUDER# FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 FWH4/LFRAME# E5 F5 G8 F6 C4 G9 E6 AF13 AG26 AF26 AE26 AD24 AG29 AF27 AE24 AC20 AH14 AD23 AG28 AA24 AE27 AA23 V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 H_THERMTRIP_R ICH_TP8 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDA0 PDA1 PDA2 T52 PDD[15:0] (22) R287 H_PWRGD (3) H_IGNNE# (3) H_INIT# (3) H_INTR (3) RCIN# (29) H_NMI (3) H_SMI# (3) H_STPCLK# (3) 24/F_6 LDRQ#1 GATEA20 LAD0 LAD1 LAD2 LAD3 (25,29) (25,29) (25,29) (25,29) +1.05V_V_CPU_IO
D
C366
15p_4
SM_INTRUDER# AD22
LFRAME# (25,29) T46 LDRQ#1 (25) GATEA20 (29) H_A20M# (3) ICH_DPRSTP# (3,6,32) H_DPSLP# (3)
CMOS Setting Clear CMOS Keep CMOS
G1 Short Open
ICH_INTVRMEN LAN100_SLP
AF25 AD21 B24 D22 C21 B21 C22 D21 E20 C20 AH21
INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GLAN_DOCK#/GPIO13 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
RTC LPC
LDRQ0# LDRQ1#/GPIO23 A20GATE A20M# DPRSTP# DPSLP#
R309 56.2_4
VCCRTC_3
01/15 REV_3B Change R574 footprint
+5VPCU R574 R582 6.8K/F_4
C
LAN / GLAN CPU
FERR#
H_FERR# (3)
CPUPWRGD/GPIO49 IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#
2K/F_4
VCCRTC_1 R568
2K/F_4
VCCRTC_2 3 Q47 MMBT3904
1
+1.5V_PCIE
R255
24.9/F_4 GLAN_COMP_SB ACZ_BCLK ACZ_SYNC ACZ_RST#
D25 C25 AJ16 AJ15 AE14 AJ17 AH17 AH15 AD13 AE13
RCIN#
+1.05V_V_CPU_IO
R283 56.2_4 R285 *0_4 PM_THRMTRIP# (3,6)
C
2
(26) ACZ_SDIN0 T90 R585 15K_4
10/25 REV_A1 Change value 01/08 REV_3B Change value
+3V
IHDA
(20) ACZ_SDIN2 T55
ACZ_SDIN2 ACZ_SDIN3 ACZ_SDOUT
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT
TP8 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
12/04 REV_3A Swap SATA channel
SATA Disable
B
T84 T85 T82 T83
C613 C614 C350 C353
*3900p_4 *3900p_4 *3900p_4 *3900p_4
SATA_RXN2_C SATA_RXP2_C SATA_TXN2_C SATA_TXP2_C
AF2 AF1 AE4 AE3
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
SATA
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R364 *10K_4 +3V +3V T56 T60 AE10 AG14 AF10 HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED# (22) SATA_LED# SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_LED# R547 R352 R520 R522 *10K_4 *10K_4 SATA_RXN2_C SATA_RXP2_C (2