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A
B
C
D
E
Compal confidential
Model Name : CY23 LA-1281 Rev1.0
Block Diagram
1
INTEL FC-PGA370
APICCLK
1
CRT Connector
page 14 HA#(3..31)
HCLK_CPU
Page 2,3 HD#(0..63)
HCLK_NB PCLK_NB
DCLKWR DCLKO
CLK_SDRAM0 CLK_SDRAM2,3
2
Y1 14.318MHZ 14MOSC
TV_OUT Connector
page 13
Twister PN-133T (VT8606) PCIGNT#/PCIREQ#
page 4,5,6 PIRQA#
MD(0..63) MA(0..13)
Clock Generator
ICS 9248-195
14MCRT/14.3M_TV PCLK_1394 PCLK_PCM PCLK_MINI
page 11
TFT Panel Interface
2
page 14
Memory Damping Resistor
page 6
page 7
PCI BUS
GNT#0/REQ#0 GNT#1/REQ#1 page 23 AD27/AD28
3
Mini PCI Socket PIRQB#/PIRQD#
CardBus OZ6933
PIRQA#/PIRQB# GNT#3/REQ#3 AD15 page 15
IEEE 1394
PIRQC# GNT#2/REQ#2 AD24
USB Port 0,1 FIR
PCLK_SB
On Board 64/128MB (Bank 0)
AD(0..31)
SO-DIMM 0 (Bank 2,3)
page 8
page 29
AC97 Interface
page 27
VT686B
page 9,10
48MHZ 14MOSC
page 25
IDE CHANNEL 1
DIRECT CD-PLAY FUNCTION
page 18
Slot 0&1
page 16
Slot 0
page 29
SA(0..15) SD(0..15)
Pull Up/Down Resistor IDE Damping Resistor
page 17 page 12
3
Power On/Off Reset Circuit
page 28
ISA BUS
KeyBoard 87570 page 20
DC/DC Interface RTC Battery
page 22
IDE Connector (FDD/HDD/CR-ROM)
page 19
page 24
PIO
I/O Buffer
page 21
4
page 21
4
KBD
Power Circuit DC/DC
page 30,31,32,33
page 21
BIOS
Touch Pad
page 26
Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-1281
Document Number
PROPRIETARY NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Size B Date:
401202
, 22, 2001 Sheet
E
Rev 1B 1 of 34
A
B
A
B
C
D
E
+5VS 4 HA#[3..31] 1 R90 200 C79 .1UF 2 1617VCC U6 1 C80 THERMDA THERMDC 1 2 3 4 5 6 7 8 NC VCC DXP DXN NC ADD1 GND GND MAX1617 NC STBY SMBCLK NC SMBDATA ALERT ADD0 NC 16 15 14 13 12 11 10 9 2 1 HA#[3..31] HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 X6 AC1 W3 AF4 AK18 AH16 AH18 AL19 AL17 AN23 AN31 AK24 AL11 AN13 V4 B36 AE35 4 4 4 4 4 4 4 BREQ0# BPRI# BNR# HLOCK# HIT# HITM# DEFER# BREQ0# BPRI# BNR# LOCK# HIT# HITM# DEFER# AN29 AN17 AH14 AK20 X2 AL25 AL23 AN19 G33 E37 C35 E35 AN25 AH26 AH22 AK28 AC37 U38A A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# REQ0# REQ1# REQ2# REQ3# REQ4# RP# ADS# AERR# AP0# AP1# BERR# BINIT# IERR# BR0# BPRI# BNR# LOCK# BR1#/RSVD* HIT# HITM# DEFER# BP2# BP3# BPM0# BPM1# TRDY# RS0# RS1# RS2# RSP# A20M# FERR# IGNNE# PWRGOOD SMI# TDO TDI TMS TRST# TCK PREQ# PRDY# BSEL0 BSEL1 INTR/LINT0 NMI/LINT1 STPCLK# SLP# THERMDA THERMDC FC-PGA2 SELPSB[1:0] 00 01 10 11
A
HD#[0..63] D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DBSY# DRDY# DIAGNOSTIC & TEST SIGNALS PICCLK PICD1 PICD0 INIT# FLUSH# RESET# RESET2#/VSS* BCLK EDGCTRL/VTT* J33 L35 J35 AG33 AE37 AH4 X4 W37 AG1 3 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9 A9 D8 D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16 C33 C31 A33 A31 E31 C29 E29 A29 AL27 AN27 DBSY# DRDY# HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
HD#[0..63] 4
FC-PGA2
4
VCMOS VCMOS +3VS
from 87570
SMC SMD 18,20,24 18,20,24
4
2200PF 2
2
2
R64 1.5K
R67 1.5K
R73 10K
1
21
1
2
ATF#
21
1 R89 1K 9,27,32 VR_POK 1 D7 RB751V 2 PWRGD_CPU 1 R27 1 R395 2 +2.5V_CLK 180 2 @1.8K
1 R96 1K +5VS 2
FERR#1.5
3
1
FERR#
9
Q5 FDV301N
REQUEST PHASE SIGNALS
DATA PHASE SIGNALS
2
CPU_IO
3
4 4 4 4 4
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 ADS#
BREQ0# RS#2 DBSY# DRDY#
8 7 6 5
1 2 3 4 RP2 @8P4R-56
HA#5 HA#13 HA#10 HA#12
8 7 6 5
1 2 3 4 RP6 @8P4R-56 1 2 3 4 RP14 @8P4R-56 1 2 3 4 RP20 @8P4R-56 1 2 3 4 RP19 @8P4R-56 1 2 3 4 RP22 @8P4R-56 1 2 3 4 RP9 @8P4R-56 1 2 3 4 RP10 @8P4R-56 1 2 3 4 RP11 @8P4R-56 1 2 3 4 RP8 @8P4R-56
HD#39 HD#36 HD#37 HD#38
1 2 3 4
8 7 6 5 RP43 @8P4R-56 8 7 6 5 RP44 @8P4R-56 8 7 6 5 RP45 @8P4R-56 8 7 6 5 RP46 @8P4R-56 8 7 6 5 RP47 @8P4R-56 8 7 6 5 RP48 @8P4R-56 8 7 6 5 RP49 @8P4R-56 1 2 3 4 RP7 @8P4R-56 1 2 3 4 RP1 @8P4R-56
HD#1 HD#5 HD#8 HD#17
8 7 6 5
1 2 3 4 RP25 @8P4R-56 1 2 3 4 RP24 @8P4R-56 1 2 3 4 RP28 @8P4R-56 1 2 3 4 RP27 @8P4R-56 1 2 3 4 RP31 @8P4R-56 1 2 3 4 RP30 @8P4R-56 8 7 6 5 RP42 @8P4R-56 8 7 6 5 RP41 @8P4R-56 8 7 6 5 RP40 @8P4R-56
3
4 ADS#
ERROR SIGNALS
IGNNE# A20M# INTR NMI PRDY# SLP# CPUINIT# STPCLK# FLUSH# SMI# PREQ#
1 2 3 4
RP26
HA#16 HA#15 HA#28 HA#31 8 7 6 5 2 150 2 150 2 150 2 150 2 150 2 150 2 330 VCMOS HA#19 HA#25 HA#22 HA#17
8 7 6 5
HD#27 HD#42 HD#45 HD#44
1 2 3 4
HD#0 HD#4 HD#15 HD#6
8 7 6 5
8P4R-150 1 R151 1 R54 1 R61 1 R53 1 R57 1 R47 1 R127
ARBITRATION PHASE SIGNALS SNOOP PHASE SIGNALS RESPONSE PHASE SIGNALS
8 7 6 5
HD#40 HD#41 HD#49 HD#51
1 2 3 4
HD#12 HD#10 HD#9 HD#18
8 7 6 5
HA#23 HA#24 HA#20 HA#27
8 7 6 5
HD#48 HD#63 HD#52 HD#47
1 2 3 4
HD#14 HD#2 HD#3 HD#11
8 7 6 5
2
4 4 4 4 3 3 9
HTRDY# RS#0 RS#1 RS#2 A20M# IGNNE# SMI# 1 2 3 4
HTRDY# RS#0 RS#1 RS#2
HA#30 HA#29 HA#18 HA#26 CPU_IO HREQ#2 HREQ#0 HREQ#4 BPRI#
8 7 6 5
HD#46 HD#55 HD#57 HD#59
1 2 3 4
HD#13 HD#20 HD#7 HD#16
8 7 6 5
2
CPURST# ADS#
A20M# AE33 FERR#1.5 AC35 IGNNE# AG37 PWRGD_CPU AK26 SMI# AJ35 8 7 6 5 PWRGD_CPU PREQ# PRDY# AN37 AN35 AK32 AN33 AL33 J37 A35 AJ33 AJ31 M36 L37 AG35 AH30 AL31 AL29
1 R26 1 R7
2 56.2_1% 2 @56.2_1%
PC COMPATIBILITY SIGNALS
8 7 6 5
HD#50 HD#58 HD#53 HD#54
1 2 3 4
HD#19 HD#24 HD#30 HD#22
8 7 6 5
DBSY# DRDY#
4 4
RS#1 HLOCK# HREQ#3 DEFER#
8 7 6 5
HD#61 HD#56 HD#62 HD#60
1 2 3 4
HD#43 HD#34 HD#32 HD#28
1 2 3 4
6 6,11 +3VS
BSEL0 BSEL1 2 2 2 NMI C533 reserve for Intel Celeron ,VIA recommend 1 R6 1 R5 1 R10 NMI 1K 1K @1K 3 9 9 C139 1UF
RP98 8P4R-1K
INTR STPCLK# SLP#
INTR STPCLK# SLP# THERMDA THERMDC
3
EXECUTION CONTROL SIGNALS THERMAL DIODE
R117 R131 CPUINIT# FLUSH# CPURST# R94 1 R396 2 Q56 FDV301N 1
150 150
APICCLK 11 VCMOS CPUINIT# 9 CPURST# 4,9
RS#0 HIT# HTRDY# HITM#
8 7 6 5
HA#4 HA#8 HA#11 HA#9
8 7 6 5
HD#31 HD#25 HD#29 HD#35
1 2 3 4
1
1K 2 1K
HCLK_CPU 11 2 R97 TUAL5 1 1 10 3,11,32 C94 2 10PF
1
* For Intel New CPU
HREQ#1 HA#7 BNR# HA#14
8 7 6 5
HA#3 HA#6 HA#21
8 7 6 5
HD#23 HD#21 HD#26 HD#33
1 2 3 4
2
1
STSEM BUS FREQUENCY 66MHZ 100MHZ RESERVED PROPRIETARY NOTE 133MHZ
B
CPU_IO Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Compal Electronics, Inc.
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 2 of 34
A
B
C
D
E
U38B CPU_IO 1 C181 AD36 Z36 E33 F18 K4 R6 V6 AD6 AK12 AK22 AA37 AA5 AB2 AB34 AD32 AE5 E5 E9 F14 F2 F22 F26 F30 F34 F4 H32 H36 J5 K2 K32 K34 M32 N5 P2 P34 R32 R36 S5 T2 T34 V32 V36 W5 X34 Y35 Z32 AF2 AF34 AH24 AH32 AH36 AJ13 AJ17 AJ21 AJ25 AJ29 AJ5 AK2 AK34 AM12 AM16 AM20 AM24 AM28 AM32 AM4 AM8 B10 B14 B18 B22 B26 B30 B34 B6 C3 D20 D24 D28 D32 D36 D6 E13 E17 AJ9 R353 56_1% 2 2 R149 110_1%
1
PROPRIETARY NOTE AM22 AM26 AM30 AM34 AM6 AN3 B12 B16 B20 B24 B28 B32 B4 B8 D18 D2 D22 D26 D30 D34 D4 E11 E15 E19 E7 F20 F24 F28 F32 F36 G5 H2 H34 K36 L5 M2 M34 P32 P36 A37 AB32 AC33 AC5 AD2 AD34 AF32 AF36 AG5 AH2 AH34 AJ11 AJ15 AJ19 AJ23 AJ27 AJ3 AJ7 AK36 AK4 AL1 AL3 AM10 AM14 AM18 Q5 R34 T32 T36 U5 V2 V34 X32 X36 Y37 Y5 Z2 Z34
.1UF 2
VCCTREF
4
R150 CPU_IO 1 75_1% 2 1 1 R118 .1UF 150_1% 2 2 2 .1UF .1UF 2 VCCTREF 1 1 C166 C144 C110
VCCTREF VCMOSREF 1
C60
4.7UF_0805 VCMOSREF R400 VCMOS 1 75_1% 2 1 1 C501 .1UF 150_1% 2 2 CPU_CORE R401
3
1 2 3 4
CPU_IO
1
1
1
1
1
1
1
1
1
1
C101 C88 .1UF 2
C425 C76 .1UF 2
C63
C62
C61
C77
C87
C120 C149 .1UF 2 9 9 SB_INTR SB_NMI CRESET# SB_INTR SB_NMI CRESET#
1
+5V
R402 10K 2 2
R403 2.7K 2
R404 2.7K TUAL5 Q57 FDV301N 3 2,11,32
2 C TUALDET
2
2 B E 3
2
2
2
2
2
2
2
2
2
2
2
TUAL5#
11
Q58 FMMT3904
VSS0 VSS1 VSS2 VSS3 VSS4 VREF0 VSS5/DYN_OE* VREF1 VSS6 VREF2 VSS7 VREF3 VSS8 VREF4 VSS9 VREF5 VSS10 VREF6 VSS11 VREF7/VCMOS_REF* VSS12 VSS13 VCC0 VSS14 VCC1 VSS15 VCC2 VSS16 VCC3 VSS17 VCC4 VSS18 VCC5 VSS19 VCC6 VSS20 VCC7 VSS21 VCC8 VSS22 VCC9 VSS23 VCC10 POWER, VSS24 VCC11 GROUND, VSS25 VCC12 RESERVED VSS26 VCC13 SIGNALS VSS27 VCC14 VSS28 VCC15 VSS29 VCC16 VSS30 VCC17 VSS31 VCC18 VSS32 VCC19 VSS33 VCC20 VSS34 VCC21 VSS35 VCC22 VSS36 VCC23 VSS37 VCC24 VSS38 VCC25 VSS39 VCC26 VSS40 VCC27 VSS41 VCC28 VSS42 VCC29 VSS43 VCC30 VSS44 VCC31 VSS45 VCC32 VSS46/DETECT* VCC33/VTT* VSS47 VCC34 VSS48 VCC35 VSS49 VCC36 VSS50 VCC37 VSS51 VCC38 VSS52 VCC39 VSS53 VCC40 VSS54 VCC41 VSS55/RESET2#* VCC42 VSS56 VCC43 VSS57/VID_25mV* VCC44 VSS58/VTT_PWRGD* VCC45 VSS59/RSVD* VCC46 VSS60 VCC47 VSS61 VCC48 VSS62 VCC49 VSS63 VCC50 VSS64 VCC51 VSS65 VCC52 VSS66 VCC53 VSS67 VCC54 VSS68 VCC55 VSS69 VCC56 VSS70 VCC57 VSS71 VCC58 VSS72 VCC59 VSS73 VCC60 VSS74 VCC61 VSS75 VCC62 VSS76 VCC63 VCC64 VCC65 VCC66 PLL1 VCC67 PLL2 VCC68 VCC69 VCC70 VCC71 VEDT/RSVD* VCC72 VCC73 VCC74 VCC1.5/VTT* VCC2.5/RSVD*
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CPU_IO AH20 AK16 AL13 AL21 AN11 AN15 G35 AA33 AA35 AN21 E23 S33 S37 U35 U37 CPU_IO RP13 RSVD/VTT* RSVD RSVD RSVD RSVD/NCHCTRL* RSVD RSVD RSVD RSVD POWER AND NC RSVD RSVD RSVD RSVD/KEY* RSVD G37 L33 N33 N35 N37 Q33 Q35 Q37 R2 W35 Y1 AK30 AM2 F10 AL35 AM36 AL37 AJ37 VID1 VID2 VID0 VID3 1 R398 VID4 1 R399 14_1% CPU_IO VID0 VID1 VID2 VID3 2 2 10K 1 2 3 4 8 7 6 5
4
R397 1K DYN_OE 1 1 1 2 1 CPU_IO 1 1 1 1 1 1
CPU_IO
U38C VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
+5V
C218 C217 C216 C215 C214 C213 C212 C211 C210 C209 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .1UF 2
.1UF 2
1
NCHCTRL
CPU_IO
FC-PGA370
8P4R-10K
FC-PGA370
1
1
1
1
1
1
1
1
1
C186 C185 C5 .1UF 2 .1UF 2
C141 C119 C111 C9 .1UF 2 .1UF 2 .1UF 2
C47
C11
1 2
C12
2
.1UF 2
.1UF 2
.1UF 2
.1UF 2
.1UF
CPU_IO
VID0 VID1 VID2 VID3
+ C6 220UF_E
1
C10
.1UF 2
* For Intel New CPU
CPU_CORE
FC-PGA370
1
1
1
1
1
1
1
1
1
1
C427
C429 C434 C445 C446 C441 C442 C443 C444 C433 C428 1UF 1UF 2 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF VCMOS 8 7 6 5 +3VS RP58 C266 U18 9 SB_A20M# SB_A20M# SB_IGNNE# 2 3 5 6 11 10 14 13 1 IOA IOA IOB IOB YB I1C I1C YC I1D I1D YD S GND E# @QS3257 VCC YA 16 4 7 9 12 8 15 A20M# IGNNE# INTR NMI 1 2 @.1UF A20M# IGNNE# INTR NMI 2 @1K 2 2 2 2 @8P4R_1K 32 VID[0..4] VID[0..4]
3
1UF 2 2 CPU_CORE
2
2
2
2
2
2
2 1
1
1
1
1
1
1
1
1
C421 C412 C411 C410 C414 C416 C415 2 2 2 2 2 2 1UF 1UF 1UF 1UF 1UF 1UF 1UF
C151 C142 C117 1UF 2 1UF 2
TUALDET 1UF 2 2
CPU_CORE
1
2
1
9
SB_IGNNE#
1
1
1
.1UF 2 VID4 2 1K
.1UF 2
.1UF 2
.1UF 2
.1UF 2
.1UF 2
.1UF 2
.1UF 2
1 R405
VTTPWRGD 11,32
1 1 1 1 4
CPU_CORE R165 R175 @0 @0 2 2 2 2
1 R172
1
1
1
1
1
1
1
1
1
1
1
.1UF CPU_CORE
R166 C160 C167 C164 C165 C170 C168 C172 C173 C162 C156 C169 @0 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF R162 @0
1
1
SW1
RATIO 3X 3.5X 1 ON ON OFF OFF OFF OFF ON ON ON ON
RATIO SELECT
2 OFF OFF ON ON OFF OFF ON ON OFF OFF 3 ON OFF ON OFF ON OFF ON OFF ON OFF 4 ON ON ON ON ON ON OFF OFF OFF OFF
2
+ C457 220UF_E 6.3V
+ C178 220UF_E 6.3V
+ C449 220UF_E 6.3V
+ C116 220UF_E 6.3V
+ C150 220UF_E 6.3V
+ C135 220UF_E 6.3V
SB_A20M#
1
R168 0 R159 0 R157 0 R158 0
2 A20M# 2 IGNNE# 2 INTR
4X 4.5X 5X 5.5X 6X 6.5X 7X 7.5X
SB_IGNNE# 1 W33 U33 VCCT VSST 1 L18 + C140 .1UF E21 2 33UF_6.3X2.5 SB_NMI 1 2 4.7Uh_0805 CPU_CORE SB_INTR 1
1
C109
2 NMI
CPU_CORE 1 1 1 1 1 1 1 1 1 1 2 1 1 S35 E27 RTTCTRL SLEWCTRL VCCCMOS/VTT* AH28 Y33 1 C83 THERMTRIP# CLKREF/BCLK#*
AB36 1 C203
CPU_IO 2
C417
C438
C418
C420
C431
C437
C426
C430
C435
C439
4.7UF_12064.7U_1206 4.7U_1206 4.7U_1206 4.7U_1206 4.7U_1206 4.7U_1206 4.7UF_1206 4.7UF_1206 4.7UF_1206 2 2 2 2 2 2 2 2 CPU_CORE
1
R91 150_1% R78 150_1%
2
1
C70
* For Intel New CPU
FC-PGA370 + C422 220UF_E 6.3V + C458 220UF_E 6.3V + C459 220UF_E 6.3V + C134 220UF_E 6.3V + C404 220UF_E 6.3V + C400 220UF_E 6.3V
4.7UF_0805 2 1
.1UF 2 Title
2
+2.5V_CLK
2
1
CLKREF
CPUPRES#
C37
.1UF
Compal Electronics, Inc.
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 3 of 34
A
B
C
D
A
B
C
D
E
HD#[0..63]
HD#[0..63] 2 2 HA#[3..31] HD#[0..63] HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 E19 B18 B16 A16 C18 C17 D18 D15 D17 C16 B17 D16 A17 A15 E16 D19 A14 E18 E17 B14 C15 E14 B11 D14 B15 D13 C13 E9 C12 D12 E15 A13 B12 B13 A12 E13 D11 D10 A11 E10 E8 C9 D9 C11 B10 A10 E7 D8 B8 C10 B6 B9 F8 D6 D7 C7 E5 A7 E6 B7 C6 D5 A6 A8 G22 2 R130 10 11 U14A HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# HCLKIN
2
HA#[3..31] HA#[3..31]
+2.5VS
4
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# ADS# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 BREQ0# BPRI# BNR# HLOCK# HIT# HITM# DEFER# DBSY# DRDY# HTRDY# RS#0 RS#1 RS#2 CPURST# CPURSTD# GTL_REFA GTL_REFB
A25 D24 B25 B26 E23 C26 C24 A23 C25 D22 B24 D25 F22 C23 D21 A20 C22 A21 B23 A22 B21 E20 B22 B19 C20 A24 B20 D20 C21 J24 E24 F23 F24 F25 E25 J25 E26 D26 G23 G24 G26 F26 H26 J23 G25 H23 K23 H25 A19 E22 E12 E21
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 ADS# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 BREQ0# BPRI# BNR# HLOCK# HIT# HITM# DEFER# DBSY# DRDY# HTRDY# RS#0 RS#1 RS#2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
U14E J9 J10 J11 J12 J15 J16 J17 J18 K9 K18 L9 L18 M9 M18 R9 R18 T9 T18 U9 U18 V9 V10 V11 V12 V15 V16 V17 V18 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A9 A18 A26 B2 C8 C14 C19 D4 D23 F6 F13 F14 F16 F21 H24 J13 J14 J26 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 M21 N3 N6 N9 N11 N12 N13 N14 N15 N16 N18 N21 P1 P6 P9 P11 P12 P13 P14 P15 P16 P18 P21 R11 R12 R13 R14 R15 R16 T11
1
1
1
1
1
1
1
1
+
C113 4.7UF_1206 2 2
C171 C248 C249 C208 C200 C127 C132 C130 .1UF .1UF 2 .1UF 2 .1UF 2 .01UF .01UF .01UF .01UF 2 2 2 2
1
4
C223 150UF_E_4V
1
1
1
1
1
1
1 2
C126 C129 C131 C196 C201 C159 C250 C128 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .1UF 2 .01UF .01UF 2
3
1
3
R111 2 @0
CPURST# 2,9 CRESET# 3 VCCT_REF
AF26 AF18 AF9 AF1 AD19 AD13 AD8 AC23 AC4 AA15 AA14 AA13 AA21 AA6 W24 V26 V14 V13 T21 T16 T15 T14 T13 T12
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VT8606
11 HCLK_NB
2
VT8606
C182 10PF 2 VCCT_REF R125 75_1%
1
CPU_IO
1
2 1 1 R122 1UF 150_1% 2 2
VCCT_REF 1 1 C158 C153 C148 2 C143 .1UF 1000PF 4.7UF_0805 2 2 1
1
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Title
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 4 of 34
A
B
C
D
E
+3VS G6 H6 J6 L4 R21 T4 U21 V6 V21 W6 Y21 Y6 AA7 AA9 AA10 AA17 AA18 AA20
U14C VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# FRAME# IRDY# TRDY# DEVSEL# PAR STOP# SERR# LOCK# WSC# REQ0# REQ1# REQ2# REQ3# REQX# PREQ# GNT0# GNT1# GNT2# GNT3# GNTX# PGNT# SUSTAT# PWRGOOD NC1 NC2 NC3 NC4 VT8606 PCIRST# CLKRUN# PCICLK AF14 AE14 AE13 AF13 AC14 AB14 AC13 AB13 AE12 AD12 AB12 AC12 AF11 AE11 AD11 AC11 AA8 AC9 AF8 AE8 AE7 AB8 AF7 AC8 AC7 AB7 AF6 AE6 AD6 AC6 AB6 AF5 AF12 AB11 AD9 AD7 AE9 AC10 AD10 AB9 AB10 AE10 AF10 AE5 AA11 AC5 AD5 AE4 AD4 AF2 AC15 AB5 AF4 AF3 AE3 AE2 AD15 AC22 AD14 AE15 AF15 AB15 FRAME# IRDY# TRDY# DEVSEL# STOP# SERR# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
AD[0..31]
AD[0..31]
9,15,23,28 9,12,15 PIRQA# SUS_STAT# 1 R119 1 VGASUSP R390 0 +3VS SUS_STAT# 4 2 W5 B4 C4 F5 F4 R6 T2 T1 R5 R2 R4 R1 R3 P5 P2 P3 P4 N5 N2 N1 N4 T3 U1 U3 F2 F3 AB3 AA3 Y4 W4 AA5 Y5 AC1 AB1 AD2 AC2 AD3 AC3 AB4 AA4 AE1 AD1 W1 W2 AB2 Y2
U14D INTA# AGP_BUSY# STP_AGP# SUSPEND STANDBY ZVD0 ZVD1 ZVD2 ZVD3 ZVD4 ZVD5 ZVD6 ZVD7 ZVD8 ZVD9 ZVD10 ZVD11 ZVD12 ZVD13 ZVD14 ZVD15 ZVHS ZVVS ZVCLK SPD1 SPCLK1 Y0M Y0P Y1M Y1P Y2M Y2P YCM YCP Z0M Z0P Z1M Z1P Z2M Z2P ZCM ZCP LVDSVCCA LVDS1VCCA PLLVCCA VCCLVDS RED GREEN BLUE HSYNC VSYNC RSET COMP VCCDAC VCCRGB GNDDAC GNDRGB BISTIN DFTIN XTALI XTALO VT8606 L20 1 2 CHB2012U121_0805 1 VCCPLL1 VCCPLL2 GNDPLL1 GNDPLL2 TVD11/PD0 TVD10/PD1 PD2 PD3 PD4 PD5 PD6 PD7 TVD9/PD8 TVD8/PD9 PD10 PD11 PD12 PD13 PD14 PD15 TVCLKR/PD16 TVBLANK/PD17 PD18 PD19 PD20 PD21 PD22 PD23 TVD6/PD24 TVD4/PD25 TVD5/PD26 TVD7/PD27 TVD0/PD28 TVD1/PD29 TVD3/PD30 TVVS/PD31 TVCLK/PD32 TVD2/PD33 TVHS/PD34 PD35 PANELDEN PANELCLK PANELVS PANELHS ENVDD ENVEE GOP0 FPGPIO STRW/GPOUT PANELDET SPCLK2 SPD2 G2 H2 H1 J2 J1 H4 K6 J4 J3 L5 K2 J5 K1 K3 L6 L2 K5 L1 L3 M6 K4 M4 M5 M1 T6 T5 U4 U2 V1 V2 V3 W3 V4 U5 V5 C5 H3 G4 G3 G5 F1 H5 C3 G1 AA12 AA16 M2 M3 C2 D3 D2 E2 E1 E3 E4 C1 D1 B1 A1
2
C118 2 2
C133 C232 C267 C256 .1UF 2 .1UF 2 .1UF 2
4.7UF_1206.1UF
RP39 ZV8 ZV11 ZV10 ZV9 6 7 8 9 10 10P8R-100K 5 4 3 2 1 ZV12 ZV15 ZV13 ZV14
20
AGP_BUSY# 2 SUSSTAT# 0 2 SUSPEND STANDBY
TVD11 TVD10
13 13
1
1
1
1
1
TVD9 TVD8
13 13
4
4
R391 @10K 5 1 ZV8 ZV9 ZV10 ZV11 ZV12 ZV13 ZV14 ZV15
1 R129 22
2
TVCLKR
13
1
1
1
1
1
C98 2 2
C92 2
C95 .1UF 2
C96 .1UF 2
C154 .1UF
SUSPEND
4.7UF_1206.1UF
1 R392
2 6 @1K +3V POWER U28B 74LVC125
1 R147 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 SMDTV SMCTV TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKOTXCLKO+ TZOUT0TZOUT0+ TZOUT1TZOUT1+ TZOUT2TZOUT2+ TZCLKOTZCLKO+
2 100K
CPU_IO E11 F7 F9 F10 F12 F17 F18 F19 F20 G21 J21 K21 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
C502 2 2
3
C503 C504 C505 C506 .1UF 2 .1UF 2 .1UF 2
C/BE#0 C/BE#1 C/BE#2 C/BE#3 FRAME# IRDY# TRDY# DEVSEL# PAR STOP# SERR# 2 PLOCK# +3VS REQ#0 REQ#1 REQ#2 REQ#3
9,15,23,28 9,15,23,28 9,15,23,28 9,15,23,28 9,12,15,23,28 9,12,15,23,28 9,12,15,23,28 9,12,15,23,28 9,12,15,23,28 9,12,15,23,28 9,12,15,23,28 12,15 23 23 28 15
TVD6 TVD4 TVD5 TVD7 TVD0 TVD1 TVD3 TVVS TVCLK TVD2 TVHS
13 13 13 13 13 13 13 13 13 13 13
1
1
1
1
4.7UF_1206.1UF
1
3
ENVDD ENVEE BLON# 2
14 14,21 14
1 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 GNT#0 GNT#1 GNT#2 GNT#3 GNT#4
R221 4.7K
R222 4.7K 1
LVDD PLLVDD +LAVDD
DDC_CLK 14 DDC_DATA 14 R G B HSYNC1 VSYNC1 1 2 C161 .1UF 2 +DACVDD 14 14 14 14 14
PCIREQ# 9,12 GNT#0 GNT#1 GNT#2 GNT#3 23 23 28 15
Y1 AA1 Y3 AA2 R110 1K 2 +3VS 2 14MCRT 1 1 R109 1K F15 F11 A2 A3
+3V
2 D42 1N4148
1 1 C465 .1UF 2
AA22
LVDSGND LVDS1GND PLLGND GNDLVDS
25VSUS
PCIGNT# 9,12 SUS_STAT# NBPWROK 2 R274 0 CLKRUN# 2 1 SUS_STAT# 9 SPWROFF# 9,20,27 PCIRST# 9,13,15,16,19,23,28 CLKRUN# 9,12,15,23,28 PCLK_NB 11 11
R121 140_1% 1
2
U6 V22 W22 AB22
+DACVDD
R210 47 11
B3 A5 A4 B5
PLLVDD
C255 15PF 2 L19 +2.5VS 1 2 CHB2012U121_0805 1 C123 .1UF 5 4 3 2 1 10P8R-10K +2.5VS GNT#2 GNT#3 GNT#1 REQ#2 +3VS T=40iml 1 1
+2.5VS PLLVDD C114 1 C125 1000PF
T=40iml 1 1 2
+DACVDD C146 C174 1000PF
C155 .1UF
2
REQ#3 GNT#0 REQ#0 REQ#1 +3VS
6 7 8 9 10
.1UF 2 2
10UF_1206 2 2
L28 1 2 CHB2012U121_0805 1 C219 .1UF +3VS 2 2 T=20iml 1 +LAVDD C227 10UF_1206
+3VS
L35 1 2 CHB2012U121_0805 1
T=40iml 1
2
RP63
C124
10UF_1206
LVDD C233 10UF_1206
1
C234 .1UF
1
PCI REQ ASSIGMENT
+3VS REQ#4 GNT#4
2
REQ#0 REQ#1
MiniPCI(Compal) MINI PCI
RP29
1 R212 1 R211
2 10K 2 10K
REQ#2 REQ#3 REQ#4
1394 PCMCIA CONTROLLER NO USED
SUS_STAT# STANDBY AGP_BUSY# SUSSTAT#
1 2 3 4 8P4R_4.7K
8 7 6 5
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Title
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
2
401202
, 22, 2001 Sheet
E
Rev 1B 5 of 34
A
B
A
B
C
D
E
MD[0..63]
MD[0..63] 7,8
4
4
U14B 7 RRAS#0 8 RRAS#2 8 RRAS#3 Y26 Y25 Y24 Y23 Y22 W21 V23 W23 AF24 AE23 W26 W25 AD23 AF23 U24 U25 U26 AA24 AA25 AA26 U22 V25 V24 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 2 DCLKO1 AA23 AB23 AB26 AB25 AB24 AC26 AC25 AC24 AD26 AD25 AE26 AD24 AE24 AE25 AF25 J22 K22 H21 H22 RAS0#/CS0# RAS1#/CS1# RAS2#/CS2# RAS3#/CS3# RAS4#/CS4# RAS5#/CS5# DQM0/CAS0# DQM1/CAS1# DQM2/CAS2# DQM3/CAS3# DQM4/CAS4# DQM5/CAS5# DQM6/CAS6# DQM7/CAS7# SWEA# SWEB#/CKE2 SWEC#/CKE0 SRASA# SRASB#/CKE5 SRASC#/CKE4 SCASA# SCASB#/CKE3 SCASC#/CKE1 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 DCLKO DCLKI VCCA VCCA MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 M23 K25 L26 L25 M26 M24 N26 N24 P23 P25 R23 R25 P22 T23 T25 T22 AD22 AF22 AB21 AE21 AB20 AD20 AE20 AC19 AF19 AC18 AE18 AD17 AF17 AB17 AE16 AC16 K26 L23 M22 L24 M25 N23 N25 N22 P26 P24 R26 R24 R22 T26 T24 U23 AE22 AC21 AD21 AF21 AC20 AF20 AB19 AE19 AB18 AD18 AA19 AE17 AC17 AD16 AF16 AB16 MDD0 MDD1 MDD2 MDD3 MDD4 MDD5 MDD6 MDD7 MDD8 MDD9 MDD10 MDD11 MDD12 MDD13 MDD14 MDD15 MDD16 MDD17 MDD18 MDD19 MDD20 MDD21 MDD22 MDD23 MDD24 MDD25 MDD26 MDD27 MDD28 MDD29 MDD30 MDD31 MDD32 MDD33 MDD34 MDD35 MDD36 MDD37 MDD38 MDD39 MDD40 MDD41 MDD42 MDD43 MDD44 MDD45 MDD46 MDD47 MDD48 MDD49 MDD50 MDD51 MDD52 MDD53 MDD54 MDD55 MDD56 MDD57 MDD58 MDD59 MDD60 MDD61 MDD62 MDD63 MDD5 MDD0 MDD34 MDD6 MDD38 MDD7 MDD37 MDD39 MDD10 MDD44 MDD45 MDD14 MDD46 MDD13 MDD15 MDD47 MDD20 MDD52 MDD21 MDD22 MDD53 MDD58 MDD54 MDD23 MDD27 MDD59 MDD28 MDD62 MDD30 MDD61 MDD31 MDD63 MDD1 MDD32 MDD33 MDD35 MDD3 MDD2 MDD36 MDD4 MDD40 MDD9 MDD41 MDD8 MDD12 MDD42 MDD11 MDD43 MDD16 MDD48 MDD17 MDD18 MDD49 MDD50 MDD19 MDD51 MDD55 MDD24 MDD56 MDD25 MDD57 MDD26 MDD29 MDD60 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 MD5 MD0 MD34 MD6 MD38 MD7 MD37 MD39 MD10 MD44 MD45 MD14 MD46 MD13 MD15 MD47 MD20 MD52 MD21 MD22 MD53 MD58 MD54 MD23 MD27 MD59 MD28 MD62 MD30 MD61 MD31 MD63 MD1 MD32 MD33 MD35 MD3 MD2 MD36 MD4 MD40 MD9 MD41 MD8 MD12 MD42 MD11 MD43 MD16 MD48 MD17 MD18 MD49 MD50 MD19 MD51 MD55 MD24 MD56 MD25 MD57 MD26 MD29 MD60
RP34 16P8R-22
7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8
RCAS#0 RCAS#1 RCAS#2 RCAS#3 RCAS#4 RCAS#5 RCAS#6 RCAS#7
MA0 MA1 MA13 MA14 RP50 16P8R-22 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA12 MA9 MA11 RP62 16P8R-22 MA8 R170 1 MA12 R185 1
R362 R364 R370 R368 R366 R361 R363 R365 R164 R167 R174 R369
1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
@10K @10K @10K @10K @10K @10K @10K @10K 10K @10K @10K @10K
+3VS
Strap
Description
Setting 01=100Mhz 11=133Mhz 00=66Mhz 0=Map0 1=Map1 0=Enable 1=Disable 0=Enable 1=Disable 0=Normal 1=Test 0=PLL 1= External 0=4Level 1=1Level
MA12,8 +3VS
CPU Clcok Frequency
MA2
PCI Base Address Mapping
MA3 +3VS
Graphic IO Enable/Disable
7,8 RMWEA# 8 CKE2 7 CKE0
3
MA4
PCI Interrupt
RP54 16P8R-22
7,8 SRASA#
MA7 +3VS
Graphic Test Mode
3
R180 1 R367 1
2 @10K 2 @10K
MA9
VGA Clock Select
7,8 SCASA# 8 CKE3
MA11 2 10K 2 10K BSEL0 BSEL1 2 2,11
IOQ Level
MA0,1,13,14
Panel Type
RP38 16P8R-22
RP33 16P8R-22
C187 10PF 1 2 1
11 DCLKO
2
11 DCLKWR 2
R134 33
RP57 16P8R-22
2
R137 @15VCCA 11
RP61 16P8R-22
C189 @47PF 2 2
L21 L22 K24
GNDA GNDA PLLTEST VT8606
R354 4.7K 1
+2.5VS
1
L23 1 2 CHB2012U121_0805 1
T=40iml 1
VCCA C448 10UF_1210
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA11 MA10 MA12 MA13 MA14
C451 .1UF 2 2 7,8 MMA[0..14]
8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16
MMA0 MMA1 MMA2 MMA3 MMA4 MMA5 MMA6 MMA7 MMA8 MMA9 MMA11 MMA10 MMA12 MMA13 MMA14
RP53 16P8R-22
RP56 16P8R-22
1
MMA[0..14]
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title
SCHEMATIC, M/B LA-1281
Size Custom Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 6 of 34
A
B
C
D
A
B
C
D
E
+3V +3V
1 14 27 3 9 43 49
U44 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CKE CLK RVD RVD 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 37 38 36 40 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 CKE0 CLK_SDRAM0 MMA14
1
MMA0 MMA1 MMA2 MMA3 MMA4 MMA5 MMA6 MMA7 MMA8 MMA9 MMA10 MMA13 MMA12 MMA11 RCAS#0 RCAS#1 RMWEA# SCASA# SRASA# RRAS#0
23 24 25 26 29 30 31 32 33 34 22 35 21 20 15 39 16 17 18 19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BA1 A13/BA0 DQML DQMH WE# CAS# RAS# CS#
VCC VCC VCC VCCQ VCCQ VCCQ VCCQ
BANK0
MMA0 MMA1 MMA2 MMA3 MMA4 MMA5 MMA6 MMA7 MMA8 MMA9 MMA10 MMA13 MMA12 MMA11 RCAS#4 RCAS#5 RMWEA# SCASA# SRASA# RRAS#0
1 14 27 3 9 43 49
U43 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CKE CLK RVD RVD 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 37 38 36 40 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 CKE0 CLK_SDRAM0 MMA14
64/128MB SDRAM
1
23 24 25 26 29 30 31 32 33 34 22 35 21 20 15 39 16 17 18 19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BA1 A13/BA0 DQML DQMH WE# CAS# RAS# CS#
VSS VSS VSS VSSQ VSSQ VSSQ VSSQ
CKE0 6 CLK_SDRAM0 11
28 41 54 6 12 46 52
8MX16S
+3V
28 41 54 6 12 46 52
R286 @10
VSS VSS VSS VSSQ VSSQ VSSQ VSSQ
VCC VCC VCC VCCQ VCCQ VCCQ VCCQ
8MX16S +3V
2
6,8 6,8 6,8
MMA[0..14] MD[0..63] RCAS#[0..7]
MMA[0..14] MD[0..63] RCAS#[0..7]
MMA0 MMA1 MMA2 MMA3 MMA4 MMA5 MMA6 MMA7 MMA8 MMA9 MMA10 MMA13 MMA12 MMA11 RCAS#2 RCAS#3 RMWEA# SCASA# SRASA# RRAS#0
1 14 27 3 9 43 49
C330 @15PF 23 24 25 26 29 30 31 32 33 34 22 35 21 20 15 39 16 17 18 19
U42 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CKE CLK RVD RVD 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 37 38 36 40 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 CKE0 CLK_SDRAM0 MMA14 1 14 27 3 9 43 49 U41 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CKE CLK RVD RVD 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 37 38 36 40 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 CKE0 CLK_SDRAM0 MMA14
2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BA1 A13/BA0 DQML DQMH WE# CAS# RAS# CS#
VCC VCC VCC VCCQ VCCQ VCCQ VCCQ
MMA0 MMA1 MMA2 MMA3 MMA4 MMA5 MMA6 MMA7 MMA8 MMA9 MMA10 MMA13 MMA12 MMA11 RCAS#6 RCAS#7 RMWEA# SCASA# SRASA# RRAS#0
23 24 25 26 29 30 31 32 33 34 22 35 21 20 15 39 16 17 18 19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BA1 A13/BA0 DQML DQMH WE# CAS# RAS# CS#
28 41 54 6 12 46 52
8MX16S
VSS VSS VSS VSSQ VSSQ VSSQ VSSQ
6,8 6,8 6,8 6
RMWEA# SCASA# SRASA# RRAS#0
VSS VSS VSS VSSQ VSSQ VSSQ VSSQ
VCC VCC VCC VCCQ VCCQ VCCQ VCCQ
3
28 41 54 6 12 46 52
8MX16S
3
+3V
+3V
+3V
C332 .1UF
C368 .1UF
C344 .1UF
C331 .1UF
C351 .1UF
C389 .1UF
C339 .1UF
C335 .1UF
C365 .1UF
C362 .1UF
C338 .1UF
C485 .1UF
+3V
+3V
+3V
4
C352 1000PF
C393 1000PF
C364 1000PF
C336 1000PF
C367 1000PF
C363 1000PF
C329 1000PF
C350 1000PF
C392 1000PF
C343 1000PF
C482 1000PF
C384 1000PF
4
Compal Electronics, Inc.
Title PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 7 of 34
A
B
A
B
C
D
E
SO-DIM 144 PINS RAM MODULE CONN.
6,7
1
BANK2/3
1
MMA[0..14] MD[0..63] RCAS#[0..7] RRAS#[2..3]
MMA[0..14] MD[0..63] RCAS#[0..7] RRAS#[2..3] JP20 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 RCAS#0 RCAS#4 MMA0 MMA1 MMA2 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS CE0# CE1# VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS RESVD/DQ64 RESVD/DQ65 RFU/CLK0 VCC RFU WE# RE0# RE1# OE#/RESVD VSS RESVD/DQ66 RESVD/DQ67 VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10 VCC CE2#/RESVD CE3#/RESVD VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC SO-DIMM144 VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS CE4# CE5# VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS RESVD/DQ68 RESVD/DQ69 RFU/CKE0 VCC RFU RFU/CKE1 RFU RFU RFU/CLK1 VSS RESVD/DQ70 RESVD/DQ71 VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 A11/BA0 VSS A12/BA1 A13/A11 VCC CE6#/RESVD CE7#/RESVD VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 RCAS#1 RCAS#5 MMA3 MMA4 MMA5 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 +3V +3V
6,7 6,7 6
2
2
C298 22PF 11 CLK_SDRAM2 6,7 6,7 SRASA# RMWEA#
R260 33
CKE2 CKE3 MMA14
CKE2 SCASA# CKE3
6 6,7 6 + CLK_SDRAM3 11
+3V
RMWEA# RRAS#2 RRAS#3
C473 10UF_1206 6.3V
C483 .1UF
C474 .1UF
C484 .1UF
C476 .1UF
C477 .01UF
C475 .01UF
C488 .01UF
MD16 MD17 MD18 MD19
3
MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MMA7 MMA11 MMA12 MMA13 RCAS#3 RCAS#7 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
R277 33
+3V C319 22PF +
3
MD20 MD21 MD22 MD23 MMA6 MMA8 MMA9 MMA10 RCAS#2 RCAS#6 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55
C472 10UF_1206 6.3V
C478 .01UF
C479 1000PF
C489 1000PF
C358 1000PF
C487 1000PF
+3V
+3V
R372 10K
R278 10K
9,11
SMBDATA
SMBCLK
9,11
4
4
DIMM1
Compal Electronics, Inc.
Title PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 8 of 34
A
B
1
2
3
4
5
6
7
8
17
PDD[0..15]
PDD[0..15] U30A PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 P16 P18 P20 R17 R19 T16 T18 T20 T19 T17 R20 R18 R16 P19 P17 N20 M17 M19 M18 L20 M16 M20 N19 N17 N18 N16 L17 L16 K20 K19 K18 K17 K16 J20 J18 J17 J16 H20 H19 H18 H17 H16 F16 E20 E19 E18 E17 D20 D19 D18 B20 A20 A19 B19 A18 B18 C18 A17 J19 G20 F17 C19 FRAME# F18 IRDY# F19 TRDY# F20 STOP# G17 DEVSEL# G16 SERR# G18 PAR G19 IDSEL C20 PCIREQ# L18 PCIGNT# L19 PCI_RST# B16 A16 D17 C17 B17 PCLK_SB RTCX1 E16 Y5 W5 R9 R10 Y6 H15 J15 K15 M15 N15 R7 R8 R11 R14 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDA0 PDA1 PDA2 PDCS1 PDCS3 PDDACK PDDREQ PDIOR PDIOW PDRDY AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0 C/BE1 C/BE2 C/BE3 FRAME IRDY TRDY STOP DEVSEL SERR PAR IDSEL REQ GNT PCIRST PINTA PINTB PINTC PINTD PCICLK RTCX1 RTCX2 TSEN1 VCCSUS VCCSUS VBAT VCC VCC VCC VCC VCC VCC VCC VCC VCC VT82C686-B
2 3 4
VT82C686A-A
2 R306 SDD0/BITCLK SDD1/SDIN SDD2 SDD3/SYNC SDD4/SDOUT SDD5/-ACRST SDD6/JBY SDD7/JBX SDD8/JAY SDD9/JAX SDD10/JAB2 SDD11/JAB1 SDD12/JBB2 SDD13/JBB1 SDD14/MSO SDD15/MSI SDA0 SDA1 SDA2 SDCS1 SDCS3 SDDACK SDDREQ SDIOR SDIOW SDRDY A20M CPURST FERR IGNNE INIT INTR NMI SLP/GPO7 SMI STPCLK SMBCLK SMBDATA PWRGD CPUSTP/GPO4 PCISTP/GPO5 CLKRUN PWRBTN RSMRST SUSCLK RING/GPI7 SPKR GPIOD/GPIO11 EXTSMI PME/GPI5/THRM SUSST1/GPO6 BATLOW/GPI2 GPI1/IRQ8 GPIOA/GPIO8 GPO0 LID/APICREQ/GPI3 SMBALT/GPI6 SUSA/APICACK/GPO1 SUSB/APICCS/GPO2 SUSC GND GND GND GND GND VSENS4(12V) VSENS3(5V) VSENS1(2.0V) VSENS2(2.2V) W18 V17 Y17 V16 Y16 U15 W15 U14 Y15 V15 T15 W16 U16 W17 Y18 Y19 U19 V18 U20 U17 U18 V19 Y20 W19 W20 V20 Y7 V8 V7 Y8 T6 W8 U7 T7 U6 W7 U9 T9 W6 Y12 V12 W12 Y11 V6 T10 V11 V5 U8 Y10 T11 V10 U11 W11 T14 T8 U10 W10 V9 W9 Y9 F15 G15 L15 P15 R15 RP83 Y14 W14 U13 V13 PCI_RST# W13 T13 Y13 T12 U12 R12 R13 2 1 2 R299 0 1 C359 1 2 .1UF FAN_SENSE 20,22 2 R385 1 C383 .1UF 2 1 10K +3VS +3VS 2 R290 1 100K +5VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
D
2 R312 2 R310
2 1 R300 2 1 R295 22 0
1 10K 1 0
1 1 2 @33 C369 @22PF IAC_BITCLK 26 IAC_SDATAI 26 IAC_SYNC 26 IAC_SDATAO 26 IAC_RST# 26
Signals Pullup
+3V
A
A
RP92 1 2 3 4 5 10P8R-10K D29 PBTN# 2 1 @RB751V D30 2 RB751V 0 0 1 1 CPURST# 2,4 CLKRUN# CPUINIT# 2 2 R288 2 R289 1 10K 1 @1K +3VS SUSA# 1 PBTN_OUT# 21 ON/OFF 20,26 LID# SCI# VLB# 1 2 3 4 10 9 8 7 6 +3VS PBTN# ATF_INT# PX4_RI# IRQ8# 1 2 3 4
RP86 8 7 6 5 8P4R_10K
17 17 17 17 17 17 17 17 17 17
PDA0 PDA1 PDA2 PDCS1# PDCS3# PDDACK# PDDREQ PDIOR# PDIOW# PDIORDY
PDA0 PDA1 PDA2 PDCS1# PDCS3# PDDACK# PDDREQ PDIOR# PDIOW# PIORDY AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
2 R313 SDA0 SDA1 SDA2 SDCS1# SDCS3# SDDACK# SDDREQ SDIOR# SDIOW#
1 22
+3VS SDA0 SDA1 SDA2 SDCS1# SDCS3# SDDACK# SDDREQ SDIOR# SDIOW# SDIORDY
+3VS 17 17 17 17 17 17 18 17 17 18
8 7 6 5
RP82 8P4R_10K SUSCLK 2 1 R272 10K +3V
FERR#
5,15,23,28 AD[0..31]
AD[0..31]
B
2 R8 SB_SMC SB_SMD
0
1
SB_A20M# 3 2 R247 FERR# 2 SB_IGNNE# 3 2 R248 SB_INTR 3 SB_NMI 3 SLP# SMI# 2 STPCLK# 2 SMBCLK 8,11 SMBDATA 8,11
2 R268
1 10K
B
2
2 R267 SPKR
1 10K
+3VS
2 R264
1 @10K
CLKRUN# PBTN# RSMRST# SUSCLK PX4_RI# SPKR ACIN_SYS# 2 R275
SPWROFF# 5,20,27 CPU_STP# 11 PCI_STP# 11 CLKRUN# 5,12,15,23,28 RSMRST# 27 0 1 21 26 RTCCLK 15,16
NOTE:DISABLE INTERNAL AUDIO CTRL
+3VS 1 R265 4.7K ACIN_SYS# Q40 2N7002 3 2
PX4_RI# SPKR
ATF_INT# VLB# IRQ8# 133M/100M# LID# SCI# SUSA# SUSB# SUSC#
D25 1 RB751V D28 2 SUS_STAT# 5 20,26,29 ACIN 2
C
5,15,23,28 5,15,23,28 5,15,23,28 5,15,23,28
C/BE#0 C/BE#1 C/BE#2 C/BE#3
IRQ8# LID# SCI# SUSA# SUSB# SUSC#
20 21 20 11,20 20 20
1
AD18
2 R315
1 100
IDSEL
EXTSMI# 20 ATF_INT# 20
C
PCLK_SB 1
5,12,15,23,28 FRAME# 5,12,15,23,28 IRDY# 5,12,15,23,28 TRDY# 5,12,15,23,28 STOP# 5,12,15,23,28 DEVSEL# 5,12,15,23,28 SERR# 5,12,15,23,28 PAR 5,12 5,12 PCIREQ# PCIGNT# PIRQA# PIRQB# PIRQC# PIRQD#
2 RB751V
1
LLBATT#
21
+3VS +3VS 2,27,32 VR_POK PCI_RST# 1 4 2 U45 @7SH08FU 3 5 1 R319 2 10K 133M/100M#
R292 @22 2
C353 @10PF
5,12,15 12,15,23 12,28 12,23 11
8 7 6 5
1 2 3 4 8P4R_10K
PCIRST#
PCIRST#
5,13,15,16,19,23,28
1 R318
2 @10K
PCLK_SB
As close as 686A
X3 RTCX1 RTCX2 32.768KHZ 1 2 R386 @20M C288 22PF 2 +3VS RTCX2
Populate R318 and not populate R319 When 100MHz SDRAM on board Populate R319 and not populate R318 When 133MHz SDRAM on board
2 R394
0
1 PCIRST#
1
D
1
+3V C294 22PF +RTCVCC C311 1 2 .01UF
VREF TSEN2 FAN1 FAN2/GPIOB/GPIO9 VCCHWM GNDHWM
2
Compal Electronics, Inc.
Title
C263 2 2
C278 C277 C279 C360 .1UF 2 .1UF 2 .1UF 2
+C376
10UF_1210
1
1
1
1
1
SCHEMATIC, M/B LA-1281
Size B Date:
5 6
4.7U_1206 .1UF
Document Number
401202
, 22, 2001
7
Rev 1B Sheet 9
8
of
34
1
1
2
3
4
5
6
7
8
U30B SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SA16 SA17 SA18 SA19 W1 V2 V1 U3 U2 U1 T4 T3 T2 T1 R5 R4 R3 R2 R1 P5 P4 P3 K2 K1 J5 J4 J3 J2 Y1 Y2 W2 Y3 W3 V3 Y4 W4 L5 M2 M4 N1 N3 N5 P1 P2 L2 E1 D2 L4 M3 N2 64M#/128M L3 E2 D3 M1 M5 N4 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 LA20 LA21 LA22 LA23 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 PRD0 PRD1 PRD2 PRD3 PRD4 PRD5 PRD6 PRD7 ACK BUSY PE SLCT ERROR PINIT AUTOFD SLCTIN STROBE TXD1 DTR1 RTS1 CTS1 DSR1 DCD1 RI1 RXD1 TXD2 DTR2 RTS2 CTS2 DSR2 DCD2 RI2 RXD2 VCCUSB GNDUSB B15 D15 A14 B14 C14 D14 E14 A13 B13 C13 D13 E13 A15 C15 C16 E15 D16 A11 D11 B11 C11 C12 A12 E11 B12 D10 B9 E10 A9 C10 A10 C9 B10 F9 F8 C3 A3 B3 C4 D4 H3 G5 V14 A4 B4 B5 E6 E5 A5 D5 C5 C1 D9 D6 D7 E9 A8 B8 C8 D8 E8 A7 B7 E7 A6 B6 C7 C6 F6 F11 G6 J9 J10 J11 J12 K9 K10 K11 K12 L6 L9 L10 L11 L12 M9 M10 M11 M12 P6 R6 USBP0+ USBP0USBP1+ USBP1OVCUR#1 25 OVCUR#0 25 RP80 1 2 3 4 8 7 6 5 8P4R_15K GATEA20 RC# IRQ1 IRQ12 20 20 12,20 12,20 1 R255 3MODE# INDEX# MTR0# DRV0# FDDIR# STEP# WDATA# WGATE# TRACK0# WP# RDATA# HDSEL# DSKCHG# 19 19 19 19,21 19 19 19 19 19 19 19 19 19 L38 0_0805 2 +3VS 2 4.7K TXD1 DTR#1 RTS#1 CTS#1 DSR#1 DCD#1 DCD#1 DSR#1 RI#1 RXD1 LPD0 LPD1 LPD2 LPD3 LPD4 LPD5 LPD6 LPD7 LPTACK# LPTBUSY LPTPE LPTSLCT LPTERR# INIT# LPTAFD# SLCTIN# LPTSTB# 24 24 24 24 24 24 24 24 24
The components most place cloely 686B
17 24 12,20
A
SDD[0..15] LPD[0..7] SD[0..15] SA[0..19]
SDD[0..15] LPD[0..7] SD[0..15] SA[0..19]
RP76 USBP1+ USBP1USBP0+ USBP08 7 6 5 1 2 3 4 8P4R-27 CP7 8P4C-47PF JP1 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 USB1_D+ USB1_DUSB0_D+ USB0_D25 25 25 25
A
12,20
+5V
RP77 8P4R-15K
1 R28510K
RP84 1 2 3 4 8 7 6 5 8P4R_10K RP81 +3VS
B
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
2 RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1
@96212-1011S
CTS2 DSR2 DCD2 RI2 1 R28410K VCCUSB GNDUSB
RI2 CTS2 DSR2 DCD2 2
1 2 3 4
8 7 6 5 8P4R_10K
+3VS RP73 SDD0 SDD1 SDD2 SDD3 4 3 2 1 8P4R_0 RP71 5 6 7 8 SA0 SA1 SA2 SA3
B
12
+3VS
12,15 19 19 1 R383 1 R384 14 14 14 14 20
SIRQ PHDRST# SHDRST# 2 10K 2 @10K PID0 PID1 PID2 PID3 AEN
Populate R384 and not populate R383 When 64M SDRAM on board Populate R383 and not populate R384 When 128M SDRAM on board
DACK0/IDEIRQA/GPO16 USBCLK DACK1/IDEIRQB/GPO17 DACK3/AC97IRQ/GPO18 USBP0+ DACK5/MC97IRQ/GPO19/SERIRQ USBP0DACK6/USBIRQA/GPO20 USBP1+ DACK7/USBIRQB/GPO21 USBP1DRQ2/OC1/SERIRQ/GPIOE DACK2/OC0/GPIOF DRQ0/GPI16 CHAS/GPIOC/GPIO10 DRQ1/GPI17 DRQ3/GPI18 USBP2+ DRQ5/GPI19 USBP2USBP3+ DRQ6/GPI20 DRQ7/GPI21(CF/CG) USBP3AEN BALE SBHE REFRESH IOR IOW MEMR MEMW SMEMR SMEMW IOCS16 MEMCS16 IOCHRDY IOCHK/GPI0 TC RSTDRV OSC BCLK IRRX/GPO15 IRTX/GPO14 IRQ3 IRQ4 IRQ5 IRQ6/GPI4/SLPBTN# IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 XDIR/GPO12 SOE/GPO13 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VT82C686-B KBCK/KA20G KBDT/KBRC MSCK/IRQ1 MSDT/IRQ12 ROMCS/KBCS DRVDEN0 DRVDEN1 INDEX MTR0 DS1 DS0 MTR1 DIR STEP WDATA WGATE TRAK00 WRTPRT RDATA HDSEL DSKCHG GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
48M 1 R263 @33
48M
11
SDD4 SDD5 SDD6 SDD7
4 3 2 1 8P4R_0
5 6 7 8
SA4 SA5 SA6 SA7
C303 @10PF SDD9 SDD14 SDD8 SDD13 8 7 6 5
RP78 1 2 3 4 8P4R_0 RP79 SDD12 SDD11 SDD10 SDD15 8 7 6 5 8P4R_0 1 2 3 4 SA12 SA11 SA10 SA15 SA9 SA14 SA8 SA13
12,20 12,20 12,20 12,20
IOR# IOW# MEMR# MEMW#
C
14MOSC 1 R252 @10 12
B2 H2 1 F2 +3VS 1 E3 +3VS PIOR# 1 D1 PIOW# 2 C2 PMEMR# MEMR# 3 U4 PMEMW# MEMW# 4 V4 A1 RP72 8P4R_22 B1 R240 1 1K F3 2 +3VS R251 1 2 4.7K F1 +3VS A2 12,20 IOCHRDY IOCHK# F4 TC H1 J1 R253 R254 8 7 6 5 2 1K 2 1K 11 14MOSC 14MOSC E4 H5 D12 E12 12 12 12 12 12 12 12 12 12,17 12,18 21 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 FLASH# +3VS IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 G4 G3 G2 G1 F5 H4 K3 K4 L1 K5 T5 U5 F7 F10 F12 F13 F14 H6 J6 K6 M6 N6
IRQ1 IRQ12 BIOSCS#
2
BIOSCS# 20 +3VS
PH: SOCKET 370; SLOT 1,SOCKET-A PL: SOCKET 7
C
C265 @10PF
2
1
C333 .1UF
1
VCCUSB
1
+
2
C325 10UF_1206
GNDUSB
2
1
L37 0_0805
2
+3VS
D
+3VS
R250 1 R239 1
4.7K TC 2 4.7K 2 IOCHK#
D
C379 2
C374
C366 C375 C373 .1UF 2 .1UF 2 .1UF 2
Compal Electronics, Inc.
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
1
1
1
1
4.7UF_1206 .1UF 2
1
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001
7
Rev 1B Sheet 10
8
of
34
1
2
3
4
5
6
CLOCK GENERATOR & BUFFER
+3VS
2
1
1
1
1
1
1
1
1
1
C462 4.7UF_10V_0805 10V
C264 1000PF
1000PF .1UF 2 2 2
.1UF 2
.1UF
C225 4.7UF_10V_0805 10V
.1UF 2 2
.01UF 2
1000PF
C236 1000PF 2
C283 4.7UF_10V_0805 10V
C270 .01UF
C276 1000PF
1 10 2 3
C466
C469
C463
C464
C231
C235
C242
1
L32 1 2 CHB2012U170 L34 1 2 CHB2012U170
W=40MILS
+3VCLK_CORE
L30 1 2 @CHB2012U170 L31 1 2 +3VS CHB2012U170 +3V
+3VBUFF
CLK_CPUIO +3VBUFF +2.5V_CLK L36 1 CHB2012U170 2
W=30MILS
W=30MILS
CLK_CPUIO C262 .1UF
1
2
U22 CLK_CPUIO +3VCLK_CORE +3VBUFF +3VBUFF +3VCLK_CORE +3VCLK_CORE +3VCLK_CORE +3VCLK_CORE 2 XIN XOUT 1 6 DCLKO 2 9 PCI_STP# SUS_A# 9 CPU_STP# 2 D45 C237 @10PF 1 2 @RB751V D20 9,20 SUSA# 1 2 @RB751V CPU_IO 1 R407 2 10K E SUS_A# 1 CPUSTP# +12VS 2 1 2 R389 @10K +3VS 1 R388 0 2 CPUSTP# DCLKO 47 19 36 30 27 14 6 1 4 5 15 20 21 41 23 24 3 9 16 22 33 40 44 VDDL VDDCOR VDDSDR VDDSDR VDD48 VDDPCI VDDPCI VDDREF XIN XOUT BUFIN PCI_STP# PWR_DWN# CLK_STP# SDATA SCLK VSS VSS VSS VSS VSS VSS VSS ICS9248-195 2 1 R184 10K 2 C 2 +3VS 3 C254 C260 C252 R378 150 1 11 R406 49.9_1% SDRAMF SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 REF0 REF1/FS2 PCI0/FS3 PCI1 PCI2 PCI3 PCI4 PCI5 PCI6 24/48MHZ/FS1 48MHZ/FS0 CPUCLKF CPUCLK0 CPUCLK1 CPUCLK2 PCIF 25 26 46 45 43 42 7 8 10 11 12 13 17 18 39 38 37 35 34 32 31 29 28 2 48 SPECTRUM FS2 MODE FS1 FS0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 R187 22 2 R387 22 2 R225 22 2 R219 @22 2 R213 22 2 2 2 2 R377 R216 R206 R202 33 33 33 33 48M
HCLK_CPU 2 HCLK_NB 4 PCLK_SB 9 APICCLK 2 PCLK_PCM 15 PCLK_MINI 23 PCLK_1394 28 PCLK_NB 5 DCLKWR 6 CLK_SDRAM0 7 CLK_SDRAM2 8 CLK_SDRAM3 8
Y3 1 14.318MHZ 1 2 R257 @2M C280 10PF 2
DCLKO 1 R196 @22
C281 10PF
1
EARLY
2 R190 33 2 R214 22 2 R204 10 2 R198 10 2 R197 10
R169 10K
1 R237 1 R238 1 R243
2 @10 2 10 2 10 2 2
14.3M_TV 13 14MCRT 5 14MOSC 10
@10PF @10PF @15PF 1 SMBCLK 8,9
3,32 VTTPWRGD
3
2
1 3
Q28 2N7002 R176 2,6 BSEL1 1 @10K R186 1 10K 2 FS1 1 @10K R246 FS2 1 10K 2 2 FS0 1 @10K R177 2 R179 2 3
1
Q61 FMMT3904
Q27 1 2N7002
2 SMBDATA 8,9 3 Q59 FDV301N
2 TUAL5
B
2,3,32
2 Q60 FDV301N
TUAL5#
+3VS R220 R227 2 10K EARLY 1 @10K R218 MODE 2 1
0 NO 1 EARLY CLOCK
CPU / PCI CLOCK
FS3 FS2 FS1 FS0 CPU / PCI
0 3.3V CPU 1 2.5V CPU
1 10K R226
2
0 NO 1 SPREAD SPECTRUM
SPECTRUM 1 10K
2
1 1 1
0 0 1
1 0 1
1 0 0
133 / 33 MHz 100 / 33 MHz 66 / 33 MHz
Compal Electronics, Inc.
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. Date:
SCHEMATIC, M/B LA-1281
Document Number
401202
, 22, 2001 Sheet 11 of 34
Rev 1B
A
B
C
D
E
ISA BUS Pullup
10,20 10,20 SD[0..15] SA[0..19] SD[0..15] SA[0..19]
PCI BUS Pullup
1
+3VS
1
1 R256
2 1K
IOCHRDY
10,20
+3VS RP87 1 2 3 4 8 7 6 5 8P4R-10K PIRQC# PIRQD# PAR PLOCK# 9,28 9,23 5,9,15,23,28 5,15
+5VS 1 R233 R234 +3VS RP67 1 2 3 4 8 7 6 5 8P4R-10K
2
H4 H26 H32 H23 H13 H5 S3.14X0.66mm S3.14X0.66mm S3.14X0.66mm S3.14X0.66mm S3.14X0.66mm S3.14X0.66mm
2 10K 10K
IRQ14 IRQ15
10,17 10,18
+3VS RP90 1 1 1 1 1 8 7 6 5 1 2 3 4 8P4R-10K DEVSEL# FRAME# IRDY# TRDY# 5,9,15,23,28 5,9,15,23,28 5,9,15,23,28 5,9,15,23,28 1 H30 H31 S4X2.8mm S4X2.8mm 1 1
H14 C276PAD
H15 C276PAD
H16 C276PAD
H17 C276PAD
H12 C236PAD
H9 C236PAD
1
1
1
1
1
2 10K
1
SIRQ
10,15
RP69 10,20 10 10 IRQ1 IRQ3 IRQ4 +3VS 1 2 3 4 5 10P8R-10K RP74 SD3 SD4 SD6 SD7 +3VS 1 2 3 4 5 10P8R-4.7K EP1 EMIPAD 5 4 3 2 1 10P8R-4.7K SD11 SD10 SD9 SD8 +3VS 1 1 1 1 1 1 1 1 EP4 EMIPAD EP7 EMIPAD EP9 EMIPAD EP8 EMIPAD EP6 EMIPAD EP10 EMIPAD EP11 EMIPAD 10 9 8 7 6 SD0 SD2 SD1 SD5 +3VS 10 9 8 7 6 +3VS IRQ6 IRQ7 IRQ9 IRQ10 10 10 10 10
H36 S276D146X114 RP91 1
H19 H18 H21 H11 H10 H22 S4X1.5mm S4X1.5mm S6.5X3.8mm S6.5X3.8mm S6.5X3.8mm S6.5X3.8mm
1
IRQ11 IRQ12 IRQ5
10 10,20 10
+3VS R241
2
1
1
1
1
1
15,23,28 5,9 5,9,15,23,28 5,9,15,23,28
PERR# PCIGNT# STOP# SERR# +3VS
1 2 3 4 5 10P8R-10K
10 9 8 7 6
+3VS PIRQA# PIRQB# PCIREQ# CLKRUN#
5,9,15 9,15,23 5,9 5,9,15,23,28
H27 H34 H38 S7X3.0mm S7X3.0mm C177D98
H6 H24 H25 H20 H7 H8 S7X3.0mm S7X3.0mm S7X3.0mm S7X3.0mm S7X3.0mm S7X3.0mm
1
1
1
1
1
1
1
1
1
RP60 SD15 SD14 SD13 SD12 +3VS 6 7 8 9 10
CF2 SMD40M80
CF5 SMD40M80
CF10 SMD40M80
CF13 SMD40M80
1
1
1
3
+3VS RP66 SA18 SA17 SA16 SA19 +3VS 6 7 8 9 10 10P8R-4.7K 5 4 3 2 1 MEMW# MEMR# IOR# IOW# 10,20 10,20 10,20 10,20
EP2 EMIPAD
EP5 EMIPAD
EP3 EMIPAD
EP12 EMIPAD
EP13 EMIPAD
EP14 EMIPAD
EP15 EMIPAD
EP16 EMIPAD
EP17 EMIPAD
1
1
CF7 SMD40M80
CF9 SMD40M80
CF12 SMD40M80
CF14 SMD40M80
3
1
1
1
1
1
1
1
1
1
1
1
1
CF8 SMD40M80 H37 H28 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 H35 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 H33 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
CF11 SMD40M80
CF3 SMD40M80
CF6 SMD40M80
RP75 SA13 SA9 SA10 SA8 +3VS 1 2 3 4 5 10P8R-4.7K RP65 SA1 SA3 SA2 SA0 +3VS
4
1
1
10 9 8 7 6
SA15 SA12 SA14 SA11
+3VS
CF1 SMD40M80
CF4 SMD40M80
SCREW-GND118 +3VS 10 9 8 7 6 10P8R-4.7K H1 SA5 SA7 SA6 SA4 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9
SCREW-GND118 H3 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9
SCREW-GND118 H2 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9
SCREW-GND118 H29 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9
1
1 2 3 4 5
FD3 FIDUCAL
FD2 FIDUCAL
1
FD4 FIDUCAL
FD6 FIDUCAL
1
1
FD1 FIDUCAL
FD5 FIDUCAL
1
1
1
1
1
1
4
SCREW-GND150 SCREW-GND118
SCREW-GND169
SCREW-GND169
Compal Electronics, Inc.
Title PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 12 of 34
A
B
5
4
3
2
1
L11 +3VS
D
1
2 1 1 1
DVDD
+5VS
1
2
TVDD
D
CHB1608B121
1
1
C64 .1UF 2 2
C50 .1UF 2
C49 4.7UF_10V_0805
C48 .1UF 2 2
C52 .1UF 2
1 C51 4.7UF_10V_0805
CHB1608B121 L10
TV-OUT Encode
+3VS TVDD 2 2 DVDD
TV-GNDA
1
1
31 25
2.2K 1 26 27 42 43 44 1 2 3 4 6 7 9 10 11 12 13 14 15 29 SD SC
30 5 16 38
R49 2.2K 1
R50 U4 CVBS/B Y/R D0 D1 D2 D3 D4 D5 D6 D7 D8/SUSP D9 D10 D11 D12 D13 D14 D15 RESET# C/G CSYNC DS/BCD P-OUT XTALO XTALI XCLK HS VS DGND DGND DGND DGND AGND GND GND IRSET 20 22 21 17 35 37 33 32 39 40 41 24 1 2 R59 360_1% 2 CH7005 TV-GNDA 14.3M_TVOUT 1 R82 L17 1 CHB1608B121 2 L16 1 2 2 @0 C78 1 R81 2 1 @10 2 @15PF 14.3M_TV 11 14.3M_TVOUT TVCLKR TVHS TVVS 5 5 5 14.318MHZ Y2 2 1 C121 18PF 2 1 1 C122 18PF 1 1 R31 75_1% 2 CRMA COMPS COMPS
D10
D8
D3
AVDD VDD
2
3
2
3
2
C
5 5 5 5 5 5 5 5 5 5 5 5
TVD0 TVD1 TVD2 TVD3 TVD4 TVD5 TVD6 TVD7 TVD8 TVD9 TVD10 TVD11
TVD0 TVD1 TVD2 TVD3 TVD4 TVD5 TVD6 TVD7 TVD8 TVD9 TVD10 TVD11
3
5 5
SMDTV SMCTV
DVDD DVDD DVDD DVDD
@DAN217 LUMA CRMA 1 1 R48 R104 2 @75_1% 2 47 1 TVCLK 5 LUMA 2
@DAN217
@DAN217 +5VS
C20 47PF L7 CHB1608G301 1 2 1 2 C37 47PF 1 2 L5 CHB1608G301 L6 1 2 CHB1608G301 1 2 47PF 1 1 C17 270PF 2 2 C16 1 C18 270PF
1
JP8 1 2 3 4 5 6 7 S CONN._SUYIN
C
1
1
5,9,15,16,19,23,28 PCIRST#
1 R75
2 33
1
C41 1 R30 75_1% 2 R21 75_1% 150PF 2 150PF 2 150PF 2 2 C35 C34 C19
34 23 19
8 18 36
28
270PF 2
B
B
CHB1608B121 TV-GNDA
A
A
Compal Electronics, Inc.
Title PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
1
Rev 1B 13 of 34
5
4
A
B
C
D
E
+5VALW C27 4.7UF_1210 1 2 1 +5VALW JP2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 5 5 5 5 TXCLKO+ TXCLKOTXOUT2+ TXOUT2TXCLK0+ TXCLK0TXOUT2+ TXOUT25 6 7 8 8P4R-0 RP17 +3VS L_LCD0 L_LCD1 L_LCD2 L_LCD3 L_LCD4 L_LCD5 L_LCD6 L_LCD7 L_LCD8 L_LCD9 TXOUT1+ TXOUT1TXOUT0+ TXOUT0+12V LVDDVGA R100 100K +
2
RP16 4 3 2 1 L_LCD7 L_LCD6 L_LCD5 L_LCD4 5 5 5 5 TZCLKO+ TZCLKOTZOUT2+ TZOUT2TZCLK0+ TZCLK0TZOUT2+ TZOUT28 7 6 5
RP101 1 2 3 4 8P4R-0 RP102 4 3 2 1 L_LCD3 L_LCD2 L_LCD1 L_LCD0 5 5 5 5 TZOUT0TZOUT0+ TZOUT1+ TZOUT1TZOUT0TZOUT0+ TZOUT1+ TZOUT18 7 6 5 8P4R-0 1 2 3 4 L_LCD8 L_LCD9 L_LCD11 L_LCD10 L_LCD15 L_LCD14 L_LCD13 L_LCD12
C26 2 @4.7UF_1210 20 INVT_PWM
DISPOFF# LCDVDD LVDDVGA
PID[0..3]
PID[0..3]
10
+5VALW +3VS
1
RP18 5 6 7 8 4 3 2 1 8P4R-10K PID3 PID2 PID1 PID0
PID0 PID1 PID2 PID3 ENVDD DISPOFF# L_LCD15 L_LCD14 L_LCD13 L_LCD12 L_LCD11 L_LCD10
5 5 5 5
TXOUT1+ TXOUT1TXOUT0+ TXOUT0-
TXOUT1+ TXOUT1TXOUT0+ TXOUT0-
5 6 7 8 8P4R-0
1
CP3 TXCLK0+ TXCLK0TXOUT2+ TXOUT24 3 2 1 5 6 7 8 @8P4C-220PF CP5 4 3 2 1 5 6 7 8 TZOUT1TZOUT1+ TZOUT0+ TZOUT04 3 2 1 TZCLK0+ TZCLK0TZOUT2+ TZOUT21 2 3 4
CP18 8 7 6 5
@8P4C-220PF CP19 5 6 7 8
HEADER 25X2-LCD
@8P4C-220PF
@8P4C-220PF
LCDVDD +5V 1 2 R74 100 12 R83 10K R84 2 1 3 2 47K Q6 DTC124EK 22K 22K DTC124EK 3 C71 .1UF + Q13 R101 200K C100 1000PF 1 1 3 Q9 SI2302DS LCDVDD
C75 4.7UF_1206 10V +3VS
2
Q8 2N7002
R76 4.7K C90 4.7UF_1206 10V D11 RB717F 20 5,21 BKOFF# ENVEE 5 BLON# ENVEE 1 3 2 1 D Q11 2N7002 S 3 BLON# 2 G DISPOFF# DISPOFF# C24 220PF
5
ENVDD
ENVDD
2
22K 22K
3
3
CRT Connector
+5VS 1 1 D4 D40 D5 1
+5VS 2
D41 1 1 RB491D
F1 2 1
3
FUSE_1A C402 .1UF
2
3
2
3
2
3
DAN217
DAN217
DAN217
JP9 CRT-15P 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 D
L2 5 5 5 R G B R11 75 1 1 2 FCM2012C80_0805 L41 1 2 FCM2012C80_0805 L1 1 2 FCM2012C80_0805 1 1 1 1 1 1 C7 18PF 2 2 1 C399 18PF 2 C14 18PF 2 C13 15PF 2 L42 5 HSYNC1 3 2N7002 2 1 Q50
4
2
+12VS +5VS R32 100K 1 1 R65 2K G 2 S 2 R44 2K
2
2
2
CRT_VCC C398 15PF 2 C8 15PF
R336 75 1
R9 75
1 2 CHB1608U121 Q2 1 1 1 2 CHB1608U121 C43 220PF C403 @100PF 2 1 L3 1 1 1
2
1 3 Q4 2N7002 C33 220PF 2 2 D
2
1
2
DDC_DATA 5 G
1
S
5
VSYNC1 R28 +12VS 100K
3 2N7002 2
3
4
DDC_CLK 5
C397 68PF 2 2
C4 68PF
Q3 2N7002
Compal Electronics, Inc.
Title
PROPRIETARY NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
SCHEMATIC, M/B LA-1281
Size B Date: Document Number
401202
, 22, 2001 Sheet
E
Rev 1B 14 of 34
A
B
A
B
C
D
E
S1_IOWR# S1_IORD# S1_OE# S1_CE2#
S1_IOWR# 16 S1_IORD# 16 S1_OE# 16 S1_CE2# 16 +3V
S1_A[0..25] S1_D[0..15]
S1_A[0..25] 16 S1_D[0..15] 16
S1_D10 S1_D9 S1_D1 S1_D8 S1_D0 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A25 S1_A7 S1_A24 S1_A17 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_OE# S1_CE2# S1_A10 S1_D15 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_D3
+3VS
+3VS
CBRST# S1_VCC
16,23,28
1
1
127
79 134 180
124 122 121 120 119 116 113 111 109 107 105 103 102 100 99 83 81 80 78 77 75 74 73 71 68 67 66 65 64 63 62 59
5,9,23,28 AD[0..31]
6 21 37 50
U26 C246 GRST# A_SKT_VCC A_SKT_VCC A_REG#/CCBE3# A_A12/CCBE2# A_A8/CCBE1# A_CE1#/CCBE0# A_A16/CCLK A_A23/CFRAME# A_A15/CIRDY# A_A22/CTRDY# A_A21/CDEVSEL# A_A20/CSTOP# A_A13/CPAR A_A14/CPERR# A_WAIT#/CSERR# A_INPACK#/CREQ# A_WE#/CGNT# A_RDY_IRQ#/CINT# A_A19/CBLOCK# A_WP/CCLKRUN# A_RST/CRST# A_R2_D2/RFU A_R2_D14/RFU A_R2_A18/RFU A_VS1/CVS1 A_VS2/CVS2 A_CD1#/CCD1# A_CD2#/CCD2# A_BVD2/CAUDIO A_BVD1/CSTSCHG B_BVD1/CSTCHG B_BVD2/CAUDIO B_CD2#/CCD2# B_CD1#/CCD1# B_VS2/CVS2 B_VS1/CVS1 B_R2_A18/RFU B_R2_D14/RFU B_R2_D2/RFU B_RST/CRST# B_WP/CCLKRUN# B_A19/CBLOCK# B_RDY_IRQ#/CINT# B_WE#/CGNT# B_INPACK#/CREQ# B_WAIT#/CSERR# B_A14/CPERR# B_A13/CPAR B_A20/CSTOP# B_A21/CDEVSEL# B_A22/CTRDY# B_A15/CIRDY# B_A23/CFRAME# B_A16/CCLK B_CE1#/CCBE0# B_A8/CCBE1# B_A12/CCBE2# B_REG#/CCBE3# B_SKT_VCC B_SKT_VCC B_SKT_VCC OZ6933TQFP .1UF .1UF .1UF 117 98 60 112 97 82 70 .1UF C244 .1UF C247 .1UF
AUX_VCC
PCI_VCC PCI_VCC PCI_VCC PCI_VCC
CORE_VCC CORE_VCC CORE_VCC
2
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 5,9,23,28 5,9,23,28 5,9,23,28 5,9,23,28 PCLK_PCM 2 R283 @33 C/BE#3 C/BE#2 C/BE#1 C/BE#0
4 5 7 8 9 10 11 12 16 17 18 19 20 22 23 24 38 39 40 41 42 43 45 46 48 49 51 52 53 54 55 56 13 25 36 47 15 1 31 27 29 30 32 35 33 34 3 2 203 204 58 207 163 208 72 128 133 193 205 206
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE3# C/BE2# C/BE1# C/BE0#
A_D10/CAD31 A_D9/CAD30 A_D1/CAD29 A_D8/CAD28 A_D0/CAD27 A_A0/CAD26 A_A1/CAD25 A_A2/CAD24 A_A3/CAD23 A_A4/CAD22 A_A5/CAD21 A_A6/CAD20 A_A25/CAD19 A_A7/CAD18 A_A24/CAD17 A_A17/CAD16 A_IOWR/CAD15 A_A9/CAD14 A_IORD#/CAD13 A_A11/CAD12 A_OE#/CAD11 A_CE2#/CAD10 A_A10/CAD9 A_D15/CAD8 A_D7/CAD7 A_D13/CAD6 A_D6/CAD5 A_D12/CAD4 A_D5/CAD3 A_D11/CAD2 A_D4/CAD1 A_D3/CAD0
S1_A12 S1_A8
S1_REG# 16 S1_CE1# S1_A16 16
CardBus Controller OZ6933T (TQFP)
93 R208 1 2 33 S1_A23 96 S1_A15 95 S1_A22 94 S1_A21 92 S1_A20 90 S1_A13 84 S1_A14 86 108 110 89 91 S1_A19 88 125 106 S1_D2 123 S1_D14 69 S1_A18 85 76 104 61 126 114 118 192 190 202 136 179 152 161 145 198 182 201 164 167 165 186 184 162 159 166 168 170 171 172 169 147 157 173 188 143 160 200
S1_WAIT# 16 S1_INPACK# 16 S1_WE# 16 S1_RDY# 16 S1_WP S1_RST 16 16
2
S1_VS1 S1_VS2 S1_CD1# S1_CD2# S1_BVD2 S1_BVD1 S2_BVD1 S2_BVD2 S2_CD2# S2_CD1# S2_VS2 S2_VS1
16 16 16 16 16 16 16 16 16 16 16 16
C326 @10PF
3
5,9,23,28 AD15 11 PCLK_PCM 5,9,12,23,28 DEVSEL# 5,9,12,23,28 FRAME# 5,9,12,23,28 IRDY# 5,9,12,23,28 TRDY# 5,9,12,23,28 STOP# 5,9,12,23,28 PAR 12,23,28 PERR# 5,9,12,23,28 SERR# 5 REQ#3 5 GNT#3 5,9,12 PIRQA# 9,12,23 PIRQB# 5,12 PLOCK# 5,9,13,16,19,23,28 PCIRST# 21 PCM_PME# 5,9,12,23,28 CLKRUN# 23 PCM_RI# 26 PCM_SPK# 21 PCM1_LED 21 PCM2_LED 10,12 SIRQ
R269 100 1 2 PCLK_PCM
IDSEL PCI_CLK DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# SERR# PCI_REQ# PCI_GNT# IRQ9/INTA# IRQ4/INTB#/A_VPP_PGM LOCK# RST# IRQ12/PME# IRQ14/CLKRUN# IRQ15/RI_OUT# SPKR_OUT# LEDO#/SKTA_ACTV IRQ11/SKTB_ACTV IRQ5/SERIRQ# IRQ7/SIN#/B_VPP_PGM GND GND GND GND GND GND GND GND IRQ3/A_VCC_3# SCLK/A_VCC_5# SDATA/B_VCC_3# SLATCH/SMBCLK/B_VCC_5# IRQ9/A_VPP_VCC_PGM IRQ10/B_VPP_VCC_PGM
S2_A18 S2_D14 S2_D2 S2_A19
S2_RST S2_WP
16 16
S2_A14 S2_A13 S2_A20 S2_A21 S2_A22 S2_A15 S2_A23 1 R291 S2_A8 S2_A12
S2_RDY# 16 S2_WE# 16 S2_INPACK# 16 S2_WAIT# 16
1
3
2 33
S2_A16 16
S2_CE1#
B_D10/CAD31 B_D9/CAD30 B_D1/CAD29 B_D8/CAD28 B_D0/CAD27 B_A0/CAD26 B_A1/CAD25 B_A2/CAD24 B_A3/CAD23 B_A4/CAD22 B_A5/CAD21 B_A6/CAD20 B_A25/CAD19 B_A7/CAD18 B_A24/CAD17 B_A17/CAD16 B_IOWR#/CAD15 B_A9/CAD14 B_IORD#/CAD13 B_A11/CAD12 B_OE#/CAD11 B_CE2#/CAD10 B_A10/CAD9 B_D15/CAD8 B_D7/CAD7 B_D13/CAD6 B_D6/CAD5 B_D12/CAD4 B_D5/CAD3 B_D11/CAD2 B_D4/CAD1 B_D3/CAD0
S2_REG# 16 S2_VCC
C340
C345
C310
14 26 28 44 57 101 129 177
87 132 131 130 115 146
S2_D10 S2_D9 S2_D1 S2_D8 S2_D0 S2_A0 S2_A1 S2_A2 S2_A3 S2_A4 S2_A5 S2_A6 S2_A25 S2_A7 S2_A24 S2_A17
C302 4.7UF_10V_0805 2
C321 .1UF
C341 .1UF
C301 .1UF +3V
S2_A9
+3VS 1
4
S2_A10 S2_D15 S2_D7 S2_D13 S2_D6 S2_D12 S2_D5 S2_D11 S2_D4 S2_D3 S2_CE2# S2_OE# S2_IORD# S2_IOWR# S2_A[0..25] S2_D[0..15]
S2_A11
199 197 196 195 194 191 189 187 185 183 181 178 176 175 174 158 156 155 154 153 151 150 149 148 144 142 141 140 139 138 137 135
+3VS C291 C258 .1UF C245 .1UF C261 .1UF C282 .1UF .1UF
SLATCH SLDATA RTCCLK
16 16 9,16
S2_CE2# 16 S2_OE# 16 S2_IORD# 16 S2_IOWR# 16 S2_A[0..25] 16 S2_D[0..15] 16 Title
4
Compal Electronics, Inc.
SCHEMATIC, M/B LA-1281 401202
Rev 1B Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
Size Document Number Custom Date: , 22, 2001 15 of 34
PCMCIA POWER CTRL.
+3V +5V +12V
Wire ZV PORT to Slot A
S1_VPP W=40mils U36 25 VCC_5V 12V 12V 5V 5V 5V 3.3V 3.3V 3.3V DATA LATCH CLOCK APWR_GOOD# BPWR_GOOD# OC# TPS2206AI/TPS2216 AVPP AVCC AVCC AVCC BVPP BVCC BVCC BVCC RESET RESET# NC NC NC NC GND 8 9 10 11 23 20 21 22 6 14 2 26 27 28 29 12 1 C354
S1_VPP S1_VCC
CARDBUS SOCKET
JP19 A77 A76 A75 A74 A73 A72 A71 A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 A50 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 a68 a34 a67 a33 GND a66 a32 a65 a31 a64 a30 a63 GND a29 a62 a28 a61 a27 a60 a26 GND a59 a25 a58 a24 a57 a23 a56 GND a22 a55 a21 a54 a20 a53 GND a19 a52 a18 a51 a17 a50 a16 a49 a15 a48 a14 a47 a13 GND a46 a12 a45 a11 a44 GND a10 a43 a9 a42 a8 GND a41 a7 a40 a6 a39 a5 GND a38 a4 a37 a3 a36 a2 a35 a1 b68 b34 b67 b33 GND b66 b32 b65 b31 b64 b30 b63 GND b29 b62 b28 b61 b27 b60 b26 GND b59 b25 b58 b24 b57 b23 b56 GND b22 b55 b21 b54 b20 b53 GND b19 b52 b18 b51 b17 b50 b16 b49 b15 b48 b14 b47 b13 GND b46 b12 b45 b11 b44 GND b10 b43 b9 b42 b8 GND b41 b7 b40 b6 b39 b5 GND b38 b4 b37 b3 b36 b2 b35 b1 B77 B76 B75 B74 B73 B72 B71 B70 B69 B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 15 15 S1_CD2# S1_WP S1_CD2# S1_WP S1_D10 S1_D2 S1_D9 S1_D1 S1_D8 S1_D0 S1_BVD1 S1_A0 S1_BVD2 S1_A1 S1_REG# S1_A2 S1_INPACK# S1_A3 S1_WAIT# S1_A4 S1_RST S1_A5 S1_VS2 S1_A6 S1_A25 S1_A7 S1_A24 S1_A12 S1_A23 S1_A15 S1_A22 S1_A16 S1_VPP S1_VCC S1_A21 S1_RDY# S1_A20 S1_WE# S1_A19 S1_A14 S1_A18 S1_A13 S1_A17 S1_A8 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_VS1 S1_OE# S1_CE2# S1_A10 S1_D15 S1_CE1# S1_D14 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_CD1# S1_D3 S2_CD2# S2_WP S2_D10 S2_D2 S2_D9 S2_D1 S2_D8 S2_D0 S2_BVD1 S2_A0 S2_BVD2 S2_A1 S2_REG# S2_A2 S2_INPACK# S2_A3 S2_WAIT# S2_A4 S2_RST S2_A5 S2_VS2 S2_A6 S2_A25 S2_A7 S2_A24 S2_A12 S2_A23 S2_A15 S2_A22 S2_A16 S2_VPP S2_VCC S2_A21 S2_RDY# S2_A20 S2_WE# S2_A19 S2_A14 S2_A18 S2_A13 S2_A17 S2_A8 S2_IOWR# S2_A9 S2_IORD# S2_A11 S2_VS1 S2_OE# S2_CE2# S2_A10 S2_D15 S2_CE1# S2_D14 S2_D7 S2_D13 S2_D6 S2_D12 S2_D5 S2_D11 S2_D4 S2_CD1# S2_D3 S2_RDY# 15 S2_WE# 15 S2_CD2# 15 S2_WP 15
1 1 1 1 1 1 1
C355 2 1UF_25V_0805 2 C356 .1UF 2 C357 .1UF 2 C395 .1UF 2 C370 .1UF 2 C381 .1UF 2 C382 .1UF
7 24 1 2 30 15 16 17 15 15 9,15 SLDATA SLATCH RTCCLK 3 5 4 13 19 18 2
4.7UF_10V_0805 S2_VPP S2_VCC
S2_VPP W=40mils 1 C394
2
4.7UF_10V_0805
15 15
S1_BVD1 S1_BVD2 S1_REG# S1_INPACK# S1_WAIT# S1_RST S1_VS2
S2_BVD1 15 S2_BVD2 15 S2_REG# 15 S2_INPACK# 15 S2_WAIT# 15 S2_RST S2_VS2 15 15
CBRST#
15 15 15 15 15
21
OCCB# +3V 1 R314 100K
15 15 15 15
S1_A[0..25] S1_D[0..15] S2_A[0..25] S2_D[0..15]
S1_A[0..25] S1_D[0..15] S2_A[0..25] S2_D[0..15] +3V PCMRST# 20
15 15
S1_RDY# S1_WE#
S2_VPP 1
W=30mils 5,9,13,15,19,23,28 PCIRST# C300 1UF_25V_0805 U28A 74LVC125 2 1
14 2 7 +3V POWER 3 1 CBRST# CBRST# 15,23,28
1
15 15 15 15 15 C494 S1_CD1# 1 1000PF S1_CD2# 1 1000PF 2 C468 15
S1_IOWR# S1_IORD# S1_VS1 S1_OE# S1_CE2#
S2_IOWR# 15 S2_IORD# 15 S2_VS1 S2_OE# S2_CE2# 15 15 15
C293 .01UF 2
R262 10K 2
S1_VPP 1
W=30mils 1
+3V C299 1UF_25V_0805 2
S1_CE1#
S2_CE1#
15
C292 .01UF 2
2
C493 S2_CD1# 1 2 1000PF C467 S2_CD2# 1 2 15 S1_CD1#
S1_VCC
S2_CD1# 15
1000PF 1 1 1 C312 56PF 2 2 C308 .1UF 2 C305 1000PF
PCMC154PIN
C322 10UF_1206
S2_VCC
Compal Electronics, Inc.
1 1 1 C309 C306 .1UF 2 2 C313 1000PF THIS SHEET OF ENGINEERING DRAWING IS T