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Service Guide
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Acer AL2032W Service Guide
Service guide files and updates are available on the CSD web: for more information, Please refer to http://csd.acer.com.tw/
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Copyright
Copyright © 2004 by Acer Incorporated. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written permission of Acer Incorporated.
Disclaimer
The information in this guide is subject to change without notice. Acer Incorporated makes no representations or warranties, either expresses or implied, with respect to the contents hereof and specifically disclaims any warranties of merchantability or fitness for any particular purpose, Any Acer Incorporated software described in this manual is sold or licensed "as is ". Should the programs prove defective following their purchase, the buyer (and not Acer Incorporated, its distributor, of its dealer) assumes the entire cost of all necessary servicing, repair, and any incidental or consequential damages resulting from any defect in the software.
Acer is a registered trademark of Acer Corporation. Intel is a registered trademark of Intel Corporation. Pentium and Pentium II/III are trademarks of Intel Corporation. Other brand and product names are trademarks and/or registered trademarks of their respective holders.
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Conventions
The following conventions are used in this manual:
Screen messages Note Warning Caution Important
Denotes actual messages that appear on screen Gives bits and pieces of additional information related to the current topic. Alerts you to any damage that might result from doing or not doing specific actions. Gives precautionary measures to avoid possible hardware or software problems. Reminds you to do specific actions relevant to the accomplishment of procedures.
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Preface
Before using this information and the product it supports, please read the following general information. 1. this Service Guide provides you with all technical information relating to the BASICCONFIGURATION decided for Acer's "global" product offering. To better fit local market requirements and enhance product competitiveness, your regional office MAY have decided to extend the functionality of a machine (e.g. add-on card, modem, or extra memory capability). These LOCALIZED FEATURES will NOT be covered in this generic service guide. In such cases, please contact your regional offices or the responsible personnel/channel to provide you with further technical details. 2. please not WHEN ORDERING FRU PARTS, that you should check the most up-to-date information available on your regional web or channel. If, for whatever reason, a part number change is made, it will not be noted in the printed Service Guide, for ACER-AUTHORIZED SERVICE PROVIDERS, your Acer office may have a DIFFERENT part number code to those given in the FRU list of this printed Service Guide. You MUST use the list provided by your regional Acer office to order FRU parts for repair and Service of customer machines.
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WARNING: (FOR FCC CERTIFIED MODELS) NOTE: this equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy, and if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, Which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: 1. Reorient or relocate the receiving antenna. 2. Increase the separation between the equipment and receiver. 3. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. 4. Consult the dealer or an experienced radio/TV technician for help.
NOTICE:
1. The changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. 2. Shielded interface cables and AC power cord, if any, must be used in order to comply with the emission limits. 3. The manufacturer is not responsible for any radio or TV interference caused by unauthorized modification to this equipment. It is the responsibility of the user to correct such interference. As an ENERGY STAR® Partner our company has determined that this product meets the ENERGY STAR® guidelines for energy efficiency.
WARNING:
To prevent fire or chock hazard, do not expose the monitor to rain or moisture. Dangerously high voltages are present inside the monitor. Do not open the cabinet. Refer servicing to qualified personnel only.
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PRECAUTIONS
Do not use the monitor near water, e.g. near a bathtub, washbowl, kitchen sink, laundry tub, Swimming pool or in a wet basement. Do not place the monitor on an unstable trolley, stand, or table. If the monitor falls, it can injure a person and cause serious damage to the appliance. Use only a trolley or stand recommended by the manufacture or sold with the monitor. If you mount the monitor on a wall or shelf, use a mounting kit approved by the manufacture and follow the kit instructions. Slots and openings in the back and bottom of the cabinet area provided for ventilation. To ensure reliable operation of the monitor and to protect it from overheating, be sure these openings are not blocked or covered. Do not place the monitor on a bed, sofa, rug or similar surface. Do not place the monitor near or over a radiator or heat register. Do not place the monitor in a bookcase or cabinet unless proper ventilation is provided. The monitor should be operated only from the type of power source indicated on the label. If you are not sure of the type of power supplied to your home, consult your dealer or local power company. The monitor is equipped with a three-pronged grounded plug, a plug with a third (grounding) pin. This plug will fit only into a grounded power outlet as a safety feature. If your outlet does not accommodate the three-wire plug, have an electrician install the correct outlet, or use an adapter to ground the appliance safely. Do not defeat the safety purpose of the grounded plug. Unplug the unit during a lightning storm or when it will not be used for long periods of time. This will protect the monitor from damage due to power surges. Do not overload power strips and extension cords. Overloading can result in fire or electric shock. Never push any object into the slot on the monitor cabinet. It could short circuit parts causing a fire or electric shock. Never spill liquids on the monitor. Do not attempt to service the monitor yourself; opening or removing covers can expose you to dangerous voltages and other hazards. Please refer all servicing to qualified service personnel. To ensure satisfactory operation, use the monitor only with UL listed computers which have appropriate configured receptacles marked between 100-240V AC, Min. 3.5A. The wall socket shall be installed near the equipment and shall be easily accessible. For use only with the attached power adapter (output 12V DC) which have UL,CSA listed license
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SPECIAL NOTES ON LCD MONITORS
The following symptoms are normal with LCD monitor and do not indicate a problem.
NOTES
Due to the nature of the fluorescent light, the screen may flicker during initial use. Turn off the Power Switch and then turn it on again to make sure the flicker disappears. You may find slightly uneven brightness in the screen depending on the desktop pattern you use. The LCD screen has effective pixels of 99.99% or more. It may include blemishes of 0.01% or less such as a missing pixel or a pixel lit all of the time. Due to the nature of the LCD screen, an afterimage of the previous screen may remain after switching the image, when the same image is displayed for hours. In this case, the screen is recovered slowly by changing the image or turning off the Power Switch for hours.
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Table of contents
Chapter 1 MONITOR FEATURE ...................................................................9
Chapter 2 OPERATING INSTRUTION .............................................................15 Chapter 3 Machine assembly .....................................................................21 Chapter 4 TROBLE SHOOTING ...................................................................27 Chapter 5 CONNECTOR INFORMATION .......................................................29
Chapter 6 FRU LIST ...................................................................................30 Chapter 7 SCHEMATIC DIAGRAM ..................................................................31
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Chapter 1
Monitor Feature
Driving system Size Pixel pitch Viewable angle Brightness Contrast Ratio LCD Panel Input Response time Video Separate Sync H-Frequency V-Frequency Display Color Maximum Dot Clock ® Max Resolution Plug & Play ON Mode EPA ENERGY STAY Audio output Input Connector Input Video Signal Screen Size (Active) Power Source Environmental Considerations Weight (N.W.) Dimension OFF Mode TFT Color LCD 20.1" wide 0.258 mm 178(H) x 178 (V) degree LG panel: 300 cd/m2(typ) 600:1 (typ) 16ms (Tr+Tf) R,G,B Analog & DVI box (optional) H/V TTL 31-81KHZ 50-75HZ 16.7 million Colors 162MHz 1680X1050@60HZ VESA DDC2B <75W <3W Rated Power 5.0W rms(Per channel) D-Sub 15 pin, or DVI-D cable Analog : 0.7Vp-p,75OHM Horizontal : 433.4mm Vertical : 270.9mm 90~240 Vac, 50~60HZ Operating Temp : 5 to 40 degree ; Storage Temp : -20 to 60 degree ; Operating Humidity : 15% to 85% 6.8kg 510.3(W) x 443.9(H) x 206.6D) mm
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Switch
* Power Switch * MENU/ENTER * / Volume * / Volume * Auto Adjust KEY
Function External Controls : Regulatory Compliance
* Contrast/brightness * Focus * Clock * H.Position * W.Position * Language * OSD Color temperature * OSD Position & Timeout * Auto Config * Input * Information * Reset * Exit cUL, FCC, TUV, CE, ISO13406-2
Timeings
The product has 29 memory modes in total. 19 modes are preset and 10 modes
are user definable. MODE NO. RESOLUTION 1 720 x 400 2 640 x 480 3 640x480 4 640 x 480
Dot clock(MHz)
28.321
25.175
30.24
31.5
fh H-Total ( us ) H-Sync ( us ) H-B-P ( us ) H-Active ( us ) H-F-P ( us )
31.469kHz 31.78(900dots) 3.813(108dots) 1.907(54dots) 25.42(720dots) 0.636(18dots)
31.469kHz 31.778 (800 dots) 3.813 (96 dots) 1.907 (48 dots) 25.422 (640 dots) 0.636 (16 dots)
35.0kHz 28.571(864 dots) 2.116 (64 dots) 3.175 (96 dots) 21.164 (640 dots) 2.116 (64 dots)
37.861kHz 26.413 (832 dots) 1.270(40 dots) 4.064(128 dots) 20.317(640 dots) 0.762(24 dots)
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fv V-Total (ms ) V-Sync ( ms ) V-B-P (ms ) V-Active ( ms ) V-F-P ( ms ) SYNC. H/V POLARITY SEP . SYNC
70Hz(70.087) 14.27(449 lines) 0.064(2 lines) 1.112(35 lines) 12.71(400 lines) 0.384(12 lines) -/+
60Hz (59.940) 16.683 (525 lines ) 0.064 (2 lines ) 1.049 (33 lines ) 15.253 (480 lines ) 0.317 ( 10 lines) -/-
66.7 HZ (66.667) 15.000 (525 lines ) 0.086 (3 lines ) 1.114 (39 lines ) 13.714 (480 lines ) 0.086 (3 lines ) +/+ Or -/-
72.809Hz 13.735(520 lines) 0.079(3 lines) 0.739(28 lines) 12.678(480 lines) 0.237(9 lines) -/-
Y
Y
Y
Y
MODE NO. RESOLUTION
5 640 x 480
6 800 x 600
7 800 x 600
8 800 x 600
Dot clock(MHz)
31.5
36
40
49.5
fh H-Total ( us ) H-Sync ( us ) H-B-P ( us ) H-Active ( us ) H-F-P ( us )
37.500kHz 26.667(840 dots) 2.032 (64 dots) 3.810 (120 dots) 20.317 (640 dots) 0.508 (16 dots)
35.16kHz 28.44(1024 dots) 2.00(72 dots) 3.56(128 dots) 22.22(800 dots) 0.67(24 dots)
37.879kHz
46.875kHz
26.40 (1056 dots) 21.333 (1056dots) 3.200 (128 dots) 2.200 ( 88 dots) 20.00 ( 800 dots) 1.000 (40 dots) 1.616 (80 dots) 3.232 (160 dots) 16.162 (800 dots) 0.323 (16 dots)
fv V-Total (ms ) V-Sync ( ms ) V-B-P (ms ) V-Active ( ms ) V-F-P ( ms ) SYNC. H/V POLARITY SEP . SYNC
75Hz (75) 13.333 (500 lines) 0.080 (3 lines) 0.427 (16 lines) 12.80 (480 lines) 0.027 ( 1 line ) -/-
56.25 17.78(625 lines) 0.06(2 lines) 0.63(22 lines) 17.07(600 lines) 0.03( 1 line) +/+
60Hz (60.316) 16.58 (628 lines) 0.106 (4 lines) 0.607 (23 lines) 15.84 (600 lines) 0.026 (1 line ) +/+
75Hz (75.000) 13.333 (625lines) 0.064 (3 lines) 0.448 (21 lines) 12.80 (600lines) 0.021 (1 line ) +/+
Y
Y
Y
Y
MODE NO. RESOLUTION
9 800 x 600
10 832 x 624
11 1024 x 768
12 1024 x 768
Dot clock(MHz)
50
57.283
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65
75
fh H-Total ( us ) H-Sync ( us ) H-B-P ( us ) H-Active ( us ) H-F-P ( us )
48.077kHz 20.80 (1040dots) 2.400 ( 120 dots) 1.280 (64 dots) 16.00 (800 dots) 1.120 (56 dots)
49.72kHz 20.11(1152 dots) 1.12(64 dots) 3.91(224 dots) 14.52( 832 dots ) 0.56(32 dots )
48.363kHz 20.677(1344 dots) 2.092(136 dots) 2.462(160 dots) 15.754(1024 dots) 0.369(24 dots)
56.48kHz 17.71(1328 dots) 1.81(136 dots) 1.92(144 dots) 13.65(1024 dots) 0.32(24 dots)
fv V-Total (ms ) V-Sync ( ms ) V-B-P (ms ) V-Active ( ms ) V-F-P ( ms ) SYNC. H/V POLARITY SEP . SYNC
72Hz (72.188) 13.85 (666 lines) 0.125 (6 lines) 0.478 (23 lines) 12.48 (600 lines) 0.770 ( 37 +/+ line )
74.55Hz 13.41(667 lines) 0.06(3 lines) 0.78(39 lines) 12.55 (624 lines) 0.02(1 line) +/+
60.004Hz 16.666(806 lines) 0.124(6 lines) 0.600(29 lines) 15.880(768 lines) 0.062(3 lines) -/-
70.07Hz 14.27(806 lines) 0.11(6 lines) 0.51(29 lines) 13.60(768 lines) 0.05(3 lines) -/-
Y
Y
Y
Y
MODE NO. RESOLUTION
13 1024 x 768
14 1280 x 1024
15 1280 x 1024
16 1152 x 864
Dot clock(MHz)
78.75
108
135
108
fh H-Total ( us ) H-Sync ( us ) H-B-P ( us ) H-Active ( us ) H-F-P ( us )
60.02kHz 16.66(1312 dots) 1.22 (96 dots) 2.23 (176 dots) 13.00 (1024 dots) 0.20 (16 dots)
63.981kHz 15.630 (1688 dots) 1.037 (112 dots) 2.296 (248 dots) 11.852 (1280 dots) 0.444 (48 dots)
79.976KHz
67.5 KHz
12.504 (1688 dots) 14.815(1600 dots) 1.067 (144 dots) 1.837 (248 dots) 9.481 (1280dots) 0.119 (16 dots) 1.185(128 dots) 2.370(256 dots) 10.667(1152 dots) 0.593(64 dots)
fv V-Total (ms ) V-Sync ( ms ) V-B-P (ms ) V-Active ( ms ) V-F-P ( ms )
75.03Hz 13.33 (800 lines) 0.05 (3 lines) 0.47 (28 lines) 12.80 (768 lines) 0.02 (1 lines)
60.020Hz
75.025 Hz
75.06 Hz 13.333(900 lines) 0.044(3 lines) 0.474(32 lines) 12.800(864 lines) 0.015(1 lines)
16.661 (1066 lines) 13.329 (1066 lines) 0.047 ( 3 lines) 0.594 ( 38 lines) 16.005 (1024 lines) 0.016 (1 line )
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0.038 (3 lines) 0.475 (38 lines) 12.804(1024 lines) 0.013 (1 lines)
SYNC. H/V POLARITY SEP . SYNC 17" MODE NO. RESOLUTION
-/-
+/+
+/+
+/+
Y
Y
Y
Y
17 1280 x 960
18 1600 x 1200
19 1280 x 720
20
Dot clock(MHz)
108
162
74.176
fh H-Total ( us ) H-Sync ( us ) H-B-P ( us ) H-Active ( us ) H-F-P ( us )
60.000 KHz 16.667 (1800dots) 1.037 ( 112 dots) 2.889 (312 dots) 11.852 (1280 dots) 0.889 (96 dots)
75.000 KHz 13.333 (2160 dots) 1.185 ( 192 dots) 1.877 (304 dots) 9.877 (1600 dots) 0.395 (64 dots)
44.955KHz 22.244 (1650dots) 0.539 ( 40 dots) 2.966 (220 dots) 17.256 (1280 dots) 1.483 (110 dots)
fv V-Total (ms ) V-Sync ( ms ) V-B-P (ms ) V-Active ( ms ) V-F-P ( ms ) SYNC. H/V POLARITY SEP . SYNC
60.00Hz
60.00 Hz
59.94Hz 16.683 (750 lines) 0.111 (5 lines) 0.445 (20 lines) 16.016 (720 lines) 0.111 (5 lines) +/+
16.667 (1000 lines) 16.667 (1250 lines) 0.050 (3 lines) 0.600 (36 lines) 16.000 (960 lines) 0.017 ( 1 +/+ line ) 0.040 (3 lines) 0.613 (46 lines) 16.000 (1200 lines) 0.013 ( 1 +/+ line )
Y
Y
HDTV
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Monitor Block Diagram
+3.3V I/O A U +2.5V D +3.3V D _ _M LIB _D R _LV SA
+1.8V V _D I
+1.8V D _A C
+3.3V _PLL
+1.8V RE _CO
+3.3V _LBA C D
+3.3V D _LV SB
+3.3V D _LV S
+3.3V V _D I
+3.3V D _A C
D ITA D C IG L D 24A 02 (U A 12)
SD /SCL A
PO ERSW W ITCH A 1563(U IC 2) (U +2.5V 3) (U +3.3V 4) +12VFRO M (U +1.8V 6) PO ERB A W O RD
D I IN T V PU ( CN ) 8
A A GD C N LO D 24A 02 (U A 10)
RX , RX RX , RX 2 1, 0 C
RESET
/RESET MX A 809_1(U 8)
G 1601 (U M 5)
RED, G REEN, BLU , SD /SCL E A
V AIN T G PU ( CN ) 7
SD /SCL A
M SCL/SD STR A
I2C 24LC32SN(U 7)
FSD TA D R,FSB SEL0/1 A ,FSA D K FSCLK -/+,FSD M Q
FRA ESTO M RE M 2M -4( U ) T46V 32LG 1
M O I/F EM RY 39V ( X 1) F020 U
O AD CM D R[0..19],O M A [0..7] C D TA
TX 0+/-, TX 1+/-, TX 2+/-,TX 3+/-, TX C+/A A A A A TX 0+/-,TX 1+/-, TX 2+/-, TX 3+/-, TX C+/B B B B B
TOPA EL N (CN 2)
LBA C_RETU / IN / IN / IN D RN 1 2 3
K CO TRO EY N L (CN 4)
M TE U
PW 1 M
V LU E O M
A D IN( L/R) U IO
AD U IO TPA 3002D ( U ) 2 9
SPK R0+/SPK L0+/-
SPEA K ( CN ) 6
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PCB CONDUCTOR VIEW
Main Board
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Button Board
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Chapter 2
OPERATING INSTRUCTIONS Front Panel Definition
This Section defines the front panel User Interface for Led Indictor and Key function. Key Definition: There are five keys defined in this system and described bellows. * Adjusting display settings
External Controls
Power on/off 1 POWER Blue: power on Orange: in sleep mode 2 OSD Function Press to view OSD. Press again to enter a selection in OSD.
3
If OSD is active, press to select or adjust OSD options. If OSD UP/ PLUS is inactive, press once, then press the buttons marked or to adjust the volume. DOWN / MINUS If OSD is active, press to select or adjust OSD options. If OSD is inactive, press once, then press the buttons marked or to adjust the volume. If OSD is active, press to exit a selection in OSD. If OSD is inactive, press and the monitor will automatically optimize the position, focus and clock of your display.
4
5
AUTO
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OSD Menu Picture
Brightness: This adjusts the brightness of the picture on the screen. Contrast: This adjusts dark and light shades of color relative to each other to achieve a comfortable contrast. Color temp. : There are three ways of adjusting color: Warm (Reddish white) Cool (Bluish white) User : You can adjust the colors red, green and blue to the intensity you desire. Focus: This removes any horizontal distortion and makes the picture clear and sharp. Clock: If there are any vertical stripes seen on the background of the screen this renders them less noticeable by minimizing their size. It also changes the size of the horizontal screen. H-Position: This adjusts the horizontal screen position. V-Position: This adjusts the vertical screen position.
Audio
Volume: Adjusts the volume. Mute : on /off
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Option
Auto Config. : System runs auto-configuration. Reset: Recall to default settings. Information: This shows brief information on the screen.
Setting
Language: Select the OSD menu language from English, French, German, Italian, Spanish, Simplified Chinese, Traditional Chinese, Japanese and Russian. OSD H. Position OSD V. Position OSD Time-out This changes the position of the OSD window on the screen and staying time.
LED Definition
The system equips one dual color (blue/amber) led to indict system status and defined as bellows : LED Color Blue Amber Dark System Status System in normal operation mode System in power-saving mode System in power-off mode
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LOGO :
When the monitor is power on, the LOGO will be showed in the center, and disappear slowly.
HOW TO OPTIMIZE THE DOS-MODE Plug and play
Plug & play DDC2B feature This monitor is equipped with VESA DDC2B capabilities according to the VESA DDC STANDARD. It allows the monitor to inform the host system of its identity and, depending on the level of DDC used, communicate additional information about its display capabilities. The communication channel is defined in two levels, DDC2B. The DDC2B is a bi-directional data channel based on the I2C protocol. The host can request EDID information over the DDC2B channel. THIS MONITOR WILL APPEAR TO BE NON-FUNCTIONAL IF THERE IS NO VIDEO INPUT SIGNAL. IN ORDER FOR THIS MONITOR TO OPERATE PROPERLY, THERE MUST BE A VIDEO INPUT SIGNAL. This monitor meets the Green monitor standards as set by the Video Electronics Standards Association(VESA) and/or the United States Environmental Protection Agency (EPA) and The Swedish Confederation Employees (NUTEK). This feature is designed to conserve electrical energy by reducing power consumption when there is no video-input signal present. When there is no video input signal this monitor, following a time-out period, will automatically switch to an OFF mode. This reduces the monitor's internal power supply consumption. After the video input signal is restored, full power is restored and the display is automatically redrawn. The appearance is similar to a "Screen Saver" feature except the display is completely off. The display is restored by pressing a key on the keyboard, or clicking the mouse.
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USING THE RIGHT POWER CORD
The accessory power cord for the Northern American region is the wallet plug with NEMA 5-15 style and is UL listed and CSA labeled. The voltage rating for the power cord shall be 125 volt AC. Supplied with units intended for connection to power outlet of personal computer: Please use a cord set consisting of a minimum No. 18 AWG, type SJT or SVT three conductors flexible cord. One end terminates with a grounding type attachment plug, rated 10A, 250V,CEE-22 male configuration. The other end terminates with a molded-on type connector body, rated 10A, 250V, having standard CEE-22 female configuration. Please note that power supply card needs to use VDE 0602, 0625, 0821 approval power cord in European counties.
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Chapter 3
Machine assembly
This chapter contains step-by-step procedures on how to assemble the monitor for maintenance and trouble shooting NOTE : 1. The screws for the different components vary in size. During the disassembly process, group the
screws with the corresponding to avoid mismatch when putting back the components. 2. Note : The monitor surface is susceptible to scratching! Therefore, lay the monitor on a soft surface when mounting or removing the base. 3. Wear gloves.
Front View :
( unit : mm )
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Real View :
Top View :
- 23 -
Side View :
( unit : mm )
Assembly process Picture
Description
1. Get the panel and put it on the table carefully.
1. Fix left and right bracket (BKT) on the panel.
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1. Get bezel and put it on the table 2. Assemble panel into bezel
1. Lock screw * 3 pcs to fasten bezel and left side bracket (BKT) . 2. Lock screw * 3 pcs to fasten bezel and right side bracket (BKT).
1. Insert LCD cable in panel connector
1. Assemble speaker on the bezel
1. Tidy speaker cable as picture shows.
1. Assemble PCB BKT on the L/R of BKT 2. Tidy cable as picture shows
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1. Get inverter and insert cable
2. Insert button cable in main board connector
1. Lock 4*pcs screw to fasten m/b and PCB BKT
1.
First to lock 4*pcs screw to fasten Inverter board on the PCB BKT
2. Get m/b and insert speaker cable, then assemble it on the
1. Lock 4 pcs screw to fasten m/b on the pcb BKT
1. Insert INV-M/B cable, then tidy button cable and inv-m/b
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1.
Lock screw*2pcs to fasten panel hold
1.
insert LCD cable in m/b connector
1. Assemble shielding and pcb BKT 2. Lock 7pcs screw to fasten shielding 3. Insert ccft cable L/R of into inverter/b connector
1. Stick al foil *2pcs on ccft connector of pcb shielding
1. Lock io nut 2pcs in VGA connector
1. Assemble button/b and back cover
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1. Insert button/b cable in button/b connector
1. Assembly back cover and bezel 2. Lock screw * 6 pcs cover to fasten and back
1. Lock screw*2 pcs to fasten bezel and PCB shielding.
2. Assembly DVI box, if necessary.
1. Assembly stand base and back cover. 2. lock screw *6 pcs to fix it.
1. Assembly VESA cover and back cover.
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Chapter 4
TROUBLE SHOOTING This chapter provides trouble shooting information forAL2032
1. No Power No Power
Check Adaptor Power Output =18V
NO
Change Adaptor Power Board
OK
Check Scalar Module Output L4 =5V? U4 #2 = 3.3V ? L 13 = 1.8V ? NO Change Scalar Module Board
OKKK
Check Power Button From Scalar/B(CN5) to Button/B(CN1)
NO
Check Cable Yes Open ?
Change Cable
NO
Change Switch or Button Board
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2. No Characters , Missing one color
NoCharacters Missing one color
Check CN4 12Vdc Output
No
Change Adaptor
OK
Check L4 5Vdc Output
No
Check or Change U2 , Q6 , D3
OK
Check U6(pin2) 1.8Vdc Output
No
Check or Change U6
OK
Check U4(pin2) 3.3Vdc Output
No
Check or Change U4
OK
Change Inverter Board
No
Check Inverter From Scaler board OK ?
Check CN2 to Panel Signal Output
No
Check or Change Cable Or Panel
OK
Check X Tal 14.318 Mhz ?
No
Change X1
OK No
Change VGA Cable Check H , V SYNC ?
OK
Change U5
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3. No audio
No Audio
No
Check Input source Or Change CN9 Check Input Signal CN9 OK ?
OK No
Check CN6 to Speaker OK ? Change Speaker or CN6(Cable)
OK No
Check U12(Pin9) Change U12 or U9 & U9 OK ?
OK
Check U9Pin1(Mute) & Q10 & U9 OK ?
No
Change Q9 or U9
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Chapter 5
Connector Information
Phonejack stereo PIN1. AC power cord : CEE22 typed connector PIN2. Audio cable PIN3. Audio : Line-in receptacle
J1
1
2 3
PHONEJACK STEREO
Video signal connector 15P Mini D-Sub connector x 1
1 6 2 7 3 8 4 9 5 10
16
11
12
13
14
CN6 DB15HD
17
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MNEMO RV GV BV NC GND RG GG BG +5V SG NC SDA HS VS SCL
15
SIGNAL Red Video Green Video Blue Video None Ground(DDC return) Red GND Green GND Blue GND + 5V (for DDC) Sync GND None DDC Data Horizontal Sync Vertical Sync DDC Clock
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Proprietary connecting of DVI box The 44 pin of proprietary DVI box is defined as follows: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RX2RX2+ RX1RX1+ RX0RX0+ RXCRXC+ GND GND Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 LLC VPC KEY1 GND KEY2 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SCART_FUNC KEY3 SCART RGB_CON SCL5V nYCOEN SDA5V NVDSW_SEL HSCL REST HSDA DVI_ DETECT CORD_ RESET CORD_DETECT ADO_L DETECT AGND IR0 ADO_R V51R GND V12 V12
- 33 -
Chapter 6
FRU (Field Replaceable Unit) list
This chapter gives you the FRU (Field Replaceable Unit) listing in global configurations of AL2032W. Refer to this chapter whenever ordering for parts to repair or for RMA (Return Merchandise Authorization). NOTE : Please note WHEN ORDERING FRU PARTS, that you should check the most up-to-date information available on your regional web or channel(http://aicsl.acer.com.tw/spl/). For whatever reasons a part number change is made, it will not be noted in the printed Service Guide. For ACER-AUTHORIZED CERVICE PROVIDERS, your Acer office may have a DIFFERENT part number code to those given in the FRU list of this printed Service Guide. You MUST use the local FRU list provided by your regional Acer office to order FRU parts repair and service of customer machines. NOTE: To scrap or to return the defective parts, you should follow the local government ordinance or regulations on how best to dispose it, or follow the rules set by your regional Acer office on how to return it.
- 34 -
AL2032W Exploded Diagram
35
Chapter 6
Chapter 7
SCHEMATIC DIAGRAM
Main Board Circuit
+1.8V_CORE
V 5 2 / F u 8 2 5 2 C
GND
V 5 2 / F u 72 52 C
6 / F u 7 1 4 . 1 0 C
6 / F u 41 . 50 1 C
6 / F u 0 1 5 . 1 0 C
6 / F u 11 4 . 10 C
6 / F u 8 1 3 . 1 0 C
6 / F u 51 3 . 10 C
6 / F u 0 1 . 4 0 1 C
6 / F u 91 3 . 10 C
6 / F u 7 1 3 . 1 0 C
6 / F 6 u / 61 F 3 . u 10 2 1 2 . C 1 0 C
6 / F u 51 . 40 1 C
6 / F u 3 1 5 . 1 0 C
6 / F u 61 4 . 10 C
+3.3V_LBADC
+2.5V_DDR
+1.8V_CORE
+3.3V_I/O_MALIBU
+2.5V_DDR
+3.3V_LVDSB +3.3V_LVDSA +3.3V_LVDS FSVREF
+1.8V_DVI
+3.3V_DVI
+1.8V_ADC+3.3V_ADC
CN8
+3.3V_PLL
V 5 2 / F u 7 2 3 2 C GND
V 5 2 / F u 52 42 C
6 / F u 4 1 . 2 0 1 C
6 / F u 51 . 20 1 C
6 / F u 3 1 . 2 0 1 C
6 / F u 91 . 20 1 C
6 / F u 1 1 . 2 0 1 C
6 / F u 01 . 20 1 C
6 / F u 9 1 . 1 0 1 C
6 / F u 01 . 30 1 C
6 / 6 F / 6 6 u / / F 81 F F . u u u 6 1 20 7 1 61 1 . 1 . . 2 0 20 1 0 C 1 1 C C C +3.3V_I/O_MALIBU
6 / F u 0 1 . 4 0 C
6 / F u 81 . 10 1 C
6 / F u 2 1 . 4 0 C
77166710616013 11111111111112 K UU L T T L K K T U U KK
8 88 88 88 88 88 88 L . . . . . . . . . . . . . L 1 11 11 11 11 11 11D _ __ __ __ __ __ __ EEEEEEEEEEEEE_ RRRRRRRRRRRRR 8 1 OOOOOOOOOOOOOA CCCCCCCCCCCCCD DVI_SCL D V DVI_SDA RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCNO_CONNECT NO_CONNECT REXT BLUEBLUE+ GREENGREEN+ REDRED+ SOG NO_CONNECT VGA_SCL VGA_SDA AHSYNC AVSYNC EXTCLK
0 468 1 4 4 7 3 CCCC2 A 4 B 4 3 2 1 1 2 D D A A A A D AWA YC
3 33 33 33 33 33 3 . . . . . . . . . . . 3 33 33 33 33 33 3 _ __ __ __ __ __D OOOOOOOOOOOC I I I I I I I I I I I A B L
3333 33 33 33 33322223 3 22 22 2 2 22 2ABC 2 2 H J M P L T V R Y A A AWF E
55 55 55 55 55 55 55 5 . . . . . . . . . . . . . . . 22 22 22 22 22 22 22 2 __ __ __ __ __ __ __ _ SSSSSSSSSSSSSSS FFFFFFFFFFFFFFF
2 23 1 11 CDD AAA
3 33 . . . 3 33 _ __ BBB SSS DDD VVV L LL
021 222 DCC AAA
3 33 . . . 3 33 _ __ AAA SSS DDD VVV L LL
7 1 E A
S D V L _ 3 3 D D D V
U5
45 22 JW
FF EE RR VV SS FF
0 6 8 91 DDDD
88 88 . . . . 11 11 __ __ I I I I VVVV DDDD
10 11986 CCCCC
33 33 3 . . . . . 33 33 3 __ __ _ I I I I I VVVVV DDDDD
34 AA
8 8 . . 1 1 _ _ CC DD AA
23 3 3 ABDE
33 33 . . . . 33 33 __ __ CCCC DDDD AAAA
4 21 31 31 F FGHH J J
LL L LL LSSSS PPPDDDD _ DDD R3 FDSDD _ _S__ _ 33 3_ 33 3 3 3A33 33 3 ADAAAAA DDD DVDDDDD V VDDDD VVVV
GM1601 416PBGA
E24 E25 E26 G26 G24 H26 H24 J25 T26 R25 P24 P26 N24 N26 M25 L24 L25 M26 M24 N25 N23 P25 R26 R24 K24 J26 H25 G23 G25 F24 F25 F26
FSDATA[0..31] FSDATAU0 FSDATAU1 FSDATAU2 FSDATAU3 FSDATAU4 FSDATAU5 FSDATAU6 FSDATAU7 FSDATAU8 FSDATAU9 FSDATAU10 FSDATAU11 FSDATAU12 FSDATAU13 FSDATAU14 FSDATAU15 FSDATAU16 FSDATAU17 FSDATAU18 FSDATAU19 FSDATAU20 FSDATAU21 FSDATAU22 FSDATAU23 FSDATAU24 FSDATAU25 FSDATAU26 FSDATAU27 FSDATAU28 FSDATAU29 FSDATAU30 FSDATAU31 FSDATAU0 FSDATAU1 FSDATAU2 FSDATAU3 FSDATAU4 FSDATAU5 FSDATAU6 FSDATAU7 FSDATAU10 FSDATAU11 FSDATAU9 FSDATAU8 FSDATAU14 FSDATAU15 FSDATAU12 FSDATAU13 FSDATAU16 FSDATAU17 FSDATAU18 FSDATAU19 FSDATAU20 FSDATAU21 FSDATAU22 FSDATAU23 FSDATAU28 FSDATAU26 FSDATAU25 FSDATAU24 FSDATAU29 FSDATAU30 FSDATAU31 FSDATAU27
FSDATA[0..31] 5
V 5 2 / 6F u 4 2 C2
V 5 2 / 5F u 52 C2
6 / F u 4 1 . 6 0 1 C
6 / F u 71 . 60 1 C
6 / F u 2 1 7 . 1 0 C
6 / F u 31 . 70 1 C
6 / F u 1 . 4 0 3 1 C
6 / F u 1 . 70 1 1 C
6 / F u 1 . 5 0 1 1 C
6 / F u 1 . 10 5 1 C
6 / F u 1 . 8 0 5 1 C
6 / F u 1 . 00 6 1 C
6 / F u 1 . 3 0 6 1 C
R170 0/6/NC R171 0/6/NC
RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXC-
GND +1.8V_DVI
+3.3V_DVI
6 / F u 1 1 . 6 0 1 C
GND
6 / F u 91 5 . 10 C
6 / F u 6 1 5 . 1 0 C
6 / F u 21 5 . 10 C
V 5 2 / 4F 5u C2 2
6 / F u 7 1 5 . 1 0 C
6 / F u 31 . 40 1 C
6 / F u 9 1 4 . 1 0 C
6 / F u 51 5 . 10 C
6 / F u 2 1 6 . 1 0 C
+3.3V_DVI
R54
249R/6 1%
N4 N3 A8 B8 A9 B9 A10 B10 A6 B6 D5 C5 B11
B1 B2 C1 C2 D1 D2 C3 A1 N2 N1 L4 L3 R4
TXD RXD
R131 0/6
R132 0/6
3 BLUE3 BLUE+
3 3 3 3 3 GREENGREEN+ REDRED+ SOG
GND
+3.3V_PLL
+3.3V_PLL 22pF/6 C67 C68 22pF/6
X1
3 VGA_SCL 3 VGA_SDA
3 AHS
3 AVS
14.318MHz
XTAL TCLK
Route (VIN1/ADC_IN1, ADC1_RETURN) and (VIN2/ADC_IN2, ADC2_RETURN) as differential tracks close to each other and ground the return track of each pair very close to the Malibu D12 ball and ground pin Optional Filter Caps in between a pair on LBADC differential tracks close to the Malibu chip
R77
GND
3K3/6
ACS_RSET_HD
G4 G3 XTAL F1 TCLK K3 NO_CONNECT K2 NO_CONNECT ACS_RSET_HD
FSDATA0 FSDATA1 FSDATA2 FSDATA3 FSDATA4 FSDATA5 FSDATA6 FSDATA7 FSDATA8 FSDATA9 FSDATA10 FSDATA11 FSDATA12 FSDATA13 FSDATA14 FSDATA15 FSDATA16 FSDATA17 FSDATA18 FSDATA19 FSDATA20 FSDATA21 FSDATA22 FSDATA23 FSDATA24 FSDATA25 FSDATA26 FSDATA27 FSDATA28 FSDATA29 FSDATA30 FSDATA31
RN11 1 33 2 3 4 RN12 1 33 2 3 RN74 1 33 2 3 4
8 7 6 5 8 7 6 58 7 6 5
RN6 1 33 2 3 4 RN13 1 33 2 3 4 RN9 1 33 2 3 4
RN5 1 33 2 3 RN44 1 33 2 3 4
8 7 6 58 7 6 5 8 7 6 5
8 7 6 58 7 6 5
FSDATA0 FSDATA1 FSDATA2 FSDATA3 FSDATA4 FSDATA5 FSDATA6 FSDATA7 FSDATA10 FSDATA11 FSDATA9 FSDATA8 FSDATA14 FSDATA15 FSDATA12 FSDATA13 FSDATA16 FSDATA17 FSDATA18 FSDATA19 FSDATA20 FSDATA21 FSDATA22 FSDATA23 FSDATA28 FSDATA26 FSDATA25 FSDATA24 FSDATA29 FSDATA30 FSDATA31 FSDATA27
V5IR
1 3 5 7 9 11 13 15 17 19 21 SCART_FUNC 23 SCART_RGB_CON 25 nYCOEN 27 nVDSW_SEL 29 nRESET 31 DVI DETECT 33 CARD DETECT 35 TVBOX_DETECT 37 37 39 IR1 41 39 43 41 43
Y0 Y2 Y4 Y6 LLC_VPC
RX2RX1RX0RXC-
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
RX2+ RX1+ RX0+ RXC+ Y1 Y3 Y5 Y7 KEY1 KEY2 KEY3 MSTR_SCL MSTR_SDA TT_I2CSCL TT_I2CSDA CARD_RESET ADO_L 8
ADO_R 8
V12
GND
1841 44P
GND
AGND
FSBKSEL1 5
FSBKSEL0 5
C19 B19 A19 D18 C18 B18 A18 C17
R78 10K/6
VRED0 VRED1 VRED2 VRED3 VRED4 VRED5 VRED6 VRED7 VGRN0 VGRN1 VGRN2 VGRN3 VGRN4 VGRN5 VGRN6 VGRN7 VBLU0 VBLU1 VBLU2 VBLU3 VBLU4 VBLU5 VBLU6 VBLU7
GND
A23 C22 B22 A22 D21 C21 B21 A21
FSADDR0 FSADDR1 FSADDR2 FSADDR3 FSADDR4 FSADDR5 FSADDR6 FSADDR7 FSADDR8 FSADDR9 FSADDR10 FSADDR11 FSCLKp FSCLKn FSDQS FSDQM0 FSDQM1 FSDQM2 FSDQM3 FSWE FSCAS FSRAS FSCKE FSBKSEL0 FSBKSEL1
AD25 AD26 AC24 AC25 AB26 AA24 AA25 AA26 Y24 AB25 AC26 AB24
U24 U23
FSADDRU0 FSADDRU1 FSADDRU2 FSADDRU3 FSADDRU4 FSADDRU5 FSADDRU6 FSADDRU7 FSADDRU8 FSADDRU9 FSADDRU10 FSADDRU11 FSCLKU+ FSCLKUFSDQSU FSDQMU0 FSDQMU1 FSDQMU2 FSDQMU3 /FSWEU /FSCASU /FSRASU FSCKEU FSBKSELU0 FSBKSELU1
FSADDRU6 FSADDRU5 FSADDRU4 FSADDRU9 FSBKSELU1 FSBKSELU0 FSADDRU8 FSADDRU7
RN3 1 2 33 3 4 RN2 1 33 2 3 4
R36 R35 1 2 3 4
8 7 6 5 8 7 6 5
33R/6 33R/6 8 7 6 5
FSADDR6 FSADDR5 FSADDR4 FSADDR9 FSBKSEL1 FSBKSEL0 FSADDR8 FSADDR7 FSADDR0 FSADDR1 FSADDR11 FSADDR10 FSADDR3 FSADDR2
FSADDR[0..11] 5
FSADDRU0 FSADDRU1 RN8 FSADDRU11 FSADDRU10 33 FSADDRU3 FSADDRU2 FSCLK+ FSCLK-
L26
FSCLK+ 5 FSCLK- 5
FSDQS 5
R34
33R/6
B25 A25 D24 C24 B24 A24 C23 B23
R37 10K/6
T25 U25 U26 T24 V26 V25 V24 W26 Y25 Y26
FSDQM[0..3] 5
/FSWEU /FSRASU /FSCASU FSCKEU FSDQMU0 FSDQMU3 FSDQMU1 FSDQMU2
RN10 1 33 2 3 4 RN1 1 2 33 3 4
8 7 6 5 8 7 6 5
/FSWE /FSRAS /FSCAS FSCKE FSDQM0 FSDQM3 FSDQM1 FSDQM2
/FSWE 5 5 /FSRAS /FSCAS 5
Place Series term ination resistors on all address and control lines (RN601,RN603,RN605) very close to U600
Unloaded trace im pedance on this interface is 90 Ohm Loaded trace im pedace w ith DRAM load is 65 Ohm (for 2.5 inch total trace length)
FSCKE 5
GND
7 PWM0 7 PWM1
T106
T105
PWM0 PWM1
GND
GND
SCART_FUNC SCART_RGB_CON Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
CN3
1 2 3 4
+5V
TXD RXD
T101
T103
4606-04-04P-R/NS
T102
GND
T104
LLC_VPC
A20 B20 VCLK C20 VODD D19 VVS D20 VHS_CSYNC B17 VDV VCLAMP C26 C25 PWM0 D26 PWM1 D25 PWM2 OCM_TIMER1 A12 B12 LBADC_IN3 C12 LBADC_IN2 D12 LBADC_IN1 LBADC_RETURN C16 B16 SVDATA0 A16 SVDATA1 D15 SVDATA2 C15 SVDATA3 B15 SVDATA4 A15 SVDATA5 D14 SVDATA6 SVDATA7 A17 A14 SVDV B14 SVODD C14 SVVSYNC D16 SVHSYNC SVCLK
M1 M2 OCM_UDO OCM_UDI
GPIO_G06_B0 GPIO_G06_B1 GPIO_G06_B2 GPIO_G06_B3 A3+ A3AC+ ACGPIO_G05_B0 GPIO_G05_B3 A2+ A2A1+ A1A0+ A0GPIO_G04_B0 GPIO_G04_B1 GPIO_G04_B2 GPIO_G04_B3 GPIO_G04_B4 GPIO_G04_B5 GPIO_G04_B6 GPIO_G04_B7 GPIO_G07_B0 GPIO_G07_B1 GPIO_G07_B2 GPIO_G07_B3 GPIO_G07_B4 GPIO_G07_B5 GPIO_G07_B6 GPIO_G07_B7 LVDS_SHIELD[0] LVDS_SHIELD[1] LVDS_SHIELD[2] LVDS_SHIELD[3] B3+ B3BC+ BC-
AC18 AD18 AE18 AF18 AE19 AF19 AE20 AF20
Place Series term ination resistors on bidirectional lines-DATA and DQS (RN600,RN602,RN604,RN606,R605) m idw ay betw een U600 anf U700
Max trace length on this interfce is 2.5 inches Minim ize trace length difference betw een DQS and data and am ong the data lines
R603, R604 very close to U600
FSCLK+, FSCLK- should be routed like a differentail pair
TXA3+ TXA3TXAC+ TXAC-
AD21 AD22 AE21 AF21 AE22 AF22 AE23 AF23
AD23 AD24 AE24 AF24 AF25 AF26 AE25 AE26
MENU SEL PWR DOWN UP LED_G LED_R ADO_C
TXA2+ TXA2TXA1+ TXA1TXA0+ TXA0-
+3.3V_DIG
R173 10K/6
+3.3V_DIG
+3.3V_DIG
ADO_C 8
R128 10K/6
R33 10K/6
GND
/RESET IR1 IR0
MSTR_SDA
MSTR_SCL
MSTR_SCL MSTR_SDA
P3
K1 M4 /RESET M3 IR1 P4 IR0 MSTR_SCL MSTR_SDA
R3 R2 R1 L1 L2 P2 P1 T4
AE8 nYCOEN AF8 nVDSW_SEL AC9 nRESET AD9 AE9 AF9 CARD_RESET AD10 AE10 TUNER12V_KEY
R172 10K/6
DVI DETECT CARD DETECT TVBOX_DETECT
TUNER12V_KEY 7
6 /OCM_WE 6 /OCM_RE 6 /ROM_CS
T109 T110
T111
/OCM_WE /OCM_RE T107/OCM_CS
T108
/OCM_WE /OCM_RE /ROM_CS /OCM_INT2 /OCM_INT1 /OCM_CS2 /OCM_CS1 /OCM_CS0 OCMADDR19 OCMADDR18 OCMADDR17 OCMADDR16 OCMADDR15 OCMADDR14 OCMADDR13 OCMADDR12 OCMADDR11 OCMADDR10 OCMADDR9 OCMADDR8 OCMADDR7 OCMADDR6 OCMADDR5 OCMADDR4 OCMADDR3 OCMADDR2 OCMADDR1 OCMADDR0
AF10 AC11 AD11 AE11 AF11 AF12 AE12 AF13
TXB3+ TXB3TXBC+ TXBC-
FSVREF
+1.8V_ADC
6 OCMADDR[0..19]
OCMADDR19 T3 OCMADDR18 T2 OCMADDR17 T1 OCMADDR16 U4 OCMADDR15 U3 OCMADDR14 U2 OCMADDR13 U1 OCMADDR12 V4 OCMADDR11 V3 OCMADDR10 V2 OCMADDR9 V1 OCMADDR8 W3 OCMADDR7 W2 OCMADDR6 W1 Y3 OCMADDR5 Y2 OCMADDR4 Y1 OCMADDR3 OCMADDR2 AA3 OCMADDR1 AA2 OCMADDR0 AA1
C38 0.1uF/6
C39 0.1uF/6
C63 0.1uF/6
C62 0.1uF/6
LVDS_SHIELD[4] LVDS_SHIELD[5] B2+ B2B1+ B1B0+ B0-
AE13 AD14 AF14 AE14 AF15 AE15 AF16 AE16
TXB2+ TXB2TXB1+ TXB1TXB0+ TXB0-
GND
GND
+3.3V_ADC
DCLK GPIO_14/DHS GPIO_15/DVS GPIO_16/DEN
AC7 AF17 AD16 AD7
T115 T116
CN2
R48
R59
0/6
+3.3V_DIG
10K/6 MUTE
TXA0TXA1TXA2-
MUTE 8
+3.3V_LVDS
C70
C168
C175 0.1uF/6
C171 0.1uF/6
C169 0.1uF/6
+3.3V_PLL
+3.3V_DIG
GPIO_G08_B5/JTAG_RESET GPIO_G08_B4/JTAG_TDO GPIO_G08_B3 GPIO_G08_B2/JTAG_TDI GPIO_G08_B1/JTAG_MODE GPIO_G08_B0/JTAG_CLK GPIO_G09_B5 GPIO_G09_B4 GPIO_G09_B3 GPIO_G09_B2 GPIO_G09_B1 GPIO_G09_B0
22uF/25V 0.1uF/6
TXACTXA3TXB0TXB1TXB2TXBCTXB3-
GND
C77
6 / F 22uF/25V u 71 7 . 25V 10 C
6 / F u 4 1 7 . 1 0 C
6 / F u 61 7 . 10 C
6 / F u 8 1 7 . 1 0 C
6 6 / / F F u 51 0 u . 6 . 7 1 10 1 0 C C
6 / F u 61 6 . 10 C
GND
KEY1 KEY2 KEY3 RIGHT LEFT
T112
T113
+3.3V_LVDSA
+3.3V_LVDS
C47 0.1uF/6
T114
6 OCMDATA[0..7]
C44
C131
C133 0.1uF/6
C132 0.1uF/6
22uF/25V 0.1uF/6 25V
GND
+3.3V_LVDSB
GND
OCMDATA7 OCMDATA6 OCMDATA5 OCMDATA4 OCMDATA3 OCMDATA2 OCMDATA1 OCMDATA0
AB3 AB2 AB1 AC3 AC2 AC1 AD1 AE1 AF1 AD2 AE2 AF2 AD3 AE3 AF3 AD4
OCMDATA15 OCMDATA14 OCMDATA13 OCMDATA12 OCMDATA11 OCMDATA10 OCMDATA9 OCMDATA8 OCMDATA7 OCMDATA6 OCMDATA5 OCMDATA4 OCMDATA3 OCMDATA2 OCMDATA1 OCMDATA0
AD8 AF7 AE7 AF6 AE6 AD6 AF5 AE5 AD5 AC5 AF4 AE4
JTAG_TRST
R52
2K7/6
R15 10K/6/NC
R129 0/6/NC
TT_I2CSDA TT_I2CSCL
+3.3V_DIG
+5V
+3.3V_DIG
R16
R130
LCDVCC
0/6/NC
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
TXA0+ TXA1+ TXA2+ TXAC+ TXA3+ TXB0+ TXB1+ TXB2+ TXBC+ TXB3+ LCDVCC LCDVCC
+3.3V_LVDS
C N / 6 4 / 1 K 0 R 1
R63
10K/6
VGA_CAB
1841 30P
3 1 R
VGA_CAB 3
PANEL_VCC
T117
R174 0/6
0/6/NC
R175 0/6/NC
GND
GND
C N / 6 / 0
PPWR PBIAS NO_CONNECT OEXTR D_GND
A26 B26
PPWR PBIAS OEXTR
PPWR 7 PBIAS 7
GND
GND
PANEL_VCC
AC17 AC16 AD15
R82
R42 3K3/6
2K7/6
2K7/6
R81
GND
GND
MSTR_SCL MSTR_SDA
R84 U7 8 7 VCC 6 WP 5 SCK SI
0/6
1 A0 2 A1 3 A2 4 VSS
R85
C52
C144
C142 0.1uF/6
C148 0.1uF/6
L L D _ 8 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD1 NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNA GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGS __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _S DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDV 3 4 55 55 511167 00 22 32 22 22 33303044443 5 1 1 11 11 111111 11 11 11 11 11 11111111111 2 U L MP R UMNR P N NR K L MMN P T U L N R L T T K L N PB K A
+3.3V_ADC
22uF/25V 0.1uF/6 25V
GND
+5V
DDDDDDDDDDDDDDDDDDDD NNNNNNNNNNNNNNNNNNNN GGGGGGGGGGGGGGGGGGGG __ __ __ __ __ __ __ __ __ __ DDDDDDDDDDDDDDDDDDDD 45556662 33 34 410777 07 11111111 11 11 111111 11 T K N T MN RR K P UMR PMMP R P L
SSS DDD S D DDD VVV D SS DDDDDDD LL L N NNN _ _ _ V SS NNNNNNN L V GGG A A A _ V F GGGGGGG D DD DD DD G _ __ _ 33 3 3 F BBB 3 3 3 3 EE DAADAAA NNNNNNN C S S S A A A D RR _ _ _ _ _ _ _ GGGGGGG D _ __ __ __ I I I I I I I DDD SSS S VV CCCCCCC VVVVVVV A VVV SSS S SS DDDDDDD B L L L VVV V F F AAAAAAA DDDDDDD L 34 5 90 9 7 11 1 12 1 1 64 3 11 CCC CCD D 2 2 4 4 2 5 1 4 4 7 7 7 7 1 1 5 1 A A A A A A A KW B D E A E C E A B C D A D B D
+3.3V_DIG
L LSSSS L L LDDDD P L PDDDD RPFSSDD __ __ __ _ 33 33 33 3 33 33 33 3 ADAADAD SSSSSSS SSSSSSS VVVVVVV
GND
24LC32-SN SOIC8
GND
0/6/NC
V 5 2 / F u 2 2 1 2 C
6 / F u 11 . 10 C
I2C address: A2H and A3H
GND
+5V
GND
3 C C 1 V OUT D N G
/RESET
324 24 24 FGHH J J K
C76 0.1uF/6
C78 0.1uF/6
C80 0.1uF/6
/RESET
R150 10K/6
R151 10K/6
GND
GND
GND
2
U8 MAX809_0
LED_G
R152
4K7/6
2
3
Q12 MMBT3904L
6 / K 3 43 5 1 R
MENU SEL PWR DOWN UP RIGHT LEFT
LED_R
R153 4K7/6 2
3
6 / 6 / K K 3 3 5 3 63 5 5 1 1 R R
6 6 / / K K 3 3 7 3 83 5 5 1 1 R R
6 6 / / K K 3 3 9 30 3 5 6 1 1 R R
R161 R162 R163 R164 R165 R166 R167 R168 R169
less R94 to CN6 pin 11 R101,R103 net swap
CN5
GND
Q13 1 MMBT3904L
1
1K/6 1K/6 1K/6 1K/6 1K/6 1K/6 1K/6 220R/6 220R/6
6 / F u 81 . 90 C
6 / F u 3 1 9 . 1 0 C
6 6 / / F F u u 41 5 1 9 . 9 . 10 1 0 C C
6 / F u 61 9 . 10 C
6 6 / / F F u u 7 18 1 9 .9 . 1 01 0 C C
10 9 8 7 6 5 4 3 2 1
TO BUTTON BOARD
GND
4501-10-10P-R
Junction from A change to B
2.0mm pitch 90° E&T 4607-11Pin
PROJECT : M0TW
Quanta Computer Inc.
Title
04. gm1601
Size Date: Document Number 04. gm1601 Tuesday , September 14, 2004
M0TW
Sheet 4
of
Rev A 8
- 36 -
12V_A
L20 CX000800000/1206
+12V
C204 0.1uF/6
C205 0.1uF/6
12V_A
SPKRO+ SPKRO-
CN9
1 5 4 3 2 ZD005D100
lef t_inR109
0/6
L22 CX000800000/1206
L23 CX000800000/1206
LIN_L RIN_R
R110
0/6
C N / 6 / K 1 . 5 3 1 1 R
6 / 3 F 1 p 1 0 C 2 2
6 / 4 F 1 p 1 0 C 2 2
AGND
AGND AGND +12V
C N / 6 / K 1 . 5 4 1 1 R AGND
6 / F p 2 0 0 2 1 2 C
6 / F p 1 0 0 2 1 2 C
V 5 2 / 1 F u 8 2 C 2
6 / F u 1 . 0 2 7 C
C71 0.01uF/6
6 0 2 1 / 0 0 0 0 0 6 8 0 1 0 L 0 X C
6 / F p 0 0 0 4 1 6 C
6 / F p 0 0 0 5 1 6 C
6 0 2 1 / 0 0 0 0 0 8 0 7 0 0 1 X L C74 C
12V_A
6 / F u 3 1 . 7 0 C
V 5 2 / 6 F u 6 2 C 2
0.01uF/6
AGND AGND
U9 8 4
+ R S B
7 4
R C C V P
6 4
R C C V P
5 4
+ T U O R
4 4
+ T U O R
3 4
R D N G P
2 4
R D N G P
1 4
T U O R
0 4
T U O R
9 3
R C C V P
8 3
7 3
R C R S C B V P VCLAMPR MODEB MODE AVCC VAROUTR VAROUTL NC AVDD COSC ROSC AGND VCLAMPL
R79
AGND 10K/6
1
4 MUTE
MUTE
R75
4K7/6 2
3
6 / K 0 1 6 7 R
0M 1 QM
1
AGND
L 4 0 9 3 T B
SDZ
RIN+ RINV2P5 LINLIN+
36 C82
35
1u/8
RIN
C75
C79
1u/8
1u/8
1u/8
1u/8
1u/8
2
AGND
AGND
3
4
5
34
12V_A
C83
C85
33
32
LIN
C95
6
7
8
31
AVDDREF VREF VARDIFF VARMAX VOL AGND + L S B L C C V P L C C V P + T U O L + T U O L L D N G P L D N G P T U O L T U O L L C C V P L C C V P
30
6 / F u 4 1 . 8 0 C
0.1uF/6
V 5 2 / 6 F 8 u C 2 2
L21 CX000800000/1206
29 C87
9
10
7 VOLUME
VOLUME
28 C96
27 R87
26
220pF/6
120K/6
GND
AGND
11
6 / F u 1 . 0
AGND
12
25
C99
1u/8
+5V
L36 CX000800000/1206
6 / F u 1 . 0 9 9 1 C AGND
ADO_L LIN
U12
1 2 3 4
2Y 1 2Y 0 3Y 1 3Z 3Y 0 E VEE GND VCC 2Z 1Z 1Y 1 1Y 0 S1 S2 S3 16 15 14 13
6 / F u 1 . 0 0 0 2 C AGND
RIN ADO_R
7 9 C
AGND
L S B
3 1
4 1
5 1
6 1
7 1
8 1
9 1
0 2
1 2
2 2
3 2
4 2
TPA3003D2
4 ADO_L
ADO_R 4
RIN_R
LIN_L C202 1u/8
5 6 7 8
12 11 10 9
C201 1u/8
ADO_C
V 5 2 / 9 F 0 u 1 2 C 2
6 / F u 1 . 0 4 0 1 C 12V_A
C103 0.01uF/6 6 0 2 1 / 0 0 0 0 0 8 0 0 4 0 2 X L C
C106 0.01uF/6
6 0 2 1 / 0 0 0 0 0 8 0 0 0 6 X / C F p 0 0 0 2 1 1 C
5 2 L
6 / F p 0 0 0 1 1 1 C
6 / F u 1 . 0 5 0 1 C 12V_A
CN6
V 5 2 / 0 F 1 u 1 2 C 2
SPKRO+ SPKROSPKLO+ SPKLO-
1 2 3 4
4501-04-04P-R
ADO_C 4
74HCT4053
SPKLOSPKLO+
PROJECT : M0TW
Quanta Computer Inc.
Title
AGND
08. Audio
Size Date: Document Number 08. Audio Tuesday , September 14, 2004
M0TW
Sheet 8
of
Rev A 8
+2.5V_DDR
V 5 0 2 2 / C F u 2 2
GND
4 FSDATA[0..31]
V 5 4 2 2 / C F u 2 2
6 / 9 F 2 u . C 1 0
6 / 0 F 3 u . C 1 0
6 / 1 F 3 u . C 1 0
6 / 5 F C u 1 . 0
6 / 4 F C u 1 . 0
6 / 3 F C u 1 . 0
6 / 2 F C u 1 . 0
6 / 3 F 1 u . C 1 0
6 / F u 7 1 . 2 0 C
6 / F u 8 1 . 2 0 C
6 / F u 8 1 . 1 0 C
6 / 9 F 1 u . C 1 0
6 / 7 F 1 u . C 1 0
6 / 6 F C u 1 . 0
+2.5V_DDR
FSVREF
U1
4 2 9 7 3 2 8 1 2 5 6 7 9 6 5 7 8 9
4 FSADDR[0..11]
8 5 5 5 1 3 6 6 5 9
D D D D F D D D D E V V V V R V DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
FSADDR0 FSADDR1 FSADDR2 FSADDR3 FSADDR4 FSADDR5 FSADDR6 FSADDR7 FSADDR8 FSADDR9 FSADDR10 FSADDR11 FSBKSEL0 FSBKSEL1 FSCLKFSCLK+ FSCKE
GND
31 32 33 34 47 48 49 50 51 45 36 37
29 30
54 55 53 28 27 26 25 94
A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 BA0 BA1 CLK CLK CKE CS RAS CAS WE DQS DM0 DM1 DM2 DM3
QQ Q QQ QQ Q QQ D D D D D D D D D D D D D D D D D D D D V V V V V V V V V V
97 98 100 1 3 4 6 7
FSDATA0 FSDATA1 FSDATA2 FSDATA3 FSDATA4 FSDATA5 FSDATA6 FSDATA7
+2.5V_DDR
4 FSBKSEL0 4 FSBKSEL1
4 FSCLK4 FSCLK+ 4 FSCKE
4 /FSRAS 4 /FSCAS 4 /FSWE 4 FSDQS
4 FSDQM[0..3]
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
60 61 63 64 68 69 71 72
FSDATA8 FSDATA9 FSDATA10 FSDATA11 FSDATA12 FSDATA13 FSDATA14 FSDATA15
R3 10K/6 1%
FSVREF
FSVREF
C1
R1 10K/6 1%
0.1uF/6
/FSRAS /FSCAS /FSWE DQS FSDQM0 FSDQM1 FSDQM2 FSDQM3
23 56 24 57
38 39 40 41 42 43 44 87 88 89 90 91 93
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
9 10 12 13 17 18 20 21
FSDATA16 FSDATA17 FSDATA18 FSDATA19 FSDATA20 FSDATA21 FSDATA22 FSDATA23
GND
GND
FSCLK+
R4 140R/6 1%
NC NC NC NC NC NC NC NC NC NC NC DNC QQ Q QQ QQ Q Q NC S S S S S S S S S S S S S S S S S S V V V V V V V V V
FSCLKDQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S S S S S S S S V V V V L C M
74 75 77 78 80 81 83 84
FSDATA24 FSDATA25 FSDATA26 FSDATA27 FSDATA28 FSDATA29 FSDATA30 FSDATA31
Place R704 termination close to corresponding U600 Pins
PROJECT : M0TW
Quanta Computer Inc.
Place series termination resistors very close to U600 Title
MT46V2M32LG-4 1 9 2 0 6 2 2 9 5 1 1 6 7 7 8 9 9 TQFP-100
GND
6 6 6 5 1 4 6 8
2 5
05. Frame Store
Size Date: Document Number 05. Frame Store Thursday , September 02, 2004
MOTW
Sheet 5
of
Rev A 8
- 37 -
+1.8V_CORE
+1.8V_DVI
+1.8V_ADC
+3.3V_ADC
+3.3V_PLL
+3.3V_LVDSA
L18 CX000800000/1206 L6 CX000800000/1206 L9 CX000800000/1206 L11
+3.3V_LVDS
+3.3V_LBADC
L12 CX000800000/1206 L14 CX000800000/1206
+3.3V_DVI
+3.3V_DIG
CX000800000/1206
L19 CX000800000/1206 L7 CX000800000/1206 L10 CX000800000/1206 L26 CX000800000/1206
+3.3V_LVDSB
+3.3V_I/O_MALIBU
H5
2 3 4 5
9 8 7 6
H6
2 3 4 5
9 8 7 6
2 3 4 5
H1
9 8 7 6
1
1
1
MTH276D126
MTH276D126
GND
MTH276D126
GND
GND
GND
GND
GND
H2
2 3 4 5
9 8 7 6
2 3 4 5
H4
9 8 7 6
2 3 4 5
H3
9 8 7 6
1
1
1
MTH276D126
GND
GND AGND
MTH276D126
MTH276D126
AGND GND
GND
VGA_SDA
VGA_SCL
VGA_SCL 4 VGA_SDA 4
CN7
VGA_5V
15
VGA_CAB 4
R101
100R/6
VGASCL
7 1
GND
5 10 4 9 3 8 2 7 1 6
R106
0/6/NC
VGA_5V
+5V
R102
2
14
R88
A-BLUE A-GREEN A-RED
20R/6 1%
C89 C90
0.01uF/6 0.01uF/6
13
BLUE+ 4 BLUE- 4
SOG 4 GREEN+ 4 GREEN- 4 RED+ 4 RED- 4
D8
1
100R/6VGASDA
12
R90 R91
20R/6 1% 20R6 1%
DAN202U
11
R93
% 1 6 / R 5 7
20R/6 1%
C91 C92 C69 C94 C93
0.47uF/6 0.01uF/6 0.01uF/6 0.01uF/6 0.01uF/6
3
6 1
% 1 6 / R 5 7 4 0 1 R
% 1 6 / R 5 7 3 0 1 R
DB15 HD
GND
A-HS A-VS
C88 0.1uF/6
U10
1 2 3 4
R86 10K/6
R98 10K/6
0 0 1 R
% 1 6 / R 6 5 9 8 R
% 1 6 / R 6 5 3 8 R
% 1 6 / R 6 5 2 9 R
RGB SIGNAL GNDs at 2-mm from respective RGB series Capacitors
GNDGNDGND
A0 A1 A2 GND
VCC WP SCL SDA
8 7 6 5
GND
A-VS
Near VGA pins
R97 22R/6
R95 0/6
GND GND GND
R94
U11
0/6
24C02
3
AHS 4 AVS 4
GND
GND
3
D6
A-HS
D7
ANALOG DDC
1
5.6V/NC 5.6V/NC
1
R96
22R/6
3
3
C N / V 6 . 4 5 D
GND GND
S N / / 5 6 0 R 1 0 R 1 5
1
1
C N / V 6 5 . D 5
6 / F p 7 4 0 0 1 C
6 / F p 7 4 8 0 1 C
1 2 3 4
5 6 8 9
1A 1Y 2A 2Y 3A 3Y 4Y 4A
6A 6B 5A 5B
13 12 11 10
+3.3V
VCC GND
14 7
6 / F u 7 1 . 0 0 1 C GNDGND
GND
SN74LVC14A/NC
PROJECT : M0TW
Quanta Computer Inc.
Title
03. Graphic Inputs
Size Date: Document Number 03. Graphic Inputs Friday , September 10, 2004
M0TW
Sheet 3
Rev A
of
8
- 38 -
+3.3V_DIG
R40 R43 R67
4 /OCM_WE 4 /OCM_RE 4 /ROM_CS
10K/6/NC 10K/6 10K/6
+3.3V_DIG
Socke t for a X8 Flash (64/128/256/512K) and PROM JETm em ory Em ulator
OCMADDR18 OCMADDR17 OCMADDR16 OCMADDR15 OCMADDR14 OCMADDR13 OCMADDR12 OCMADDR11 OCMADDR10 OCMADDR9 OCMADDR8 OCMADDR7 OCMADDR6 OCMADDR5 OCMADDR4 OCMADDR3 OCMADDR2 OCMADDR1 OCMADDR0
1 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12
XU1
/OCM_WE /OCM_RE /OCM_CS
V 5 2 / 0 F 6 u C 2 2
GND
6 / F u 9 1 . 5 0 C
4 OCMADDR[0..19]
OCMADDR[0..19] OCMDATA[0..7]
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A28F001 29LV040B
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 CE# OE# WE# VCC VSS
21 20 19 18 17 15 14 13
OCMDATA7 OCMDATA6 OCMDATA5 OCMDATA4 OCMDATA3 OCMDATA2 OCMDATA1 OCMDATA0 /ROM_CS /OCM_RE /OCM_WE
+3.3V_DIG
22 24 31
32
16
GND
4 OCMDATA[0..7]
+3.3V_DIG
R68 R69 R70 R62 R55 R47 R50 10K/6 10K/6 10K/6/NC 10K/6/NC 10K/6/NC 10K/6 10K/6/NC
OCMADDR8 OCMADDR9 OCMADDR13 OCMADDR14 OCMADDR15 OCMADDR16 OCMADDR18 OCMADDR17 OCMADDR19 OCMADDR10 OCMADDR11 OCMADDR12
INT_OSC 8-BIT_FLASH2 R65 10K/6 R80 10K/6 R41 10K/6 R46 10K/6 R71 10K/6
Firmware_By pass DDC2BI Serial_Interf ace_Debug1 Serial_Interf ace_Debug2 Serial_Interf ace_Debug3 8-BIT_FLASH1 8-BIT_FLASH3 TCLK OUTPUTS_ZERO OUTPUTS_ZERO
R56 R51 R61 R64 R73
10K/6 10K/6/NC 10K/6 10K/6 10K/6
GND
10: LOW (Use TCLK) 11: LOW (s et all dis play output to '0') 12: LOW 13: LOW(disable s erial inte rface de bug) 14: LOW 15: LOW 16: HIGH (use crystal) 17: LOW (8bit bus w ith OCM acces s e xte rnal ROM ) 18: HIGH 19: LOW
GND
PROJECT : M0TW
Quanta Computer Inc.
Title
06. Memory I/F
Size Date: Document Number 06. Memory I/F Thursday , September 02, 2004
M0TW
Sheet 6
Rev A
of
8
D1
1SS355
18V
+18V
L2 CX000800000/1206
6 0 2 1 / 0
8
U2
5 6 7 8
BOOST IS VCC FB DC DE CF GND
1
2
3
4
6 / F p 2 0 3 2 C 1 GND
1 2 R
R18
47R/6
7
6
R22
330K/6
6 / F p 7 0 0 2 2 1 C
8 0 0 2 2 1 C
6 / F p
6 / F u 8 1 . C 0
+
+ 5 1 C V 5 2 / u 0 0 1
4 1 C
GND
V 5 2 / u 0 0 1
5
6 / F u 1 1 . 2 0 C
D2 1SS355
4 3 2 1
O S / A 0 1 4 9 6 S QD N
L30
C22 0.1uF/6
+12V
CX000800000/1206
C189 1u/8
R149 4K7/6
Q21
1 2 3 4
AIC1563
8 / u 1
GND
6 2 C GND
R24
3K/6 1%
% 1 6 / K 3 0 2 4 R 2
0 2 R
2
Q7 1
2N3906
8 7 6 5
L31 CX000800000/1206
V12
R148
0/6/NC
C33
R25 1K/6 1%
2200pF/6
6 / K 1
4 TUNER12V_KEY
3
R147
4K7/6
2
3
GND
L3
2
1
47UH
L4 CX000800000/1206
6 / F u 1 . 0
+5V
Q20 MMBT3904L
SI9435
C190 0.1uF/6
1
V 6 1 / 1 u 9 0 1 3 C 3
C192 0.1uF/6
GND
1
GND
GND
GND
18V
CN4
6 7 8 9 1 2 3 4 5
D3 RB081L-20
6 7 8 9
20268-04
GND
2
L37 CX000800000/1206
6 / 4 F 3 p C 0 0 0 1
GND
5 3 C
V 6 1 V / 6 6 u 1 3 0 / C 3 3 u 3 0 0 2 3 3 GND C
GND
GND
GND
D20
1SS355
+5V
18V
4500-07
V5IR
7 6 5 4 3 2 1 CN1
L35 CX000800000/1206
+18V
6 0 2 1 / 0
U20
8 BOOST IS VCC FB DC DE CF GND
1
5 6 7 8
ADJ ON/OFF
GND
0 4 1 R
7
6
2
3
4
R143
R144
47R/6
330K/6
D21 1SS355
4 3 2 1
+ 0 8 1 C
6 / F p 9 0 0 2 2 1 C
6 / F p 0 0 2 1 2 1 C
+5V
GND
V 5 2 / u 0 0 6 / 1 F u 1 1 8 . 1 0 C
5
AIC1563
GND
2 8 1 C
GND
8 / u 1
GND
4 0 8 2 1 1 C
GND
6 / F p
% 1 6 / 5 K 0 4 4 1 2 R
6 4 1 R
O S / A 0 1 4 9 3 S 2 Q D N
C188 0.1uF/6
+12V
Q22 MMST3906
6 / K 1
U6
+1.8V_CORE
R142
8K2/6 1%
C183
R141 953R/6 1%
2200pF/6
L15
CX000800000/1206
L34 2
1
47UH
3
1
VIN
VOUT
2
ADJ/GND
R72
L13 CX000800000/1206
L32 CX000800000/1206
1
+3.3V_ADC
R11 10K/6/NC
+ V 5 2 / 1 u 6 0 C 0 1
AIC1084/TO252
R74 148R/6 1%
330R/6 1% +
6 5 C
D22 RB081L-20
V 5 2 / u 0 0 1
GND
2
V 6 1 6 / / 7 u F 8 0 u 6 1 3 / 1 . C 3 5 F 6 0 8 p 8 1 0 1 C 0 C 0 1 GND GND GND
GND
GND
R126
0/6
R12
100K/6
VOLUME 8
PWM1
4 PWM1
R9
4K7/6/NC
2
3
6 / F u 1 . Q3 0 MMBT3904L/NC 0 1 C
R127 1K/6/NC
+5V
L33 CX000800000/1206/NC
1
+5V
U4
GND
+18V
+3.3V_ADC
2
R57 200/6 1%
L28 CX000800000/1206/NC L29
GND
GND
L8
CX000800000/1206
3
VIN
VOUT
1
+ V 5 2 / 8 u 4 0 0 C 1
+12V
ADJ/GND
CX000800000/1206
PANEL_VCC
C23 1u/8
AIC1084/TO252
R58 330/6 1%
+ 3 5 C
+5V
V 5 2 / u 0 0 1
R17 4K7/6
1 2 3 4
Q4
8 7 6 5
L1 CX000800000/1206
C25 0.1uF/6
R19
0/6/NS
R6
4K7/6/NC
R7
0/6
Q2 MMST3906/NC
ON/OFF
GND
4 PPWR
R29
4K7/6
2
3
Q5 MMBT3904L
SI9435
C9 330uF/16V
+
C16 0.1uF/6
GND
1
25V
4 PBIAS
R10 4K7/6/NC
GND
GND
GND
GND
U3
+5V
0.8A Max
VOUT
+2.5V_DDR
+5V
R8 1K/6
L5
CX000800000/1206
3
VIN
2
R5
10K/6
6 / F u 1 . 0 7 C
GND
ADJ
+V 5 2 / u 0 1 0 4 1 C
1
ADJ/GND
R38 200/6 1% +V 5 2 / u 0 3 0 4 1 C
LT1117/TO223
4 PWM0
PWM0
R2
4K7/6
2
3
Q1 MMBT3904L
R39 200/6 1%
1
GND
GND
PROJECT : M0TW
Quanta Computer Inc.
Title Size Date:
POWER
Document Number 07. Power Tuesday , September 14, 2004
M0TW
Sheet 7
Rev A
of
8
- 39-