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U-100A
APPLICATION NOTE
UC3842/3/4/5 PROVIDES LOW-COST
CURRENT-MODE CONTROL
INTRODUCTION CURRENT-MODE CONTROL
The fundamental challenge of power supply design is to Figure 1 shows the two-loop current-mode control system
simultaneously realize two conflicting objectives: good in a typical buck regulator application. A clock signal initi-
electrical performance and low cost. The UC3842/3/4/5 ates power pulses at a fixed frequency. The termination of
is an integrated pulse width modulator (PWM) designed each pulse occurs when an analog of the inductor current
with both these objectives in mind. This IC provides de- reaches a threshold established by the error signal. In this
signers an inexpensive controller with which they can ob- way the error signal actually controls peak inductor cur-
tain all the performance advantages of current mode op- rent. This contrasts with conventional schemes in which
eration. In addition, the UC3842 series is optimized for ef- the error signal directly controls pulse width without regard
ficient power sequencing of off-line converters, DC to DC to inductor current.
regulators and for driving power MOSFETs or transistors.
Several performance advantages result from the use of
This application note provides a functional description of current-mode control. First, an input voltage feed-forward
the UC3842 family and highlights the features of each in- characteristic is achieved; i.e., the control circuit instanta-
dividual member, the UC3842, UC3843, UC3844 and neously corrects for input voltage variations without using
UC3845 Throughout the text, the UC3842 part number up any of the error amplifier's dynamic range. Therefore,
will be referenced, however the generalized circuits and line regulation is excellent and the error amplifier can be
performance characteristics apply to each member of the dedicated to correcting for load variations exclusively.
UC3842 series unless otherwise noted. A review of cur-
rent mode control and its benefits is included and meth- For converters in which inductor current is continuous,
ods of avoiding common pitfalls are mentioned. The final controlling peak current is nearly equivalent to controlling
section presents designs of power supplies utilizing average current. Therefore, when such converters employ
UC3842 control. current-mode control, the inductor can be treated as an
clock verror vsense latch output
Figure 1. Two-Loop Current-Mode Control System
3-53
APPLICATION NOTE U-100A
error-voltage-controlled-current-source for the purposes of causes a corresponding error in supply output voltage.
small-signal analysis. This is illustrated by Figure 2. The The recovery time is R&i, which may be quite long. How-
two-pole control-to-output frequency response of these ever, the compensation network of Figure 3b can be used
converters is reduced to a single-pole (filter capacitor in where current-mode control has eliminated the inductor
parallel with load) response. One result is that the error pole. Large-signal dynamic response is then greatly im-
amplifier compensation can be designed to yield a stable proved due to the absence of Ci.
closed-loop converter response with greater gainband-
Current limiting is greatly simplified with current-mode con-
width than would be possible with pulse-width control, giv-
trol. Pulse-by-pulse limiting is, of course, inherent in the
ing the supply improved small-signal dynamic response to
changing loads. A second result is that the error amplifier control scheme. Furthermore, an upper limit on the peak
compensation circuit becomes simpler, as illustrated in Fig- current can be established by simply clamping the error
voltage. Accurate current limiting allows optimization of
ure 3. Capacitor Ci and resistor Ri, in Figure 3a add a low
frequency zero which cancels one of the two control-to-. magnetic and power semiconductor elements while ensur-
output poles of non-current-mode converters. For large- ing reliable supply operation.
signal load changes, in which converter response is limit- Finally, current-mode controlled power stages can be op-
ed by inductor slew rate, the error amplifier will saturate erated in parallel with equal current sharing. This opens
while the inductor is catching up with the load. During this the possibility of a modular approach to power supply de-
time, Ci will charge to an abnormal level. When the induc- sign.
tor current reaches its required level, the voltage on Ci
Figure 2. Inductor Looks Like a Current Source to Small Signals
Vref
A) Direct Duty Cycle Control B) Current Mode Control
Figure 3. Required Error Amplifier Compensation for Continuous Inductor Current Designs
3-54
APPLICATION NOTE U-100A
THE UC3842/3/4/5 SERIES OF CURRENT-MODE PWM IC'S
DESCRIPTION FEATURES
The UC1842/3/4/5 family of control ICs provides the nec- l Optimized for Off-Line and DC to DC Converters
essary features to implement off-line or DC to DC fixed
frequency current mode control schemes with a minimal l Low Start Up Current (< 1 mA)
external parts count. Internally implemented circuits in- @ Automatic Feed Forward Compensation
clude under-voltage lockout featuring start up current less
than 1 mA, a precision reference trimmed for accuracy at l Pulse-By-Pulse Current Limiting
the error amp input, logic to insure latched operation, a l Enhanced Load Response Characteristics
PWM comparator which also provides current limit control,
and a totem pole output stage designed to source or sink l Under-Voltage Lockout with Hysteresis
high peak current. The output stage, suitable for driving ei- l Double Pulse Suppression
ther N Channel MOSFETs or bipolar transistor switches, is
low in the off state. l High Current Totem Pole Output
Differences between members of this family are the un- l Internally Trimmed Bandgap Reference
der-voltage lockout thresholds and maximum duty cycle l 500 kHz Operation
ranges. The UC1842 and UC1844 have UVLO thresholds
of 16V (on) and 10V (off), ideally suited to off-line applica- l Low Ro Error Amp
tions. The corresponding thresholds for the UC1843 and
UC1845 are 8.5V and 7.9V. The UC1842 and UC1843 can
operate to duty cycles approaching 100%. A range of
zero to <50% is obtained by the UC1844 and UC1845 by
the addition of an internal toggle flip flip which blanks the
output off every other clock cycle.
IC SELECTION GUIDE RECOMMENDED USAGE
Note: 1. (A/B/ A= DIL-8 Pin Number. B = SO-16 Pin Number.
2. Toggle flip flop used only in 1844A and 1845A.
Figure 4
3-55
APPLICATION NOTE U-100A
UNDER-VOLTAGE LOCKOUT
The UVLO circuit insures that VCC is adequate to make
the UC3842/3/4/5 fully operational before enabling the
output stage. Figure 5 shows that the UVLO turn-on and
turn-off thresholds are fixed internally at 16V and 10V re-
spectively. The 6V hysteresis prevents Vcc oscillations
during power sequencing. Figure 6 shows supply current
requirements. Start-up current is less than 1 mA for effi-
cient bootstrapping from the rectified input of an off-line
converter, as illustrated by Figure 6. During normal circuit
Figure 6. During Under-Voltage Lockout, the output
operation, VCC is developed from auxiliary winding WAux
driver is biased to sink minor amounts of
with D1 and GIN. At start-up, however, GIN must be
current.
charged to 16V through RtN. With a start-up current of 1
mA, RtN can be as large as 100 kR and still charge GIN
when VAc = 90V RMS (low line). Power dissipation in
OSCILLATOR
RIN would then be less than 350 mW even under high line The UC3842 oscillator is programmed as shown in Figure
(VAc = 130V RMS) conditions. 8. Timing capacitor CT is charged from VREF (5V) through
the timing resistor RT, and discharged by an internal cur-
During UVLO; the output driver is in a low state. While it
rent source.
doesn't exhibit the same saturation characteristics as nor-
mal operation, it can easily sink 1 milliamp, enough to in- The first step in selecting the oscillator components is to
sure the MOSFET is held off. determine the required circuit deadtime. Once obtained,
Figure 9 is used to pinpoint the nearest standard value of
CT for a given deadtime. Next, the appropriate RT value is
interpolated using the parameters for CT and oscillator
frequency. Figure 10 illustrates the RT/CT combinations
versus oscillator frequency. The timing resistor can be cal-
culated from the following formula.
Fosc (kHz) = 1.72 / (RT (k) × CT (pf))
Figure 5
The UC3844 and UC3845 have an internal divide-by-two
flip-flop driven by the oscillator for a 50% maximum duty
cycle. Therefore, their oscillators must be set to run at
twice the desired power supply switching frequency. The
UC3842 and UC3843 oscillator runs AT the switching fre-
quency. Each oscillator of the UC3842/3/4/5 family can
be used to a maximum of 500 kHz.
0019-8
Figure 7. Providing Power to the UC3842/3/4/5
3-56
APPLICATION NOTE U-100A
MAXIMUM DUTY CYCLE CURRENT SENSING AND LIMITING
The UC3842 and UC3843 have a maximum duty cycle of The UC3842 current sense input is configured as shown
approximately 100%, whereas the UC3844 and UC3845 in Figure 12. Current-to-voltage conversion is done exter-
are clamped to 50% maximum by an internal toggle flip nally with ground-referenced resistor Rs. Under normal
flop. This duty cycle clamp is advantageous in most fly- operation the peak voltage across Rs is controlled by the
back and forward converters. For optimum IC perform- E/A according to the following relation:
ance the deadtime should not exceed 15% of the oscilla-
tor clock period.
During the discharge, or "dead" time, the internal clock
signal blanks the output to the low state. This limits the where VC = control voltage = E/A output voltage.
maximum duty cycle DMAX to: Rs can be connected to the power circuit directly or
DhnAx = 1 - ODEAD / ~PERI~D) U C 3 8 4 2 / 3 through a current transformer, as Figure 11 illustrates.
While a direct connection is simpler, a transformer can re-
DMAX = 1 - (tDEAD / 2 X tpER& UC3844/5 duce power dissipation in Rs, reduce errors caused by the
where TPERIOD = 1 / F oscillator base current, and provide level shifting to eliminate the re-
straint of ground-referenced sensing. The relation be-
tween VC and peak current in the power stage is given by:
where: N = current sense transformer turns ratio
= 1 when transformer not used.
For purposes of small-signal analysis, the control-to-
sensed-current gain is:
0019-9
Figure 8
When sensing current in series with the power transistor,
Deadtime vs CT (RT > 5k) as shown in Figure 11, the current waveform will often
have a large spike at its leading edge. This is due to recti-
fier recovery and/or inter-winding capacitance in the pow-
er transformer. If unattenuated, this transient can prema-
turely terminate the output pulse. As shown, a simple RC
filter is usually adequate to suppress this spike. The RC
time constant should be approximately equal to the cur-
rent spike duration (usually a few hundred nanoseconds).
The inverting input to the UC3842 current-sense compara-
tor is internally clamped to 1V (Figure 12). Current limiting
occurs if the voltage at pin 3 reaches this threshold value,
0019-10 i.e., the current limit is defined by:
Figure 9
Timing Resistance vs Frequency
FREOUENCY - (Hz)
0019-11
0019-13
Figure 10 Figure 11. Transformer-Coupled Current Sensing
3-57
APPLICATION NOTE U-100A
0019-12
Figure 12. Current Sensing
ERROR AMPLIFIER
The error amplifier (E/A) configuration is shown in Figure
13. The non-inverting input is not brought out to a pin, but
is internally biased to 2.5V ± 2%. The E/A output is
available at pin 1 for external compensation, allowing the
user to control the converter's closed-loop frequency re-
sponse.
Figure 14 shows an E/A compensation circuit suitable for
stabilizing any current-mode controlled topology except for
flyback and boost converters operating with inductor cur-
rent. The feedback components add a pole to the loop
transfer function at fp = 4/*7r RF,+ RF and CF are cho-
sen so that this pole cancels the zero of the output filter
capacitor ESR in the power circuit. RI and RF fix the low- Figure 14. Compensation
frequency gain. They are chosen to provide as much gain The E/A output will source 0.5 mA amd sink 2 mA. A low-
as possible while still allowing the pole formed by the out- er limit for RF is given by:
put filter capacitor and load to roll off the loop gain to uni-
ty (0 dB) at f =: fSWtTCHtNG/4. This technique insures
converter stability while providing good dynamic response.
0019-14
Figure 13. E/A Configuration
3-58
APPLICATION NOTE U-100A
E/A input bias curret (2 PA max) flows through RI, result- transistors. Cross conduction between the output transis-
ing in a DC error in output voltage (VO) given by: tors is minimal, the average added power with VIN = 30V
is only 80 mW at 200 kHz.
Limiting the peak current through the IC is accomplished
It is therefore desirable to keep the value of RI, as low as by placing a resistor between the totem-pole output and
possible. the gate of the MOSFET. The value is determined by di-
Figure 15 shows the open-loop frequency response of the viding the totem-pole collector voltage VC by the peak
UC3842 E/A. The gain represents an upper limit on the current rating of the IC's totem-pole. Without this resistor,
gain of the compensated E/A. Phase lag increases rapidly the peak current is limited only by the dV/dT rate of the
as frequency exceeds 1 MHz due to second-order poles totem-pole switching and the FET gate capacitance.
at ~ 10 MHz and above. The use of a Schottky diode from the PWM output to
Continuous-inductor-current boost and flyback converters ground will prevent the output voltage from going exces-
each have a right-half-plane zero in their transfer function. sively below ground, causing instabilities within the IC. To
An additional compensation pole is needed to roll off loop be effective, the diode selected should have a forward
gain at a frequency less than that of the RHP zero. Rp drop of less than 0.3V at 200 mA. Most l- to 3-amp
and Cp in the circuit of Figure 16 provide this pole. Schottky diodes exhibit these traits above room tempera-
ture. Placing the diode as physically close to the PWM as
TOTEM-POLE OUTPUT possible will enhance circuit performance. Implementation
of the complete drive scheme is shown in the following di-
The UC3842 PWM has a single totem-pole output which agrams. Transformer driven circuits also require the use of
can be operated to ± 1 amp peak for driving MOSFET the Schottky diodes to prevent a similar set of circum-
gates, and a + 200 mA average current for bipolar power
10 100 1K 10K 100K 1M 10M
FREQUENCY - (Hz)
0019-16
Figure 15. Error Amplifier Open-Loop Frequency Response
0019-17
Figure 16. E/A Compensation Circuit for Continuous Boost and Flyback Topologies
3-59
APPLICATION NOTE U-100A
stances from occurring on the PWM output. The ringing Figure 19 shows an isolated MOSFET drive circuit which
below ground is greatly enhanced by the transformer leak- is appropriate when the drive signal must be level shifted
age inductance and parasitic capacitance, in addition to or transmitted across an isolation boundary. Bipolar tran-
the magnetizing inductance and FET gate capacitance. sistors can be driven efficiently with the circuit of Figure
Circuit implementation is similar to the previous example. 20. Resistors R1 and R2 fix the on-state base current
while capacitor Cl provides a negative base current pulse
Figures 18, 19 and 20 show suggested circuits for driving
to remove stored charge at turn-off.
MOSFETs and bipolar transistors with the UC3842 output.
The simple circuit of Figure 18 can be used when the Since the UC3842 series has only a single output, an in-
control IC is not electrically isolated from the MOSFET terface circuit is needed to control push-pull half or full
turn-on and turn-off to ± 1 amp. It also provides damping bridge topologies. The UC3706 dual output driver with in-
for a parasitic tank circuit formed by the FET input capaci- ternal toggle flip-flop performs this function. A circuit ex-
tance and series wiring inductance. Schottky diode D1 ample at the end of this paper illustrates a typical applica-
prevents the output of the IC from going far below ground tion for these two ICs. Increased drive capability for driv-
during turn-off. ing numerous FETs in parallel, or other loads can be ac-
complished using one of the UC3705/6/7 driver ICs.
10 TO 20V
OUTPUT CURRENT SOURCE OR SINK - (A)
0019-18 Figure 18. Direct MOSFET Drive
Figure 17. Output Saturation Characteristics
20 TO 30V 12 TO 20V
Figure 19. Isolated MOSFET Drive
Figure 20. Bipolar Drive with Negative Turn-Off Bias
3-61
APPLICATION NOTE U-100A
NOISE when driving MOSFETs. A Schottky diode clamp from
ground to pin 6 will prevent such output noise from feed-
As mentioned earlier, noise on the current sense or con- ing to the oscillator. If these measures fail to correct the
trol signals can cause significant pulse-width jitter, particu- probelm, the oscillator frequency can always be stabilized
larly with continuous-inductor-current designs. While slope with an external clock. Using the circuit of Figure 31 re-
compensation helps alleviate this problem, a better solu- sults in an FIT/CT waveform like that of Figure 21B. Here
tion is to minimize the amount of noise. In general, noise the oscillator is much more immune to noise because the
immunity improves as impedances decrease at critical ramp voltage never closely approaches the internal
points in a circuit. threshold.
One such point for a switching supply is the ground line.
Small wiring inductances between various ground points
SYNCHRONIZATION
on a PC board can support common-mode noise with suf- The simplest method to force synchronization utilizes the
ficient amplitude to interfere with correct operation of the timing capacitor (CT) in near standard configuration. Rath-
modulating IC. A copper ground plane and separate return er than bring CT to ground directly, a small resistor is
lines for high-current paths greatly reduce common-mode placed in series with CT to ground. This resistor serves as
noise. Note that the UC3842 has a single ground pin. the input for the sync pulse which raises the CT voltage
High sink currents in the output therefore cannot be re- above the oscillator's internal upper threshold. The PWM
turned separately. is allowed to run at the frequency set by RT and CT until
Ceramic monolythic bypass capacitors (0.1 pF) from VCC the sync pulse appears. This scheme offers several ad-
and VREF to ground will provide low-impedance paths for vantages including having the local ramp available for
high frequency transients at those points. The input to the slope compensation. The UC3842/3/4/5 oscillator
error amplifier, however, is a high-impedance point which
cannot be bypassed without affecting the dynamic re-
sponse of the power supply. Therefore, care should be
taken to lay out the board in such a way that the feed-
back path is far removed from noise generating compo-
nents such as the power transistor(s).
Figure 21 illustrates another common noise-induced prob-
lem. When the power transistor turns off, a noise spike is
coupled to the oscillator FIT/CT terminal. At high duty cy-
cles the voltage at RT/CT is approaching its threshold lev-
el (~ 2.7V, established by the internal oscillator circuit)
when this spike occurs. A spike of sufficient amplitude will
prematurely trip the oscillator as shown by the dashed
lines. In order to minimize the noise spike, choose CT as
large as possible, remembering that deadtime increases 0019-32
with CT. It is recommended that CT never be less than Figure 22. Sync Circuit Implementation
~ 1000 pF. Often the noise which causes this problem is
caused by the output (pin 6) being pulled below ground at
turn-off by external parasitics. This is particularly true
Figure 21. (a.) Noise on Pin 4 can cause oscillator to pre-trigger.
(b.) With external sync., noise does not approach threshold level.
3-61
APPLICATION NOTE U-100A
must be set to a lower frequency than the sync pulse digital logic input rather than the conventional analog
stream, typically 20 percent with a 0.5V pulse applied mode. The primary considerations of on-time, dead-time,
across the resistor. Further information on synchronization duty cycle and frequency can be encompassed in the digi-
can be found in "Practical Considerations in Current Mode tal pulse train input.
Power Supplies" listed in the reference appendix.
A LOW logic level input determines the PWM maximum
The UC3842 can also be synchronized to an external ON time. Conversely, a HIGH input governs the OFF, or
clock source through the FIT/CT terminal (Pin 4) as shown dead time. Critical constraints of frequency, duty cycle or
in Figure 23. dead time can be acurately controlled by anything from a
555 timer to an elaborate microprocessor controlled soft-
In normal operation, the timing capacitor CT is charged
ware routine.
between two thresholds, the upper and lower comparator
limits. As CT begins its charge cycle, the output of the
PWM is initiated and turns on. The timing capacitor contin-
ues to charge until it reaches the upper threshold of the
internal comparator. Once intersected, the discharge cir-
cuitry activates and discharges CT until the lower thresh-
old is reached. During this discharge time the PWM output
is disabled, thus insuring a "dead" or off time for the out-
put.
A digital representation of the oscillator charge/discharge
status can be utilized as an input to the FIT/CT terminal.
In instances like this, where no synchronization port is
easily available, the timing circuitry can be driven from a
0019-34
Figure 23
Synchronization to an External Clock
Figure 24
3-62
APPLICATION NOTE U-100A
SYNC PULSE GENERATOR
The UC3842/3/4/5 oscillator can be used to generate scheme. Triggered by the master's deadtime, this circuit is
sync pulses with a minimum of external components. This useable to several hundred kilohertz with a minimum of
simple circuit shown in Figure 25 triggers on the falling delays between the master and slave(s). The photos
edge of the CT waveform, and generates the sync pulse shown in Figures 26 and 27 depict the circuit waveforms
required for the previously mentioned synchronization of interest.
Figure 25. Sync Pulse Generator Circuit
Top Trace:
Circuit Input
Top Trace:
Slave CT
Bottom Trace:
Circuit Output Bottom Trace:
Across 24 Ohms Master CT
Vertical: O.5V/CM Both Vertical: 0.5V/CM Both
Horizontal: 0.5~SICM Horizontal: 0.5$XYvI
001938 0019-38
001939 0019-39
Figure 26. Operating Waveforms at 500 kHz Figure 27. Master/Slave Sync Waveforms at CT
3-63
APPLICATION NOTE U-100A
CHARGE PUMP CIRCUITS
LOW POWER DC/DC CONVERSION
Step Up Inverting
Figure 28 Figure 29
Low Power Buck Regulator-Voltage Mode
The basic buck regulator is described
in the UNITRODE Applications Hand-
book.
*Consult UNITRODE Power Supply
Design Seminar Book for compensa-
tion details; see "Closing The Feed-
back Loop", Buck Topology.
Figure 30
3-64
APPLICATION NOTE U-100A
CIRCUIT EXAMPLES Also consult UNITRODE application note U-96 in the ap-
plications handbook.
1. Off-Line Flyback
Figure 31 shows a 25W multiple-output off-line flyback
regulator controlled with the UC3844. This regulator is low
in cost because it uses only two magnetic elements, a pri-
mary-side voltage sensing technique, and an inexpensive
control circuit. Specifications are listed below.
0019-46
Figure 31
Power Supply Specifications
1. Input Voltage: 95 VAC to 130 VAC (50 Hz/60 Hz)
2. Line Isolation: 3750V
3. Switching Frequency: 40 kHz
4. Efficiency @ Full Load: 70%
5. Output Voltage:
A. + 5V, ± 5%: 1A to 4A load
Ripple voltage: 50 mV P-P Max.
6. +12V, ±3% 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max.
C. -12V ±3%, 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max.
3-65
2. DC-to-DC Push-Pull Converter
Figure 45 is a 500W push-pull DC-to-DC converter
utilizing the UC3642, UC3706, and UC3901 ICs. It
operates from a standard telecommunications bus
to produce 5V at up to 100A. Operation of this cir-
cuit is detailed in Reference 6.
SPECIFICATIONS:
Input Voltage: -48V ± 8V
Output Voltage: +5V
Output Current: 25A to 100A
Oscillator Frequency: 200 kHz
Line Regulation: 0.1%
Load Regulation: 1%
Efficiency @ VIN = 48V
lo = 25A: 75%
lo = 50A: 80%
Output Ripple Voltage: 200 mV P-P
Also consult application note U-101 in the Unitrode
Applications Handbook. 0019-48
Figure 32. 500W Push-Pull DC-to-DC Converter
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