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1 1




Compal Confidential
2 2




KALH0 /KAL90+ /KALG0 M/B Schematics Document
Intel Penryn Processor with Cantiga + DDRIII + ICH9M




3 2009-3-4 3




REV:1.0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/24 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
KALH0/KALG0/KAL90+ 1.0

Date: Monday, April 27, 2009 Sheet 1 of 53
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A B C D E




Compal Confidential
Fan Control Intel Penryn Processor Thermal Sensor Clock Generator
Model Name : KALH0/KALG0/KAL90+ page 40
EMC 1402 ICS9LPRS387
uPGA-478 Package page 4 page 16

(Socket P) page 4,5,6
1 1
FSB
H_A#(3..35) H_D#(0..63)
667/800/1066MHz
HDMI Conn. LCD Conn. CRT Conn.
page 24,30 page 22 page 23
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
Intel Cantiga
LVDS Dual Channel BANK 0, 1, 2, 3 page 13,14

TMDS LVDS uFCBGA-1329 1.5V DDRIII 800/1066

PCI-Express page 7,8,9,10,11,12,13
Card Reader 16X
JMB385 VGA USB conn x3 Bluetooth CMOS LS-4494P
page 31 DMI C-Link Finger Print
page 17,18,19,20,21
USB port 0, 2, 5 Conn Camera
page 34 page 35 page 22 AES1610

PCI-Express
2
Intel ICH9-M 3.3V 48MHz
USB
2




3.3V 24.576MHz/48Mhz
HD Audio
S-ATA
BGA-676
LAN(GbE) MINI Card x2 New Card page 25,26,27,28
ATHEROS AR8121 WLAN, Robson2 Socket
page 32 page 34 page 35 GMCH HDA MDC 1.5 HDA Codec VGA HDA
Conn 38 ALC888S-VC
port 2 port 1 port 0 page 08 page page 39 page 18


RJ45 ESATA CDROM SATA HDD
page 33
Conn.
page 35
Conn.
page 29
Conn.
page 29 Audio AMP
LPC BUS page 40

3 3


ENE KB926 Phone Jack x3
page 36 page 40

RTC CKT. KAL90+ KALG0
page 38
LS-4493P Touch Pad Int.KBD LS-4495P
page 37
Power On/Off CKT. Media/B Conn. KALH0 page 37
USB/B Conn.
USB port 1
page 38 LS-4498P LS-4495P EC I/O Buffer BIOS
FUN Conn. USB/B Conn. LS-4921P
page 37 page 37
DC/DC Interface CKT. USB port 1 FUN Conn.
LS-4492P
page 44 LS-5042P
E_KEY/B Conn. LS-4494P
LED/B Conn. CIR FINGERPRINT/Comm
Power Circuit DC/DC LS-4495P page 38
LS-5041P
4
page 44,45,46,47,48 ,49,50,51 USB/B Conn. Media/B Conn.
4

USB port 1

POWER SW
Page 43
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/24 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
KALH0/KALG0/KAL90+ 1.0

Date: Monday, April 27, 2009 Sheet 2 of 53
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF 1


+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5V 1.5V power rail for HDA/DDR3 ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V GM LVDS MODULE ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.1VS 1.1V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V 3.3V power rail for SB ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON X 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2
+RTCVCC RTC power ON ON ON 2


+VGA_CORE Core voltage for GPU ON OFF OFF
BOARD ID Table BTO Option Table
Board ID PCB Revision BTO Item BOM Structure
0 0.1 KAL90 [email protected]
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
1 0.2 UMA [email protected]
External PCI Devices 2 0.3 [email protected] [email protected]
3 1.0 ALC888VC [email protected]
Device IDSEL# REQ#/GNT# Interrupts 4 1A ALC888VB [email protected]
5 AR8121 [email protected]
EC SM Bus1 address EC SM Bus2 address 6 AR8112 [email protected]
7 ALC268 [email protected]
Device Address Device Address GL40 [email protected]
Smart Battery 0001 011X b ADI ADT7421 1001 100X b GM45 [email protected]
MEDIA CONSOLE 1010 000X b NB9M THERMAL SENSOR KAL90-G0 [email protected]
3 KAL90-H0 [email protected] 3
ICH9M SM Bus address KALG0 [email protected]
KALH0 [email protected]
Device Address
BOM Configuration Table ALC268 [email protected]
Clock Generator 1101 001Xb [email protected]
(ICS9LPRS387, SLG8SP556V)

DDR DIMM0 1001 000Xb
Project BOM Configuration [email protected]
KAL90+_G0
DDR DIMM2 1001 010Xb KAL90-UMA XXXXXXXXXX:[email protected]/[email protected]/[email protected]/[email protected]/[email protected]
KALH0_G0
KAL90-Dis XXXXXXXXXX:[email protected]/[email protected]/[email protected]/[email protected]
[email protected]
KALH0-GM45 XXXXXXXXXX:[email protected]/[email protected]/[email protected]/[email protected]/[email protected]
[email protected]
KALH0-GL40 XXXXXXXXXX:[email protected]/[email protected]/[email protected]/[email protected]/[email protected]
KALH0-PM45 XXXXXXXXXX:[email protected]/[email protected]/[email protected]/[email protected] [email protected]
[email protected]
KAL90+ -UMA [email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]
KAL90+ -Dis [email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]
KALG0 -UMA(GL40) [email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/KALG0_DDR2 PCB RV0 @/[email protected]
KALG0 -Dis [email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/KALG0_DDR2 PCB RV0 @/[email protected]
4 4

KALG0 -UMA(GM45) [email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/KALG0_DDR2 PCB RV0 @/[email protected]
KALG0 -DIS(GM45) [email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/[email protected]/KALG0_DDR2 PCB RV0 @/[email protected]
KALG0 LAN to AR-8131------- [email protected] Change to [email protected] Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/24 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
KALH0/KALG0/KAL90+ 1.0

Date: Monday, April 27, 2009 Sheet 3 of 53
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5 4 3 2 1




H_A#[3..35]
<7> H_A#[3..35]
H_REQ#[0..4]
<7> H_REQ#[0..4]
H_RS#[0..2]
<7> H_RS#[0..2]
JCPU1A
H_A#3 J4 H1 H_ADS# <7>
H_A#4 A[3]# ADS#




ADDR GROUP_0
L5 E2 H_BNR# <7>
H_A#5 A[4]# BNR#
D L4 G5 H_BPRI# <7> D
H_A#6 A[5]# BPRI#
K5
H_A#7 A[6]#
M3 H5 H_DEFER# <7>
H_A#8 A[7]# DEFER#
N2 F21 H_DRDY# <7>
H_A#9 A[8]# DRDY#
J1 E1 H_DBSY# <7>
H_A#10 A[9]# DBSY#
N3
H_A#11 A[10]#
P5 F1 H_BR0# <7>
H_A#12 A[11]# BR0#
P2
H_A#13 A[12]# H_IERR#




CONTROL
L2 D20
H_A#14 A[13]# IERR#
P4 B3 H_INIT# <26>
H_A#15 A[14]# INIT#
P1
H_A#16 A[15]#
R1 H4 H_LOCK# <7>
A[16]# LOCK#
<7> H_ADSTB#0 M1
ADSTB[0]# H_RESET#
C1 H_RESET# <7>
H_REQ#0 RESET# H_RS#0
K3 F3
H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 F4
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 G3
H_REQ#3 REQ[2]# RS[2]#
J3 G2 H_TRDY# <7>
H_REQ#4 REQ[3]# TRDY#
L1
REQ[4]#
G6 H_HIT# <7>
H_A#17 HIT#
Y2 E4 H_HITM# <7>
H_A#18 A[17]# HITM#
U5
H_A#19 A[18]#
R3 AD4
H_A#20 A[19]# BPM[0]#
ADDR GROUP_1
W6 AD3
H_A#21 A[20]# BPM[1]#
U4 AD1
H_A#22 A[21]# BPM[2]#
Y5 AC4
H_A#23 A[22]# BPM[3]#
U1 AC2
XDP/ITP SIGNALS
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 AC1
H_A#25 A[24]# PREQ# XDP_TCK
T5 AC5
H_A#26 A[25]# TCK XDP_TDI
C T3 AA6 C
H_A#27 A[26]# TDI
W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 AB5
H_A#29 A[28]# TMS XDP_TRST#
Y4 AB6
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 C20 XDP_DBRESET# <27>
H_A#31 A[30]# DBR#
V4
H_A#32 A[31]# +1.05VS
W3
H_A#33 A[32]#
AA4
A[33]# THERMAL
H_A#34 AB2
H_A#35 A[34]# H_PROCHOT#
AA3 D21
A[35]# PROCHOT# H_THERMDA
<7> H_ADSTB#1 V1 A24
ADSTB[1]# THERMDA H_THERMDC XDP_TDI R2 54.9_0402_1%
B25 1 2
THERMDC
<26> H_A20M# A6
A20M#
left NC if no ITP
ICH




<26> H_FERR# A5 C7 H_THERMTRIP# <8,26>
FERR# THERMTRIP#
<26> H_IGNNE# C4
IGNNE# XDP_TMS R3 1 2 54.9_0402_1% 39Ohm
<26> H_STPCLK# D5
STPCLK# XDP_BPM#5 R5 @ 54.9_0402_1%
<26> H_INTR C6
LINT0 H CLK 1 2
<26> H_NMI B4 A22 CLK_CPU_BCLK <16>
LINT1 BCLK[0]
<26> H_SMI# A3 A21 CLK_CPU_BCLK# <16>
SMI# BCLK[1]
M4 H_PROCHOT# R13 2 1 56_0402_5%
RSVD[01]
N5
RSVD[02] H_IERR# R18 56_0402_5%
T2 2 1
RSVD[03]
V3
RSVD[04]
B2
RSVD[05] Layout Note:
RESERVED




D2
D22
RSVD[06] H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
D3
B RSVD[08] XDP_TRST# R7 54.9_0402_1% B
F6 2 1
RSVD[09]
XDP_TCK R8 1 2 54.9_0402_1%


Penryn
[email protected]


+3VS
C2
0.1U_0402_16V4Z
1 2


+1.05VS
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA
U1


0 0 0 266 1
VDD SMCLK
8 EC_SMB_CK2 <18,36,37>
1




1
R17 @ C3 2 7
DP SMDATA EC_SMB_DA2 <18,36,37>
0 1 0 200 56_0402_5%
2200P_0402_50V7K 3 6 1 2 +3VS
2 DN ALERT# R1133
2




0 1 1 166 H_THERMDC
4
THERM# GND
5 10K_0402_5%
2
B




H_PROCHOT# EMC1402-1-ACZL-TR_MSOP8
E




A 3 1 OCP# <27> A
C




Q1
MMBT3904_SOT23-3
@

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/24 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (1/3)