Text preview for : G430_LE6.pdf part of LENOVO G430_LE6 LENOVO Laptop G430_LE6.pdf
Back to : G430_LE6.pdf | Home
1 2 3 4 5 6 7 8
PCB STACK UP LE6 BLOCK DIAGRAM
6L 01
LAYER 1 : TOP CPU CPU THERMAL
SENSOR
LAYER 2 : GND Penryn 14.318MHz
A PAGE 6 A
LAYER 3 : IN1
478P (uPGA)/35W
LAYER 4 : IN2 PAGE 4,5 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK# CLOCK GEN
LAYER 5 : VCC DREFCLK,DREFCLK# ALPRS355B MLF64PIN
FSB 667/800/1066
LAYER 6 : BOT DREFSSCLK,DREFSSCLK# PAGE 3
NORTH BRIDGE
DDRII-SODIMM1 DDRII 667/800 MHz
PAGE 12,13 Cantiga
DDRII 667/800 MHz CRT
B
DDRII-SODIMM2 B
PAGE 18
PAGE 12,13
PAGE 7,8,9,10,11
Dual Link
LCD CONN
32.768KHz PAGE 18
DMI LINK NBSRCCLK, NBSRCCLK#
SYSTEM DISCHARGER
SATA - HDD
SATA0 150MB USB2.0
PAGE 28 PAGE 25
USB2.0 Ports BlueTooth CCD
SOUTH BRIDGE
SATA4 150MB X3 PAGE 26 PAGE 25 PAGE 26
SYSTEM CHARGER(ISL6251AHAZ-T) SATA - CD-ROM
PAGE 25
PAGE 29 ICH-9M
PCI-E
DDR II SMDDR_VTERM X1 X1 X1 X1
C
1.8V/1.8VSUS(TPS51116REGR) Azalia C
PAGE 30 PAGE 14,15,16,17 Mini PCI-E LAN Express J Micro 385
Card BROADCOM Card
AUDIO BCM 5906M
(NEW CARD)
VCCP +1.5V AND GMCH (Wireless
CODEC
1.05V(RT8204) 32.768KHz LPC CX20561-12Z
LAN ) (10/100 LAN)
PAGE 25
PAGE 19
PAGE 31 MDC CONN PAGE 25
PAGE 20
PAGE 21 PAGE 21
CPU CORE ISL6266A
Keyboard
AUDIO
RJ45 25MHz
PAGE 32 Touch Pad PAGE 23 ITE PAGE 20
Amplifier
8502E-L Memory
TPA6017A2
CardReader
SYSTEM POWER ISL6237IRZ-T PAGE 24 PAGE 22
PAGE 33
PAGE 19
D
microphone Audio Jacks Jack to D
(Phone/ MIC) Speaker
PAGE 21 PAGE 22 PAGE 22
GMT G9931P1U
SPI PROJECT : LE6
FAN PAGE 24 Quanta Computer Inc.
PAGE 23
Size Document Number Rev
Custom BLOCK DIAGERAM 1A
Date: Wednesday, April 23, 2008 Sheet 1 of 34
1 2 3 4 5 6 7 8
5 4 3 2 1
Board Stack up Description
PCB Layers Voltage Rails
02
Layer 1 TOP Voltage Rails ON S0~S2 ON S3 ON S4 ON S5 Control signal
Layer 2 GND VCC_CORE X VRON
+1.5V X MAINON
Layer 3 IN1
+1.05V X MAINON
Layer 4 IN2
D 5V_S5/3V_S5/1.5V_S5 X X X X S5_ON D
Layer 5 SVCC
Layer 6 BOTTOM 5VSUS/3VSUS/1.8VSUS X X SUSON
SMDDR_VTERM/+2.5V/+3V/+5V/+12V X MAINON
+VCC_GFX_CORE/+1.2V_GFX_PCIE X MAINON
LANVCC X X X X LAN_ON
Power On Sequencing Timing Diagram
3VPCU X X X X VL
5VPCU X X X X VL
VID
VRON Tsft_star_vcc
Vboot Vid
VCC_CORE Tboot
Tboot-vid-tr
CPU_UP Tcpu_up
Vccp
Vccp_UP Tvccp_up
Vccgmch ACIN POWER ON TIMING
GMCHPWRGD Tgmch_pwrgd
ACIN PCI DEVICE IDSEL# REQ# / GNT# Interrupts
CLK_ENABLE# 5VPCU/3VPCU RICOH832 AD25 REQ0# / GNT0# INT E#/F#
C IMVP4_PWRGD Tcpu_pwrgd NBSWON# C
DNBSWON# To ICH7
YONAH Power-up Timing Specifications
S5_ON
To ICH7
Td
RSMRST#
RESET#
From ICH7
SUSB#,SUSC#
SUSON From 97551
BCLK
MAINON From 97551
Tc
VSUS,VCC From 97551
Te
PWRGOOD VRON
+1.5V/+1.05V
Tf
Ta Tb
VCC_CORE
VCC
Vcc,boot CLK_EN#
To clock generator
VID[5:0] 99ms < t 214
PWROK
To GMCH/other PCI device
PLTRST#\PCIRST#
B B
VCCP
Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild
Tc=BCLK stable to PWRGOOD assertion
Td=PWRGOOD to RESET# de-assertion time
Te=Vcc,boot vaild to PWRGOOD assertion time
A A
PROJECT : LE6
Quanta Computer Inc.
Size Document Number Rev
Custom SYSTEM INFORMATION 1A
Date: Friday, May 02, 2008 Sheet 2 of 34
5 4 3 2 1
1 2 3 4 5 6 7 8
+3V
L55
1 2
BLM18PG181SN1_6
180 ohms@100Mhz
+CK_VDD_MAIN
CG_XIN 1
Y2
2 CG_XOUT
+3V
03
1
1
1
1
1
C260 14.318MHZ+/- 10ppm Q11 R164 R196
1
1
2
C539 C540 C261 C266 C538 10K_6 10K_6
10U/6.3V/X5R_8 0.1U/10V/X7R_4 C282 C288 2N7002E
2
2
2
2
2
0.1U/10V/X7R_4 0.1U/10V/X7R_4 0.1U/10V/X7R_4 0.1U/10V/X7R_4 33P/50V/NPO_4 33P/50V/NPO_4 3 1 CGDAT_SMB
(16,26) PDAT_SMB
2
2
14.318MHz
A A
L54 +3V
1 2 +CK_VDD_MAIN2
BLM18PG181SN1_6 Q12
2
180 ohms@100Mhz +3V
1
1
1
1
1
1
C515 2N7002E
C534 C533 C520 C521 C522 C535 3 1 CGCLK_SMB
(16,26) PCLK_SMB
10U/6.3V/X5R_8 0.1U/10V/X7R_4 CLK_MCH_OE# R221 2 1 10K_4
2
2
2
2
2
2
0.1U/10V/X7R_4 0.1U/10V/X7R_4 0.1U/10V/X7R_4 0.1U/10V/X7R_4 0.1U/10V/X7R_4 NEW-CARD_CLK_REQ# R180 2 1 10K_4 internal have
already build-in
PCIE_LANREQ# R213 2 1 10K_4 33ohm damping
resisteor
L35
1 2 VDDCPU U8
+CK_VDD_MAIN 2 48
BLM18PG181SN1_6 VDD_PCI NC
9 VDD_48
C257 1 16 VDD_PLL3 SCLK 64 CGCLK_SMB
CGCLK_SMB (12,13,26)
C262 61 63 CGDAT_SMB
VDD_REF SDA CGDAT_SMB (12,13,26)
10U/6.3V/X5R_8 0.1U/10V/X7R_4 CK505
2
39 38 PM_STPPCI#
VDD_SRC PCI_STOP# PM_STPPCI# (16)
VDDCPU 55 37 PM_STPCPU#
VDD_CPU CPU_STOP# PM_STPCPU# (16)
+3V +CK_VDD_MAIN2 12 54 CLK_CPU_BCLK
VDD_96_IO CPU0 CLK_CPU_BCLK (4)
20 53 CLK_CPU_BCLK#
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# (4)
26 VDD_SRC_IO_1
51 CLK_MCH_BCLK
CPU1 CLK_MCH_BCLK (7)
2
36 50 CLK_MCH_BCLK#
+3V VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# (7)
49 VDD_CPU_IO
B R215 45 47 CPU_ITP B
VDD_SRC_IO_3 SRC8/ITP T8 *PAD
10K_4
EB1213-0001 SRC8#/ITP# 46 CPU_ITP#
T9 *PAD
1
2
R197 33_4 R_PCI_CLK_8502 1 35 CLK_PCIE_NEW#
(25) PCI_CLK_8502 PCI0/CR#_A SRC10# CLK_PCIE_NEW# (26)
PCLK_MINI_LPC 34 CLK_PCIE_NEW
SRC10 CLK_PCIE_NEW (26)
R231 PCIE_LANREQ# R214 475/F_4 LANREQ# 3
(21) PCIE_LANREQ# PCI1/CR#_B
*10K_4 33 NEW-CARD_CLK_REQ#_R R176 475/F_4 NEW-CARD_CLK_REQ#
SRC11/CR#_H NEW-CARD_CLK_REQ# (26)
R217 33_4 PCLK_MINI_LPC 4 32 CLK_3GPLLREQ#_R R207 475/F_4 CLK_MCH_OE#
(26) PCLK_LPC_DEBUG CLK_MCH_OE# (8)
1
R216 FCTSEL1 PCI2/TME SRC11#/CR#_G
R218 *33_4 5 30 CLK_PCIE_3GPLL
*PAD T38 PCI3 SRC9 CLK_PCIE_3GPLL (8)
2
*4.7K_4
EB1213-0002 *PAD
R219 *33_4 FCTSEL1 6
SRC9# 31 CLK_PCIE_3GPLL#
CLK_PCIE_3GPLL# (8)
R232 T39 PCI4/27MHz_Select CLK_PCIE_CARD
SRC7/CR#_F 44 CLK_PCIE_CARD (20)
10K_4 R220 33_4 ITP_EN 7 43 CLK_PCIE_CARD#
(15) PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E CLK_PCIE_CARD# (20)
1
EB1213-0003 CG_XIN 60 XTAL_IN SRC6 41
40
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_ICH (15)
CLK_PCIE_ICH# (15)
CG_XOUT SRC6#
59 XTAL_OUT
0=overclocking 0=UMA 27 CLK_PCIE_LAN
SRC4 CLK_PCIE_LAN (21)
1 = External VGA CLK_48M_USB R208 33_4 FSA 10 28 CLK_PCIE_LAN#
of CPU and (16) CLK_48M_USB USB_48/FSA SRC4# CLK_PCIE_LAN# (21)
CPU_BSEL0 R223 2.2K_4
SRC Allowed EB1213-0004 CPU_BSEL1 R162 2.2K_4 FSB 57 FSB/TEST/MODE SRC3/CR#_C 24
25
CLK_PCIE_MINI_
CLK_PCIE_MINI_#
CLK_PCIE_WLAN (26)
CLK_PCIE_WLAN# (26)
CPU_BSEL2 R161 10K_4 FSC SRC3#/CR#_D
62 REF0/FSC/TESTSEL
+3V CLK_14M_ICH R160 33_4 CLK_PCIE_SATA
1 = overclocking (16) CLK_14M_ICH SRC2/SATA 21
CLK_PCIE_SATA#
CLK_PCIE_SATA (14)
8 22 CLK_PCIE_SATA# (14)
of CPU and SRC VSS_PCI SRC2#/SATA#
2
Enable ITP 11 VSS_48
not Allowed 15 17 DREFSSCLK
VSS_IO SRC1/SE1/27MHz_NonSS DREFSSCLK (8)
R233 19 18 DREFSSCLK#
VSS_PLL3 SRC1#/SE2/27MHz_SS DREFSSCLK# (8)
*10K_4 52
C C592 *33P/50V/NPO_4 CLK_48M_USB VSS_CPU DREFCLK C
23 13 DREFCLK (8)
1
VSS_SRC1 SRC0/DOT96
ITP_EN C311 *33P/50V/NPO_4 PCI_CLK_8502 EB1213-0005 29
42
VSS_SRC2 SRC0#/DOT96# 14 DREFCLK#
DREFCLK# (8)
VSS_SRC3
58 VSS_REF CKPWRGD/PWRDWN# 56 CK_PWG (16)
C302 *33P/50V/NPO_4 FCTSEL1
2
ICS9LPRS365AGLFT/SLG8SP512
C303 *33P/50V/NPO_4 ITP_EN
R234
10K_4 C310 *33P/50V/NPO_4 PCLK_LPC_DEBUG
1
C255 *33P/50V/NPO_4 CLK_14M_ICH
for EMI GCLK_SEL = FCTSEL1
FCTSEL1 PIN13 PIN14 PIN24 PIN25
(PIN6)
CPU Clock select FSC FSB FSA CPU SRC PCI
0=UMA DREFCLK DREFCLK# SRCT1/LCDT_100 SRCT1/LCDT_100
CPU_BSEL0 R230 0_4
1 0 1 100 100 33
(4) CPU_BSEL0 MCH_BSEL0 (8)
0 0 1 133 100 33
R239 1K_4
0 1 1 166 100 33
CPU_BSEL1 R423 0_4
0 1 0 200 100 33
(4) CPU_BSEL1 MCH_BSEL1 (8)
D
0 0 0 266 100 33 D
R152 1K_4
1 0 0 333 100 33
+1.05V
CPU_BSEL2 R425 0_4
1 1 0 400 100 33
(4) CPU_BSEL2 MCH_BSEL2 (8)
1 1 1 RSVD 100 33 PROJECT : LE6
1K to NB only when
+1.05V R151 1K_4 XDP is implement.No
XDP can use 0 ohm
Quanta Computer Inc.